Wafer package, chip package, working assembly and computing device

Abstract

Provided in the embodiments of the present application are a wafer package, a chip package, a working assembly and a computing device. The wafer package is arranged on one side of a printed circuit board, and the wafer package comprises at least one memory module, wherein the memory module comprises a memory wafer, a logic processing wafer and a circuit element wafer, which are stacked, the circuit element wafer being a deep trench capacitor wafer, or the circuit element wafer being a resistance-inductance-capacitance wafer. By means of providing a wafer-level 3D packaging solution, the technical solution provided in the embodiments of the present application can realize ultra-large computing power and an ultrahigh storage bandwidth.

Description

Wafer package, chip package, work assembly and computing device

[0001] This application claims priority from the Chinese patent application No. 202421230200.1 filed on May 31, 2024, and entitled "Wafer package, chip package, work assembly and computing device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of packaging technology, in particular to a wafer package, a chip package, a work assembly and a computing device. BACKGROUND

[0003] Traditional 2D chip packaging can reduce packaging size and improve production efficiency. However, with the increase of integration and performance requirements, 2D packaging has gradually failed to meet the needs of modern high-performance computing and storage systems. 3D packaging technology improves integration and performance by vertically stacking and interconnecting multiple chip layers, such as improving computing power and storage bandwidth. However, traditional packaging technology is usually limited to the packaging of a single chip or chip set. SUMMARY

[0004] Embodiments of the present application provide a wafer package, a chip package, a work assembly and a computing device to solve or alleviate one or more technical problems in the prior art.

[0005] As an aspect of the embodiments of the present application, a wafer package is provided for arranging on one side of a printed circuit board, the wafer package comprising at least one memory module, the memory module comprising stacked memory wafers, logic processing wafers and circuit element wafers, wherein the circuit element wafers are digitally tunable capacitance wafers, or the circuit element wafers are resistance-inductance-capacitance wafers.

[0006] In an embodiment, the non-top layer wafers of the memory module are provided with through silicon vias, and the wafers of the memory module are connected by hybrid bonding or micro-bump connection.

[0007] In an embodiment, in the memory module, the circuit element wafers are located between the memory wafers and the logic processing wafers.

[0008] In an embodiment, the memory module is provided with controllable chip collapse connection C4 bumps or solder balls on the side facing the printed circuit board, so that the wafer package is connected to the printed circuit board through the C4 bumps or the solder balls.

[0009] In an embodiment, the memory module further comprises a redistribution interposer located on a side of the C4 bumps or the solder balls away from the printed circuit board, and the memory module is connected with the C4 bumps or the solder balls through the redistribution interposer.

[0010] In an embodiment, the package further comprises a substrate located between the memory module and the printed circuit board, and used for carrying the memory module.

[0011] In an embodiment, a side of the memory module facing the substrate is provided with C4 bumps, the C4 bumps are connected with the substrate, and a redistribution interposer is arranged between the memory module and the C4 bumps, and the redistribution interposer is connected with the C4 bumps.

[0012] As an aspect of the embodiments of the present application, the embodiments of the present application provide a chip package arranged on a side of a printed circuit board, the package comprising at least one memory module, the memory module comprising stacked memory dies, logic processing dies and circuit element dies, the circuit element dies being digital adjustable capacitor dies, or the circuit element dies being resistor-inductor-capacitor dies.

[0013] As an aspect of the embodiments of the present application, the embodiments of the present application provide a working assembly comprising the package in any of the embodiments of the present application and a printed circuit board, a side of the printed circuit board being arranged with the package.

[0014] As an aspect of the embodiments of the present application, the embodiments of the present application provide a computing device comprising the working assembly in any of the embodiments of the present application and a power supply module.

[0015] The technical solutions of the embodiments of the present application provide a 3D package of a memory layer, a logic processing layer and a circuit element layer, the 3D package can be a whole-layer wafer-level package or a die-level package, can realize super-large computing power and super-high storage bandwidth, and the circuit element layer is directly packaged with the memory layer and the logic processing layer, so that special circuit functions such as filtering or noise elimination can be added to the packaged chip.

[0016] The above summary is only for the purpose of the description and is not intended to limit in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present application will be readily apparent to those skilled in the art by reference to the drawings and the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0017] In the drawings, like reference numerals refer to like elements throughout the various figures. The drawings are not necessarily to scale, and the emphasis is on the functional description of the drawings. It should be understood that the drawings only depict some embodiments in accordance with the disclosure and should not be considered limiting of the scope of the disclosure.

[0018] FIGS. 1A, 1B, 2A and 2B show structural diagrams of working assemblies according to Embodiment One of the present application;

[0019] FIGS. 3A, 3B, 4A and 4B show structural diagrams of working assemblies according to Embodiment Two of the present application;

[0020] FIGS. 5A, 5B, 6A and 6B show structural diagrams of working assemblies according to Embodiment Three of the present application;

[0021] FIGS. 7A, 7B, 8A, 8B, 9A and 9B show structural diagrams of working assemblies according to Embodiment Four of the present application.

[0022] Reference numeral explanation: 30: PCB board; 100, 200: memory module; 101: memory wafer; 102: logic processing wafer; 103: circuit element wafer; 201: memory die; 202: logic processing die; 203: circuit element die; 104: C4 bump; 105: micro bump; 110: redistribution interposer; 106: RDL medium; 107: RDL wiring layer; 109: solder ball; 204: TSV; 20: substrate. DETAILED DESCRIPTION

[0023] In the following, only some exemplary embodiments are described briefly. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present application. Therefore, the drawings and the description are considered to be exemplary in nature rather than limiting.

[0024] With the development of technology, the integration of chips is getting higher and higher, and the performance is also constantly improving. However, with the further development of technology, it becomes more and more challenging to integrate more functions and elements on a single chip, while also increasing the cost and complexity of manufacturing.

[0025] To overcome these challenges, the semiconductor manufacturing technology field has begun to emerge the concept of chiplet. Chiplet can be understood as a small, independent chip module, which usually contains a specific functional unit or processing unit. Unlike traditional single chips, chiplet splits the entire system into multiple smaller and more focused parts. These chiplets can be independently designed, manufactured and tested, and then combined together in a package to form a complete functional system or processing system, to achieve a more flexible, performance-optimized and cost-reduced design and manufacturing method. Chiplet is an innovative solution to address complexity and cost challenges in the context of increasing chip technology and performance.

[0026] Under the technical concept of chiplet, 2.5D packaging solutions such as Chip-on-Wafer-on-Substrate (CoWoS) emerge. In an exemplary CoWoS solution, by integrating logic processing dies and high bandwidth memory (HBM) stacks together, usually multiple HBM stacks are arranged around the logic die to provide excellent computing and memory performance. The CoWoS solution allows the integration of multiple chips with different functions in a single package, thereby providing higher performance and efficiency. However, compared with other packaging solutions with the same computing power and bandwidth, the chip packaging area of the CoWoS solution will also be larger, and the power consumption and cost will be higher.

[0027] Therefore, there is an urgent need for mature 3D packaging technology in the field of memory packaging to achieve ultra-large computing power and ultra-high storage bandwidth. The present application aims to provide a 3D packaging solution, which forms a memory module by stacking a memory layer, a logic processing layer and a circuit element layer, and packages one or more memory modules together to form a 3D package. Among them, the memory layer is a memory wafer, the logic processing layer is a logic processing wafer, and the circuit element layer is a circuit element wafer; or the memory layer is a memory die, the logic processing layer is a logic processing die, and the circuit element layer is a circuit element die. That is, the 3D package in the present application can be a whole-layer wafer-level package, or a die-level package, thereby meeting various application scenarios while achieving ultra-large computing power and ultra-high storage bandwidth, and the circuit element layer is directly packaged with the memory layer and the logic processing layer, which can add special circuit functions to the packaged chip, such as filtering or noise elimination.

[0028] The wafer refers to a circular silicon wafer used in the semiconductor manufacturing process, which is usually a circular wafer made of silicon material. In the traditional packaging field, first, on the wafer, a multilayer structure is established on the surface through a series of process steps, including insulating layers, conductor layers and semiconductor layers, which constitute an integral part of integrated circuits or other semiconductor devices; after manufacturing, the wafer is cut into individual dies, and then the dies are packaged.

[0029] In the embodiments of the present application, the memory layer can be any type of memory, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Non-Volatile Random Access Memory (NVRAM), Flash Memory or Electrically Erasable Programmable Read-Only Memory (EEPROM), etc. Exemplarily, the memory can be a customized memory or a standardized memory, and the embodiments of the present application do not limit this.

[0030] The logic processing layer can be responsible for logic processing functions. Illustratively, the logic processing layer can include a memory control unit, can include a processor unit, or can include both a memory control unit and a processor unit. The processor unit is, for example, a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), a knowledge processing unit (KPU), a tensor processing unit (TPU), an intelligence processing unit (IPU), a reconfigurable dataflow unit, a neural processing unit (NPU), or any type processing unit (xPU), responsible for executing instructions and performing various computing and data processing tasks, including simple arithmetic operations and complex logical operations, thereby realizing computing, control, decision-making, and other functions. The memory control unit is responsible for managing and coordinating a portion of memory access, such as converting processor-requested memory operations into memory operations and ensuring correct transmission and storage of data, to realize efficient memory access and data transmission.

[0031] The circuit element layer can be used as a digital tunable capacitor (DTC) or a resistance-inductance-capacitance (RLC). The DTC is a capacitor that can control its capacitance value through digital signals and is widely used in circuit design at radio frequency and microwave frequency, such as high-frequency filters, oscillators, etc. The RLC is an RLC circuit implemented by semiconductor technology and can be used for filters, tuning circuits, oscillators, impedance matching, power management, noise elimination, etc.

[0032] In one packaging form, the memory layer is a memory wafer, the logic processing layer is a logic processing wafer, and the circuit element layer is a circuit element wafer, i.e., the memory module is stacked by multiple wafers. In another packaging form, the memory layer is a memory die, the logic processing layer is a logic processing die, and the circuit element layer is a circuit element die, i.e., the memory module is stacked by multiple dies.

[0033] Exemplarily, the package provided by the embodiments of the present application can be used in high-performance computing semiconductor work components, sensor semiconductor work components, micro-electro-mechanical systems (MEMS), optical communication semiconductor work components, and the like. It should be noted that the above application scenarios or application examples provided in the embodiments of the present application are for ease of understanding, and the application of the package is not limited specifically in the embodiments of the present application.

[0034] The technical solutions of the present application and how the technical solutions of the present application solve the foregoing technical problems will be described in detail below with specific embodiments. The several specific embodiments listed can be combined with each other, and the same or similar concepts or processes can not be described repeatedly in some embodiments.

[0035] Embodiment One

[0036] FIGS. 1A and 1B show an architecture diagram of a work component provided by the embodiments of the present application. As shown in FIGS. 1A and 1B, the work component includes at least one package and a printed circuit board (PCB) 30, wherein the package includes at least one memory module 100, and when the package is used in the work component, the memory module 100 is arranged on one side of the PCB 30 of the work component.

[0037] The memory module 100 includes a memory wafer 101, a logic processing wafer 102, and a circuit element wafer 103 stacked in a direction perpendicular to the PCB 30. In the embodiments of the present application, the circuit element wafer 103 is arranged inside the memory module 100, that is, in one package, the circuit element wafer 103 can be arranged close to the memory wafer 101 and the logic processing wafer 102, thereby reducing the transmission distance and making the loop inductance smaller, and the decoupling effect is much better than that of the traditional package.

[0038] It should be noted that the stacking order and number of the memory wafer 101, the logic processing wafer 102 and the circuit element wafer 103 in one memory module 100 are not limited in the embodiments of the present application. For example, as shown in FIG. 1A, in one memory module 100, the number of the memory wafer 101, the logic processing wafer 102 and the circuit element wafer 103 is one respectively, and the stacking order can be that the memory wafer 101, the logic processing wafer 102 and the circuit element wafer 103 are stacked in the up-down direction shown in FIG. 1A in sequence, or that the logic processing wafer 102, the circuit element wafer 103 and the memory wafer 101 are stacked in sequence, or that the circuit element wafer 103, the memory wafer 101 and the logic processing wafer 102 are stacked in sequence; as shown in FIG. 1B, in one memory module 100, the number of the memory wafer 101, the logic processing wafer 102 and the circuit element wafer 103 is multiple respectively, and the stacking order between the multiple memory wafers 101, the multiple logic processing wafers 102 and the multiple circuit element wafers 103 can be set arbitrarily. In addition, the connection mode between adjacent wafers can be face to face or face to back, which is not limited in the embodiments of the present application.

[0039] In one embodiment, as shown in FIGS. 1A and 1B, in one memory module 100, the circuit element wafer 103 is located between the memory wafer 101 and the logic processing wafer 102. Based on this, the circuit element wafer 103 can be close to both the memory wafer 101 and the logic processing wafer 102, thereby further improving the decoupling effect of the memory module 100. That is, in the memory module, the circuit element layer can be located between the memory layer and the logic processing layer, so that the circuit element layer can be close to both the memory layer and the logic processing layer to improve the decoupling effect of the memory module.

[0040] In one memory module 100, the connection mode between adjacent wafers can be configured according to actual needs, which is not limited in the embodiments of the present application. It should be noted that in the embodiments of the present application, the connection (interconnection) refers to the electrical connection between electronic elements, chips, dies, circuit boards, wafers and the like, so as to transmit power and signals. For example, the transistors on the wafer are connected with other transistors, resistors, capacitors and the like to form a complete circuit to realize the required functions. At the same time, the wafer also needs to be connected with the circuit board, other wafers or systems to receive power and input signals and send output signals.

[0041] In one embodiment, the non-top wafer of the memory module 100 (which can be the memory wafer 101, the logic processing wafer 102, or the circuit element wafer 103) is provided with a through silicon via (TSV) (not shown in the figure due to the scale problem), i.e., a vertical through-hole formed inside the wafer, to achieve interconnection and communication between different levels of chips. Each TSV is a tiny metal through-hole that passes through the thickness of the wafer, connecting circuits at different levels, thereby achieving high-speed signal transmission, low-latency interconnection, and higher-performance, more compact packaging solutions.

[0042] As an example, the wafers of the memory module 100 are connected by hybrid bonding. Specifically, a very strong atomic-level connection between two wafers can be created using surface chemical reactions, allowing for micron-scale accurate alignment and connection of chip wafers on the wafer. Hybrid bonding can typically enable the transmission of electrical signals and data without the need for solder or conductive materials, thus reducing signal transmission loss in some applications. Due to the very close connection, hybrid bonding can achieve high-density wafer stacking, thus achieving more functionality in a smaller package size.

[0043] Based on this, shorter interconnection distances and higher interconnection densities between wafers inside the memory module 100 can be achieved, greatly improving interconnection efficiency and performance.

[0044] As another example, the wafers inside the memory module 100 are connected by micro bumps 105. Specifically, a micro bump is a tiny protruding structure, usually made of metal material, to form interconnection and communication between wafers. And this structure is usually manufactured through microelectronic processes, and its size, position and arrangement can be accurately controlled, thus achieving high-density connection.

[0045] In one connection method, as shown in FIGS. 1A and 1B, the memory module 100 is provided with C4 bumps 104 on the side facing the PCB 30, and the memory module 100 is connected to the PCB 30 through the C4 bumps 104.

[0046] Specifically, a bottom wafer (e.g., the memory wafer 101) of the memory module 100 can be provided with C4 bumps 104 on a side facing the PCB 30, and the bottom wafer (the memory wafer 101) is connected to the PCB 30 through the C4 bumps 104. Other wafers in the memory module 100 can also be connected to the PCB 30 through the bottom wafer and the C4 bumps 104.

[0047] The C4 bumps 104 are made by a bumping process, and the core process flow is metal deposition. The most common metal deposition steps include deposition of an under bump metallization (UBM) and deposition of the bump itself. The deposition of the under bump metallization (UBM) is usually achieved by sputtering, electroless plating, plating, etc.; the deposition of the bump itself is usually achieved by plating, ball planting, or printing. In the embodiments of the present application, the C4 bumps 104 are used to realize the connection between the memory module 100 and the PCB 30. Since the C4 bumps can be arranged at a small pitch, this connection mode can realize high-density and precise connection between the memory module 100 and the PCB 30.

[0048] In one connection mode, the C4 bumps can be replaced by solder balls, i.e., the PCB 30 is provided with solder balls on a side facing the memory module 100, and the memory module 100 is connected to the PCB 30 through the solder balls. The solder balls, also known as soldering beads, are usually made of tin or other alloys and have a spherical shape. As a traditional connection mode, the solder balls have a simple process and low cost. Using the solder balls to realize the connection between the memory module 100 and the PCB 30 can simplify the process, reduce the cost, and improve the yield while ensuring the connection performance.

[0049] In one connection mode, as shown in FIGS. 2A and 2B, the memory module 100 further includes a re-distribution layer (RDL) interlayer 110 located on a side of the C4 bumps 104 facing away from the PCB 30. The memory module 100 is connected to the C4 bumps 104 through the re-distribution interlayer 110, and then connected to the PCB 30 through the C4 bumps 104.

[0050] In one connection mode, the memory module 100 is connected to the solder balls through the re-distribution interlayer 110, and then connected to the PCB 30 through the solder balls.

[0051] The redistribution layer interposer 110 generally includes the RDL medium 106 and the RDL wiring layer 107 in the RDL medium 106. The RDL medium 106 is generally made of an organic material; a common material of the RDL wiring layer 107 is plated copper supplemented by a titanium primer, a copper sputtering layer; and the surface of the copper layer is covered with a corresponding protective layer ink as needed. That is, the connection of the memory module 100 to the C4 bumps 104 or solder balls, and thus to the PCB 30, can be realized based on the RDL wiring layer 107 in the redistribution layer interposer 110. In this embodiment, the high-density connection between the memory module 100 and the PCB 30 can be realized based on the redistribution layer interposer 110, and the connection accuracy can be improved.

[0052] According to the package provided in the embodiments of the present application, by directly packaging the whole-layer memory wafer and the whole-layer logic processing wafer as one memory module without cutting, super-large computing power and super-high storage bandwidth can be realized. Meanwhile, the circuit element wafer is packaged together with the memory wafer and the logic processing wafer as part of the memory module, which can add some special circuit functions to the memory module, shorten the transmission distance, and increase the connection density.

[0053] The embodiments of the present application also provide a working assembly including the PCB 30 and at least one package. It should be noted that the working assembly can include one package or multiple packages, for example, the package provided in the embodiments of the present application or a conventional package known to those skilled in the art. The type, number, and connection topology of the package are not limited in the embodiments of the present application. In addition, a connection relationship can exist between at least part of the packages.

[0054] For example, the package can be directly arranged on one side of the PCB 30 without molding packaging, that is, without molding packaging for the wafer on the PCB 30.

[0055] According to the working assembly provided in the embodiments of the present application, the disadvantages of small storage bandwidth and small computing power in the conventional packaging scheme can be avoided, and advanced packaging technology is provided to increase the storage bandwidth, thereby improving the chip computing power.

[0056] It should be noted that in the first embodiment of the present application, for the scheme in which the memory module 100 is formed by wafer stacking, the PCB 30 as a packaging board needs to carry the wafer, and thus the size of the PCB 30 is larger than that of a conventional PCB, that is, larger than the size of the carried wafer.

[0057] Other configurations of the package or working assembly of the above embodiments can be adopted by various technical solutions known to those skilled in the art now and in the future, which will not be described in detail here.

[0058] Embodiment Two

[0059] The present embodiment provides a package, which is based on the package of Embodiment One and further includes a substrate. Therefore, all or part of the implementation manners and corresponding technical effects of Embodiment One can be applied to the present embodiment.

[0060] As shown in FIGS. 3A and 3B, the package of the present embodiment further includes a substrate 20. Specifically, the substrate 20 is arranged between the memory module 100 and the PCB 30, and the memory module 100 is connected to the PCB 30 through the substrate 20.

[0061] In order to facilitate the horizontal expansion of the memory module 100, a plurality of memory modules 100 can be arranged horizontally on the substrate 20, so as to realize the horizontal connection of the memory modules 100 on the substrate 20. Then, the memory modules 100 are connected to the PCB 30 through the substrate 20, which can improve the connection reliability and realize super-large computing power and super-high storage bandwidth.

[0062] In one implementation manner, as shown in FIGS. 3A and 3B, the side of the memory module 100 facing the substrate 20 is provided with C4 bumps 104, and the memory module 100 is connected to the substrate 20 through the C4 bumps 104. Based on this, high-density and precise connection between the substrate 20 and the memory module 100 can be realized.

[0063] In one implementation manner, as shown in FIGS. 4A and 4B, a redistribution interposer 110 is arranged between the memory module 100 and the C4 bumps 104, and the memory module 100 is connected to the C4 bumps 104 through the redistribution interposer 110. Based on this, high-density connection between the substrate 20 and the memory module 100 can be realized, and the connection precision can be improved.

[0064] The present embodiment also provides a working assembly, which includes a PCB 30 and at least one package. The package can be any of the packages described above. It should be noted that the working assembly can include one package or a plurality of packages, for example, both the package provided by the present embodiment and a conventional package known to those skilled in the art. The type, number and connection topology of the package are not limited in the present embodiment. In addition, there can be a connection relationship between at least part of the packages.

[0065] For example, the package can be directly arranged on one side of the PCB 30 without molding the package, i.e., without molding the wafer on the PCB 30.

[0066] According to the working assembly provided in the embodiments of the present application, the disadvantages of small storage bandwidth and small computing power of the traditional packaging scheme can be avoided, and advanced packaging technology is provided to increase the storage bandwidth, thereby improving the computing power of the chip. It should be noted that in the second embodiment of the present application, for the scheme in which the memory module 100 is formed by wafer stacking, the substrate 20 needs to bear the wafer as a packaging board, and therefore the size of the substrate 20 is larger than the size of the conventional substrate, that is, larger than the size of the wafer to be borne.

[0067] The other configurations of the packaging body or the working assembly of the above embodiments can adopt various technical solutions known by those skilled in the art at present and in the future, and will not be described in detail here.

[0068] Embodiment three

[0069] FIGS. 5A and 5B show the architecture of the working assembly provided in the embodiments of the present application. As shown in FIGS. 5A and 5B, the working assembly includes at least one packaging body and a PCB board 30, wherein the packaging body includes at least one memory module 200, and when the packaging body is used in the working assembly, the memory module 200 is arranged on one side of the PCB board 30 of the working assembly.

[0070] The memory module 200 includes memory dies 201, logic processing dies 202, and circuit element dies 203 stacked in a direction perpendicular to the PCB board 30. In the embodiments of the present application, the circuit element dies 203 are arranged inside the memory module 200, that is, in one packaging body, the circuit element dies 203 are closer to the memory dies 201 and the logic processing dies 202, thereby reducing the transmission distance and making the loop inductance smaller, and the decoupling effect is much better than that of the traditional packaging.

[0071] It should be noted that the stacking order and the number of the memory dies 201, the logic processing dies 202 and the circuit element dies 203 in one memory module 200 are not limited in the embodiments of the present application. For example, as shown in FIG. 5A, in one memory module 200, the number of the memory dies 201, the logic processing dies 202 and the circuit element dies 203 is one respectively, and the stacking order can be that the memory die 201, the logic processing die 202 and the circuit element die 203 are stacked in sequence, or that the logic processing die 202, the circuit element die 203 and the memory die 201 are stacked in sequence, or that the circuit element die 203, the memory die 201 and the logic processing die 202 are stacked in sequence. As shown in FIG. 5B, in one memory module 200, the number of the memory dies 201, the logic processing dies 202 and the circuit element dies 203 is multiple respectively, and the stacking order between the multiple memory dies 201, the multiple logic processing dies 202 and the multiple circuit element dies 203 can be set arbitrarily. In addition, the connection mode between the adjacent dies can be face-to-face or face-to-back, which is not limited in the embodiments of the present application.

[0072] In one embodiment, as shown in FIGS. 5A and 5B, in one memory module 200, the circuit element die 203 is located between the memory die 201 and the logic processing die 202. Based on this, the circuit element die 203 can be close to both the memory die 201 and the logic processing die 202, thereby further improving the decoupling effect of the memory module 200. That is, in the memory module, the circuit element layer can be located between the memory layer and the logic processing layer, thereby making the circuit element layer close to both the memory layer and the logic processing layer to improve the decoupling effect of the memory module.

[0073] In one memory module 200, the connection mode between the adjacent dies can be configured according to actual needs, which is not limited in the embodiments of the present application.

[0074] In one embodiment, the non-top die (which can be the memory die 201, the logic processing die 202 or the circuit element die 203) of the memory module 200 is provided with a TSV 204 to realize the interconnection and communication between the dies at different levels, thereby realizing high-speed signal transmission, low-delay interconnection and higher-performance and more compact packaging scheme.

[0075] As an example, the dies of the memory module 200 are connected by the hybrid bonding mode, which can reduce the loss of signal transmission. Since the connection is very close, high-density die stacking can be realized by hybrid bonding, thereby realizing more functions in a smaller packaging size.

[0076] Based on this, shorter interconnection distance and higher interconnection density between dies inside the memory module 200 can be achieved, greatly improving interconnection efficiency and performance.

[0077] As another example, the dies inside the memory module 200 are connected by micro bumps 105, the size, position and arrangement of which can be precisely controlled, thereby achieving high-density connection.

[0078] In one connection mode, as shown in FIGS. 5A and 5B, the side of the memory module 200 facing the PCB 30 is provided with C4 bumps 104, and the memory module 200 is connected to the PCB 30 through the C4 bumps 104.

[0079] Specifically, the bottom die (e.g., the memory die 201) of the memory module 200 can be provided with C4 bumps 104 on the side facing the PCB 30, and the bottom die (the memory die 201) is connected to the PCB 30 through the C4 bumps 104. Other dies inside the memory module 200 can also be connected to the PCB 30 through the bottom die and the C4 bumps 104. Since C4 bumps can be arranged at a smaller pitch, this connection mode can achieve high-density and precise connection between the memory module 200 and the PCB 30.

[0080] In one connection mode, the C4 bumps can be replaced by solder balls, i.e., the side of the PCB 30 facing the memory module 200 is provided with solder balls, and the memory module 200 is connected to the PCB 30 through the solder balls, which can simplify the process, reduce costs, and improve yield while ensuring connection performance.

[0081] In one connection mode, as shown in FIGS. 6A and 6B, the memory module 200 further includes a redistribution interposer 110 on the side of the C4 bumps 104 facing away from the PCB 30, and the memory module 200 is connected to the C4 bumps 104 through the redistribution interposer 110, and then connected to the PCB 30 through the C4 bumps 104.

[0082] In one connection mode, the memory module 200 is connected to the solder balls through the redistribution interposer 110, and then connected to the PCB 30 through the solder balls.

[0083] The redistribution interposer 110 generally includes an RDL medium 106 and an RDL wiring layer 107 in the RDL medium 106, and the connection between the memory module 200 and the C4 bumps 104 or the solder balls can be achieved based on the RDL wiring layer 107 in the redistribution interposer 110, thereby achieving the connection between the memory module 200 and the PCB 30. In this embodiment, the redistribution interposer 110 can achieve high-density connection between the memory module 200 and the PCB 30, and can improve connection accuracy.

[0084] It should be noted that the package provided by the embodiments of the present application can include a plurality of memory modules 200, and the plurality of memory modules 200 can be connected in a direction parallel to the PCB, that is, the plurality of memory modules 200 can be horizontally expanded, and the embodiments of the present application do not limit the horizontal expansion mode and the horizontal connection mode.

[0085] For example, the TSVs 204 in the circuit element die 203, the TSVs 204 in the memory die 201, the C4 bumps 104, and the plurality of logic processing dies 202 can be connected to each other based on the substrate 20, as shown in FIG. 7A; or the TSVs 204 in the circuit element die 203, the TSVs 204 in the memory die 201, the redistribution interlayer 110, the C4 bumps 104, and the plurality of logic processing dies 202 can be connected to each other based on the substrate 20, as shown in FIG. 8A.

[0086] For example, the C4 bumps 104 and the plurality of logic processing dies 202 can be connected to each other based on the substrate 20, as shown in FIG. 9A; or the redistribution interlayer 110, the C4 bumps 104, and the plurality of logic processing dies 202 can be connected to each other based on the substrate 20, as shown in FIG. 9B.

[0087] The embodiments of the present application also provide a working assembly, which includes a PCB 30 and at least one package. The package can be any of the packages described above, for example, it can include the package provided by the embodiments of the present application, or it can include a conventional package known to those skilled in the art. It should be noted that the working assembly can include one package, or it can include a plurality of packages, and the embodiments of the present application do not limit the type, number, and connection topology of the package. In addition, there can be a connection relationship between at least part of the packages.

[0088] For example, the package can be directly arranged on one side of the PCB 30, without the need for molding packaging of the package, that is, without the need for molding packaging of the wafer on the PCB 30.

[0089] According to the working assembly provided by the embodiments of the present application, the disadvantages of small storage bandwidth and small computing power of the traditional packaging scheme can be avoided, and advanced packaging technology is provided to increase the storage bandwidth, thereby improving the chip computing power.

[0090] The other configurations of the package or the working assembly of the above embodiments can use various technical solutions known to those skilled in the art at present and in the future, which will not be described in detail here.

[0091] Embodiment Four

[0092] The embodiment provides a package, and a substrate is further added on the basis of the embodiment three, therefore, all or part of the implementation manners and the corresponding technical effects of the embodiment three can be referred to the embodiment.

[0093] As shown in FIGS. 7A and 7B, the package of the embodiment further comprises a substrate 20. Specifically, the substrate 20 is arranged between the memory module 200 and the PCB 30, and the memory module 200 is connected with the PCB 30 through the substrate 20.

[0094] In order to facilitate the horizontal expansion of the memory module 200, a plurality of memory modules 200 can be arranged horizontally on the substrate 20, and then the horizontal connection of the plurality of memory modules 200 on the substrate 20 is realized. Then, the memory module 200 is connected with the PCB 30 through the substrate 20, which can improve the connection reliability and realize super-large computing power and super-high storage bandwidth.

[0095] In an implementation manner, as shown in FIGS. 7A and 7B, the side of the memory module 200 facing the substrate 20 is provided with a C4 bump 104, and the memory module 200 is connected with the substrate 20 through the C4 bump 104. Based on this, high-density connection and accurate connection between the substrate 20 and the memory module 200 can be realized.

[0096] In an implementation manner, as shown in FIGS. 8A and 8B, a redistribution interposer 110 is arranged between the memory module 200 and the C4 bump 104, and the memory module 200 is connected with the C4 bump 104 through the redistribution interposer 110. Based on this, high-density connection between the substrate 20 and the memory module 200 can be realized, and the connection accuracy can be improved.

[0097] The embodiment of the application further provides a working assembly comprising a PCB 30 and at least one package, which can be any of the packages described above. It should be noted that the working assembly can comprise one package or a plurality of packages, for example, both the package provided in the embodiment of the application and the conventional package known by those skilled in the art. The type, quantity and connection topology of the package are not limited in the embodiment of the application. In addition, there can be a connection relationship between at least part of the packages.

[0098] For example, the package can be directly arranged on one side of the PCB 30 without molding the package, that is, without molding the wafer on the PCB 30.

[0099] According to the working assembly provided in the embodiment of the application, the disadvantages of small storage bandwidth and small computing power in the traditional packaging scheme can be avoided, and advanced packaging technology is provided to increase the storage bandwidth, thereby improving the computing power of the chip.

[0100] Other configurations of the package or working assembly of the above embodiments can be used in various technical solutions known to those of ordinary skill in the art now and in the future, which are not described in detail here.

[0101] Embodiment Five

[0102] The embodiments of the present application also provide a computing device, which includes any one of the working assemblies of the above embodiments and a power supply module, wherein the power supply module is used to provide power supply for the working assembly, and the number of the working assemblies can be one or more, which is not limited in the embodiments of the present application. Illustratively, in the plurality of working assemblies, at least part of the working assemblies are connected to each other, which can be electrical connection or physical connection, which is not limited in the embodiments of the present application.

[0103] Illustratively, the computing device provided by the embodiments of the present application can be used in devices and systems requiring a large amount of computing power, such as supercomputers, servers in data centers, high-performance workstations, scientific research equipment, etc., and can be applied in the fields of artificial intelligence, deep learning, big data analysis, etc.

[0104] Illustratively, the computing device provided by the embodiments of the present application can be used in various devices requiring monitoring and measuring physical or chemical changes, such as the fields requiring high-performance sensor chips in smartphones, automobiles, industrial automation equipment, medical equipment, etc.

[0105] Illustratively, the computing device provided by the embodiments of the present application can be used in micro-electromechanical systems, such as the gyroscope and accelerometer of a smartphone, the airbag triggering system of a car, the micro-lens array of a projector, etc.

[0106] Illustratively, the computing device provided by the embodiments of the present application can be used in optical fiber communication systems, such as the fields requiring high-speed data transmission in optical fiber network equipment, optical interconnection in data centers, long-distance optical fiber transmission systems, etc.

[0107] When the computing device is used in different systems or fields, other configurations of the computing device can be different, and other configurations of the computing device of the above embodiments can be used in various technical solutions known to those of ordinary skill in the art now and in the future, which are not described in detail here.

[0108] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0109] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature.

[0110] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0111] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0112] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described above. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0113] The above description is provided as an enabling teaching of the application and is not intended to limit its scope in any way. Any modification of the application in keeping with the spirit thereof that is apparent to those skilled in the art is to be considered within the scope of the application as defined by the appended claims.

Claims

1. A wafer package, characterized in that, For placement on one side of a printed circuit board, the wafer package includes at least one memory module, the memory module including stacked memory wafers, logic processing wafers and circuit element wafers, the circuit element wafers being digitally adjustable capacitor wafers, or the circuit element wafers being resistor-inductor-capacitor wafers.

2. The wafer package according to claim 1, characterized in that, The non-top-layer wafers of the memory module are provided with through-silicon vias, and the wafers of the memory module are connected by hybrid bonding or by microbumps.

3. The wafer package according to claim 1, characterized in that, In the memory module, the circuit element wafer is located between the memory wafer and the logic processing wafer.

4. The wafer package according to any one of claims 1 to 3, characterized in that, The memory module has a controllable collapse chip connection C4 bump or solder ball on the side facing the printed circuit board, so that the wafer package is connected to the printed circuit board through the C4 bump or solder ball.

5. The wafer package according to claim 4, characterized in that, The memory module further includes a redistribution intermediary layer located on the side of the C4 bump or the solder ball away from the printed circuit board, and the memory module is connected to the C4 bump or the solder ball through the redistribution intermediary layer.

6. The wafer package according to any one of claims 1 to 3, characterized in that, It also includes a substrate located between the memory module and the printed circuit board for supporting the memory module.

7. The wafer package according to claim 6, characterized in that, The memory module has a C4 bump on the side facing the substrate. The C4 bump is connected to the substrate. A redistribution intermediary layer is provided between the memory module and the C4 bump. The redistribution intermediary layer is connected to the C4 bump.

8. A chip package, characterized in that, For placement on one side of a printed circuit board, the package includes at least one memory module, the memory module including stacked memory dies, logic processing dies and circuit element dies, the circuit element dies being digitally adjustable capacitor dies, or resistor-inductor-capacitor dies.

9. A working component, characterized in that, include: The package according to any one of claims 1 to 8; A printed circuit board, wherein the package is disposed on one side of the printed circuit board.

10. A computing device, characterized in that, It includes the working components and power supply module as described in claim 9.

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