Display panel and display device

Abstract

The present application provides a display panel and a display device. The display panel comprises a substrate (100) and driving arrays (20) provided on one side of the substrate (100). The driving arrays (20) comprise transistors (210). The display panel further comprises shielding structures (300) provided on the side of the substrate (100) close to the driving arrays (20). The shielding structures (300) each comprise at least one shielding sub-structure (310). The shielding sub-structure (310) at least partially overlaps a channel region of the corresponding transistor (210), and the shielding sub-structure (310) is connected to a potential signal terminal.

Description

Display panel and display device

[0001] This application claims priority to Chinese Patent Application No. 202410706243.0, filed with the Chinese Patent Office on May 31, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display panel technology, such as display panels and display devices. Background Technology

[0003] With the continuous development of display technology, display panels have been widely used in people's production and daily life. However, there are still some technical problems with display panels that need to be solved. Summary of the Invention

[0004] This application provides a display panel and a display device. By connecting the shielding substructure to a potential signal, the stability of the transistor operation is effectively guaranteed, thereby ensuring the display effect of the display panel.

[0005] This application provides a display panel, including a substrate and a driving array disposed on one side of the substrate, the driving array including transistors; the display panel further includes a shielding structure disposed on the side of the substrate near the driving array, the shielding structure including at least one shielding substructure, the shielding substructure at least partially overlapping the channel region of the transistors; the shielding substructure is connected to a potential signal terminal.

[0006] This application provides a display device including the display panel described above. Attached Figure Description

[0007] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0008] Figure 2 is a circuit element diagram of a driving circuit provided in an embodiment of this application;

[0009] Figure 3 is a circuit element diagram of another driving circuit provided in an embodiment of this application;

[0010] Figure 4 is a circuit element diagram of another driving circuit provided in an embodiment of this application;

[0011] Figure 5 is a circuit element diagram of another driving circuit provided in an embodiment of this application;

[0012] Figure 6 is a schematic cross-sectional view along section line A-A' in Figure 1;

[0013] Figure 7 is a circuit element diagram of a peripheral driving circuit provided in an embodiment of this application;

[0014] Figure 8 is a schematic cross-sectional view along section line B-B' in Figure 1;

[0015] Figure 9 is a schematic diagram of another display panel provided in an embodiment of this application;

[0016] Figure 10 is a schematic diagram of the film structure of a peripheral driving circuit provided in an embodiment of this application;

[0017] Figure 11 is a schematic diagram of a part of the structure in Figure 10;

[0018] Figure 12 is a schematic diagram of another part of the structure in Figure 10;

[0019] Figure 13 is a circuit element diagram of another peripheral driving circuit provided in an embodiment of this application;

[0020] Figure 14 is another cross-sectional view along section line B-B' in Figure 1;

[0021] Figure 15 is a schematic diagram of the film structure of another peripheral driving circuit provided in an embodiment of this application;

[0022] Figure 16 is a schematic diagram of a part of the structure in Figure 15;

[0023] Figure 17 is a schematic diagram of another part of the structure in Figure 15;

[0024] Figure 18 is a circuit element diagram of another peripheral driving circuit provided in an embodiment of this application;

[0025] Figure 19 is another cross-sectional view along section line B-B' in Figure 1;

[0026] Figure 20 is another cross-sectional view along section line B-B' in Figure 1;

[0027] Figure 21 is another cross-sectional view along section line C-C' in Figure 9;

[0028] Figure 22 is a schematic diagram of another display panel provided in an embodiment of this application;

[0029] Figure 23 is a schematic cross-sectional view along section line I-I' in Figure 22;

[0030] Figure 24 is a schematic cross-section along section line K-K' in Figure 22;

[0031] Figure 25 is a schematic diagram of another display panel provided in an embodiment of this application;

[0032] Figure 26 is a schematic diagram of another display panel provided in an embodiment of this application;

[0033] Figure 27 is a schematic diagram of another display panel provided in an embodiment of this application;

[0034] Figure 28 is a schematic diagram of another display panel provided in an embodiment of this application;

[0035] Figure 29 is a schematic diagram of the structure of a display module provided in an embodiment of this application. Detailed Implementation

[0036] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, for example, including other systems, products, and devices that do not explicitly list this series of steps or units, or other units inherent to such systems, products, or devices, in addition to the system, product, or device that includes the series of units shown in the embodiments of this application.

[0037] Figure 1 is a schematic diagram of a display panel provided in an embodiment of this application. Figure 2 is a circuit element diagram of a driving circuit provided in an embodiment of this application. Figure 3 is a circuit element diagram of another driving circuit provided in an embodiment of this application. Figure 4 is a circuit element diagram of another driving circuit provided in an embodiment of this application. Figure 5 is a circuit element diagram of another driving circuit provided in an embodiment of this application. Figure 6 is a cross-sectional view along section line A-A' in Figure 1. Figure 7 is a circuit element diagram of a peripheral driving circuit provided in an embodiment of this application. Figure 8 is a cross-sectional view along section line B-B' in Figure 1. Referring to Figures 1 to 8, an embodiment of this application provides a display panel 10, which includes a substrate 100 and a driving array 20 disposed on one side of the substrate 100. The driving array includes transistors 210. The display panel 10 also includes a shielding structure 300 disposed on the side of the substrate 100 near the driving array 20. The shielding structure 300 includes at least one shielding substructure 310, and the shielding substructure 310 at least partially overlaps with the channel region of the transistor 210. The shielding substructure 310 is connected to a potential signal terminal B.

[0038] The display panel 10 includes a driving circuit 200 disposed on one side of the substrate 100. Referring to FIG1, the driving array 20 in the figure can be the driving circuit 200 or the peripheral driving circuit 710 in the peripheral circuit group 700. The driving circuit 200 is electrically connected to the light-emitting element 400 and is used to drive the light-emitting element 400 to emit light for display. The peripheral driving circuit 710 transmits control signals (such as scanning signals and light emission control signals) to the driving circuit 200, thereby ensuring that the driving circuit 200 provides driving current to the light-emitting element 400, and thus ensuring the display effect of the display panel 10.

[0039] The driving array 20 includes transistors 210. For example, referring to Figures 2 to 6, when the driving array 20 is a driving circuit 200, the arrangement of the driving circuit 200 is diverse, and the driving circuit 200 includes at least one transistor 210. Referring to Figures 7 and 8, when the driving array 20 is a peripheral driving circuit 710, the arrangement of the peripheral driving circuit 710 is also diverse, and the peripheral driving circuit 710 includes at least one first transistor 230. The number and type of transistors 210 in the driving circuit 200 and the first transistors 230 in the peripheral driving circuit 710 can be adaptively adjusted according to actual needs, and this application embodiment does not limit this.

[0040] Referring to Figures 6 and 8, the display panel 10 includes a substrate 100 and multiple alternating active layers, insulating layers, and metal layers on one side of the substrate 100, and includes a driving circuit 200 in the active layers, insulating layers, and metal layers. For example, the multiple insulating layers on one side of the substrate 100 may include a buffer layer 110, a first gate insulating layer 120, a first interlayer insulating layer 130, a second interlayer insulating layer 140, and a third interlayer insulating layer 150, etc. The number and type of insulating layers can be adaptively adjusted according to the actual display panel 10. The transistor 210 in the driving array 20 may include substructures, such as an active layer 201, a gate 202, a capacitor layer 203, a source 204, and a drain 205. The structure of the first transistor 230 in the peripheral driving circuit 710 is similar to that of the transistor 210. For example, the first transistor 230 may include an active layer 231, a gate 232, a source 233, and a drain 234. The film structure of the transistor 210 can be adaptively adjusted according to the actual situation.

[0041] Referring to Figures 6 and 8, the display panel also includes a shielding structure 300, which is disposed on the side of the substrate 100 near the driving array 20. The shielding structure 300 includes a shielding substructure 310, which at least partially overlaps with the channel region of the transistor 210, i.e., the opposite region of the active layer 201 and the gate 202. Simultaneously, the shielding substructure 310 can connect to some potential signals, i.e., it is electrically connected to some potential signal terminals B, achieving an electronic shielding effect. This effectively prevents ions from the substrate 100 side from entering the active layer 201 of the transistor 210, thereby avoiding interference with the operation of the channel region, ensuring the operational stability of the transistor 210, ensuring the operational stability of the driving array 20, and helping to improve issues such as image retention in the display panel 10, thus ensuring the display effect of the display panel 10.

[0042] In summary, this application provides a display panel in which a shielding substructure at least partially overlaps with the channel region of a transistor, and the shielding substructure is connected to a potential signal terminal, which can provide a potential signal to the shielding substructure. The shielding substructure connected to the potential acts as a shielding layer, effectively reducing the impact on the corresponding transistor under different operating environments, such as threshold drift. Therefore, it effectively ensures the stability of transistor operation, thereby guaranteeing the display effect of the display panel.

[0043] Figure 9 is a schematic diagram of another display panel structure provided in an embodiment of this application. Figure 10 is a schematic diagram of a film layer structure of a peripheral driving circuit provided in an embodiment of this application. Figure 11 is a schematic diagram of a part of the structure in Figure 10. Figure 12 is a schematic diagram of another part of the structure in Figure 10. Referring to Figures 1 to 12, the display panel 10 includes a display area 100A and non-display areas 100B located on both sides of the display area 100A. The driving array 20 includes a driving circuit 200 located in the display area 100A and a peripheral circuit group 700 located in the non-display area 100B. The peripheral circuit group 700 includes a plurality of peripheral driving circuits 710 arranged and cascaded along the first direction X. The peripheral driving circuit 710 includes a plurality of first transistors 230. The shielding substructure 310 includes a plurality of peripheral shielding substructures 330. The peripheral shielding substructures 330 and the channel regions of the first transistors 230 overlap at least partially. The first direction X is parallel to the plane where the substrate 100 is located.

[0044] Referring to Figure 1, the display area 100A of the display panel 10 is configured to house light-emitting elements 400 and driving circuits 200, primarily to realize the display function of the display panel 10. A peripheral driving circuit 710 and some wiring can be arranged around the non-display area 100B of the display area 100A. The peripheral driving circuit 710 transmits control signals to the driving circuit 200, thereby ensuring that the driving circuit 200 drives the light-emitting elements 400 and guarantees the display effect of the display panel 10. Referring to Figure 1, the display panel 10 has a peripheral circuit group 700 in the non-display area 100B. The peripheral circuit group 700 includes multiple cascaded peripheral driving circuits 710, and these multiple cascaded peripheral driving circuits 710 are arranged along a first direction X.

[0045] The drive circuit 200 can be configured in various ways. Referring to Figures 2 and 3, the drive circuit 200 can be illustrated as a "7T1C" configuration, and referring to Figures 4 and 5, the drive circuit 200 can be illustrated as an "8T1C" configuration. Here, "T" represents the transistor in the drive circuit 200, and "C" represents the capacitor. Based on the configuration of the drive circuit 200, those skilled in the art can make adaptive adjustments according to their needs.

[0046] The transistors 210 in the driving circuit 200 can be of the type of low-temperature polycrystalline silicon (LTPS) transistors, which have advantages such as high switching speed, high carrier mobility, and low power consumption. Referring to Figure 2, all transistors 210 in the driving circuit 200 are low-temperature polycrystalline silicon transistors. The transistors 210 can also be oxide transistors, such as indium gallium zinc oxide (IGZO) transistors, which have advantages such as low production cost and low power consumption. Referring to Figures 3 to 5, when the driving circuit 200 includes both low-temperature polycrystalline silicon transistors and oxide transistors, that is, combining LTPS transistors with IGZO transistors, the display panel 10 including the driving circuit 200 is a low-temperature polycrystalline oxide (LTPO) display panel. LTPO display panels not only possess the advantages of LTPS display panels such as high resolution, high response speed, high brightness, and high aperture ratio, but also the advantages of IGZO display panels such as low production cost and low power consumption.

[0047] Referring to Figure 2, this embodiment of the application uses a driving circuit 200 including "7T1C" as an example for illustration. The driving circuit 200 includes: a light-emitting control transistor M1, a data writing transistor M2, a driving transistor M3, a threshold compensation transistor M4, an initialization transistor M5, a second light-emitting control transistor M6, a reset transistor M7, and a storage capacitor Cst. The first scan signal SCAN1 controls the on / off state of the initialization transistor M5 of the driving circuit 200, and resets the gate potential of the driving transistor M3 when the initialization transistor M5 is on. Specifically, the first reset signal Vref1 is transmitted to the initialization transistor M5, resetting the connection node (first node N1) of the driving transistor M3, the initialization transistor M5, the threshold compensation transistor M4, and the storage capacitor Cst. The second scan signal SCAN2 controls the on / off state of the data writing transistor M2 of the driving circuit, and writes the data signal Vdata on the data signal line to the gate of the driving transistor M3 when the data writing transistor M2 is on. The second scan signal SCAN2 controls the on and off of the threshold compensation transistor M4, and compensates the threshold voltage of the driving transistor M3 when the threshold compensation transistor M4 is on. Simultaneously, the first scan signal SCAN1 controls the on and off of the reset transistor M7, and resets the anode of the light-emitting element 400 connected to the pixel circuit 300 when the reset transistor M7 is on, i.e., transmitting the second reset signal Vref2 to the anode of the light-emitting element 400. The light-emitting control signal Emit controls the on and off of the light-emitting control transistor M1 and the second light-emitting control transistor M6, and transmits the first power supply signal PVDD to the light-emitting element 400 when the light-emitting control transistors M1 and M6 are on, thereby realizing the display and light emission of the light-emitting element 400. Exemplarily, the light-emitting element 400 can be an organic light-emitting diode (OLED), Mini LED, Micro LED, or quantum dot light-emitting diode (QLED), etc. This application embodiment does not limit the type of light-emitting element 400. The light-emitting element 400 may include a red light-emitting element, a green light-emitting element, and a blue light-emitting element. The light-emitting elements 400 of different colors may have a variety of different arrangements, such as diamond pixel arrangement, standard RGB arrangement, triangle pixel arrangement, pearl pixel arrangement, or 2-in-1 pixel arrangement, etc. The embodiments of this application do not limit the arrangement of the light-emitting elements 400 of different colors.

[0048] Referring to Figures 4 and 5, the driving circuit 200 includes: a light-emitting control transistor M1, a data writing transistor M2, a driving transistor M3, a threshold compensation transistor M4, an initialization transistor M5, a second light-emitting control transistor M6, a reset transistor M7, a bias transistor M8, and a storage capacitor Cst. The operation of the driving circuit 200 is similar to the process described above and will not be repeated here. The control terminal of the bias transistor M8 is connected to a scan signal (shown as Sp* in the figure), which can control the conduction and turn-off of the bias transistor M8. When the bias transistor M8 is on, a reset signal (shown as DVH in the figure) is written to the bias transistor M8, and the bias of the second node N2 is adjusted. The initialization transistor M5 in Figures 4 and 5 is of a different type.

[0049] Referring to Figures 2 and 6, the shielding substructure 310 at least partially overlaps with the channel region of the transistor 210 in the driving circuit 200. Simultaneously, the shielding substructure 310 can connect to some potential signals, i.e., it is electrically connected to some potential signal terminals B, achieving an electronic shielding effect. This effectively prevents ions from the substrate 100 side from entering the active layer 201 of the transistor 210, thus avoiding interference with the operation of the channel region. This ensures the operational stability of the transistor 210 in the driving circuit 200, which helps improve issues such as image retention in the display panel 10 and guarantees the display effect of the display panel 10. If the active layer 201 of the transistor 210 is exposed to light, affecting its operational stability (e.g., when the transistor 210 is an IGZO transistor), the shielding structure 300 can also block light, preventing threshold drift in the transistor 210.

[0050] Different shielding substructures 310 can be set in the channel region of transistors 210 connected to different control signal terminals, and different shielding substructures 310 are connected to different potential signal terminals B (the different potential signal terminals are shown as B1 and B2 in Figure 6). Transistors 210 connected to different control signal terminals can operate in different states. Different operating modes can refer to the turn-on time, turn-off time, different signals input when the transistor 210 is turned on, etc., which can be limited according to the actual type of transistor 210. This embodiment of the application does not limit this. Based on the different operating modes of transistors 210, the shielding effect of the shielding structure 300 will also be different. That is, by connecting different shielding substructures 310 to different potential signal terminals, the operating stability of each transistor 210 is ensured, thereby ensuring the overall display effect of the display panel 10.

[0051] The peripheral driving circuit 710 transmits control signals (such as scan signals and light emission control signals) to the transistors 210 of the driving circuit 200 and adjusts the operating state of the transistors 210 through the control signals. As the types and uses of the transistors 210 in the driving circuit 200 vary, the control signals required by different transistors 210 in the driving circuit 200 will also be adjusted, meaning that the types of peripheral driving circuits 710 are also diverse. For example, referring to Figure 2, if the control signal input to the light emission control transistor M1 is the light emission control signal Emit, then there is a type of peripheral driving circuit 710 that outputs the light emission control signal Emit to the driving circuit 200; if the control signal input to the data writing transistor M2 is the second scan signal SCAN2, then there is a type of peripheral driving circuit 710 that outputs the second scan signal SCAN2 to the driving circuit 200. That is, different transistors 210 in the driving circuit 200 can have different operating processes, thus requiring different control signals, resulting in different types of peripheral driving circuits 710. When the types of transistors 210 in the driving circuit 200 are different, including low-temperature polysilicon transistors and oxide transistors, the enable levels for controlling these different types of transistors 210 are different. Therefore, different peripheral driving circuits 710 are required to provide different types of control signals to the different transistors 210. This demonstrates the diversity of the configuration of the peripheral driving circuits 710.

[0052] For example, the peripheral drive circuit 710 may be configured as "8T2C", "12T3C", or "15T4C", where "T" represents the first transistor 230 in the peripheral drive circuit 710 and "C" represents a capacitor. FIG7 illustrates "12T3C" as an example. Those skilled in the art can make adaptive adjustments based on the configuration of the peripheral drive circuit 710 according to their needs.

[0053] Referring to Figures 1, 7, and 8, the shielding substructure 310 also includes multiple peripheral shielding substructures 330. The transistors 210 in the driving array include the first transistors 230 in multiple peripheral driving circuits 710. The peripheral shielding substructures 330 and the channel regions of the first transistors 230 in the peripheral driving circuits 710 overlap at least partially. At the same time, the peripheral shielding substructures 330 can be connected to some potential signals, that is, electrically connected to some potential signal terminals B (shown as B3 in Figure 8), which plays an electronic shielding role. This effectively prevents ions from the substrate 100 side from entering the active layer 231 of the first transistor 230, that is, from affecting the operation of the channel region, thereby ensuring the working stability of the peripheral driving circuit 710. This is beneficial to ensuring the stability and reliability of the signal output by the peripheral driving circuit 710, thereby ensuring the driving effect of the driving circuit 200 on the light-emitting element 400, that is, ensuring the display effect of the display panel 10. The peripheral driving circuit 710 includes multiple first transistors 230, and the shielding substructure 310 also includes multiple peripheral shielding substructures 330. The channel region of each first transistor 230 can be correspondingly set with a peripheral shielding substructure 330, which overlaps with it. This can better ensure the working stability of the peripheral driving circuit 710 and further ensure the display effect of the display panel 10.

[0054] Referring to Figures 10 to 12, region C1 in Figure 10 shows a schematic diagram of the overall film layer of a peripheral driving circuit 710, and regions D1 in Figure 11 and E1 in Figure 12 show schematic diagrams of the partial film layer structure of the peripheral driving circuit 710 in region C1 of Figure 10. Specifically, region D1 in Figure 11 shows the active layer 231 of multiple first transistors 230, and region E1 in Figure 12 shows multiple peripheral shielding substructures 330. Similarly, region C2 in Figure 10 shows a schematic diagram of the overall film layer of another peripheral driving circuit 710, and regions D2 in Figure 11 and E2 in Figure 12 show schematic diagrams of the partial film layer structure of the peripheral driving circuit 710 in region C1 of Figure 10. Specifically, region D2 in Figure 11 shows the active layer 231 of multiple first transistors 230, and region E2 in Figure 12 shows multiple peripheral shielding substructures 330. As shown in Figures 10 to 12, the peripheral shielding substructure 300 is correspondingly arranged with the active layer 231. This ensures that the peripheral shielding substructure 330, acting as a barrier layer, effectively prevents ions from the substrate 100 side from entering the active layer 231 of the first transistor 230, thus avoiding interference with the channel region's operation. This ensures the stable and reliable control signal output by the peripheral driving circuit 710, thereby guaranteeing the operational stability of the driving circuit 200 and ensuring the display effect of the display panel 10. Figures 10 to 12 only show one structural schematic diagram. The arrangement of the peripheral driving circuit 710 in different display panels 10 varies, and will not be illustrated here.

[0055] Referring again to Figures 1, 7 to 12, in the same peripheral drive circuit 710, a plurality of peripheral shielding substructures 330 that at least partially overlap with the channel regions of a plurality of first transistors 230 are electrically connected.

[0056] Referring to Figures 1 and 7, the number of first transistors 230 in the peripheral drive circuit 710 varies. Figure 7 illustrates an example where the peripheral drive circuit 710 includes 12 first transistors 230.

[0057] Corresponding to the film structure of the peripheral driving circuit 710 shown in Figure 7, refer to region C1 in Figure 9. Referring to Figures 10 and 12, the same peripheral driving circuit 710 includes multiple peripheral shielding substructures 330, and these multiple peripheral shielding substructures 330 are electrically connected. By connecting the peripheral shielding substructures 330 to a potential signal, the peripheral shielding substructures 330 can act as a shielding layer, electrically shielding and protecting the first transistor 230, thereby ensuring the operational stability of the peripheral driving circuit 710. By electrically connecting multiple peripheral shielding substructures 330 that at least partially overlap with the channel regions of the multiple first transistors 230 in the same peripheral driving circuit 710, the potential signals connected to the peripheral shielding substructures 330 in the same peripheral driving circuit 710 are the same. This reduces the number of potential signal terminals B and simplifies the electrical connection method of the multiple peripheral shielding substructures 330, thereby reducing the manufacturing cost of the display panel 10 and improving the feasibility of the display panel 10 provided in this embodiment.

[0058] Figure 13 is a circuit element diagram of another peripheral driving circuit provided in an embodiment of this application. Figure 14 is another cross-sectional view along section line B-B' in Figure 1. Figure 15 is a film layer structure diagram of another peripheral driving circuit provided in an embodiment of this application. Figure 16 is a schematic diagram of a part of the structure in Figure 15. Figure 17 is a schematic diagram of another part of the structure in Figure 15. Referring to Figures 1, 13 to 17, the peripheral driving circuit 710 further includes at least one second transistor 240. The second transistor 240 includes an active layer 241, a bottom gate 242, and a top gate 243. The bottom gate 242 is located between the active layer 241 and the substrate 100, and the top gate 243 is located on the side of the active layer 241 away from the substrate 100. The bottom gate 242 and the top gate 243 are electrically connected in the same second transistor 240. The bottom gate 242 and the peripheral shielding substructure 330 are formed in the same layer, and the bottom gate 242 and the peripheral shielding substructure 330 are insulated from each other.

[0059] The peripheral driving circuit 710 may further include at least one second transistor 240. Referring to FIG14, the second transistor 240 includes an active layer 241, a bottom gate 242, a top gate 243, a source 244, and a drain 245. The bottom gate 242 is located between the active layer 241 and the substrate 100, and the top gate 243 is located on the side of the active layer 241 away from the substrate 100. It can be understood that the second transistor 240 is a top-bottom dual-gate transistor. Referring to FIG14, the bottom gate 242 and the top gate 243 in the same second transistor 240 are electrically connected, which can ensure the efficiency of the switching state adjustment of the second transistor 240.

[0060] Referring to Figure 14, the bottom gate 242 of the second transistor 240 can be disposed on the same layer as the peripheral shielding substructure 330. This reduces the number of film layers in the display panel 10, thereby facilitating a thinner design for the display panel 10 and reducing the manufacturing cost of the display panel 10. Since the bottom gate 242 is electrically connected to the top gate 243, the signals transmitted in the bottom gate 242 and the top gate 243 are the same. The peripheral shielding substructure 330 is electrically connected to the potential signal terminal B. Although the bottom gate 242 and the peripheral shielding substructure 330 are disposed on the same layer, their insulation relationship must be maintained to ensure stable signal transmission in the peripheral driving circuit 710 and to guarantee the overall display effect of the display panel 10.

[0061] Referring to Figures 15 to 17, region F in Figure 15 shows a schematic diagram of the overall film layer of a peripheral driving circuit 710, and regions G in Figure 16 and H in Figure 17 show schematic diagrams of the partial film layer structure of the peripheral driving circuit 710 in region F of Figure 9. Specifically, region G in Figure 15 shows the active layer 231 of multiple first transistors 230, and region H in Figure 17 shows multiple peripheral shielding substructures 330. Referring to Figure 17, region E2 in Figure 12 shows multiple peripheral shielding substructures 330. As shown in Figures 10 to 12, the bottom gate 242 and the peripheral shielding substructure 330 are arranged in the same layer. This reduces the number of film layers in the display panel 10, which facilitates the thinning design of the display panel 10 and reduces the manufacturing cost of the display panel 10. Furthermore, the peripheral shielding substructure 330 also acts as a barrier layer to effectively prevent ions from the substrate 100 side from entering the active layer 231 of the first transistor 230, thus avoiding interference with the channel region and ensuring the stable and reliable control signal output by the peripheral driving circuit 710. This, in turn, ensures the operational stability of the driving circuit 200 and guarantees the display effect of the display panel 10. Figures 15 to 17 only show one structural schematic diagram. The arrangement of the peripheral driving circuit 710 in different display panels 10 varies, and will not be illustrated here.

[0062] Figure 18 is a circuit element diagram of another peripheral driving circuit provided in an embodiment of this application; Figure 19 is another cross-sectional view along section line B-B' in Figure 1. Referring to Figures 1, 3, 9, 13, 18 and 19, the peripheral driving circuit 710 includes a first scanning driving circuit 710b and a second scanning driving circuit 710c. The transistors 210 in the driving array 20 include a first scanning transistor 251 and a second scanning transistor 252 in the driving circuit 200. The first scanning driving circuit 710b is connected to the control terminal of the first scanning transistor 251 through a first scanning signal line s1, and the second scanning driving circuit 710c is connected to the control terminal of the second scanning transistor 252 through a second scanning signal line s2. The peripheral shielding substructure 330 includes a first peripheral shielding substructure 330a corresponding to the first scanning driving circuit 710b and a second peripheral shielding substructure 330b corresponding to the second scanning driving circuit 710c. The first peripheral shielding substructure 330a and the second peripheral shielding substructure 330b are connected to different potential signal terminals B.

[0063] The transistors 210 in the driving circuit 200 may include a first scanning transistor 251 and a second scanning transistor 252. The difference between the first scanning transistor 251 and the second scanning transistor 252 may be a difference in transistor type; for example, the first scanning transistor 251 may be an oxide transistor, and the second scanning transistor 252 may be a low-temperature polysilicon transistor. For example, referring to Figures 3 and 9, the first scanning transistor 251 may be a threshold compensation transistor M4 and / or an initialization transistor M5, etc., and the second scanning transistor 252 may be a data writing transistor M2, etc. Based on the configuration of the first scanning transistor 251 and the second scanning transistor 252, adaptive adjustments can be made according to different driving circuits 200. This embodiment does not limit this. In this embodiment, the first scanning signal line s1 refers to the scan line configured to electrically connect the first scanning driving circuit 710b and the first scanning transistor 251, and the second scanning signal line s2 refers to the scan line configured to electrically connect the second scanning driving circuit 710c and the second scanning transistor 252.

[0064] The display panel 10 includes multiple peripheral driving circuits 710, and the control signals output by different peripheral driving circuits 710 may be different. The peripheral driving circuit 710 includes a first scanning driving circuit 710b and a second scanning driving circuit 710c. The first scanning driving circuit 710b transmits the output control signal to the first scanning transistor 251, and the second scanning driving circuit 710c transmits the output control signal to the second scanning transistor 252, thereby ensuring that the peripheral driving circuit 710 controls the driving circuit 200 and drives the light-emitting element 400, ensuring the display effect of the display panel 10.

[0065] For example, as shown in Figures 3, 9, 13, 18 and 19, the first scan drive circuit 710b is connected to the control terminal of the first scan transistor 251 (for example, the initialization transistor M5 in Figure 3) via the first scan signal line s1 (for example, the signal line corresponding to SCAN1 in Figure 3), and the second scan drive circuit 710c is connected to the control terminal of the second scan transistor 252 (for example, the data writing transistor M2 in Figure 3) via the second scan signal line s2 (for example, Sp in Figure 3).

[0066] The peripheral shielding substructure 330 may include a first peripheral shielding substructure 330a and a second peripheral shielding substructure 330b. The first peripheral shielding substructure 330a overlaps with the channel region of the transistor in the first scan driving circuit 710b, and the second peripheral shielding substructure 330b overlaps with the channel region of the transistor in the second scan driving circuit 710c. For example, referring to FIG19, cross-sectional views of the first scan driving circuit 710b and the second scan driving circuit 710c are placed in one figure for easy observation.

[0067] Referring to Figure 19, the first peripheral shielding substructure 330a and the second peripheral shielding substructure 330b are respectively placed in different peripheral driving circuits 710, allowing the connection of the first peripheral shielding substructure 330a and the second peripheral shielding substructure 330b to different potential signal terminals (the different potential signal terminals are shown as B4 and B5 in Figure 19). The control signals output by different peripheral driving circuits 710 differ, thus limiting the type of peripheral driving circuit 710 based on actual conditions. In general, by differentiating the potential signals connected to the peripheral shielding substructure 330 in the peripheral driving circuit 710 according to the differences in the peripheral driving circuits 710, the reliability and stability of the signals output by the peripheral driving circuit 710 can be better guaranteed, thereby ensuring the overall display effect of the display panel 10.

[0068] In the same peripheral driving circuit 710, there are multiple first transistors 230, and multiple peripheral shielding substructures 330 overlap with the channel regions of the first transistors 230. As mentioned above, for multiple different peripheral driving circuits 710, the potential signals connected to the peripheral shielding substructures 330 in different peripheral driving circuits 710 may differ. Therefore, it can also be considered that in the same peripheral driving circuit 710, different peripheral shielding substructures 330 corresponding to the channel regions of different first transistors 230 can also connect to different potential signals, further ensuring the reliability and stability of the signal output by the driving circuit 710.

[0069] Referring again to Figures 1, 3, 9, 13, 18 and 20, the first scanning transistor 251 includes an initialization transistor M5, and the second scanning transistor 252 includes a data writing transistor M2; the potential signal of the second peripheral shielding substructure 330b is greater than the potential signal of the first peripheral shielding substructure 330a.

[0070] Referring to Figure 3, in the driving circuit 200, the first scanning transistor 251 can be an initialization transistor M5, and the second scanning transistor 252 can be a data writing transistor M2. Based on the difference between the first scanning transistor 251 and the second scanning transistor 252 in the driving circuit 200, the potential signal of the corresponding peripheral shielding substructure 330 in the peripheral driving circuit 710 can be adjusted accordingly. The channel regions of the transistors in the first peripheral shielding substructure 330a and the first scanning driving circuit 710b overlap, and the channel regions of the transistors in the second peripheral shielding substructure 330b and the second scanning driving circuit 710c overlap. The potential signal of the second peripheral shielding substructure 330b can be adjusted to be greater than the potential signal of the first peripheral shielding substructure 330a, thereby ensuring that the peripheral driving circuit 710 of the entire display panel 10 can output stable control signals and ensure the display effect of the display panel 10.

[0071] Figure 20 is another cross-sectional view along section line B-B' in Figure 1. Referring to Figures 1, 3, 7, 9, 18, and 20, the peripheral driving circuit includes a second scanning driving circuit 710c and a light-emitting control driving circuit 710a. The driving circuit 200 includes a second scanning transistor 252 and a light-emitting control transistor 253. The second scanning driving circuit 710c is connected to the control terminal of the second scanning transistor 252 through the second scanning signal line s2, and the light-emitting control driving circuit 710a is connected to the control terminal of the light-emitting control transistor 253 through the signal line that transmits the light-emitting control signal Emit. The peripheral shielding substructure 330 includes a second peripheral shielding substructure 330b corresponding to the second scanning driving circuit 710c and a third peripheral shielding substructure 330c corresponding to the light-emitting control driving circuit 710a. The second peripheral shielding substructure 330b and the third peripheral shielding substructure 330c are connected to different potential signal terminals B.

[0072] The driving circuit 200 may include a second scanning transistor 252 and a light-emitting control transistor 253. The difference between the second scanning transistor 252 and the light-emitting control transistor 253 may lie in their operating processes. For example, the second scanning transistor 252 operates during the data writing phase of the driving circuit 200, while the light-emitting control transistor 253 operates during the light-emitting control phase. For instance, referring to Figure 3, the second scanning transistor 252 may be a data writing transistor M2, etc., and the light-emitting control transistor 253 may be a light-emitting control transistor M1 and / or a second light-emitting control transistor M6. Based on the configuration of the light-emitting control transistor 253 and the second scanning transistor 252, adaptive adjustments can be made according to different driving circuits 200. This embodiment does not limit this.

[0073] The display panel 10 includes multiple peripheral driving circuits 710, and the control signals output by different peripheral driving circuits 710 may be different. Each peripheral driving circuit 710 includes a second scanning driving circuit 710c and a light-emitting control driving circuit 710a. The second scanning driving circuit 710c transmits its output control signal to a second scanning transistor 252, and the light-emitting control driving circuit 710a transmits its output control signal to a light-emitting control transistor 253. This ensures that the peripheral driving circuit 710 controls the driving circuit 200 and drives the light-emitting element 400, thus guaranteeing the display effect of the display panel 10.

[0074] For example, as shown in Figures 3, 7, 9, 18, and 20, the second scan drive circuit 710c is connected to the control terminal of the second scan transistor 252 (shown as an example of the data write transistor M2 in Figure 3) via the second scan signal line s2 (shown as an example of Sp in Figure 3). The light emission control drive circuit 710a is connected to the control terminal of the light emission control transistor 253 (shown as an example of the light emission control transistor M1 in Figure 3) via the signal line that transmits the light emission control signal Emit (shown as an example of the signal line corresponding to Emit in Figure 3).

[0075] The peripheral shielding substructure 330 may include a second peripheral shielding substructure 330b and a third peripheral shielding substructure 330c. The second peripheral shielding substructure 330b overlaps with the channel region of the transistor in the second scan driving circuit 710c, and the third peripheral shielding substructure 330c overlaps with the channel region of the transistor in the light emission control driving circuit 710a. For example, referring to FIG20, cross-sectional views of the second scan driving circuit 710c and the third scan driving circuit 710a are placed in one figure for easy observation.

[0076] Referring to Figure 20, the second peripheral shielding substructure 330b and the third peripheral shielding substructure 330c are respectively placed in different peripheral driving circuits 710. Therefore, the second peripheral shielding substructure 330b and the third peripheral shielding substructure 330c can be connected to different potential signal terminals (the different potential signal terminals in Figure 20 are shown as B5 and B6). The control signals output by different peripheral driving circuits 710 differ, and are limited according to the actual type of peripheral driving circuit 710. In general, by differentiating the potential signals connected to the peripheral shielding substructure 330 in the peripheral driving circuit 710 according to the differences in the peripheral driving circuit 710, the reliability and stability of the signals output by the peripheral driving circuit 710 can be better guaranteed, thereby ensuring the overall display effect of the display panel 10.

[0077] Referring again to Figures 1, 3, 7, 9, 18 and 20, the second scanning transistor 252 includes a data writing transistor M2; the potential signal of the third peripheral shielding substructure 330c is greater than the potential signal of the second peripheral shielding substructure 330b.

[0078] Referring to Figure 3, in the driving circuit 200, the second scanning transistor 252 can be a data writing transistor M2, and the light-emitting control transistor 253 can be a light-emitting control transistor M1. Based on the difference between the second scanning transistor 252 and the light-emitting control transistor 253 in the driving circuit 200, the potential signal of the corresponding peripheral shielding substructure 330 in the peripheral driving circuit 710 can be adjusted accordingly. The channel regions of the transistors in the second peripheral shielding substructure 330b and the second scanning driving circuit 710c overlap, and the channel regions of the transistors in the third peripheral shielding substructure 330c and the light-emitting control driving circuit 710a overlap. The potential signal of the third peripheral shielding substructure 330c can be adjusted to be greater than the potential signal of the second peripheral shielding substructure 330b, thereby ensuring that the peripheral driving circuit 710 of the entire display panel 10 can output stable control signals and ensure the display effect of the display panel 10.

[0079] Figure 21 is another cross-sectional view along section line C-C' in Figure 9. Referring to Figures 1, 3, 7, 9 to 18 and 21, the peripheral driving circuit 710 further includes a first scanning driving circuit 710b, and the driving circuit 200 further includes a first scanning transistor 251. The first scanning driving circuit 710b is connected to the control terminal of the first scanning transistor 251 through a first scanning signal line s1. The peripheral shielding substructure 330 further includes a first peripheral shielding substructure 330a corresponding to the first scanning driving circuit 710b. The first peripheral shielding substructure 330a and the third peripheral shielding substructure 330c are connected to different potential signals.

[0080] The driving circuit 200 may include a first scanning transistor 251, a second scanning transistor 252 and a light-emitting control transistor 253, and the corresponding peripheral driving circuit 710 may include a first scanning driving circuit 710b, a second scanning driving circuit 710c and a light-emitting control driving circuit 710a.

[0081] The peripheral shielding substructure 330 may include a first peripheral shielding substructure 330a, a second peripheral shielding substructure 330b, and a third peripheral shielding substructure 330c. The first peripheral shielding substructure 330a overlaps with the channel region of the transistor in the first scan driving circuit 710b, the second peripheral shielding substructure 330b overlaps with the channel region of the transistor in the second scan driving circuit 710c, and the third peripheral shielding substructure 330c overlaps with the channel region of the transistor in the light emission control driving circuit 710a. For example, referring to FIG21, cross-sectional views of the first scan driving circuit 710b, the second scan driving circuit 710c, and the third scan driving circuit 710a are placed in one figure for easy observation. Furthermore, in conjunction with FIGS. 10 to 12 or FIGS. 15 to 17, the film structure illustrates three different peripheral driving circuits 710.

[0082] Referring to Figure 21, the first peripheral shielding substructure 330a, the second peripheral shielding substructure 330b, and the third peripheral shielding substructure 330c are respectively placed in different peripheral driving circuits 710. Therefore, the connections of the first peripheral shielding substructure 330a, the second peripheral shielding substructure 330b, and the third peripheral shielding substructure 330c to different potential signal terminals can be adjusted (the different potential signal terminals in Figure 21 are shown as B4, B5, and B6). The control signals output by different peripheral driving circuits 710 differ, and are limited according to the actual type of peripheral driving circuit 710. In general, by differentiating the potential signals connected to the peripheral shielding substructure 330 in the peripheral driving circuit 710 based on the differences in the peripheral driving circuit 710, the reliability and stability of the signals output by the peripheral driving circuit 710 can be better guaranteed, thereby ensuring the overall display effect of the display panel 10.

[0083] Referring again to Figures 1, 3, 8 to 18 and 21, the potential signal of the second peripheral shielding substructure 330b is greater than or equal to the potential signal of the first peripheral shielding substructure 330a.

[0084] Referring to Figure 3, in the driving circuit 200, the first scanning transistor 251 can be an initialization transistor M5, the second scanning transistor 252 can be a data writing transistor M2, and the light-emitting control transistor 253 can be a light-emitting control transistor M1. Based on the differences between the first scanning transistor 251, the second scanning transistor 252, and the light-emitting control transistor 253 in the driving circuit 200, the potential signal magnitude of the corresponding peripheral shielding substructure 330 in the peripheral driving circuit 710 can be adjusted accordingly. The first peripheral shielding substructure 330a overlaps with the channel region of the transistor in the first scanning drive circuit 710b, the second peripheral shielding substructure 330b overlaps with the channel region of the transistor in the second scanning drive circuit 710c, and the third peripheral shielding substructure 330c overlaps with the channel region of the transistor in the light emission control drive circuit 710a. The potential signal of the third peripheral shielding substructure 330c can be adjusted to be greater than the potential signal of the second peripheral shielding substructure 330b. At the same time, the potential signal of the second peripheral shielding substructure 330b is greater than or equal to the potential signal of the first peripheral shielding substructure 330a. This ensures that the peripheral drive circuit 710 of the entire display panel 10 can output stable control signals, thus ensuring the display effect of the display panel 10.

[0085] Figure 22 is a schematic diagram of another display panel structure provided in an embodiment of this application. Referring to Figures 3, 18 and 22, the non-display area 100B includes a first non-display area 100B1 and a second non-display area 100B2 located on opposite sides of the display area 100A; the peripheral circuit group 700 also includes two second scan driving circuit groups 720, one second scan driving circuit group 720 located in the first non-display area 100B1 and the other second scan driving circuit group 720 located in the second non-display area 100B2, each second scan driving circuit group 720 including a plurality of second scan driving circuits 710c arranged and cascaded along the first direction X; the driving circuit 200 includes a second scan transistor 252, the second scan driving circuit 710c is connected to the control terminal of the second scan transistor 252 through a second scan signal line s2, and one end of the second scan signal line s2 is connected to the second scan driving circuit 710c located in the first non-display area 100B1, and the other end is connected to the second scan driving circuit 710c located in the second non-display area 100B2.

[0086] Referring to Figure 22, the display panel 10 includes a first non-display area 100B1 and a second non-display area 100B2 in the non-display area 100B, and the first non-display area 100B1 and the second non-display area 100B2 are located on both sides of the display area 100A.

[0087] The peripheral circuit group 700 may include a second scan driving circuit 720, which includes a plurality of second scan driving circuits 710c arranged and cascaded along the first direction X. Referring to FIG22, the peripheral circuit group 700 may include two second scan driving circuits 720, and the two second scan driving circuits 720 are respectively located in the first non-display area 100B1 and the second non-display area 100B2. It can be understood that the second scan driving circuit 710c is a peripheral driving circuit with dual-sided driving, which ensures the driving effect of the second scan driving circuit 710c and the display effect of the display panel 10.

[0088] The driving circuit 200 in the display area 100A includes a second scanning transistor 252. The second scanning driving circuit 710c located in the first non-display area 100B1 can be connected to the control terminal of the second scanning transistor 252 through the second scanning signal line s2. At the same time, the second scanning driving circuit 710c located in the second non-display area 100B2 can also be connected to the control terminal of the second scanning transistor 252 through the second scanning signal line s2, thereby ensuring a more stable driving effect on the driving circuit 200.

[0089] Figure 23 is a cross-sectional view along section line I-I' in Figure 22, and Figure 24 is a cross-sectional view along section line K-K' in Figure 22. Referring to Figures 22 to 24, the peripheral shielding substructure 330 includes a second peripheral shielding substructure 330b corresponding to the second scanning drive circuit 710c; the second peripheral shielding substructure 330b located in the first non-display area 100B1 and the second peripheral shielding substructure 330b located in the second non-display area 100B2 are connected to different potential signal terminals.

[0090] Referring to Figures 22 to 24, the second scanning drive circuit 710c exists in the first non-display area 100B1 and the second non-display area 100B2, while the peripheral shielding substructure 330 includes a second peripheral shielding substructure 330b corresponding to the second scanning drive circuit 710c. That is, the second peripheral shielding substructure 330b is correspondingly provided in each of the second scanning drive circuits 710c located in the first non-display area 100B1 and the second non-display area 100B2. This ensures the driving stability of the second scanning drive circuit 710c at each location and guarantees the display effect of the display panel 10.

[0091] The second scanning drive circuits 710c located in the first non-display area 100B1 and the second display area 100B2 may differ, for example, in their setting positions or in their total number. This embodiment does not limit the specific differences. The second peripheral shielding substructure 330b located in the first non-display area 100B1 and the second peripheral shielding substructure 330b located in the second non-display area 100B2 can be connected to different potential signal terminals (refer to B5' in Figure 23 and B5" in Figure 24). This allows for adaptive adjustment of the corresponding second peripheral shielding substructure 330b to different potential signals based on the differentiated settings of the different third scanning drive circuits 710b, thereby better ensuring the driving effect of the peripheral drive circuit 710 and guaranteeing the overall display effect of the display panel 10.

[0092] Figure 25 is a schematic diagram of another display panel structure provided in an embodiment of this application. Referring to Figure 25, the peripheral circuit group 700 further includes a first scan driving circuit group 730 located in the first non-display area 100B1. The first scan driving circuit group 730 includes a plurality of first scan driving circuits 710b arranged and cascaded along the first direction X. The driving circuit 200 includes a first scan transistor 251. The first scan driving circuit 710b is connected to the control terminal of the first scan transistor 251 through a first scan signal line s1. The potential signal of the second peripheral shielding substructure 330b located in the second non-display area 100B2 is greater than the potential signal of the second peripheral shielding substructure 330b located in the first non-display area 100B1.

[0093] The peripheral circuit group 700 may further include a first scan drive circuit group 730, which includes a plurality of first scan drive circuits 710b arranged and cascaded along the first direction X. Referring to FIG25, the first scan drive circuit group 730 may be located in the first non-display area 100B1, and can be understood as the first scan drive circuit 710b being a peripheral drive circuit with single-sided drive. Thus, referring to FIG25, the first non-display area 100B1 includes the first scan drive circuit group 730 and the second scan drive circuit group 720, while the second non-display area 100B2 only includes the second scan drive circuit group 720. Therefore, the arrangement of the peripheral drive circuits 710 differs in different non-display areas 100B of the display panel 10.

[0094] The driving circuit 200 in the display area 100A also includes a first scanning transistor 251. The first scanning driving circuit 710b located in the first non-display area 100B1 can be connected to the control terminal of the first scanning transistor 251 through the first scanning signal line s1, thereby driving the driving circuit 200.

[0095] Referring to Figure 25, since the first scanning drive circuit 710b is located only in the first non-display area 100B1, the driving effect of the first scanning drive circuit 710b on the drive circuit 200 in the display area 100A will gradually weaken as the load increases. The driving effect of the drive circuit 200 closer to the first scanning drive circuit 710b will be better than that of the drive circuit 200 farther away from the first scanning drive circuit 710b. Referring to Figure 25, the second scanning drive circuit 710c can exist simultaneously in the first non-display area 100B1 and the second non-display area 100B2, and the peripheral shielding substructure 330 includes a second peripheral shielding substructure 330b corresponding to the second scanning drive circuit 710c. That is, the second scanning drive circuit 710c located in both the first non-display area 100B1 and the second non-display area 100B2 is provided with a corresponding second peripheral shielding substructure 330b. In this way, the potential signal of the second peripheral shielding substructure 330b located in the second non-display area 100B2 can be adjusted to be greater than the potential signal of the second peripheral shielding substructure 330b located in the first non-display area 100B1, so as to ensure the overall driving effect of the peripheral driving circuit 710 on the driving circuit 200.

[0096] The first non-display area 100B1 includes a first scan drive circuit 710b, while the second non-display area 100B2 does not. Therefore, the driving effect of the first scan drive circuit 710b on the drive circuit 200 in the display area 100A gradually weakens with increasing load. Both the first non-display area 100B1 and the second non-display area 100B2 are equipped with second scan drive circuits 710c. Furthermore, the potential signal of the second peripheral shielding substructure 330b corresponding to the second scan drive circuit 710c in the second non-display area 100B2 is adjusted to be slightly larger, which compensates for the insufficient driving caused by the load problem of the first scan drive circuit 710b and improves the driving effect. This balances the overall driving effect of the peripheral drive circuit 710 on the drive circuit 200, ensuring the display effect of the display panel 10.

[0097] The positions of the first scan driving circuit 710b and the second scan driving circuit 710c in the first non-display area 100B1 of the display panel 10 can be adaptively adjusted, and this application embodiment does not limit this.

[0098] The potential signal connected to the peripheral shielding substructure 330 is V, where 0 < V ≤ 4.6V.

[0099] The potential signal connected to the peripheral shielding substructure 330 can be between 0 and 4.6V. For example, the potential signal can be 1V, 2V, 2.5V, 3V or 4V, etc. The potential signal connected to the peripheral shielding substructure 330 can be adaptively adjusted according to the actual situation.

[0100] Figure 26 is a schematic diagram of another display panel structure provided in an embodiment of this application. Referring to Figure 26, the non-display area 100B also includes a bonding area 100C. The bonding area 100C is located in the lower frame area of ​​the display panel 10. The bonding area 100C is provided with at least one potential signal terminal B. The peripheral shielding substructure 330 is connected to the potential signal terminal B through the first signal line 800.

[0101] Referring to Figure 26, the non-display area 100B also includes a bonding area 100C. The bonding area 100C is provided with at least one potential signal terminal B, which is configured to provide a potential signal. As shown in Figure 26, the potential signal terminal B of the bonding area 100C can transmit the potential signal to the peripheral shielding substructure 330 via the first signal line 800, thereby ensuring that the shielding substructure 330 has a potential signal. This serves as electrical signal shielding, ensuring the operational stability of the peripheral driving circuit 710 and guaranteeing the display effect of the display panel 10. The electrical connection method between the shielding substructure 330 and the potential signal terminal B can be diverse, meaning the configuration of the first signal line 800 can be varied.

[0102] Referring again to Figure 26, the peripheral circuit group 700 includes an i-th peripheral driving circuit 710(i) and a j-th peripheral driving circuit 710(j), with the i-th peripheral driving circuit 710(i) located on the side of the j-th peripheral driving circuit 710(j) near the bonding region 100C; the peripheral shielding substructure 330 includes an x-th peripheral shielding substructure 330(x) and a y-th peripheral shielding substructure 330(y), with the x-th peripheral shielding substructure 330(x) at least partially intersecting with the channel region of the first transistor 230 in the i-th peripheral driving circuit 710(i). The y-th peripheral shielding substructure 330(y) and the channel region of the first transistor 330 in the j-th peripheral driving circuit 710(j) overlap at least partially; the x-th peripheral shielding substructure 330(x) and the y-th peripheral shielding substructure 330(y) are respectively connected to the first signal line 800 through a converter line 900; wherein, the first signal line 800 extends along the first direction X, the converter line 900 extends along the second direction Y, the second direction Y intersects with the first direction X, and the first signal line 800 is located on the side of the peripheral driving circuit 710 away from the display area 100A.

[0103] Referring to Figure 26, a peripheral circuit group 700 may include a plurality of peripheral driving circuits 710 arranged and cascaded along a first direction X. As shown in Figure 26, the peripheral circuit group 700 includes an i-th peripheral driving circuit 710(i) and a j-th peripheral driving circuit 710(j), and the position of the i-th peripheral driving circuit 710(i) is closer to the bonding area 100C than the position of the j-th peripheral driving circuit 710(j).

[0104] The peripheral shielding substructure 330 includes an xth peripheral shielding substructure 330(x) that at least partially overlaps with the channel region of the first transistor 230 in the i-th peripheral driving circuit 710(i), and a yth peripheral shielding substructure 330(y) that at least partially overlaps with the channel region of the first transistor 330 in the j-th peripheral driving circuit 710(j). Based on the positional relationship between the i-th peripheral driving circuit 710(i) and the j-th peripheral driving circuit 710(j), it can be determined that the xth peripheral shielding substructure 330(x) is located on the side of the yth peripheral shielding substructure 330(y) closer to the bonding region 100C.

[0105] Referring to Figure 26, the display panel 10 includes a first signal line 800 extending along a first direction X. The first signal line 800 is electrically connected to a potential signal terminal B, meaning that the first signal line 800 transmits an electrical signal provided by the potential signal terminal B. If a potential signal provided by the potential signal terminal B needs to be connected to the peripheral shielding substructure 330, the peripheral shielding substructure 330 and the first signal line 800 are adjusted to maintain an electrical connection. Referring to Figure 26, the peripheral shielding substructure 330 is electrically connected to the first signal line 800 via a transition cable 900 extending along a second direction Y. Specifically, the xth peripheral shielding substructure 330(x) and the yth peripheral shielding substructure 330(y) are each connected to the first signal line 800 via two transition cables 900. This means that peripheral shielding substructures 330 located in different peripheral driving circuits 710 are electrically connected to the first signal line 800 via different transition cables 900. The electrical signal provided by the potential signal terminal B has a small voltage drop on the transmission path of the first signal line 800, which can ensure that the potential signals received by different peripheral shielding substructures 330 are the same or similar, thus ensuring the shielding effect of the peripheral shielding substructures 330, ensuring the working stability of the peripheral driving circuit 710, and thus ensuring the display effect of the display panel 10.

[0106] The peripheral driving circuit 710 may include a plurality of first transistors 230. Therefore, the area where the corresponding peripheral shielding substructure 330 is shown in Figure 26 for each peripheral driving circuit 710 can be understood as all the peripheral shielding substructures 330 corresponding to that peripheral driving circuit 710.

[0107] Figure 27 is a schematic diagram of another display panel structure provided in an embodiment of this application, and Figure 28 is a schematic diagram of another display panel structure provided in an embodiment of this application. Referring to Figures 27 and 28, the peripheral circuit group 700 includes the i-th peripheral driving circuit 710(i) and the j-th peripheral driving circuit 710(j), with the i-th peripheral driving circuit 710(i) located on the side of the j-th peripheral driving circuit 710(j) close to the bonding area 100C; the peripheral shielding substructure 330 includes the x-th peripheral shielding substructure 330(x) and the y-th peripheral shielding substructure 330(y), with the x-th peripheral shielding substructure 330(x) and the j-th peripheral driving circuit 710(j) close to the bonding area 100C; The channel regions of the first transistor 230 in the i peripheral driving circuits 710(i) at least partially overlap, and the yth peripheral shielding substructure 330(y) at least partially overlaps with the channel region of the first transistor 330 in the jth peripheral driving circuit 710(j); each peripheral shielding substructure 330 includes a main structure 331 and a substructure 332 connected to the main structure 331, each substructure 332 at least partially overlaps with the channel region of the first transistor 230, the xth peripheral shielding substructure 330(x) and the yth peripheral shielding substructure 330(y) are connected through the main structure 331 and connected to the first signal line 800 through the main structure 331.

[0108] Referring to Figures 27 and 28, the peripheral shielding substructure 330 includes a main structure 331 and a substructure 332. The substructure 332 at least partially overlaps with the channel region of the first transistor 230. Referring to Figures 27 and 28, the x-th peripheral shielding substructure 330(x) and the y-th peripheral shielding substructure 330(y) can be understood as the substructure 332 within the peripheral shielding substructure 330. The substructure 332 and the main structure 331 are electrically connected. As shown in Figures 27 and 28, the main structure 331 can be understood as a bridge connecting two adjacent substructures 332. Thus, in the peripheral circuit group 700, multiple peripheral driving circuits 710 are cascaded, and the peripheral shielding substructures 330 corresponding to the multiple peripheral driving circuits 710 are electrically connected. Based on this, if it is necessary to provide a potential signal to the peripheral shielding substructure 330, it can be provided only to the main structure 331 to ensure that the entire peripheral shielding substructure 330 has a potential signal, thereby achieving the shielding effect, ensuring the working stability of the peripheral driving circuit 710, and thus ensuring the display effect of the display panel 10.

[0109] Referring to Figure 27, the main structure 331 is electrically connected to the first signal line 800, and the first signal line 800 is electrically connected to the potential signal terminal B, thereby ensuring that the main structure 331 acquires a potential signal, and consequently, the entire peripheral shielding substructure 330 acquires a potential signal. This configuration eliminates the need for additional traces to maintain electrical connection with the first signal line 800 at multiple peripheral shielding substructures 330, reducing the space occupied by traces in the non-display area 100B. This facilitates the realization of a narrow-bezel display panel 10 and also saves on the manufacturing cost of the display panel 10.

[0110] Referring again to Figures 27 and 28, the first signal line 800 is located between the peripheral driving circuit 710 and the bonding area 100C; or, the first signal line 800 is located on the side of the peripheral driving circuit 710 away from the display area 100A and extends along the first direction X, and the main structure 331 is connected to the end of the first signal line 800 away from the bonding area 100C.

[0111] Referring to Figure 27, the first signal line 800 is located between the peripheral driving circuit 710 and the bonding area 100C. Specifically, the first signal line 800 is electrically connected to the peripheral shielding substructure 330 via the main structure 331 near the bonding area 100C. This reduces the extension length of the first trace 800, saving space occupied by the trace in the non-display area 100B, facilitating the narrow bezel design of the display panel 10, and reducing the manufacturing cost of the display panel 10. Alternatively, referring to Figure 28, the first signal line 800 is located on the side of the peripheral driving circuit 710 away from the display area 100A and extends along the first direction X. The main structure 331 is connected to the end of the first signal line 800 away from the bonding area 100C. This demonstrates the flexibility of the first signal line 800's routing, allowing for adaptive adjustments based on the needs of different display panels 10.

[0112] This application also provides a display device. FIG29 is a schematic diagram of the structure of a display device provided in this application embodiment. As shown in FIG29, the display device 1 includes the display panel 10 described in any of the above embodiments. Therefore, the display device 1 provided in this application embodiment has the corresponding beneficial effects in the above embodiments, which will not be repeated here. Exemplarily, the display device 1 can be an electronic device such as a mobile phone, computer, smart wearable device (e.g., smartwatch), and in-vehicle display device. This application embodiment does not limit this.

Claims

1. A display panel, comprising a substrate (100) and a driving array (20) disposed on one side of the substrate (100), the driving array (20) comprising a transistor (210); the display panel further comprising a shielding structure (300) disposed on the substrate (100) near the driving array (20), the shielding structure (300) comprising at least one shielding substructure (310), the shielding substructure (310) at least partially overlapping a channel region of the transistor (210); the shielding substructure (310) being connected to a potential signal terminal.

2. The display panel of claim 1, wherein, the display panel comprising a display area (100A) and a non-display area (100B) located on both sides of the display area (100A); the driving array (20) comprising a driving circuit (200) located in the display area (100A) and a peripheral circuit group (700) located in the non-display area (100B), the driving circuit (200) comprising at least one transistor (210); the peripheral circuit group (700) comprising a plurality of peripheral driving circuits (710) arranged in a first direction and cascaded, the peripheral driving circuit (710) comprising a plurality of first transistors (230); the shielding substructure (310) comprising a plurality of peripheral shielding substructures (330), the peripheral shielding substructure (330) at least partially overlapping a channel region of the first transistor (230); wherein the first direction is parallel to the plane in which the substrate (100) lies.

3. The display panel of claim 2, wherein, In the same peripheral driving circuit (710), the plurality of peripheral shielding substructures (330) at least partially overlapping the channel regions of the plurality of first transistors (230) of the same peripheral driving circuit (710) are electrically connected.

4. The display panel of claim 3, wherein, the peripheral driving circuit (710) further comprising at least one second transistor (240); the second transistor (240) comprising an active layer (241), a bottom gate (242) and a top gate (243); the bottom gate (242) being located between the active layer (241) and the substrate (100), the top gate (243) being located on the side of the active layer (241) away from the substrate (100), the bottom gate (242) and the top gate (243) in the same second transistor (240) being electrically connected; the bottom gate (242) and the peripheral shielding substructure (330) are formed in the same layer, and the bottom gate (242) and the peripheral shielding substructure (330) are insulated.

5. The display panel of claim 2, wherein, the peripheral driving circuit (710) comprising a first scan driving circuit (710b) and a second scan driving circuit (710c), the driving circuit comprising a first scan transistor (251) and a second scan transistor (252); the first scan driving circuit (710b) being connected to the control end of the first scan transistor (251) through a first scan signal line, the second scan driving circuit (710c) being connected to the control end of the second scan transistor (252) through a second scan signal line; The peripheral shielding sub-structure (330) comprises a first peripheral shielding sub-structure (330a) corresponding to the first scan driving circuit (710b) and a second peripheral shielding sub-structure (330b) corresponding to the second scan driving circuit (710c); The first peripheral shielding sub-structure (330a) and the second peripheral shielding sub-structure (330b) are connected to different potential signal terminals.

6. The display panel of claim 5, wherein, The first scan transistor (251) comprises an initialization transistor, and the second scan transistor (252) comprises a data writing transistor. The potential signal of the second peripheral shielding sub-structure (330b) is greater than the potential signal of the first peripheral shielding sub-structure (330a).

7. The display panel of claim 2, wherein, The peripheral driving circuit (710) comprises a second scan driving circuit (710c) and a light-emitting control driving circuit (710a), and the driving circuit comprises a second scan transistor (252) and a light-emitting control transistor (253); The second scan driving circuit (710c) is connected to the control end of the second scan transistor (252) through a second scan signal line, and the light-emitting control driving circuit (710a) is connected to the control end of the light-emitting control transistor (253) through a light-emitting control signal line; The peripheral shielding sub-structure (330) comprises a second peripheral shielding sub-structure (330b) corresponding to the second scan driving circuit (710c) and a third peripheral shielding sub-structure (330c) corresponding to the light-emitting control driving circuit (710a); The second peripheral shielding sub-structure (330b) and the third peripheral shielding sub-structure (330c) are connected to different potential signal terminals.

8. The display panel of claim 7, wherein, The second scan transistor (252) comprises a data writing transistor. The potential signal of the third peripheral shielding sub-structure (330c) is greater than the potential signal of the second peripheral shielding sub-structure (330b).

9. The display panel of claim 7 or 8, wherein, The peripheral driving circuit (710) further comprises a first scan driving circuit (710b), and the driving circuit (200) further comprises a first scan transistor (251); the first scan driving circuit (710b) is connected to the control end of the first scan transistor (251) through a first scan signal line; The peripheral shielding sub-structure (330) further comprises a first peripheral shielding sub-structure (330a) corresponding to the first scan driving circuit (710b); The first peripheral shielding sub-structure (330a) and the third peripheral shielding sub-structure (330c) are connected to different potential signal terminals.

10. The display panel of claim 9, wherein, The potential signal of the second peripheral shielding sub-structure (330b) is greater than or equal to the potential signal of the first peripheral shielding sub-structure (330a).

11. The display panel of claim 2, wherein, The non-display area (100B) comprises a first non-display area (100B1) and a second non-display area (100B2) located on opposite sides of the display area (100A); The peripheral circuit group (700) further includes two second scan driving circuit groups (720), one second scan driving circuit group (720) is located in the first non-display area (100B1), and the other second scan driving circuit group (720) is located in the second non-display area (100B2). Each second scan driving circuit group (720) includes a plurality of second scan driving circuits (710c) arranged and cascaded along the first direction. The driving circuit (200) includes a second scanning transistor (252). The second scanning driving circuit (710c) is connected to the control terminal of the second scanning transistor (252) through a second scanning signal line. One end of the second scanning signal line is connected to the second scanning driving circuit (710c) located in the first non-display area (100B1), and the other end is connected to the second scanning driving circuit (710c) located in the second non-display area (100B2).

12. The display panel of claim 11, wherein, The peripheral shielding substructure (330) includes a second peripheral shielding substructure (330b) corresponding to the second scanning drive circuit (710c); The second peripheral shielding substructure (330b) located in the first non-display area (100B1) and the second peripheral shielding substructure (330b) located in the second non-display area (100B2) are connected to different potential signal terminals.

13. The display panel of claim 12, wherein, The peripheral circuit group (700) further includes a first scan driving circuit group (730) located in the first non-display area (100B1), the first scan driving circuit group (730) including a plurality of first scan driving circuits (710b) arranged and cascaded along the first direction; The driving circuit (200) includes a first scanning transistor (251), and the first scanning driving circuit (710b) is connected to the control terminal of the first scanning transistor (251) through a first scanning signal line; The potential signal of the second peripheral shielding substructure (330b) located in the second non-display area (100B2) is greater than the potential signal of the second peripheral shielding substructure (330b) located in the first non-display area (100B1).

14. The display panel of claim 2, wherein, The potential signal connected to the peripheral shielding substructure (330) is V. Where 0 < V ≤ 4.6v.

15. The display panel according to claim 2, wherein, The non-display area (100B) also includes a bonding area (100C), which is located in the lower border area of ​​the display panel and is provided with at least one potential signal terminal. The peripheral shielding substructure (330) is connected to the potential signal terminal via a first signal line (800).

16. The display panel of claim 15, wherein, The peripheral circuit group (700) includes an i-th peripheral driving circuit and a j-th peripheral driving circuit, wherein the i-th peripheral driving circuit is located on the side of the j-th peripheral driving circuit that is closer to the bonding area (100C). The peripheral shielding sub-structure (330) comprises an xth peripheral shielding sub-structure and a yth peripheral shielding sub-structure, the xth peripheral shielding sub-structure at least partially overlaps with the channel region of the first transistor (230) in the ith peripheral drive circuit, and the yth peripheral shielding sub-structure at least partially overlaps with the channel region of the first transistor (230) in the jth peripheral drive circuit; The xth peripheral shielding sub-structure and the yth peripheral shielding sub-structure are connected to the first signal line (800) through a switching line (900) respectively; The first signal line (800) extends along the first direction, the switching line (900) extends along a second direction, the second direction intersects with the first direction, and the first signal line (800) is located on a side of the peripheral drive circuit (710) away from the display area (100A).

17. The display panel of claim 15, wherein, The peripheral circuit group (700) comprises an ith peripheral drive circuit and a jth peripheral drive circuit, and the ith peripheral drive circuit is located on a side of the jth peripheral drive circuit close to the binding area (100C); The peripheral shielding sub-structure (330) comprises an xth peripheral shielding sub-structure and a yth peripheral shielding sub-structure, the xth peripheral shielding sub-structure at least partially overlaps with the channel region of the first transistor (230) in the ith peripheral drive circuit, and the yth peripheral shielding sub-structure at least partially overlaps with the channel region of the first transistor (230) in the jth peripheral drive circuit; Each peripheral shielding sub-structure (330) comprises a main structure (331) and a sub-structure (332) connected to the main structure (331), each sub-structure (332) at least partially overlaps with the channel region of the first transistor (230), the xth peripheral shielding sub-structure and the yth peripheral shielding sub-structure are connected through the main structure (331), and are connected to the first signal line (800) through the main structure (331).

18. The display panel of claim 16, wherein, The first signal line (800) is located between the peripheral drive circuit (710) and the binding area (100C); or, The first signal line (800) is located on a side of the peripheral drive circuit (710) away from the display area (100A) and extends along the first direction, and the main structure (331) is connected to an end of the first signal line (800) away from the binding area (100C).

19. A display device comprising: The display panel comprises the display panel of any one of claims 1-18. The display panel comprises the display panel of any one of claims 1-18.

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