Shift register, driving circuit, driving method, and display apparatus

Abstract

The present disclosure relates to the technical field of display, and provides a shift register, a driving circuit, a driving method, and a display apparatus. The shift register comprises: an input circuit, configured to, under the control of a first clock signal or a second clock signal, provide an input signal to a first node, and control the potential of a second node by using a first power supply voltage of a first power supply or a third clock signal from a third clock end; a first control circuit, configured to, under the control of the first power supply voltage, provide a potential of the first node to a third node, and, under the control of the potential of the first node and the first clock signal, or under the control of the potential of the first node and the second clock signal, provide at least one of a second power supply voltage of a second power supply and a potential of the second node to a fourth node; and an output circuit, configured to, under the control of the potential of the third node and the potential of the fourth node, provide the first power supply voltage or the second power supply voltage to an output end as an output signal.

Description

Shift Register, Driving Circuit, Driving Method and Display Device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular, to a shift register, a driving circuit, a driving method and a display device. Background Art

[0002] The circuit structure and internal connection relationship of the current shift register circuit are complex, and it occupies a large space. In addition, the shift register circuit has the problem of unstable pull-down ability, which may cause the voltage waveforms output by each stage of the shift register in the driving circuit to be different, thereby affecting the display quality of the display screen. Summary of the Invention

[0003] To solve the above problems, the present disclosure provides a shift register, a driving circuit, a driving method and a display device.

[0004] According to a first aspect, the present disclosure provides a shift register, including: an input circuit configured to provide an input signal from an input terminal to a first node under the control of a first clock signal from a first clock terminal or a second clock signal from a second clock terminal, and control the potential of a second node by using a first power supply voltage of a first power supply or a third clock signal from a third clock terminal; a first control circuit configured to provide the potential of the first node to a third node under the control of the first power supply voltage, and provide at least one of a second power supply voltage of a second power supply and the potential of the second node to a fourth node under the control of the first node and the first clock signal or under the control of the potential of the first node and the second clock signal; and an output circuit configured to provide the first power supply voltage or the second power supply voltage to an output terminal as an output signal under the control of the potential of the third node and the potential of the fourth node.

[0005] According to a second aspect, the present disclosure provides a driving circuit, including M cascaded shift registers provided in embodiments of the present disclosure, where the input terminal of the m-th stage shift register is electrically connected to the output terminal of the (m - 1)-th stage shift register, 1 < m ≤ M, m is an integer, and M is an integer greater than 1.

[0006] According to a third aspect, the present disclosure provides a display device, including the driving circuit provided in embodiments of the present disclosure.

[0007] According to a fourth aspect, this disclosure provides a driving method applied to a shift register provided in any of the embodiments of this disclosure, comprising: a first stage in which the input signal is at a first level, the first clock signal is at a second level, and the third clock signal is at a first level; a second stage in which the input signal is at a first level, the first clock signal is at a first level, and the third clock signal is at a second level; a third stage in which the input signal is at a second level, the first clock signal is at a first level, and the third clock signal is at a second level; a fourth stage in which the input signal is at a second level, the first clock signal is at a second level, and the third clock signal is at a first level; and a fifth stage in which the input signal is at a second level, the first clock signal is at a first level, and the third clock signal is at a second level. Attached Figure Description

[0008] Figure 1 is a schematic diagram of the structure of a shift register according to an embodiment of the present disclosure;

[0009] Figure 2 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0010] Figure 3 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0011] Figure 4 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0012] Figure 5 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0013] Figure 6A is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0014] Figure 6B is a signal timing diagram of a shift register according to an embodiment of the present disclosure;

[0015] Figure 7 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0016] Figure 8 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0017] Figure 9A is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0018] Figure 9B is a signal timing diagram of a shift register according to an embodiment of the present disclosure;

[0019] Figure 10A is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure;

[0020] Figure 10B is a signal timing diagram of a shift register according to an embodiment of the present disclosure;

[0021] Figure 11A is a schematic diagram of the drive circuit according to an embodiment of the present disclosure;

[0022] Figure 11B is a schematic diagram of the drive circuit according to an embodiment of the present disclosure;

[0023] Figure 11C is a schematic diagram of the drive circuit according to an embodiment of the present disclosure;

[0024] Figure 11D is a schematic diagram of the drive circuit according to an embodiment of the present disclosure;

[0025] Figure 12A is a signal timing diagram of a drive circuit according to an embodiment of the present disclosure;

[0026] Figure 12B is a signal timing diagram of a drive circuit according to another embodiment of the present disclosure;

[0027] Figure 13 is a schematic diagram of the structure of a display device according to an embodiment of the present disclosure; and

[0028] Figure 14 is a flowchart of a driving method according to an embodiment of the present disclosure. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. It should be noted that throughout the accompanying drawings, the same elements are represented by the same or similar reference numerals. In the following description, some specific embodiments are used for descriptive purposes only and should not be construed as limiting this disclosure in any way, but are merely examples of embodiments of this disclosure. Conventional structures or configurations will be omitted where they may cause confusion in understanding this disclosure. It should be noted that the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are only schematic representations of the embodiments of this disclosure.

[0030] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning as understood by those skilled in the art. The terms "first," "second," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0031] Furthermore, in the description of the embodiments disclosed herein, the terms "connected" or "connected to" can refer to two components being directly connected, or to two components being connected via one or more other components. Additionally, these two components can be connected or coupled via wired or wireless means.

[0032] The source and drain of the switching transistor used in this embodiment are symmetrical, so their source and drain can be interchanged. In this embodiment, according to their function, the gate can be called the control electrode, one of the source and drain can be called the first electrode, and the other of the source and drain can be called the second electrode.

[0033] Furthermore, in the description of the embodiments of this disclosure, the terms "first power supply voltage" and "second power supply voltage" are used only to distinguish the different amplitudes of the two power supply voltages. For example, the following description uses "first power supply voltage" as a relatively low voltage and "second power supply voltage" as a relatively high voltage. Those skilled in the art will understand that this disclosure is not limited thereto.

[0034] It should be noted that, in the description of the embodiments of this disclosure, INPUT can represent either an input signal terminal or an input signal provided by the input signal terminal. Similarly, the symbol CK1 can represent either a clock terminal or a clock signal provided by the clock terminal, OUT can represent either an output signal terminal or an output signal output by the output signal terminal, and VGH and VGL can represent either a power supply terminal or a power supply voltage provided by the power supply terminal. For example, power supply VGH can provide a high-level voltage, and power supply VGL can provide a low-level voltage. The following embodiments are the same and will not be described again.

[0035] Figure 1 is a schematic diagram of the structure of a shift register according to an embodiment of the present disclosure.

[0036] As shown in Figure 1, the shift register 100 includes an input circuit 110, a first control circuit 120, and an output circuit 130.

[0037] In this embodiment of the disclosure, the input circuit 110 is electrically connected to the first clock terminal CK1 or the second clock terminal CK2. Under the control of the first clock signal CK1 from the first clock terminal CK1 or the second clock signal CK2 from the second clock terminal CK2, the input circuit 110 provides the input signal INPUT from the input terminal INPUT to the first node N1.

[0038] The input circuit 110 is also electrically connected to the first power supply VGL and the third clock terminal CK3. Under the control of the third clock signal CK3 from the third clock terminal CK3, the input circuit 110 can provide the first power supply voltage VGL of the first power supply VGL to the second node N2. In some embodiments, the input circuit 110 can also directly provide the third clock signal CK3 to the second node N2 to control the potential of the second node N2.

[0039] In this embodiment, the first control circuit 120 is electrically connected to a first power supply VGL, a first clock terminal CK1, a second clock terminal CK2, and a second power supply VGH. Under the control of the first power supply voltage VGL, the potential of the first node N1 is provided to the third node N3. Under the control of the potential of the first node N1 and the first clock signal CK1, or under the control of the potential of the first node N1 and the second clock signal CK2, the first control circuit 120 provides at least one of the second power supply voltage VGH and the potential of the second node N2 to the fourth node N4. For example, under the control of the potential of the first node N1 and the first clock signal CK1, the first control circuit 120 can provide the second power supply voltage VGH to the fourth node N4, or it can provide the potential of the second node N2 to the fourth node N4, or it can provide the second power supply voltage VGH and the potential of the second node N2 together to the fourth node N4 to control the potential of the fourth node N4.

[0040] For example, under the control of the potential of the first node N1 and the second clock signal CK2, the first control circuit 120 can provide the second power supply voltage VGH to the fourth node N4, or provide the potential of the second node N2 to the fourth node N4, or provide the second power supply voltage VGH and the potential of the second node N2 together to the fourth node N4, so as to control the potential of the fourth node N4.

[0041] In this embodiment, the input circuit 110 is controlled by a second clock signal CK2, and the first control circuit 120 is controlled by a first clock signal CK1. Under the control of the second clock signal CK2, the input circuit 110 provides the input signal INPUT from the input terminal INPUT to the first node N1. Under the control of the potential of the first node N1 and the first clock signal CK1, the first control circuit 120 provides at least one of the second power supply voltage VGH and the potential of the second node N2 to the fourth node N4.

[0042] In this embodiment, the input circuit 110 is controlled by a first clock signal CK1 and a second clock signal CK2, and the first control circuit 120 is controlled by the second clock signal CK2. Under the control of the first clock signal CK1, the input circuit 110 provides the input signal INPUT from the input terminal INPUT to the first node N1. Under the control of the potential of the first node N1 and the second clock signal CK2, the first control circuit 120 provides at least one of the second power supply voltage VGH and the potential of the second node N2 to the fourth node N4.

[0043] In this embodiment, both the input circuit 110 and the first control circuit 120 are controlled by a first clock signal CK1 and a second clock signal CK2. Under the control of the first clock signal CK1, the input circuit 110 provides the input signal INPUT from the input terminal INPUT to the first node N1. Under the control of the potential of the first node N1 and the first clock signal CK1, the first control circuit 120 provides at least one of the second power supply voltage VGH and the potential of the second node N2 to the fourth node N4.

[0044] In this embodiment, the output circuit 130 is electrically connected to a first power supply VGL, a second power supply VGH, and an output terminal OUT. Under the control of the potentials of the third node N3 and the fourth node N4, either the first power supply voltage VGL or the second power supply voltage VGH is provided to the output terminal OUT as an output signal OUT. The output signal OUT can serve as a scanning signal or a light emission control signal for driving the pixel circuit.

[0045] For example, when the third node N3 controls the first power supply VGL to be connected to the output terminal OUT, the output circuit 130 outputs the first power supply voltage VGL to the output terminal OUT. When the fourth node N4 controls the second power supply VGH to be connected to the output terminal OUT, the output circuit 130 outputs the second power supply voltage VGH to the output terminal OUT.

[0046] In this embodiment of the disclosure, under the control of the potential of the first node N1, the first control circuit 120 can jointly control the potential of the fourth node N4 with the first clock signal CK and the second power supply VGH. The potential of the fourth node N4 is used to control whether the second power supply VGH and the output terminal OUT are in a connected or cut-off state, thereby controlling whether the output terminal OUT outputs a high level. When the second power supply VGH and the output terminal OUT are in a connected state, the output terminal OUT can output a high-level signal.

[0047] When the potential of the fourth node N4 controls the second power supply VGH to remain in the off state with the output terminal OUT, the first control circuit 120 controls the potential of the third node N3, so that the potential of the third node N3 can control the first power supply VGL to be in the connected state with the output terminal OUT. In this case, the output terminal OUT can output a low-level signal.

[0048] In this embodiment of the disclosure, the first control circuit 120 uses the first clock signal CK and the second power supply VGH to jointly control the potential of the fourth node N4. When the potential of the fourth node N4 is pulled up, it can ensure that the fourth node N4 and the second node N2 are in a cut-off state, thereby ensuring that the potential of the fourth node N4 can switch between high and low levels. This allows the second power supply VGH and the output terminal OUT to switch between a connected state and a cut-off state.

[0049] According to an embodiment of this disclosure, the first control circuit 120 uses the first clock signal CK and the second power supply VGH to jointly control the potential of the fourth node N4, ensuring the switching of the potential of the fourth node N4, thereby realizing the stable switching of the output signal OUT level between high and low levels, and outputting the scanning signal or light emission control signal required by the pixel circuit.

[0050] Figure 2 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0051] As shown in Figure 2, the shift register 200 includes an input circuit 210, a first control circuit 220, and an output circuit 230. The first control circuit 220 includes a first control unit 221, a second control unit 222, and a third control unit 223.

[0052] In this embodiment, the input circuit 210 and the output circuit 230 are similar to the input circuit 110 and the output circuit 130 described above, respectively, and will not be repeated for the sake of brevity.

[0053] In this embodiment, the first control unit 221 is electrically connected to the first node N1, the second node N2, the fourth node N4, and the first clock terminal CK1. Under the control of the potential of the first node N1 and the first clock signal CK1, the first control unit 221 controls the potential of the fourth node N4 using the potential of the second node N2.

[0054] For example, based on the potential of the first node N1 and the first clock signal CK1, the first control unit 221 can control the second node N2 and the fourth node N4 to be in a connected or disconnected state. When the second node N2 and the fourth node N4 are in a connected state, the first control unit 221 provides the potential of the second node N2 to the fourth node N4.

[0055] In this embodiment, the second control unit 222 is electrically connected to the first node N1, the fourth node N4, and the second power supply VGH. Under the control of the potential of the first node N1, the second control unit 222 controls the potential of the fourth node N4 using the second power supply voltage VGH.

[0056] For example, based on the potential of the first node N1, the second control unit 222 can control the second power supply VGH to be in a connected or disconnected state with the fourth node N4. When the second power supply VGH is in a connected state with the fourth node N4, the second control unit 222 provides the second power supply voltage VGH to the fourth node N4.

[0057] In this embodiment, the third control unit 223 is electrically connected to the first node N1, the third node N3, and the first power supply VGL. Under the control of the first power supply voltage VGL, the potentials of the third nodes N1 and N3 are controlled by the potential of the first node N1.

[0058] For example, based on the first power supply voltage VGL, the third control unit 223 can control the connection or disconnection between the first node N1 and the third node N3. When the first node N1 and the third node N3 are in a connected state, the third control unit 223 supplies power from the first node N1 to the third node N3.

[0059] In this embodiment, the first control unit 221 can use the potential of the second node N2 to pull down the potential of the fourth node N4, so that under the control of the low potential of the fourth node N4, the output circuit 230 controls the connection between the second power supply VGH and the output terminal OUT, and the output terminal OUT outputs a high-level signal. The second control unit 222 can use the second power supply voltage VGH to pull up the potential of the fourth node N4, so that under the control of the high potential of the fourth node N4, the output circuit 230 controls the connection between the second power supply VGH and the output terminal OUT to be cut off.

[0060] In this embodiment, the third control unit 223 can use the potential of the first node N1 to pull down the potential of the third node N3, so that under the control of the low potential of the third node N3, the output circuit 230 controls the connection between the first power supply VGL and the output terminal OUT, and the output terminal OUT outputs a low-level signal. The third control unit 223 can also use the potential of the first node N1 to pull up the potential of the third node N3, so that under the control of the high potential of the third node N3, the output circuit 230 controls the connection between the first power supply VGL and the output terminal OUT to be cut off.

[0061] In this embodiment of the disclosure, the first control circuit 120 uses the first clock signal CK and the second power supply VGH to jointly control the potential of the fourth node N4, which can maintain the potential of the fourth node N4 stably at a high level. This makes the second power supply VGH and the output terminal OUT stably maintain a cut-off state, thereby determining that the level of the output terminal OUT is pulled down by the first power supply VGL, and thus stably outputting a low level signal.

[0062] In this embodiment of the disclosure, the first control unit 221 and the second control unit 222 jointly control the potential of the fourth node N4 to switch between high and low potentials, thereby realizing the stable switching of the output signal OUT level between high and low levels, and outputting the scanning signal or light emission control signal required by the pixel circuit.

[0063] Figure 3 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0064] As shown in Figure 3, the shift register 300 includes an input circuit 310, a first control circuit 320, and an output circuit 330. The first control circuit 320 includes a first control unit 321, a second control unit 322, a third control unit 323, and a fourth control unit 324.

[0065] In this embodiment, the input circuit 310 and the output circuit 330 are similar to the input circuit 110 and the output circuit 130 described above, respectively. The second control unit 322 and the third control unit 323 are similar to the second control unit 222 and the third control unit 223 described above, respectively. For the sake of brevity, they will not be described again.

[0066] In this embodiment, the first control unit 321 is electrically connected to the first node N1, the second node N2, the fourth node N4, and the second clock terminal CK2. Under the control of the potential of the first node N1 and the first clock signal CK1, the first control unit 321 controls the potential of the fourth node N4 using the potential of the second node N2.

[0067] For example, based on the potential of the first node N1 and the second clock signal CK2, the first control unit 221 can control the second node N2 and the fourth node N4 to be in a connected or disconnected state. When the second node N2 and the fourth node N4 are in a connected state, the first control unit 221 provides the potential of the second node N2 to the fourth node N4.

[0068] In this embodiment, the fourth control unit 324 is electrically connected to the third node N3, the fourth node N4, the second power supply VGH, and the second clock signal CK2. Under the control of the potential of the fourth node N4 and the potential of the third node N3, the fourth control unit 324 uses the second power supply voltage VGH and the second clock signal CK2 to control the potential of the third node N3.

[0069] After the input circuit 310 writes the low level of the input signal INPUT to the second node N2, the third control unit 323 can provide the low potential of the second node N2 to the third node N3. The fourth control unit 324 can accelerate the pull-down of the potential of the third node N3 based on the second power supply voltage VGH and the second clock signal CK2, thereby enabling the first power supply VGL and the input terminal OUT to quickly switch to a connected state, shortening the time for the output signal OUT to switch from a high level to a low level.

[0070] Figure 4 is a schematic diagram of the structure of a shift register according to an embodiment of the present disclosure.

[0071] As shown in Figure 4, the shift register 400 includes an input circuit 410, a first control circuit 420, an output circuit 430, and a second control circuit 440.

[0072] In this embodiment, the input circuit 410, the first control circuit 420, and the output circuit 430 are similar to the input circuit 110, the first control circuit 120, and the output circuit 130 described above, respectively, and will not be repeated for the sake of brevity.

[0073] In this embodiment, the second control circuit 440 is electrically connected to the first node N1, the second node N2, and the third clock terminal. Under the control of the potential of the first node N1, the second control circuit 440 uses the third clock signal CK3 to control the potential of the second node N2.

[0074] For example, based on the potential of the first node N1, the second control circuit 440 controls the third clock terminal CK3 to be in a connected or cut-off state with the second node N2, thereby using the third clock signal CK3 to control the potential of the second node N2.

[0075] For example, when the third clock signal CK3 is high, the second control circuit 440 can control the connection between the third clock terminal CK3 and the second node N2 based on the potential of the first node N1. By using the third clock signal CK3 to pull up the potential of the second node N2, the potential of the fourth node N4 can be maintained at a high level. When the fourth node N4 is high, the second power supply VGH is cut off from the output terminal OUT, thereby ensuring that the output terminal OUT can stably output a low-level signal.

[0076] Figure 5 is a schematic diagram of the structure of a shift register according to an embodiment of the present disclosure.

[0077] As shown in Figure 5, the shift register 500 includes an input circuit 510, a first control circuit 520, an output circuit 530, and a third control circuit 550.

[0078] In this embodiment, the input circuit 510, the first control circuit 520, and the output circuit 530 are similar to the input circuit 110, the first control circuit 120, and the output circuit 130 described above, respectively, and will not be repeated for the sake of brevity.

[0079] In this embodiment, the third control circuit 550 is electrically connected to the control terminal CX, the fourth node N4, and the third power supply VGX. Under the control of the control signal CX from the control terminal CX, the potential of the third node N3 is controlled by the third power supply voltage VGX of the third power supply VGX.

[0080] In this embodiment, the shift register 500 is electrically connected to the pixel circuitry in the display panel. When the display panel is powered on or in the initialization phase, the control signal CX is low. When the display panel is in the normal display phase, the control signal CX remains high. The third power supply VGX can be either the first power supply VGL or the second power supply VGH. For example, when the display panel is powered on or in the initialization phase, the third power supply voltage VGX is written to the third node N3 based on the low level of the control signal CX.

[0081] For example, the output signal OUT can be a light-emitting control signal applied to the pixel circuit, and the transistor controlled by the light-emitting control signal is a PMOS transistor. In this case, the third power supply VGX can be the second power supply VGH. The third control circuit 550 uses the third power supply voltage VGX to pull the potential of the third node N3 high. The high potential of the third node N3 can quickly control the first power supply VGL and the output terminal OUT to be in a cutoff state, and the output terminal OUT can output a high-level signal. At this time, the output signal OUT controls the PMOS transistor to turn off, thereby avoiding the screen flickering phenomenon on the display panel upon power-on.

[0082] For example, the output signal OUT can be a scan signal applied to the pixel circuit, and the transistor controlled by the scan signal is an NMOS transistor. In this case, the third power supply VGX can be the first power supply VGL. The third control circuit 550 uses the third power supply voltage VGX to pull down the potential of the third node N3. The low potential of the third node N3 can quickly control the connection between the first power supply VGL and the output terminal OUT, allowing the output terminal OUT to output a low-level signal. At this time, the output signal OUT controls the NMOS transistor to turn off, thereby preventing screen flickering upon power-up.

[0083] Figure 6A is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0084] In this embodiment of the disclosure, the shift register 600 includes an input circuit 610, a first control circuit 620, and an output circuit 630.

[0085] In this embodiment of the disclosure, the input circuit 610 includes a first transistor T1 and a second transistor T2.

[0086] The control electrode of the first transistor T1 is electrically connected to the second clock terminal CK2, the first electrode of the first transistor T1 is electrically connected to the input terminal INPUT, and the second electrode of the first transistor T1 is electrically connected to the first node N1.

[0087] The control electrode of the second transistor T2 is connected to the third clock terminal CK3, the first electrode of the second transistor T2 is connected to the first power supply VGL, and the second electrode of the second transistor T2 is connected to the second node N2.

[0088] In this embodiment of the disclosure, the first control circuit 620 includes a first control unit 621, a second control unit 622, and a third control unit 623.

[0089] In this embodiment of the disclosure, the first control unit 621 includes a third transistor T3, a fourth transistor T4, and a first capacitor C1.

[0090] The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the fifth node N5, and the second electrode of the third transistor T3 is connected to the first clock terminal CK1.

[0091] The control electrode of the fourth transistor T4 is electrically connected to the fifth node N5, the first electrode of the fourth transistor T4 is electrically connected to the second node N2, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node N4.

[0092] The first terminal of the first capacitor C1 is electrically connected to the second node N2, and the second terminal of the first capacitor C1 is electrically connected to the fifth node N5.

[0093] In this embodiment of the disclosure, the third control unit 623 includes a fifth transistor T5. The control electrode of the fifth transistor T5 is electrically connected to the first power supply VGL, the first electrode of the fifth transistor T5 is electrically connected to the first node N1, and the second electrode of the fifth transistor T5 is electrically connected to the third node N3.

[0094] In this embodiment of the disclosure, the second control unit 622 includes a sixth transistor T6. The control electrode of the sixth transistor T6 is electrically connected to the first node N1, the first electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the second electrode of the sixth transistor T6 is electrically connected to the second power supply VGH.

[0095] In this embodiment of the disclosure, the output circuit 630 includes a seventh transistor T7, an eighth transistor T8, a second capacitor C2, and a third capacitor C3.

[0096] The control electrode of the seventh transistor T7 is connected to the fourth node N4, the first electrode of the seventh transistor T7 is connected to the second power supply VGH, and the second electrode of the seventh transistor T7 is connected to the output terminal OUT.

[0097] The control electrode of the eighth transistor T8 is electrically connected to the third node N3, the first electrode of the eighth transistor T8 is electrically connected to the output terminal OUT, and the second electrode of the eighth transistor T8 is electrically connected to the first power supply VGL.

[0098] The first terminal of the second capacitor C2 is electrically connected to the output terminal OUT, and the second terminal of the second capacitor C2 is electrically connected to the third node N3.

[0099] The first terminal of the third capacitor C3 is electrically connected to the second power supply VGH, and the second terminal of the third capacitor C3 is electrically connected to the fourth node N4.

[0100] In the embodiments of this disclosure, the first transistor T1 to the second transistor T8 are P-type TFT transistors. It should be noted that the first transistor T1 to the second transistor T8 in this disclosure can also be N-type TFT transistors.

[0101] Figure 6B is a signal timing diagram of a shift register according to an embodiment of the present disclosure.

[0102] The following description uses the structure of shift register 600 shown in Figure 6A as an example, combined with the signal timing diagram shown in Figure 6B, to illustrate the operation of the shift register provided in this embodiment. The operation of shift register 300 is divided into five stages.

[0103] In this embodiment of the disclosure, the first clock signal CK1 and the third clock signal CK3 are not at active levels. For example, in the shift register 600, the first clock signal CK1 and the third clock signal CK3 are used to control the PMOS transistor. When the first clock signal CK1 is low, the third clock signal CK3 is high. When the third clock signal CK3 is low, the first clock signal CK1 is high.

[0104] Compared to the second clock signal CK2, the first clock signal CK1 transitions from a high level to a low level first. Similarly, compared to the first clock signal CK1, the second clock signal CK2 transitions from a low level to a high level first. For example, when the first clock signal CK1 transitions from a high level to a low level, the second clock signal CK2 remains high. When the first clock signal CK1 becomes low, the second clock signal CK2 transitions from a high level to a low level. When the second clock signal CK2 transitions from a low level to a high level, the first clock signal CK1 remains low. When the second clock signal CK2 becomes high, the first clock signal CK1 transitions from a low level to a high level.

[0105] In this embodiment, when the input signal INPUT transitions from low to high, the first clock signal CK1 and the second clock signal CK2 are high, and the third clock signal CK3 is low. While the input signal INPUT remains high, the first clock signal CK1 and the second clock signal CK2 transition from high to low and then back to high, and the third clock signal CK3 transitions from low to high and then back to low. When the input signal INPUT remains high and the third clock signal CK3 transitions from high to low, the output terminal OUT outputs a high-level signal, thus scanning the corresponding pixel circuit.

[0106] In the first stage S1, the input signal INPUT is at a high level, the third clock signal CK3 is at a high level, the first clock signal CK1 is at a low level, and the second clock signal CK2 changes from a high level to a low level and then from a low level to a high level.

[0107] Upon entering the first stage S1, the first clock signal CK1 transitions from high to low, while the second clock signal CK2 remains high. During the first stage S1, when the second clock signal CK2 transitions from low to high, the first clock signal CK1 remains low. At the end of the first stage S1, the first clock signal CK1 transitions from low to high.

[0108] In the first stage S1, when the first clock signal CK1 is low, the second clock signal CK2 is high, and the third clock signal CK3 is high, the first transistor T1 and the second transistor T2 are turned off. The first node N1 remains at the low level of the previous stage.

[0109] Under the control of the low level of the first node N1, the third transistor T3 and the sixth transistor T6 are turned on. The first clock signal CK1 is written to the fifth node N5 through the third transistor T3, and the potential of the fifth node N5 is pulled low. At this time, the fourth transistor T4 is turned on. The second power supply voltage VGH is written to the fourth node N4 through the sixth transistor T6. At this time, the seventh transistor T7 is turned off, and the second power supply voltage VGH charges the third capacitor C3, causing the third capacitor C3 to store a high level.

[0110] Under the control of the first power supply voltage VGL, the fifth transistor T5 is turned on. The low potential of the first node N1 is written to the third node N3 through the fifth transistor T5. Under the control of the low potential of the third node N3, the eighth transistor T8 is turned on, and the first power supply voltage VGL is written to the output terminal OUT through the eighth transistor T8. The output terminal OUT outputs a low-level signal.

[0111] In the first stage S1, when the first clock signal CK1 is low, the second clock signal CK2 is low, and the third clock signal CK3 is high, the first transistor T1 is turned on, and the second transistor T2 is turned off. The input signal INPUT is written to the first node N1, and the node of the first node N1 is pulled high.

[0112] Under the control of the high level of the first node N1, the third transistor T3 and the sixth transistor T6 are turned off. The high potential of the first node N1 is written to the third node N3 through the fifth transistor T5, pulling the potential of the third node N3 high. The eighth transistor T8 is turned off, and the third node N3 charges the second capacitor C2, causing the second capacitor C2 to store a high level. The high level stored in the third capacitor C3 keeps the fourth node N4 at a high level, and the seventh transistor T7 is turned off. At this time, the output terminal OUT maintains a low level signal.

[0113] In the second stage S2, the input signal INPUT is high, the first clock signal CK1 is high, the second clock signal CK2 is high, and the third clock signal CK3 is low. The first transistor T1 is off, and the second transistor T2 is on. The first power supply voltage VGL is written to the second node N2 through the second transistor T2, pulling the potential of the second node N2 low. Under the action of the first capacitor C1, the potential of the fifth node N5 is pulled low again. Under the low potential of the fifth node N5, the fourth transistor T4 is on. The low potential of the second node N2 is written to the fourth node N4, at which point the seventh transistor T7 is on. Because the first transistor T1 is off, the high level stored in the second capacitor C2 keeps the third node N3 high, and the eighth transistor T8 is off. At this time, the output terminal OUT maintains a high-level output signal.

[0114] In the third stage S3, the input signal INPUT is low, the first clock signal CK1 is high, the second clock signal CK2 is high, and the third clock signal CK3 is low. The first transistor T1 is off, and the second transistor T2 is on. The first power supply voltage VGL is written to the second node N2 through the second transistor T2. Under the influence of the first capacitor C1, the potential of the fifth node N5 remains low. Under the influence of the low potential of the fifth node N5, the fourth transistor T4 is on. The low potential of the second node N2 is written to the fourth node N4, at which point the seventh transistor T7 is on. Because the first transistor T1 is off, the high level stored in the second capacitor C2 keeps the third node N3 high, and the eighth transistor T8 is off. At this time, the output terminal OUT maintains a high-level output signal.

[0115] In the fourth stage S4, the input signal INPUT is low, the first clock signal CK1 is low, the second clock signal CK2 is low, and the third clock signal CK3 is high. The first transistor T1 is turned on, and the second transistor T2 is turned off. The input signal INPUT is written to the first node N1, and the node of the first node N1 is pulled low.

[0116] Under the control of the low level of the first node N1, the third transistor T3 and the sixth transistor T6 are turned on. The second power supply voltage VGH is written to the fourth node N4 through the sixth transistor T6. At this time, the seventh transistor T7 is turned off, and the second power supply voltage VGH charges the third capacitor C3.

[0117] Under the control of the first power supply voltage VGL, the fifth transistor T5 is turned on. The low potential of the first node N1 is written to the third node N3 through the fifth transistor T5. Under the control of the low potential of the third node N3, the eighth transistor T8 is turned on, and the first power supply voltage VGL is written to the output terminal OUT through the eighth transistor T8. The potential of the output terminal OUT is pulled down, and the output terminal OUT outputs a low-level signal, realizing the step reduction of the output signal OUT. The low level of the third node N3 charges the second capacitor C2. Under the action of the second capacitor C2, the potential of the third node N3 remains at a low level, the eighth transistor T8 remains on, and the output terminal OUT maintains the output of a low-level signal.

[0118] In stage S5, the input signal INPUT is low, the first clock signal CK1 is high, the second clock signal CK2 is high, and the third clock signal CK3 is low. The first transistor T1 is off, and the second transistor T2 is on. The first power supply voltage VGL is written to the second node N2 through the second transistor T2.

[0119] The potentials of the first node N1 and the third node N3 remain at the low level of the previous stage, and the third transistor T3, the sixth transistor T6, and the eighth transistor T8 are turned on. The first clock signal CK1 is written to the fifth node N5 through the third transistor T3, pulling the potential of the fifth node N5 high, and the fourth transistor T4 is turned off. The second power supply voltage VGH is written to the fourth node N4 through the sixth transistor T6, keeping the potential of the fourth node N4 high, and the seventh transistor T7 is turned off. At this time, the output terminal OUT maintains a low-level output signal.

[0120] In this embodiment, since the first clock signal CK1 transitions from high to low before the second clock signal CK2, when the second clock signal CK2 is high in stage S1, the low level of the first node N1 controls the third transistor T3 to turn on. The first clock signal CK1 can also pull the potential of the fifth node N5 low in advance, causing the fourth transistor T4 to turn on. If the fourth transistor T4 remains on, when the input signal INPUT is high, the potential of the fourth node N4 can remain low, thereby controlling the output terminal OUT to stably output a high-level signal. Furthermore, the first capacitor C1 can further pull the potential of the fifth node N5 low, thereby controlling the output terminal OUT to stably output a high-level signal.

[0121] In this embodiment, the timing variation of the first clock signal CK1 can also be the same as the timing variation of the second clock signal CK2. For example, the control terminal of the first transistor T1 and the second terminal of the third transistor T3 are both electrically connected to the first clock terminal CK1.

[0122] In this embodiment, the shift register 600 has an 8T3C circuit structure, which has a simple circuit connection, fewer transistors and capacitors, and occupies less space, which is beneficial for narrowing the bezel of the display panel.

[0123] Figure 7 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0124] In this embodiment of the present disclosure, the shift register 700 includes first transistors T1 to ninth transistors T9 and first capacitors C1 to third capacitors C3. The shift register 700 including first transistors T1 to eighth transistors T8 and first capacitors C1 to third capacitors C3 can be referenced to the shift register 600 described above, and will not be repeated for the sake of brevity.

[0125] In this embodiment, the ninth transistor T9 can be the second control circuit described above. The control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is electrically connected to the second node N2, and the second electrode of the ninth transistor T9 is electrically connected to the third clock terminal CK3.

[0126] In this embodiment of the disclosure, for example in the fourth stage S4 shown in FIG6B, the ninth transistor T9 is turned on based on the low potential of the first node N1. The third clock terminal CK3 is written to the second node N2, and the potential of the second node N2 is pulled high. When the fourth transistor T4 is turned on, the potential of the second node N2 is provided to the fourth node N4 to ensure that the potential of the fourth node N4 does not drop, thereby ensuring that the seventh transistor T7 is completely cut off.

[0127] Figure 8 is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0128] In this embodiment of the present disclosure, the shift register 800 includes first transistors T1 to eighth transistors T8, tenth transistor T10, and first capacitors C1 to third capacitors C3. The shift register 800, including first transistors T1 to eighth transistors T8 and first capacitors C1 to third capacitors C3, can be referenced to the shift register 600 described above, and will not be repeated for the sake of brevity.

[0129] In this embodiment, the tenth transistor T10 can be the third control circuit described above. The control electrode of the tenth transistor T10 is electrically connected to the control terminal CX, the first electrode of the tenth transistor T10 is electrically connected to the third node N3, and the second electrode of the tenth transistor T10 is electrically connected to the third power supply VGX.

[0130] For example, the output signal OUT can be a light-emitting control signal applied to the pixel circuit, and the transistor controlled by the light-emitting control signal is a PMOS transistor. In this case, the third power supply VGX can be the second power supply VGH. After the display panel is powered on, the low level of the control signal CX controls the tenth transistor T10 to conduct, and the third power supply voltage VGX pulls the potential of the third node N3 high. The high potential of the third node N3 can quickly control the eighth transistor T8 to turn off, and the output terminal OUT can maintain a high-level output signal. At this time, the output signal OUT controls the PMOS transistor to turn off, thereby preventing the display panel from flickering upon power-on.

[0131] For example, the output signal OUT can be a scan signal applied to the pixel circuit, and the transistor controlled by the scan signal is an NMOS transistor. In this case, the third power supply VGX can be the first power supply VGL. After the display panel is powered on, the low level of the control signal CX controls the tenth transistor T10 to conduct, and the third power supply voltage VGX pulls down the potential of the third node N3. The low potential of the third node N3 can quickly control the eighth transistor T8 to conduct, and the output terminal OUT can output a low-level signal. At this time, the output signal OUT controls the NMOS transistor to turn off, thereby preventing screen flickering upon power-up.

[0132] Figure 9A is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0133] In this embodiment of the present disclosure, the shift register 900 includes a first transistor T1, third transistors T3 to T8, and first capacitors C1 to C3. The third transistor T3, fifth transistors T5 to T8, second capacitor C3, and third capacitor C3 included in the shift register 900 can be referred to the shift register 600 described above, and will not be repeated for the sake of brevity.

[0134] In this embodiment of the disclosure, the input circuit includes a first transistor T1, the control electrode of the first transistor T1 is electrically connected to the first clock terminal CK1, the first electrode of the first transistor T1 is electrically connected to the input terminal INPUT, and the second electrode of the first transistor T1 is electrically connected to the first node N1.

[0135] In this embodiment, the third clock signal CK3 is directly written to the second node N2. The control electrode of the fourth transistor T4 is electrically connected to the fifth node N5, the first electrode of the fourth transistor T4 is electrically connected to the second node N2, and the second electrode of the fourth transistor T4 is electrically connected to the fourth node. The first terminal of the first capacitor C1 is electrically connected to the second node, and the second terminal of the first capacitor C1 is electrically connected to the fifth node N5.

[0136] Figure 9B is a signal timing diagram of a shift register according to an embodiment of the present disclosure. Figure 9B shows the potential changes of signals and nodes in the shift register 900.

[0137] As shown in Figure 9B, the input signal INPUT, the first clock signal CK1, the third clock signal CK3, the output signal OUT, and the potential changes of the first node N1 and the third node N3 can be referred to the timing waveforms described in Figure 6B, which will not be repeated for the sake of simplicity.

[0138] In this embodiment, under the action of the first capacitor C1 and the third capacitor C3, the potentials of the fifth node N5 and the fourth node N4 switch between high and low levels, thus the seventh transistor T7 switches between being on and off. When the seventh transistor T7 is on, the output terminal OUT outputs a high-level signal. When the seventh transistor T7 is off, the output terminal OUT maintains the high-level signal of the previous stage.

[0139] In this embodiment, the shift register 900 uses a 7T3C circuit structure, which further simplifies the circuit connection. The number of transistors and capacitors is reduced, and the space occupied is smaller, which is beneficial for narrowing the bezel of the display panel.

[0140] Figure 10A is a schematic diagram of the structure of a shift register according to another embodiment of the present disclosure.

[0141] In this embodiment, the shift register 1000 includes a first transistor T1, third transistors T3 through T8, an eleventh transistor T11, a twelfth transistor T12, and first capacitors C1 through C4. The first transistor T1, fourth transistors T4 through T8, and first capacitors C1 through C3 included in the shift register 1000 can be referenced to the shift register 900 described above, and will not be repeated for the sake of brevity.

[0142] In this embodiment of the disclosure, the control electrode of the third transistor T3 is electrically connected to the first node, the first electrode of the third transistor T3 is electrically connected to the fifth node N5, and the second electrode of the third transistor T3 is electrically connected to the second clock terminal CK2.

[0143] The control electrode of the eleventh transistor T11 is connected to the fourth node N4, the first electrode of the eleventh transistor T11 is connected to the second power supply VGH, and the second electrode of the eleventh transistor T11 is connected to the sixth node N6.

[0144] The control electrode of the twelfth transistor T12 is electrically connected to the third node N3, the first electrode of the twelfth transistor T12 is electrically connected to the sixth node N6, and the second electrode of the twelfth transistor T12 is electrically connected to the second clock terminal CK2.

[0145] The first terminal of the fourth capacitor C4 is electrically connected to the sixth node N6, and the second terminal of the fourth capacitor C4 is electrically connected to the third node N3.

[0146] Figure 10B is a signal timing diagram of a shift register according to an embodiment of the present disclosure. Figure 10B shows the potential changes of signals and nodes in the shift register 1000.

[0147] As shown in Figure 10B, the potential changes of the input signal INPUT, the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the output signal OUT, the first node N1, and the third node N3 can be referred to the timing waveforms described in Figure 6B, which will not be repeated for the sake of simplicity.

[0148] In this embodiment, when the input signal INPUT is high, and the first clock signal CK1 transitions from high to low, the second clock signal CK2 remains high. The first transistor T1 is turned on, and the high level of the input signal INPUT is written to the first node N1. When the second clock signal CK2 transitions from high to low, the third transistor T3 is already cut off by the high potential of the first node N1. At this time, the low level of the second clock signal CK2 is not partially written to the fifth node N5 through the third transistor T3, thus ensuring that the fifth node N5 remains high. The fourth transistor T4 is turned off, therefore, the potential of the fourth node N4 can remain at the low potential of the previous stage, and the second power supply tower VGH can be stably output through the turned-on seventh transistor T7, with the output terminal OUT stably outputting a high-level signal.

[0149] In this embodiment of the disclosure, when the potential of the fourth node N4 is kept at a low potential, the eleventh transistor T11 is turned on, and the second power supply voltage VGH is written to the sixth node N6 through the eleventh transistor T11, and the potential of the sixth node N6 is kept at a high level.

[0150] When the input signal INPUT is at a low level and the first clock signal CK1 transitions from a high level to a low level, the low level of the input signal INPUT is written to the third node N3 through the first transistor T1 and the fifth transistor T5, and at this time, the twelfth transistor T12 is turned on. When the second clock signal CK2 transitions from a high level to a low level, the second clock signal CK2 pulls down the potential of the sixth node N6. At this time, under the action of the fourth capacitor C4, the potential of the third node N3 is quickly pulled down, so that the eighth transistor T8 can be quickly turned on, realizing a quick pull-down of the potential of the output terminal OUT, improving the falling speed of the output signal OUT level, and reducing the falling time of the OUT signal level.

[0151] FIG. 11A is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure.

[0152] As shown in FIG. 11A, the driving circuit 1100a includes M cascaded shift registers, and M is a positive integer greater than 1. The M shift registers include the first-stage shift register ST1, the third-stage shift register ST2,..., the M-stage shift register STM.

[0153] In the embodiments of the present disclosure, the shift register ST1 can be any one of the foregoing shift registers 100, 200, 300, 400, 500, 600, 700, 800, 900, and 1000. For example, all M shift registers are shift register 300. For example, all M shift registers are shift register 500. Details are not described herein again.

[0154] In the embodiments of the present disclosure, in the M cascaded shift registers, the input signal INPUT at the input terminal INPUT of the first-stage shift register ST1 is the start signal STV, and the input terminal INPUT of the m-stage shift register is electrically connected to the output terminal OUT(m - 1) of the (m - 1)-stage shift register. The input terminal INPUT of the (m + 1)-stage shift register is electrically connected to the output terminal OUT(m) of the m-stage shift register, 1 < m ≤ M - 1, and m is an integer. For example, the input terminal INPUT of the second-stage shift register ST2 is electrically connected to the output terminal OUT(1) of the first-stage shift register ST1.

[0155] FIG. 11B is a schematic structural diagram of a driving circuit according to another embodiment of the present disclosure.

[0156] In the embodiments of the present disclosure, the driving circuit 1100b includes M cascaded shift registers, and the cascading manner of the M shift registers can refer to that of the driving circuit 1100a.

[0157] In this embodiment of the disclosure, shift register ST1 can be any one of shift register 100, shift register 200, shift register 300, shift register 400, shift register 500, shift register 600, shift register 700 and shift register 800 mentioned above.

[0158] In this embodiment of the present disclosure, the driving circuit 1100b includes a first clock signal line ck1, a second clock signal line ck2, and a third clock signal line ck3. The first clock terminal CK1 of the m-th stage shift register is electrically connected to the first clock signal line ck1, the second clock terminal CK2 of the m-th stage shift register is electrically connected to the second clock signal line ck2, and the third clock terminal CK3 of the m-th stage shift register is electrically connected to the third clock signal line ck3.

[0159] The timing of the signals provided by the first clock signal line ck1, the second clock signal line ck2, and the third clock signal line ck3 can be referenced in Figure 6B, which shows the timing of the first clock signal CK1, the second clock signal CK2, and the third clock signal CK3.

[0160] In this embodiment of the present disclosure, the driving circuit 1100b further includes a fourth clock signal line ck4. The clock signals provided by the first clock signal line ck1 and the third clock signal line ck3 are not simultaneously active, and the clock signals provided by the second clock signal line ck2 and the fourth clock signal line ck4 are not simultaneously active.

[0161] For example, the control electrode of the first transistor T1 in the m-th stage shift register is electrically connected to the second clock signal line ck2, the control electrode of the second transistor T2 in the m-th stage shift register is electrically connected to the third clock signal line ck3, and the second electrode of the third transistor T3 in the m-th stage shift register is electrically connected to the first clock signal line ck1.

[0162] For example, the control electrode of the first transistor T1 in the (m+1)th stage shift register is electrically connected to the fourth clock signal line ck4, the control electrode of the second transistor T2 in the (m+1)th stage shift register is electrically connected to the first clock signal line ck1, and the second electrode of the third transistor T3 in the (m+1)th stage shift register is electrically connected to the third clock signal line ck3.

[0163] When the clock signal provided by the first clock signal line ck1 transitions from high to low, the clock signal provided by the second clock signal line ck2 remains high. Conversely, when the clock signal provided by the second clock signal line ck2 transitions from low to high, the clock signal provided by the first clock signal line ck1 remains low.

[0164] When the clock signal provided by the third clock signal line ck3 transitions from high to low, the clock signal provided by the fourth clock signal line ck4 remains high. Conversely, when the clock signal provided by the fourth clock signal line ck4 transitions from low to high, the clock signal provided by the third clock signal line ck3 remains low.

[0165] For example, in the first-stage shift register, the first clock input CK1 is electrically connected to the first clock signal line ck1; the second clock input CK2 is electrically connected to the second clock signal line ck2; and the third clock input CK3 is electrically connected to the third clock signal line ck3. In the second-stage shift register, the first clock input CK1 is electrically connected to the third clock signal line ck3; the second clock input CK2 is electrically connected to the fourth clock signal line ck4; and the third clock input CK3 is electrically connected to the first clock signal line ck1.

[0166] Figure 11C is a schematic diagram of the structure of a drive circuit according to another embodiment of the present disclosure.

[0167] In this embodiment of the disclosure, the driving circuit 1100c includes M cascaded shift registers, and the cascading method of the M shift registers can be referred to the driving circuit 1100a.

[0168] In this embodiment of the disclosure, shift register ST1 can be any one of shift registers 100, 200, 300, 400, 500, 600, 700, 800, and 900 mentioned above. For shift registers 100, 200, 300, 400, 500, 600, 700, and 800, the first clock terminal CK1 and the second clock terminal CK2 are connected to the same clock signal line.

[0169] In this embodiment of the present disclosure, the driving circuit 1100c includes a first clock signal line ck1 and a third clock signal line ck3. The first clock terminal CK1 and the second clock terminal CK2 of the m-th stage shift register are both electrically connected to the first clock signal line ck1, and the third clock terminal CK3 of the m-th stage shift register is electrically connected to the third clock signal line ck3.

[0170] For example, in the first-stage shift register, the first clock input CK1 and the second clock input CK2 are electrically connected to the first clock signal line ck1, and the third clock input CK3 is electrically connected to the third clock signal line ck3. Similarly, in the second-stage shift register, the first clock input CK1 and the second clock input CK2 are both electrically connected to the third clock signal line ck3, and the third clock input CK3 is electrically connected to the first clock signal line ck1.

[0171] Figure 11D is a schematic diagram of the structure of a drive circuit according to another embodiment of the present disclosure.

[0172] In this embodiment of the disclosure, the driving circuit 1100d includes M cascaded shift registers, and the cascading method of the M shift registers can be referred to the driving circuit 1100a.

[0173] In this embodiment of the disclosure, shift register ST1 can be shift register 900 as described above.

[0174] In this embodiment of the disclosure, the driving circuit 1100d includes a first clock signal line ck1, a second clock signal line ck2, a third clock signal line ck3, and a fourth clock signal line ck4.

[0175] For example, in the first-stage shift register, the first clock input CK1 is electrically connected to the second clock signal line ck2, the second clock input CK2 is electrically connected to the first clock signal line ck1, and the third clock input CK3 is electrically connected to the third clock signal line ck3. In the second-stage shift register, the first clock input CK1 is electrically connected to the fourth clock signal line ck4, the second clock input CK2 is electrically connected to the third clock signal line ck3, and the third clock input CK3 is electrically connected to the first clock signal line ck1.

[0176] Figure 12A is a signal timing diagram of a drive circuit according to an embodiment of the present disclosure. Figure 12A shows the timing changes of the clock signals output by the first clock signal line ck1, the second clock signal line ck2, the third clock signal line ck3, and the fourth clock signal line ck4 in the drive circuit 1100b, as well as the timing changes of the output signals of the first-stage shift register, the second-stage shift register, the third-stage shift register, and the fourth-stage shift register.

[0177] As shown in Figure 12A, the output signals of the first-stage shift register, the second-stage shift register, the third-stage shift register, and the fourth-stage shift register are shifted and output sequentially.

[0178] For example, the timing change of the output signal OUT(1) of the first-stage shift register can be referred to the change process described in Figure 6B, which will not be repeated for the sake of brevity.

[0179] Figure 12B is a signal timing diagram of a drive circuit according to an embodiment of the present disclosure. Figure 12B shows the timing changes of the clock signals output by the first clock signal line ck1, the second clock signal line ck2, and the third clock signal line ck3 in the drive circuit 1100d, as well as the timing changes of the output signals of the first-stage shift register, the second-stage shift register, the third-stage shift register, and the fourth-stage shift register.

[0180] As shown in Figure 12B, the output signals of the first-stage shift register, the second-stage shift register, the third-stage shift register, and the fourth-stage shift register are shifted and output sequentially.

[0181] For example, the timing change of the output signal OUT(1) of the first-stage shift register can be referred to the change process described in Figure 10B, which will not be repeated for the sake of brevity.

[0182] Figure 13 is a schematic diagram of the structure of a display device according to an embodiment of the present disclosure.

[0183] As shown in Figure 13, the display device 1300 may include a driving circuit 1310.

[0184] In this embodiment of the disclosure, the driving circuit 1310 can be any one of the driving circuits 1100a, 1100b, 1100c and 1100d described above, and will not be repeated here.

[0185] Figure 14 is a flowchart of a driving method according to an embodiment of the present disclosure.

[0186] As shown in Figure 14, the driving method may include operations S1410 to S1450.

[0187] In operation of S1410, in the first stage, the input signal is at the first level, the first clock signal is at the second level, and the third clock signal is at the first level.

[0188] In operation of S1420, in the second stage, the input signal is at the first level, the first clock signal is at the first level, and the third clock signal is at the second level.

[0189] During operation of S1430, in the third stage, the input signal is at the second level, the first clock signal is at the first level, and the third clock signal is at the second level.

[0190] During operation of S1440, in the fourth stage, the input signal is at the second level, the first clock signal is at the second level, and the third clock signal is at the first level.

[0191] When operating S1450, the input signal is at the second level, the first clock signal is at the first level, and the third clock signal is at the second level.

[0192] In this embodiment of the disclosure, operations S1410 to S1450 are similar to the operations performed by the shift register 600 described above, and will not be repeated here.

[0193] In this embodiment, the first stage is similar to the operation of the first stage S1 shown in FIG. 6B, the second stage includes the operation of the second stage S2 shown in FIG. 6B, the third stage is similar to the operation of the third stage S3 shown in FIG. 6B, the fourth stage is similar to the operation of the fourth stage S4 shown in FIG. 6B, and the fifth stage is similar to the operation of the fifth stage S5 shown in FIG. 6B. For the sake of simplicity, the same parts will not be described again here.

[0194] In this embodiment, the first level is high and the second level is low. Those skilled in the art can also set the first level to low and the second level to high depending on the type of transistor in the shift register.

[0195] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0196] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0197] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A shift register comprising: an input circuit configured to supply an input signal from an input terminal to a first node under control of a first clock signal from a first clock terminal or a second clock signal from a second clock terminal, and to control a potential of a second node with a first power supply voltage of a first power supply or a third clock signal from a third clock terminal; a first control circuit configured to supply a potential of the first node to a third node under control of the first power supply voltage, and to supply at least one of a second power supply voltage of a second power supply and the potential of the second node to a fourth node under control of the potential of the first node and the first clock signal or under control of the potential of the first node and the second clock signal; and an output circuit configured to supply the first power supply voltage or the second power supply voltage to an output terminal as an output signal under control of the potential of the third node and the potential of the fourth node.

2. The shift register of claim 1, wherein, the first control circuit includes: a first control unit configured to control the potential of the fourth node with the potential of the second node under control of the potential of the first node and the first clock signal; a second control unit configured to control the potential of the fourth node with the second power supply voltage under control of the potential of the first node; and a third control unit configured to supply the potential of the first node to the third node under control of the first power supply voltage.

3. The shift register of claim 1, wherein, the first control circuit includes: a first control unit configured to control the potential of the fourth node with the potential of the second node under control of the potential of the first node and the second clock signal; a second control unit configured to control the potential of the fourth node with the second power supply voltage under control of the potential of the first node; a third control unit configured to supply the potential of the first node to the third node under control of the first power supply voltage; and a fourth control unit configured to control the potential of the third node with the second power supply voltage and the second clock signal under control of the potential of the fourth node.

4. The shift register according to claim 1, further comprising: a second control circuit configured to control the potential of the second node with the third clock signal under control of the potential of the first node.

5. The shift register according to claim 1, further comprising: a third control circuit configured to control the potential of the third node with a third power supply voltage of a third power supply under control of a control signal.

6. The shift register of claim 1, wherein, the input circuit includes a first transistor and a second transistor; wherein a control electrode of the first transistor is electrically connected to the second clock terminal, a first electrode of the first transistor is electrically connected to the input terminal, and a second electrode of the first transistor is electrically connected to the first node; a control electrode of the second transistor is electrically connected to the third clock terminal, a first electrode of the second transistor is electrically connected to the first power supply, and a second electrode of the second transistor is electrically connected to the second node.

7. The shift register of claim 1, wherein, The first control circuit includes a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor; The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the fifth node, and the second electrode of the third transistor is electrically connected to the first clock terminal. The control electrode of the fourth transistor is electrically connected to the fifth node, the first electrode of the fourth transistor is electrically connected to the second node, and the second electrode of the fourth transistor is electrically connected to the fourth node. The control electrode of the fifth transistor is electrically connected to the first power supply, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the third node; The control electrode of the sixth transistor is electrically connected to the first node, the first electrode of the sixth transistor is electrically connected to the fourth node, and the second electrode of the sixth transistor is electrically connected to the second power supply. The first terminal of the first capacitor is electrically connected to the second node, and the second terminal of the first capacitor is electrically connected to the fifth node.

8. The shift register of claim 1, wherein, The output circuit includes a seventh transistor, an eighth transistor, a second capacitor, and a third capacitor; The control electrode of the seventh transistor is electrically connected to the fourth node, the first electrode of the seventh transistor is electrically connected to the second power supply, and the second electrode of the seventh transistor is electrically connected to the output terminal. The control electrode of the eighth transistor is electrically connected to the third node, the first electrode of the eighth transistor is electrically connected to the output terminal, and the second electrode of the eighth transistor is electrically connected to the first power supply. The first terminal of the second capacitor is electrically connected to the output terminal, and the second terminal of the second capacitor is electrically connected to the third node; The first terminal of the third capacitor is electrically connected to the second power source, and the second terminal of the third capacitor is electrically connected to the fourth node.

9. The shift register of claim 4, wherein, The second control circuit includes a ninth transistor; The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is electrically connected to the second node, and the second electrode of the ninth transistor is electrically connected to the third clock terminal.

10. The shift register of claim 5, wherein, The third control circuit includes a tenth transistor; The control electrode of the tenth transistor is electrically connected to the control terminal, the first electrode of the tenth transistor is electrically connected to the third node, and the second electrode of the tenth transistor is electrically connected to the third power supply.

11. The shift register of claim 1, wherein the first control circuit comprises a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, an eleventh transistor, a twelfth transistor, a first capacitor, and a fourth capacitor; wherein The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the fifth node, and the second electrode of the third transistor is electrically connected to the second clock terminal. The control electrode of the fourth transistor is electrically connected to the fifth node, the first electrode of the fourth transistor is electrically connected to the second node, and the second electrode of the fourth transistor is electrically connected to the fourth node. The control electrode of the fifth transistor is electrically connected to the first power supply, the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the third node; The control electrode of the sixth transistor is electrically connected to the first node, the first electrode of the sixth transistor is electrically connected to the fourth node, and the second electrode of the sixth transistor is electrically connected to the second power supply; The control electrode of the eleventh transistor is electrically connected to the fourth node, the first electrode of the eleventh transistor is electrically connected to the second power supply, and the second electrode of the eleventh transistor is electrically connected to the sixth node; The control electrode of the twelfth transistor is electrically connected to the third node, the first electrode of the twelfth transistor is electrically connected to the sixth node, and the second electrode of the twelfth transistor is electrically connected to the second clock terminal; The first end of the first capacitor is electrically connected to the second node, and the second end of the first capacitor is electrically connected to the fifth node; The first end of the fourth capacitor is electrically connected to the sixth node, and the second end of the fourth capacitor is electrically connected to the third node.

12. A driving circuit, comprising M cascaded shift registers as described in any one of claims 1 to 11, wherein the input terminal of the m-th stage shift register is electrically connected to the output terminal of the (m - 1)-th stage shift register, 1 < m ≤ M, m is an integer, and M is an integer greater than 1.

13. The driving circuit according to claim 12, further comprising: A first clock signal line, a second clock signal line, and a third clock signal line; Wherein, the first clock terminal of the m-th stage shift register is electrically connected to the first clock signal line, the second clock terminal of the m-th stage shift register is electrically connected to the second clock signal line, and the third clock terminal of the m-th stage shift register is electrically connected to the third clock signal line.

14. The driving circuit according to claim 12, further comprising: A first clock signal line and a third clock signal line; Wherein, both the first clock terminal and the second clock terminal of the m-th stage shift register are electrically connected to the first clock signal line, and the third clock terminal of the m-th stage shift register is electrically connected to the third clock signal line.

15. A display device, comprising the driving circuit according to claims 12 to 14.

16. A driving method, applied to the shift register as described in any one of claims 1 - 11, comprising: A first stage, wherein the input signal is at a first level, the first clock signal is at a second level, and the third clock signal is at a first level; A second stage, wherein the input signal is at a first level, the first clock signal is at a first level, and the third clock signal is at a second level; A third stage, wherein the input signal is at a second level, the first clock signal is at a first level, and the third clock signal is at a second level; A fourth stage, wherein the input signal is at a second level, the first clock signal is at a second level, and the third clock signal is at a first level; And A fifth stage, wherein the input signal is at a second level, the first clock signal is at a first level, and the third clock signal is at a second level.

17. The driving method according to claim 16, wherein, When the first clock signal switches from the first level to the second level, the second clock signal is at the first level; as well as When the second clock signal switches from the second level to the first level, the first clock signal is at the second level.

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