Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a substrate, a driving circuit layer and a light-emitting structure layer; the driving circuit layer comprises a first circuit unit, a second circuit unit, a signal line, an auxiliary power line (59) and a first power line (72), wherein at least part of the auxiliary power line (59) and the first power line (72) are arranged in pairs on a one-to-one correspondence basis and are electrically connected; the signal line extends in a first direction, the first power line (72) extends in a second direction, the first direction intersects with the second direction, and the signal line is located on a side of the auxiliary power line (59) in the second direction; the first circuit unit comprises a first pixel driving circuit, and the second circuit unit comprises a second pixel driving circuit; the first pixel driving circuit and the second pixel driving circuit are electrically connected to the same auxiliary power line (59); and the orthographic projection of the at least one auxiliary power line (59) on the substrate does not overlap the orthographic projection of the at least one signal line on the substrate.

Description

Display substrate and display device

[0001] This application claims priority to Chinese Patent Application No. 202410692195.4, filed on May 30, 2024, entitled “Display Substrate and Display Device”, the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] On one hand, this disclosure provides a display substrate, including a substrate, a driving circuit layer disposed on the substrate, and a light-emitting structure layer disposed on the driving circuit layer on a side away from the substrate; the driving circuit layer includes at least one first circuit unit, at least one second circuit unit, at least one signal line, at least one auxiliary power line, and at least one first power line, at least a portion of the auxiliary power lines are grouped together with the first power lines and electrically connected; the at least one signal line extends along a first direction, the at least one first power line extends along a second direction, the first direction and the second direction intersect and the plane formed is parallel to the plane where the substrate is located, and the at least one signal line is located on the side of the at least one auxiliary power line along the second direction;

[0006] The first circuit unit includes a first pixel driving circuit, and the second circuit unit includes a second pixel driving circuit. At least one first pixel driving circuit and at least one second pixel driving circuit are electrically connected to the same auxiliary power line, and the first power line is configured to provide a constant level signal to the first pixel driving circuit and the second pixel driving circuit. The orthographic projection of the at least one auxiliary power line onto the plane where the substrate is located does not overlap with the orthographic projection of the at least one signal line onto the plane where the substrate is located.

[0007] In some exemplary embodiments, the auxiliary power line includes a first portion and a second portion connected to each other; the first portion includes a first end and a second end disposed opposite to each other, the first portion extending along the second direction; the second portion includes a first end and a second end disposed opposite to each other, the first end of the second portion being connected to the second end of the first portion, and the second end of the second portion being away from the second end of the first portion; in the plane where the substrate is located, there is a minimum distance between the second end of the second portion and the at least one signal line, the minimum distance being greater than or equal to 3 micrometers.

[0008] In some exemplary embodiments, the at least one first power line is electrically connected to the second end of the second portion, and the orthographic projection of the at least one first power line onto the plane of the substrate does not overlap with the orthographic projection of the first portion onto the plane of the substrate.

[0009] In some exemplary embodiments, there is an angle between the first portion and the second portion, the angle being greater than 90 degrees and less than 180 degrees.

[0010] In some exemplary embodiments, the first pixel driving circuit includes a shielding electrode and at least one dual-gate transistor; the orthographic projection of the shielding electrode onto the plane of the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the dual-gate transistor onto the plane of the substrate.

[0011] In some exemplary embodiments, the transistor of the dual-gate structure includes a compensation transistor.

[0012] In some exemplary embodiments, the shielding electrode and the first power line are located in the same conductive layer.

[0013] In some exemplary embodiments, the shielding electrode and the first power line are an integral structure that is interconnected.

[0014] In some exemplary embodiments, the light-emitting structure layer includes at least one light-emitting device, the at least one light-emitting device including an anode, an organic light-emitting layer and a cathode stacked sequentially; the orthographic projection of the shielding electrode on the plane where the substrate is located at least partially overlaps with the orthographic projection of the anode of the at least one light-emitting device on the plane where the substrate is located.

[0015] In some exemplary embodiments, the at least one light-emitting device includes at least one green light-emitting device that emits green light, and the orthographic projection of the shielding electrode onto the plane of the substrate at least partially overlaps with the orthographic projection of the anode of at least one of the green light-emitting devices onto the plane of the substrate.

[0016] In some exemplary embodiments, the driving circuit layer includes at least one first initial signal line extending along the first direction and at least one first auxiliary initial signal line extending along the second direction; the first initial signal line and the first auxiliary initial signal line are connected to form a mesh structure for transmitting the first initial signal.

[0017] In some exemplary embodiments, the driving circuit layer includes at least one second initial signal line extending along the first direction and at least one second auxiliary initial signal line extending along the second direction; the second initial signal line and the second auxiliary initial signal line are connected to form a mesh structure for transmitting a second initial signal.

[0018] In some exemplary embodiments, the driving circuit layer includes at least one third initial signal line extending along the first direction and at least one third auxiliary initial signal line extending along the second direction; the third initial signal line and the third auxiliary initial signal line are connected to form a mesh structure for transmitting the third initial signal.

[0019] On the other hand, this disclosure provides a display device including the display substrate described in any of the foregoing embodiments.

[0020] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0021] Overview of the attached figures

[0022] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0023] Figure 1 is a schematic diagram of the structure of a display device;

[0024] Figure 2 is a schematic diagram of a planar structure of a display substrate;

[0025] Figure 3 is a schematic cross-sectional view of a display substrate;

[0026] Figure 4 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to an embodiment of the present disclosure;

[0027] Figure 5 is a schematic diagram of a partial planar structure of a display substrate according to an embodiment of the present disclosure;

[0028] Figure 6 is a schematic diagram of a display substrate after a first semiconductor layer pattern has been formed according to an embodiment of the present disclosure;

[0029] Figures 7A and 7B are schematic diagrams of a display substrate after a first conductive layer pattern has been formed according to an embodiment of the present disclosure;

[0030] Figures 8A and 8B are schematic diagrams of a display substrate after a second conductive layer pattern has been formed according to an embodiment of the present disclosure;

[0031] Figure 9 is a schematic diagram of a display substrate after a second semiconductor layer pattern has been formed according to an embodiment of the present disclosure;

[0032] Figures 10A and 10B are schematic diagrams of a display substrate after a third conductive layer pattern has been formed according to an embodiment of the present disclosure.

[0033] Figure 11 is a schematic diagram of a display substrate after a fifth insulating layer pattern has been formed according to an embodiment of the present disclosure;

[0034] Figures 12A and 12B are schematic diagrams of a display substrate after a fourth conductive layer pattern has been formed according to an embodiment of the present disclosure.

[0035] Figure 13 is a schematic diagram of a display substrate after a sixth insulating layer pattern has been formed according to an embodiment of the present disclosure;

[0036] Figures 14A and 14B are schematic diagrams of a display substrate after a fifth conductive layer pattern has been formed according to an embodiment of the present disclosure.

[0037] Figure 15 is a schematic diagram of a display substrate after a seventh insulating layer pattern has been formed according to an embodiment of the present disclosure;

[0038] Figures 16A and 16B are schematic diagrams of a display substrate after a sixth conductive layer pattern has been formed according to an embodiment of the present disclosure.

[0039] Figure 17 is a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an embodiment of the present disclosure.

[0040] Detailed Explanation

[0041] The embodiments of this disclosure will be described below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be changed to one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0042] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0043] The ordinal numbers such as "first," "second," and "third" in this disclosure are used to avoid confusion among the constituent elements, not to limit the quantity. "Multiple" in this disclosure includes two or more quantities.

[0044] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0045] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0046] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0047] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0048] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components having one or more functions.

[0049] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore can include a state in which the angle is greater than or equal to -5° and less than 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore can include a state in which the angle is greater than or equal to 85° and less than 95°.

[0050] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0051] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0052] This disclosure provides a display substrate, including a substrate, a driving circuit layer disposed on the substrate, and a light-emitting structure layer disposed on the driving circuit layer on a side away from the substrate; the driving circuit layer includes at least one first circuit unit, at least one second circuit unit, at least one signal line, at least one auxiliary power line, and at least one first power line, at least a portion of the auxiliary power lines are grouped with and electrically connected to the first power lines; the at least one signal line extends along a first direction, the at least one first power line extends along a second direction, the first direction and the second direction intersect and the plane formed is parallel to the plane of the substrate, and the at least one signal line is located on the side of the at least one auxiliary power line along the second direction;

[0053] The first circuit unit includes a first pixel driving circuit, and the second circuit unit includes a second pixel driving circuit. At least one first pixel driving circuit and at least one second pixel driving circuit are electrically connected to the same auxiliary power line, and the first power line is configured to provide a constant level signal to the first pixel driving circuit and the second pixel driving circuit. The orthographic projection of the at least one auxiliary power line onto the plane where the substrate is located does not overlap with the orthographic projection of the at least one signal line onto the plane where the substrate is located.

[0054] The display substrate provided in this embodiment can improve the rationality of wiring by optimizing the layout of auxiliary power lines and signal lines, as well as optimizing the layout of auxiliary power lines and first power lines, and can avoid problems such as short circuits caused by tight wiring.

[0055] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc. of specifications suitable for the scan driver to the scan driver, and provide clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm, where m can be a natural number. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal. The light-emitting driver can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, the light-emitting driver can sequentially provide transmit signals with cutoff level pulses to the light-emitting signal lines E1 to Eo, where o can be a natural number. For example, the light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0056] Figure 2 is a schematic diagram of a planar structure of a display substrate. In an exemplary embodiment, the display substrate may include a display area and a border area surrounding the display area. As shown in Figure 2, the display area of ​​the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting unit may include at least a light-emitting device, which is connected to the pixel driving circuit of the sub-pixel and is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0057] In some exemplary embodiments, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 may be a green sub-pixel (G) emitting green light. In one example, the shape of the sub-pixels may be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels may be arranged in a horizontal, vertical, or triangular manner, etc., which is not limited herein.

[0058] In some exemplary embodiments, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0059] Figure 3 is a cross-sectional schematic diagram of a display substrate, illustrating the structure of three sub-pixels in the display substrate. As shown in Figure 3, on a plane perpendicular to the display substrate, the display area of ​​the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may also include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0060] In some exemplary embodiments, the substrate 101 may be a flexible substrate or a rigid substrate. The rigid substrate may be one or more of glass and quartz, while the flexible substrate may be one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers, among others.

[0061] In some exemplary embodiments, the substrate 101 may be a flexible substrate or a rigid substrate. The flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0062] In some exemplary embodiments, the driving circuit layer 102 may include multiple circuit units, each of which may include at least a pixel driving circuit, and the pixel driving circuit may include multiple transistors and capacitors. The light-emitting structure layer 103 may include multiple light-emitting units, each of which may include at least a light-emitting device. The light-emitting device may include an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and the cathode.

[0063] In some exemplary embodiments, the encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0064] In some exemplary embodiments, the organic light-emitting layer may include a light-emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0065] Figure 4 is an equivalent circuit diagram of a pixel driving circuit for a display substrate according to an embodiment of the present disclosure. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C, or 9T2C structure. As shown in Figure 4, the pixel driving circuit of an exemplary embodiment of the present disclosure adopts an 8T1C structure. The pixel driving circuit may include eight transistors (first transistor T1 to eighth transistor T8) and one storage capacitor C. The pixel driving circuit is connected to ten signal lines (first scan signal line S1, second scan signal line S2, light emission signal line EM, first reference signal line REF1, second reference signal line REF2, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA, and first power supply line VDD).

[0066] In some exemplary embodiments, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the first terminal of the second transistor T2, the gate electrode of the third transistor T3, and the second terminal of the storage capacitor C. The second node N2 is connected to the first terminal of the third transistor T3, the second terminal of the fifth transistor T5, the second terminal of the fourth transistor T4, and the second terminal of the eighth transistor T8. The third node N3 is connected to the second terminals of the second transistor T2, the second terminal of the third transistor T3, the second terminal of the first transistor T1, and the first terminal of the sixth transistor T6. The fourth node N4 is connected to the second terminal of the sixth transistor T6, the second terminal of the seventh transistor T7, and the first terminal of the light-emitting device EL.

[0067] In some exemplary embodiments, the first transistor T1 may also be referred to as the first initialization transistor. The gate electrode of the first transistor T1 is connected to the first reference signal line REF1, the first terminal of the first transistor T1 is connected to the first initial signal line INIT1, and the second terminal of the first transistor T1 is connected to the third node N3.

[0068] In some exemplary embodiments, the second transistor T2 may also be referred to as a compensation transistor. The gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3.

[0069] In some exemplary embodiments, the third transistor T3 may also be referred to as the driving transistor. The gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.

[0070] In some exemplary embodiments, the fourth transistor T4 can also be referred to as the data writing transistor. The gate electrode of the fourth transistor T4 is connected to the second scan signal line S2, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2.

[0071] In some exemplary embodiments, the fifth transistor T5 may also be referred to as the first light-emitting transistor. The gate electrode of the fifth transistor T5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.

[0072] In some exemplary embodiments, the sixth transistor T6 may also be referred to as the second light-emitting transistor. The gate electrode of the sixth transistor T6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0073] In some exemplary embodiments, the seventh transistor T7 may also be referred to as the second initialization transistor. The gate electrode of the seventh transistor T7 is connected to the second reference signal line REF2, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0074] In some exemplary embodiments, the eighth transistor T8 may also be referred to as the third initialization transistor. The gate electrode of the eighth transistor T8 is connected to the second reference signal line REF2, the first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is connected to the second node N2.

[0075] In some exemplary embodiments, the first terminal of the storage capacitor C is connected to the first power line VDD, and the second terminal of the storage capacitor C is connected to the first node N1. The first electrode of the light-emitting device EL is connected to the fourth node N4, and the second electrode of the light-emitting device EL is connected to the second power line VSS. The light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0076] In some exemplary embodiments, the first power line VDD can be configured to provide a constant first voltage signal to the pixel driving circuit, and the second power line VSS can be configured to provide a constant second voltage signal to the light-emitting device, wherein the first voltage signal is greater than the second voltage signal. In some examples, the reference signal and the initial signal can be constant voltage signals, which is not limited herein.

[0077] In some exemplary embodiments, the first transistor T1 to the eighth transistor T8 can be P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the processing difficulty of the display substrate, and improve the product yield. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include both P-type and N-type transistors.

[0078] In some exemplary embodiments, the first transistor T1 to the eighth transistor T8 may be a low-temperature polysilicon transistor (LTPS), or an oxide transistor, or a combination of LTPS and metal-oxide transistors. The active layer of the LTPS transistor is made of low-temperature polysilicon (LTPS), while the active layer of the metal-oxide transistor is made of metal-oxide semiconductor (Oxide). LTPS transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating LTPS transistors and metal-oxide transistors onto a single display substrate to form an LTPO (Low Temperature Poly-Silicon+Oxide) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0079] Figure 5 is a partial planar structure schematic diagram of a display substrate according to an embodiment of the present disclosure. As shown in Figure 5, only a partial structural schematic diagram of the display substrate after the fifth conductive layer pattern is formed is illustrated. The display substrate may include a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate. The driving circuit layer may include at least a plurality of circuit units, and the plurality of circuit units may include at least a first circuit unit and a second circuit unit. The circuit unit may include at least a pixel driving circuit, the first circuit unit may include a first pixel driving circuit, and the second circuit unit may include a second pixel driving circuit. The first circuit unit and the second circuit unit may be the same or different, and the first pixel driving circuit and the second pixel driving circuit may be the same or different. The light-emitting structure layer may include at least a plurality of light-emitting units, and at least one light-emitting unit may include a light-emitting device. The light-emitting device may include at least an anode, an organic light-emitting layer, and a cathode. The anode in the light-emitting unit is connected to the pixel driving circuit in the corresponding circuit unit. The position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0080] In a plane perpendicular to the display substrate, the driving circuit layer may include, sequentially located on one side of the substrate, a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a second semiconductor layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer, a fifth conductive layer, and a seventh insulating layer. The light-emitting structure layer may include a sixth conductive layer and a pixel definition layer (see Figure 17). The sixth conductive layer may include at least the anodes of multiple light-emitting devices, and the pixel definition layer may include at least multiple pixel opening regions. The multiple light-emitting devices may include at least a red light-emitting device emitting red light, a blue light-emitting device emitting blue light, and a green light-emitting device emitting green light. The light-emitting devices can emit light of the corresponding color under the drive of the pixel driving circuit electrically connected to them, and the light emitted by the light-emitting devices can exit the display substrate through the corresponding pixel opening region.

[0081] The first semiconductor layer may include multiple active layers of multiple transistors, and the multiple active layers may include at least the first active layer 11 of the first transistor T1, the third active layer 13 of the third transistor T3, the fourth active layer 14 of the fourth transistor T4, the fifth active layer 15 of the fifth transistor T5, the sixth active layer 16 of the sixth transistor T6, the seventh active layer 17 of the seventh transistor T7, and the eighth active layer 18 of the eighth transistor T8.

[0082] The first conductive layer may include at least a first electrode 21, a second scan signal line 22, a light emission signal line 23, a second reference signal line 24, and a first reference signal line 25. The first electrode 21 is the second terminal of the storage capacitor. The second conductive layer may include at least a first scan signal line 31 and a second electrode 32. The second electrode 32 is the first terminal of the storage capacitor. The first electrode 21 and the second electrode 32 constitute the storage capacitor.

[0083] The second semiconductor layer may include at least the second active layer 12 of the second transistor T2. The third conductive layer may include at least a first initial signal line 41, a second initial signal line 42, a third initial signal line 43, and a third scan signal line 44. The fourth conductive layer may include at least a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57, an eighth connection electrode 58, an auxiliary power line 59, a first auxiliary initial signal line 61, a second auxiliary initial signal line 62, and a third auxiliary initial signal line 63. The fifth conductive layer may include at least a data signal line 71, a first power line 72, an anode connection electrode 73, and a shielding electrode 74. The first power line 72 may be configured to provide a constant level signal to at least one pixel driving circuit; for example, the constant level signal may be a high level signal.

[0084] In some exemplary embodiments, at least a portion of the auxiliary power line 59 may be located between two adjacent circuit units, and the auxiliary power line 59 is connected to both adjacent circuit units, providing electrical signals to both circuit units. The auxiliary power line 59 is connected to the pixel driving circuits of both adjacent circuit units; for example, the auxiliary power line 59 is electrically connected to both adjacent first pixel driving circuits and second pixel driving circuits. For example, the auxiliary power line 59 may be connected to the first region of the fifth active layer of the fifth transistor in the pixel driving circuit. The orthographic projection of the auxiliary power line 59 onto the plane of the substrate may at least partially overlap with the orthographic projection of the second electrode plate 32 onto the plane of the substrate, and the auxiliary power line 59 may be connected to the second electrode plate 32 through a via disposed on the insulating layer.

[0085] In some exemplary embodiments, the auxiliary power cord 59 may include a first portion 59-1 and a second portion 59-2 connected to each other. The first portion 59-1 may be a strip extending along a second direction Y, and may include a first end and a second end positioned opposite each other. The second portion 59-2 may be rectangular, extending along a direction different from both the first direction X and the second direction Y, and may include a first end and a second end positioned opposite each other. The first end of the second portion 59-2 may be connected to the second end of the first portion 59-1, and the second end of the second portion 59-2 may be located away from the second end of the first portion 59-1. In some possible embodiments, the second portion 59-2 may be located on the side of the first portion 59-1 opposite to the first direction X. In one example, the first portion 59-1 and the second portion 59-2 may be an integral structure connected to each other.

[0086] In some exemplary embodiments, a minimum distance of 3 micrometers exists between the auxiliary power line 59 and the signal line in the plane of the substrate to prevent short circuits between the signal line and the auxiliary power line. For example, the signal line may include a first scan signal line 31 and a third scan signal line 44. For example, a minimum distance exists between the second end of the second portion 59-2 of the auxiliary power line 59 and at least one signal line.

[0087] In some exemplary embodiments, the orthographic projection of the first power line 72 onto the plane of the substrate does not overlap with the orthographic projection of the first portion 59-1 onto the plane of the substrate, and the orthographic projection of the data signal line 71 onto the plane of the substrate does not overlap with the orthographic projection of the first portion 59-1 onto the plane of the substrate. This can prevent parasitic capacitance from being generated between the first power line and the first portion of the auxiliary power line, and between the data signal line and the first portion of the auxiliary power line, thereby improving the display performance of the display substrate.

[0088] In some exemplary embodiments, the shielding electrode 74 may be located on one side of the second electrode plate 32 in the second direction Y. The shielding electrode 74 may be rectangular in shape; for example, the shielding electrode 74 may be a rounded rectangle. The orthographic projection of the shielding electrode 74 onto the plane of the substrate at least partially overlaps with the orthographic projection of the second active layer 12 of the second transistor T2 onto the plane of the substrate. For example, the orthographic projection of the shielding electrode 74 onto the plane of the substrate may include the orthographic projection of the second active layer 12 of the second transistor T2 onto the plane of the substrate. For example, the orthographic projection of the shielding electrode 74 onto the plane of the substrate may include the orthographic projection of the second active layer 12 of the second transistor T2 onto the plane of the substrate, and the area of ​​the orthographic projection of the shielding electrode 74 onto the plane of the substrate is larger than the area of ​​the orthographic projection of the second active layer 12 of the second transistor T2 onto the plane of the substrate.

[0089] In some exemplary embodiments, the shielding electrode 74 and the first power line 72 may be located in the same conductive layer. For example, the shielding electrode 74 and the first power line 72 may be an integral structure that is interconnected.

[0090] In some exemplary embodiments, the orthographic projection of the shielding electrode 74 onto the plane of the substrate and the orthographic projection of the anode of the green light-emitting device onto the plane of the substrate may at least partially overlap. Typically, white light perceived by the human eye is a mixture of red, green, and blue primary colors. Different colored light-emitting devices have different luminous intensities; therefore, the luminous areas of different colored light-emitting devices are usually designed differently, with green light-emitting devices typically having the smallest luminous area and blue light-emitting devices having the largest. During display, it is generally desirable for different colored light-emitting devices to be activated synchronously; however, the characteristics of the luminous materials of different colored light-emitting devices are different, with green light-emitting materials being the easiest to excite and blue light-emitting materials being the most difficult to excite. This disclosure proposes that by designing the anode and shielding electrode of the green light-emitting device to form a parasitic capacitance, before the light-emitting signal emits light, the anode of the green light-emitting device is reset through the second initial signal line, forming a plate of the parasitic capacitance, that is, the anode of the green light-emitting device, which carries a negative charge. When current flows into the first power line, it will first neutralize the negative charge on the anode and then charge the storage capacitor. This will delay the lighting of the green light-emitting device, thereby enabling light-emitting devices of different colors to light up synchronously to form a uniform white.

[0091] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0092] Taking a display substrate comprising two circuit units as an example, the two circuit units are a first circuit unit and a second circuit unit, the first circuit unit including a first pixel driving circuit, and the second circuit unit including a second pixel driving circuit. In the embodiments of this disclosure, the first pixel driving circuit and the second pixel driving circuit have the same structure. The fabrication process of the display substrate may include the following steps:

[0093] (11) Forming a first semiconductor layer pattern. Forming a first semiconductor layer pattern may include: depositing a first semiconductor thin film on a substrate, and patterning the first semiconductor thin film through a patterning process so that the first semiconductor thin film forms a first semiconductor layer pattern, as shown in FIG6.

[0094] In some exemplary embodiments, the first semiconductor layer pattern in the display substrate may include at least the first active layer 11 of the first transistor T1, the third active layer 13 of the third transistor T3, and the eighth active layer 18 of the eighth transistor T8. The third active layer 13, the fourth active layer 14, the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 may be an integral structure interconnected. The first active layer 11 and the eighth active layer 18 may be located on opposite sides of the seventh active layer 17 along the first direction X.

[0095] In some exemplary embodiments, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. The first region may be used as the first electrode of the transistor, and the second region may be used as the second electrode of the transistor. The second region 17-2 of the seventh active layer and the second region 16-2 of the sixth active layer may be interconnected, and the second region 17-2 of the seventh active layer may serve as the second region 16-2 of the sixth active layer. The first region 16-1 of the sixth active layer and the second region 13-2 of the third active layer may be interconnected, and the first region 16-1 of the sixth active layer may serve as the second region 13-2 of the third active layer. The first region 13-1 of the third active layer and the second region 15-2 of the fifth active layer may be interconnected, and the first region 13-1 of the third active layer may serve as the second region 15-2 of the fifth active layer. The first region 11-1 and the second region 11-2 of the first active layer may be located on opposite sides of the channel region of the first active layer along the second direction Y. The first region 18-1 and the second region 18-2 of the eighth active layer can be located on opposite sides of the channel region of the eighth active layer along the second direction Y. The first region 14-1 and the second region 14-2 of the fourth active layer can be located on opposite sides of the channel region of the fourth active layer along the second direction Y, and the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer can be interconnected.

[0096] In some exemplary embodiments, the transistor may be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, an oxide thin-film transistor, or a combination of both. The active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors offer advantages such as high mobility and fast charging, while oxide thin-film transistors offer advantages such as low leakage current. In one example, the LTPS and oxide thin-film transistors can be integrated onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate. This leverages the advantages of both, enabling high resolution (Pixels Per Inch, PPI), low-frequency driving, reduced power consumption, and improved display quality. In one example, the first, third, through eighth transistors may be LTPS transistors, and the second transistor may be an oxide thin-film transistor.

[0097] In some exemplary embodiments, the active layer of the oxide thin-film transistor is an oxide, which can be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc nitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper oxysulfide oxide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), indium gallium zinc oxide (IGZO), and indium gallium aluminum nitride (InGaAlN).

[0098] (12) Forming a first conductive layer pattern. Forming the first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a first insulating layer on the side of the first semiconductor layer pattern away from the substrate, and forming a first conductive layer pattern on the side of the first insulating layer away from the substrate, as shown in Figures 7A and 7B, where Figure 7B is a planar schematic diagram of the first conductive layer in Figure 7A. The first conductive layer may be referred to as a first gate metal (GATE1) layer. The first conductive layer pattern may include at least a first electrode 21, a second scan signal line 22, a light emission signal line 23, a second reference signal line 24, and a first reference signal line 25. The first electrode 21 is also the second terminal of the storage capacitor.

[0099] In some exemplary embodiments, the second scan signal line 22, the light emission signal line 23, the second reference signal line 24, and the first reference signal line 25 may be arranged sequentially along the second direction Y, and may all be lines extending along the first direction X. The orthographic projection of the second scan signal line 22 onto the plane of the substrate at least partially overlaps with the orthographic projection of the channel region of the fourth transistor T4 onto the plane of the substrate. The overlapping portion of the second scan signal line 22 and the orthographic projection of the channel region of the fourth transistor T4 can serve as the gate electrode of the fourth transistor T4. The orthographic projection of the light emission signal line 23 onto the plane of the substrate at least partially overlaps with the orthographic projection of the channel region of the fifth transistor T5 onto the plane of the substrate, and the orthographic projection of the light emission signal line 23 onto the plane of the substrate at least partially overlaps with the orthographic projection of the channel region of the sixth transistor T6 onto the plane of the substrate. The overlapping portion of the orthographic projection of the light emission signal line 23 and the channel region of the fifth transistor T5 can serve as the gate electrode of the fifth transistor T5. The overlapping portion of the orthographic projection of the light emission signal line 23 and the channel region of the sixth transistor T6 can serve as the gate electrode of the sixth transistor T6. The orthographic projection of the second reference signal line 24 onto the plane of the substrate at least partially overlaps with the orthographic projection of the channel region of the seventh transistor T7 onto the plane of the substrate, and the orthographic projection of the second reference signal line 24 onto the plane of the substrate at least partially overlaps with the orthographic projection of the channel region of the eighth transistor T8 onto the plane of the substrate. The portion of the second reference signal line 24 overlapping with the orthographic projection of the channel region of the seventh transistor T7 can serve as the gate electrode of the seventh transistor T7. The portion of the second reference signal line 24 overlapping with the orthographic projection of the channel region of the eighth transistor T8 can serve as the gate electrode of the eighth transistor T8. The orthographic projection of the first reference signal line 25 onto the plane of the substrate at least partially overlaps with the orthographic projection of the channel region of the first transistor T1 onto the plane of the substrate, and the portion of the first reference signal line 25 overlapping with the orthographic projection of the channel region of the first transistor T1 can serve as the gate electrode of the first transistor T1.

[0100] In some exemplary embodiments, the first electrode 21 may be located between the second scan signal line 22 and the light emission signal line 23. The first electrode 21 may be block-shaped; for example, the first electrode 21 may be a rectangular block. For example, the first electrode 21 may be a rounded rectangular block.

[0101] In some exemplary embodiments, the first electrode 21 can be reused as the gate electrode of the third transistor T3.

[0102] (13) Forming a second conductive layer pattern. Forming a second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a second insulating layer on the side of the first conductive layer pattern away from the substrate, and forming a second conductive layer pattern on the side of the second insulating layer away from the substrate, as shown in Figures 8A and 8B, where Figure 8B is a planar schematic diagram of the second conductive layer in Figure 8A. The second conductive layer may be referred to as a second gate metal (GATE2) layer. The second conductive layer pattern may include at least a first scan signal line 31 and a second electrode 32. The second electrode 32 is the first terminal of the storage capacitor.

[0103] In some exemplary embodiments, the first scan signal line 31 may be a line extending along a first direction X. The first scan signal line 31 may be located between the second scan signal line 22 and the first electrode 21. The orthographic projection of the second electrode 32 onto the plane of the substrate at least partially overlaps with the orthographic projection of the first electrode 21 onto the plane of the substrate. The second electrode 32 may be block-shaped; for example, the second electrode 32 may be a rectangular block. For example, the second electrode 32 may be a rounded rectangular block.

[0104] In some exemplary embodiments, the second electrode plate located in the first circuit unit and the second electrode plate located in the second circuit unit can be an integral structure interconnected. The second electrode plate 32 may have at least one opening K, the orthographic projection of the opening K onto the plane of the substrate at least partially overlapping the orthographic projection of the first electrode plate 21 onto the plane of the substrate, and the opening K exposing at least a portion of the first electrode plate 21.

[0105] In some exemplary embodiments, the orthographic projection of the opening K onto the plane of the base can be a circle, ellipse, rectangle, hexagon, or octagon, etc. This disclosure does not limit the shape of the opening K.

[0106] (14) Forming a second semiconductor layer pattern. Forming a second semiconductor layer pattern may include: depositing a third insulating film and a second semiconductor film sequentially on the substrate on which the aforementioned pattern is formed, and patterning the second semiconductor film by a patterning process, so that the third insulating film forms a third insulating layer on the side of the second conductive layer pattern away from the substrate and the second semiconductor film forms a second semiconductor layer pattern on the side of the third insulating layer away from the substrate, as shown in FIG9. The second semiconductor layer pattern may include at least the second active layer 12 of the second transistor T2.

[0107] In some exemplary embodiments, the orthographic projection of the second active layer 12 of the second transistor T2 onto the plane of the substrate can be irregularly shaped. The orthographic projection of the second active layer 12 onto the plane of the substrate at least partially overlaps with the orthographic projections of the second scan signal line 22 onto the plane of the substrate and the first scan signal line 31 onto the plane of the substrate. The first region 12-1 of the second active layer and the second region 12-2 of the second active layer can be located on opposite sides of the first scan signal line 31 along the second direction Y, respectively. The second region 12-2 of the second active layer is closer to the second region 13-2 of the third active layer than the first region 12-1 of the second active layer.

[0108] (15) Forming a third conductive layer pattern. Forming a third conductive layer pattern may include: sequentially depositing a fourth insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; patterning the third conductive film using a patterning process, such that the fourth insulating film forms a fourth insulating layer located on the side of the second semiconductor layer pattern away from the substrate, and the third conductive film forms a third conductive layer pattern located on the side of the fourth insulating layer away from the substrate, as shown in Figures 10A and 10B, where Figure 10B is a planar schematic diagram of the third conductive layer in Figure 10A. The third conductive layer may be referred to as a third gate metal (GATE3) layer. The third conductive layer pattern may include at least a first initial signal line 41, a second initial signal line 42, a third initial signal line 43, and a third scan signal line 44.

[0109] In some exemplary embodiments, the third scan signal line 44, the third initial signal line 43, the first initial signal line 41, and the second initial signal line 42 can be arranged sequentially along the second direction Y, and can all be lines extending along the first direction X. The orthographic projection of the third scan signal line 44 onto the plane of the substrate at least partially overlaps with the orthographic projection of the first scan signal line 31 onto the plane of the substrate. For example, the orthographic projection of the third scan signal line 44 onto the plane of the substrate can be located within the orthographic projection of the first scan signal line 31 onto the plane of the substrate. The orthographic projection of the third scan signal line 44 onto the plane of the substrate at least partially overlaps with the orthographic projection of the channel region of the second active layer onto the plane of the substrate. The overlapping portion of the orthographic projection of the third scan signal line 44 and the channel region of the second active layer can serve as the gate electrode of the second transistor T2, which can be a transistor with a dual-gate structure. Both the third scan signal line 44 and the first scan signal line 31 can transmit signals to the second transistor T2.

[0110] In some exemplary embodiments, the orthographic projection of the third initial signal line 43 onto the plane of the substrate at least partially overlaps with the orthographic projection of the light-emitting signal line 23 onto the plane of the substrate. For example, the orthographic projection of the third initial signal line 43 onto the plane of the substrate may be located within the orthographic projection of the light-emitting signal line 23 onto the plane of the substrate.

[0111] In some exemplary embodiments, the orthographic projection of the first initial signal line 41 onto the plane of the substrate at least partially overlaps with the orthographic projection of the second reference signal line 24 onto the plane of the substrate. For example, the orthographic projection of the first initial signal line 41 onto the plane of the substrate may be located within the orthographic projection of the second reference signal line 24 onto the plane of the substrate.

[0112] In some exemplary embodiments, the orthographic projection of the second initial signal line 42 onto the plane of the substrate at least partially overlaps with the orthographic projection of the first reference signal line 25 onto the plane of the substrate. For example, the orthographic projection of the second initial signal line 42 onto the plane of the substrate may lie within the orthographic projection of the first reference signal line 25 onto the plane of the substrate.

[0113] (16) Forming a fifth insulating layer pattern. Forming a fifth insulating layer pattern may include: depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, and patterning the fifth insulating film by a patterning process so that the fifth insulating film forms a fifth insulating layer located on the side of the third conductive layer pattern away from the substrate, as shown in FIG11. Multiple vias may be provided on the fifth insulating layer.

[0114] In some exemplary embodiments, the plurality of vias in the display substrate may include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, and a twentieth via V20.

[0115] In some exemplary embodiments, the orthographic projection of the first via V1 onto the plane of the substrate at least partially overlaps with the orthographic projection of the first region 14-1 of the fourth active layer onto the plane of the substrate. For example, the orthographic projection of the first via V1 onto the plane of the substrate may be within the range of the orthographic projection of the first region 14-1 of the fourth active layer onto the plane of the substrate. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer within the first via V1 are all etched away, exposing at least a portion of the surface of the first region 14-1 of the fourth active layer. The first via V1 is configured such that a subsequently formed first connection electrode can be connected to the first region 14-1 of the fourth active layer through the via.

[0116] In some exemplary embodiments, the orthographic projection of the second via V2 onto the plane of the substrate at least partially overlaps with the orthographic projection of the first region 12-1 of the second active layer onto the plane of the substrate. For example, the orthographic projection of the second via V2 onto the plane of the substrate may be within the range of the orthographic projection of the first region 12-1 of the second active layer onto the plane of the substrate. The fourth and fifth insulating layers within the second via V2 are etched away, exposing at least a portion of the surface of the first region 12-1 of the second active layer. The second via V2 is configured such that a subsequently formed second connection electrode can be connected to the first region 12-1 of the second active layer through the via.

[0117] In some exemplary embodiments, the orthographic projection of the third via V3 onto the plane of the substrate at least partially overlaps with the orthographic projection of the second region 12-2 of the second active layer onto the plane of the substrate. For example, the orthographic projection of the third via V3 onto the plane of the substrate may be within the range of the orthographic projection of the second region 12-2 of the second active layer onto the plane of the substrate. The fourth and fifth insulating layers within the third via V3 are etched away, exposing at least a portion of the surface of the second region 12-2 of the second active layer. The third via V3 is configured such that a subsequently formed third connection electrode can be connected to the second region 12-2 of the second active layer through this via.

[0118] In some exemplary embodiments, the orthographic projection of the fourth via V4 onto the plane of the substrate at least partially overlaps with the orthographic projection of the second region 13-2 of the third active layer (i.e., the first region 16-1 of the sixth active layer) onto the plane of the substrate. For example, the orthographic projection of the fourth via V4 onto the plane of the substrate may be within the range of the orthographic projection of the second region 13-2 of the third active layer onto the plane of the substrate. The first, second, third, fourth, and fifth insulating layers within the fourth via V4 are all etched away, exposing at least a portion of the surface of the second region 13-2 of the third active layer. The fourth via V4 is configured such that a subsequently formed third connection electrode can be connected to the second region 13-2 of the third active layer through this via.

[0119] In some exemplary embodiments, the orthographic projection of the fifth via V5 onto the plane of the substrate at least partially overlaps with the orthographic projection of the third initial signal line 43 onto the plane of the substrate. For example, the orthographic projection of the fifth via V5 onto the plane of the substrate may be within the range of the orthographic projection of the third initial signal line 43 onto the plane of the substrate. The fifth insulating layer within the fifth via V5 is etched away, exposing a portion of the surface of the third initial signal line 43. The fifth via V5 is configured such that a subsequently formed third auxiliary initial signal line can be connected to the third initial signal line 43 through the via.

[0120] In some exemplary embodiments, the orthographic projection of the sixth via V6 onto the plane of the substrate at least partially overlaps with the orthographic projection of the second region 16-2 of the sixth active layer (i.e., the second region 17-2 of the seventh active layer) onto the plane of the substrate. For example, the orthographic projection of the sixth via V6 onto the plane of the substrate may be within the range of the orthographic projection of the second region 16-2 of the sixth active layer onto the plane of the substrate. The first, second, third, fourth, and fifth insulating layers within the sixth via V6 are all etched away, exposing at least a portion of the surface of the second region 16-2 of the sixth active layer. The sixth via V6 is configured such that a subsequently formed fourth connection electrode can be connected to the second region 16-2 of the sixth active layer through this via.

[0121] In some exemplary embodiments, the orthographic projection of the seventh via V7 onto the plane of the substrate at least partially overlaps with the orthographic projection of the first initial signal line 41 onto the plane of the substrate. For example, the orthographic projection of the seventh via V7 onto the plane of the substrate may be within the range of the orthographic projection of the first initial signal line 41 onto the plane of the substrate. The fifth insulating layer within the seventh via V7 is etched away, exposing a portion of the surface of the first initial signal line 41. The seventh via V7 is configured such that a subsequently formed fifth connection electrode can be connected to the first initial signal line 41 through the via.

[0122] In some exemplary embodiments, the orthographic projection of the eighth via V8 onto the plane of the substrate at least partially overlaps with the orthographic projection of the first region 11-1 of the first active layer onto the plane of the substrate. For example, the orthographic projection of the eighth via V8 onto the plane of the substrate may be within the range of the orthographic projection of the first region 11-1 of the first active layer onto the plane of the substrate. The first, second, third, fourth, and fifth insulating layers within the eighth via V8 are all etched away, exposing at least a portion of the surface of the first region 11-1 of the first active layer. The eighth via V8 is configured such that a subsequently formed fifth connection electrode can be connected to the first region 11-1 of the first active layer through the via.

[0123] In some exemplary embodiments, the orthographic projection of the ninth via V9 onto the plane of the substrate at least partially overlaps with the orthographic projection of the second region 11-2 of the first active layer onto the plane of the substrate. For example, the orthographic projection of the ninth via V9 onto the plane of the substrate may be within the range of the orthographic projection of the second region 11-2 of the first active layer onto the plane of the substrate. The first, second, third, fourth, and fifth insulating layers within the ninth via V9 are all etched away, exposing at least a portion of the surface of the second region 11-2 of the first active layer. The ninth via V9 is configured such that a subsequently formed third connection electrode can be connected to the second region 11-2 of the first active layer through this via.

[0124] In some exemplary embodiments, the orthographic projection of the tenth via V10 onto the plane of the substrate at least partially overlaps with the orthographic projection of the second initial signal line 42 onto the plane of the substrate. For example, the orthographic projection of the tenth via V10 onto the plane of the substrate may be within the range of the orthographic projection of the second initial signal line 42 onto the plane of the substrate. The fifth insulating layer within the tenth via V10 is etched away, exposing a portion of the surface of the second initial signal line 42. The tenth via V10 is configured such that a subsequently formed sixth connection electrode can be connected to the second initial signal line 42 through the via.

[0125] In some exemplary embodiments, the orthographic projection of the eleventh via V11 onto the plane of the substrate at least partially overlaps with the orthographic projection of the first region 17-1 of the seventh active layer onto the plane of the substrate. For example, the orthographic projection of the eleventh via V11 onto the plane of the substrate may be within the range of the orthographic projection of the first region 17-1 of the seventh active layer onto the plane of the substrate. The first, second, third, fourth, and fifth insulating layers within the eleventh via V11 are all etched away, exposing at least a portion of the surface of the first region 17-1 of the seventh active layer. The eleventh via V11 is configured such that a subsequently formed sixth connection electrode can be connected to the first region 17-1 of the seventh active layer through the via.

[0126] In some exemplary embodiments, the orthographic projection of the twelfth via V12 onto the plane of the substrate at least partially overlaps with the orthographic projection of the first region 18-1 of the eighth active layer onto the plane of the substrate. For example, the orthographic projection of the twelfth via V12 onto the plane of the substrate may be within the range of the orthographic projection of the first region 18-1 of the eighth active layer onto the plane of the substrate. The first, second, third, fourth, and fifth insulating layers within the twelfth via V12 are all etched away, exposing at least a portion of the surface of the first region 18-1 of the eighth active layer. The twelfth via V12 is configured such that a subsequently formed seventh connection electrode can be connected to the first region 18-1 of the eighth active layer through this via. Two adjacent circuit units may share a single twelfth via V12.

[0127] In some exemplary embodiments, the orthographic projection of the thirteenth via V13 onto the plane of the substrate at least partially overlaps with the orthographic projection of the second region 18-2 of the eighth active layer onto the plane of the substrate. For example, the orthographic projection of the thirteenth via V13 onto the plane of the substrate may be within the range of the orthographic projection of the second region 18-2 of the eighth active layer onto the plane of the substrate. The first, second, third, fourth, and fifth insulating layers within the thirteenth via V13 are all etched away, exposing at least a portion of the surface of the second region 18-2 of the eighth active layer. The thirteenth via V13 is configured such that a subsequently formed eighth connection electrode can be connected to the second region 18-2 of the eighth active layer through this via.

[0128] In some exemplary embodiments, the orthographic projection of the fourteenth via V14 onto the plane of the substrate at least partially overlaps with the orthographic projection of the first region 15-1 of the fifth active layer onto the plane of the substrate. For example, the orthographic projection of the fourteenth via V14 onto the plane of the substrate may be within the range of the orthographic projection of the first region 15-1 of the fifth active layer onto the plane of the substrate. The first, second, third, fourth, and fifth insulating layers within the fourteenth via V14 are all etched away, exposing at least a portion of the surface of the first region 15-1 of the fifth active layer. The fourteenth via V14 is configured such that subsequently formed auxiliary power lines can be connected to the first region 15-1 of the fifth active layer through this via. Two adjacent circuit units may share one fourteenth via V14.

[0129] In some exemplary embodiments, the orthographic projection of the fifteenth via V15 onto the plane of the substrate at least partially overlaps with the orthographic projection of the third initial signal line 43 onto the plane of the substrate. For example, the orthographic projection of the fifteenth via V15 onto the plane of the substrate may be within the range of the orthographic projection of the third initial signal line 43 onto the plane of the substrate. The fifth insulating layer within the fifteenth via V15 is etched away, exposing a portion of the surface of the third initial signal line 43. The fifteenth via V15 is configured such that a subsequently formed seventh connection electrode can be connected to the third initial signal line 43 through the via.

[0130] In some exemplary embodiments, the orthographic projection of the sixteenth via V16 onto the plane of the substrate at least partially overlaps with the orthographic projection of the first region 13-1 of the third active layer (i.e., the second region 15-2 of the fifth active layer) onto the plane of the substrate. For example, the orthographic projection of the sixteenth via V16 onto the plane of the substrate may be within the range of the orthographic projection of the first region 13-1 of the third active layer onto the plane of the substrate. The first, second, third, fourth, and fifth insulating layers within the sixteenth via V16 are all etched away, exposing at least a portion of the surface of the first region 13-1 of the third active layer. The sixteenth via V16 is configured such that a subsequently formed eighth connection electrode can be connected to the first region 13-1 of the third active layer through this via.

[0131] In some exemplary embodiments, the orthographic projection of the seventeenth via V17 onto the plane of the substrate at least partially overlaps with the orthographic projection of the second electrode 32 onto the plane of the substrate. For example, the orthographic projection of the seventeenth via V17 onto the plane of the substrate may be within the range of the orthographic projection of the second electrode 32 onto the plane of the substrate. The third, fourth, and fifth insulating layers within the seventeenth via V17 are etched away, exposing a portion of the surface of the second electrode 32. The seventeenth via V17 is configured such that subsequently formed auxiliary power lines can be connected to the second electrode 32 through this via. Two adjacent circuit units may share one seventeenth via V17.

[0132] In some exemplary embodiments, the orthographic projection of the eighteenth via V18 onto the plane of the substrate at least partially overlaps with the orthographic projection of the first electrode 21 onto the plane of the substrate. For example, the orthographic projection of the eighteenth via V18 onto the plane of the substrate may be within the range of the orthographic projection of the first electrode 21 onto the plane of the substrate. The second, third, fourth, and fifth insulating layers within the eighteenth via V18 are all etched away, exposing a portion of the surface of the first electrode 21. The eighteenth via V18 is configured such that a subsequently formed second connection electrode can be connected to the first electrode 21 through the via.

[0133] In some exemplary embodiments, the orthographic projection of the nineteenth via V19 onto the plane of the substrate at least partially overlaps with the orthographic projection of the first initial signal line 41 onto the plane of the substrate. For example, the orthographic projection of the nineteenth via V19 onto the plane of the substrate may be within the range of the orthographic projection of the first initial signal line 41 onto the plane of the substrate. The fifth insulating layer within the nineteenth via V19 is etched away, exposing a portion of the surface of the first initial signal line 41. The nineteenth via V19 is configured such that a subsequently formed first auxiliary initial signal line can be connected to the first initial signal line 41 through the via.

[0134] In some exemplary embodiments, the orthographic projection of the twentieth via V20 onto the plane of the substrate at least partially overlaps with the orthographic projection of the second initial signal line 42 onto the plane of the substrate. For example, the orthographic projection of the twentieth via V20 onto the plane of the substrate may be located within the range of the orthographic projection of the second initial signal line 42 onto the plane of the substrate. The fifth insulating layer within the twentieth via V20 is etched away, exposing a portion of the surface of the second initial signal line 42. The twentieth via V20 is configured such that a subsequently formed second auxiliary initial signal line can be connected to the second initial signal line 42 through the via.

[0135] (17) Forming a fourth conductive layer pattern. Forming a fourth conductive layer pattern may include: depositing a fourth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the fourth conductive thin film through a patterning process so that the fourth conductive thin film forms a fourth conductive layer pattern located on the side of the fifth insulating layer pattern away from the substrate, as shown in Figures 12A and 12B, where Figure 12B is a planar schematic diagram of the fourth conductive layer in Figure 12A. The fourth conductive layer may be referred to as a first source / drain metal (SD1) layer. The fourth conductive layer pattern may include at least a first connecting electrode 51, a second connecting electrode 52, a third connecting electrode 53, a fourth connecting electrode 54, a fifth connecting electrode 55, a sixth connecting electrode 56, a seventh connecting electrode 57, an eighth connecting electrode 58, an auxiliary power line 59, a first auxiliary initial signal line 61, a second auxiliary initial signal line 62, and a third auxiliary initial signal line 63.

[0136] In some exemplary embodiments, the first connection electrode 51 may be located on one side of the second scan signal line 22 along the second direction Y. The shape of the first connection electrode 51 may be rectangular; for example, the shape of the first connection electrode 51 may be a rounded rectangle. The orthographic projection of the first connection electrode 51 onto the plane of the substrate may at least partially overlap with the orthographic projection of the first region 14-1 of the fourth active layer onto the plane of the substrate. The orthographic projection of the first connection electrode 51 onto the plane of the substrate may at least partially overlap with the orthographic projection of the first via V1 onto the plane of the substrate; for example, the orthographic projection of the first connection electrode 51 onto the plane of the substrate may include the orthographic projection of the first via V1 onto the plane of the substrate, and the first connection electrode 51 may be connected to the first region 14-1 of the fourth active layer through the first via V1.

[0137] In some exemplary embodiments, the second connecting electrode 52 may be located on one side of the light-emitting signal line 23 along the second direction Y. The shape of the second connecting electrode 52 may be rectangular; for example, the shape of the second connecting electrode 52 may be a rounded rectangle. The orthographic projection of the second connecting electrode 52 onto the plane of the substrate may at least partially overlap with the orthographic projection of the first region 12-1 of the second active layer onto the plane of the substrate. The orthographic projection of the second connecting electrode 52 onto the plane of the substrate may at least partially overlap with the orthographic projection of the second via V2 onto the plane of the substrate; for example, the orthographic projection of the second connecting electrode 52 onto the plane of the substrate may include the orthographic projection of the second via V2 onto the plane of the substrate, and the second connecting electrode 52 may be connected to the first region 12-1 of the second active layer through the second via V2. The orthographic projection of the second connecting electrode 52 onto the plane of the substrate can at least partially overlap with the orthographic projection of the first electrode plate 21 onto the plane of the substrate. The orthographic projection of the second connecting electrode 52 onto the plane of the substrate can at least partially overlap with the orthographic projection of the eighteenth via V18 onto the plane of the substrate. For example, the orthographic projection of the second connecting electrode 52 onto the plane of the substrate may include the orthographic projection of the eighteenth via V18 onto the plane of the substrate. The second connecting electrode 52 can be connected to the first electrode plate 21 through the eighteenth via V18.

[0138] In some exemplary embodiments, the third connecting electrode 53 may be located on one side of the light-emitting signal line 23 along the second direction Y. The shape of the third connecting electrode 53 may be rectangular; for example, the shape of the third connecting electrode 53 may be a rounded rectangle. The orthographic projection of the third connecting electrode 53 onto the plane of the substrate may at least partially overlap with the orthographic projection of the second region 12-2 of the second active layer onto the plane of the substrate. The orthographic projection of the third connecting electrode 53 onto the plane of the substrate may at least partially overlap with the orthographic projection of the third via V3 onto the plane of the substrate; for example, the orthographic projection of the third connecting electrode 53 onto the plane of the substrate may include the orthographic projection of the third via V3 onto the plane of the substrate, and the third connecting electrode 53 may be connected to the second region 12-2 of the second active layer through the third via V3. The orthographic projection of the third connecting electrode 53 onto the plane of the substrate can at least partially overlap with the orthographic projection of the second region 13-2 of the third active layer (i.e., the first region 16-1 of the sixth active layer) onto the plane of the substrate. The orthographic projection of the third connecting electrode 53 onto the plane of the substrate can also at least partially overlap with the orthographic projection of the fourth via V4 onto the plane of the substrate. For example, the orthographic projection of the third connecting electrode 53 onto the plane of the substrate may include the orthographic projection of the fourth via V4 onto the plane of the substrate, and the third connecting electrode 53 can be connected to the second region 13-2 of the third active layer through the fourth via V4. The orthographic projection of the third connecting electrode 53 onto the plane of the substrate can at least partially overlap with the orthographic projection of the second region 11-2 of the first active layer of another first circuit unit onto the plane of the substrate. The orthographic projection of the third connecting electrode 53 onto the plane of the substrate at least partially overlaps with the orthographic projection of the ninth via V9 onto the plane of the substrate. For example, the orthographic projection of the third connecting electrode 53 onto the plane of the substrate may include the orthographic projection of the ninth via V9 onto the plane of the substrate, and the third connecting electrode 53 can be connected to the second region 11-2 of the first active layer of another first circuit unit via the ninth via V9. The other first circuit unit is located on one side of the first circuit unit in the second direction Y in the figure.

[0139] In some exemplary embodiments, the fourth connecting electrode 54 may be located on one side of the second reference signal line 24 along the second direction Y, and the orthographic projection of the fourth connecting electrode 54 onto the plane of the substrate at least partially overlaps with the orthographic projection of the third initial signal line 43 onto the plane of the substrate. The shape of the fourth connecting electrode 54 may be rectangular; for example, the shape of the fourth connecting electrode 54 may be a rounded rectangle. The orthographic projection of the fourth connecting electrode 54 onto the plane of the substrate may at least partially overlap with the orthographic projection of the second region 16-2 of the sixth active layer (that is, the second region 17-2 of the seventh active layer) onto the plane of the substrate. The orthographic projection of the fourth connecting electrode 54 onto the plane of the substrate may at least partially overlap with the orthographic projection of the sixth via V6 onto the plane of the substrate; for example, the orthographic projection of the fourth connecting electrode 54 onto the plane of the substrate may include the orthographic projection of the sixth via V6 onto the plane of the substrate, and the fourth connecting electrode 54 may be connected to the second region 16-2 of the sixth active layer through the sixth via V6.

[0140] In some exemplary embodiments, the fifth connecting electrode 55 may be located between the light-emitting signal line 23 and the first reference signal line 25. The fifth connecting electrode 55 may be rectangular in shape; for example, it may be a rounded rectangle. The orthographic projection of the fifth connecting electrode 55 onto the plane of the substrate may at least partially overlap with the orthographic projection of the first initial signal line 41 onto the plane of the substrate. The orthographic projection of the fifth connecting electrode 55 onto the plane of the substrate may at least partially overlap with the orthographic projection of the seventh via V7 onto the plane of the substrate; for example, the orthographic projection of the fifth connecting electrode 55 onto the plane of the substrate may include the orthographic projection of the seventh via V7 onto the plane of the substrate, and the fifth connecting electrode 55 may be connected to the first initial signal line 41 through the seventh via V7. The orthographic projection of the fifth connecting electrode 55 onto the plane of the substrate can at least partially overlap with the orthographic projection of the first region 11-1 of the first active layer onto the plane of the substrate. The orthographic projection of the fifth connecting electrode 55 onto the plane of the substrate can at least partially overlap with the orthographic projection of the eighth via V8 onto the plane of the substrate. For example, the orthographic projection of the fifth connecting electrode 55 onto the plane of the substrate may include the orthographic projection of the eighth via V8 onto the plane of the substrate. The fifth connecting electrode 55 can be connected to the first region 11-1 of the first active layer through the eighth via V8.

[0141] In some exemplary embodiments, the sixth connecting electrode 56 may be located on the side opposite to the second direction Y of the second reference signal line 24. The shape of the sixth connecting electrode 56 may be rectangular; for example, the shape of the sixth connecting electrode 56 may be a rounded rectangle. The orthographic projection of the sixth connecting electrode 56 onto the plane of the substrate may at least partially overlap with the orthographic projection of the second initial signal line 42 onto the plane of the substrate. The orthographic projection of the sixth connecting electrode 56 onto the plane of the substrate may at least partially overlap with the orthographic projection of the tenth via V10 onto the plane of the substrate; for example, the orthographic projection of the sixth connecting electrode 56 onto the plane of the substrate may include the orthographic projection of the tenth via V10 onto the plane of the substrate, and the sixth connecting electrode 56 may be connected to the second initial signal line 42 through the tenth via V10. The orthographic projection of the sixth connecting electrode 56 onto the plane of the substrate can at least partially overlap with the orthographic projection of the first region 17-1 of the seventh active layer onto the plane of the substrate. The orthographic projection of the sixth connecting electrode 56 onto the plane of the substrate can at least partially overlap with the orthographic projection of the eleventh via V11 onto the plane of the substrate. For example, the orthographic projection of the sixth connecting electrode 56 onto the plane of the substrate may include the orthographic projection of the eleventh via V11 onto the plane of the substrate. The sixth connecting electrode 56 can be connected to the first region 17-1 of the seventh active layer through the eleventh via V11.

[0142] In some exemplary embodiments, the seventh connecting electrode 57 may be located between the first reference signal line 25 and the first electrode plate 21. The shape of the seventh connecting electrode 57 may be arc-shaped; for example, the shape of the seventh connecting electrode 57 may be an arc shape. The orthographic projection of the seventh connecting electrode 57 onto the plane of the substrate may at least partially overlap with the orthographic projection of the third initial signal line 43 onto the plane of the substrate. The orthographic projection of the seventh connecting electrode 57 onto the plane of the substrate may at least partially overlap with the orthographic projection of the fifteenth via V15 onto the plane of the substrate; for example, the orthographic projection of the seventh connecting electrode 57 onto the plane of the substrate may include the orthographic projection of the fifteenth via V15 onto the plane of the substrate, and the seventh connecting electrode 57 may be connected to the third initial signal line 43 through the fifteenth via V15. The orthographic projection of the seventh connecting electrode 57 onto the plane of the substrate can at least partially overlap with the orthographic projection of the first region 18-1 of the eighth active layer onto the plane of the substrate. The orthographic projection of the seventh connecting electrode 57 onto the plane of the substrate can at least partially overlap with the orthographic projection of the twelfth via V12 onto the plane of the substrate. For example, the orthographic projection of the seventh connecting electrode 57 onto the plane of the substrate may include the orthographic projection of the twelfth via V12 onto the plane of the substrate. The seventh connecting electrode 57 can be connected to the first region 18-1 of the eighth active layer through the twelfth via V12.

[0143] In some exemplary embodiments, the eighth connection electrode 58 may be located between the second reference signal line 24 and the first electrode plate 21. The shape of the eighth connection electrode 58 may be rectangular; for example, the shape of the eighth connection electrode 58 may be a rounded rectangle. The orthographic projection of the eighth connection electrode 58 onto the plane of the substrate may at least partially overlap with the orthographic projection of the first region 13-1 of the third active layer (that is, the second region 15-2 of the fifth active layer) onto the plane of the substrate. The orthographic projection of the eighth connection electrode 58 onto the plane of the substrate may at least partially overlap with the orthographic projection of the sixteenth via V16 onto the plane of the substrate; for example, the orthographic projection of the eighth connection electrode 58 onto the plane of the substrate may include the orthographic projection of the sixteenth via V16 onto the plane of the substrate, and the eighth connection electrode 58 may be connected to the first region 13-1 of the third active layer through the sixteenth via V16. The orthographic projection of the eighth connecting electrode 58 onto the plane of the substrate can at least partially overlap with the orthographic projection of the second region 18-2 of the eighth active layer onto the plane of the substrate. The orthographic projection of the eighth connecting electrode 58 onto the plane of the substrate can at least partially overlap with the orthographic projection of the thirteenth via V13 onto the plane of the substrate. For example, the orthographic projection of the eighth connecting electrode 58 onto the plane of the substrate may include the orthographic projection of the thirteenth via V13 onto the plane of the substrate. The eighth connecting electrode 58 can be connected to the second region 18-2 of the eighth active layer through the thirteenth via V13.

[0144] In some exemplary embodiments, the auxiliary power line 59 may be located between the first initial signal line 41 and the third scan signal line 44. The orthographic projection of the auxiliary power line 59 onto the plane of the substrate may at least partially overlap with the orthographic projection of the first region 15-1 of the fifth active layer onto the plane of the substrate. The orthographic projection of the auxiliary power line 59 onto the plane of the substrate may at least partially overlap with the orthographic projection of the fourteenth via V14 onto the plane of the substrate. For example, the orthographic projection of the auxiliary power line 59 onto the plane of the substrate may include the orthographic projection of the fourteenth via V14 onto the plane of the substrate, and the auxiliary power line 59 may be connected to the first region 15-1 of the fifth active layer through the fourteenth via V14.

[0145] In some exemplary embodiments, the orthographic projection of the auxiliary power line 59 onto the plane of the substrate may at least partially overlap with the orthographic projection of the second electrode plate 32 onto the plane of the substrate. The orthographic projection of the auxiliary power line 59 onto the plane of the substrate may at least partially overlap with the orthographic projection of the seventeenth via V17 onto the plane of the substrate. For example, the orthographic projection of the auxiliary power line 59 onto the plane of the substrate may include the orthographic projection of the seventeenth via V17 onto the plane of the substrate, and the auxiliary power line 59 may be connected to the second electrode plate 32 through the seventeenth via V17.

[0146] In some exemplary embodiments, the orthographic projection of the auxiliary power line 59 onto the plane of the substrate does not overlap with the orthographic projection of the first scan signal line 31 onto the plane of the substrate, and the orthographic projection of the auxiliary power line 59 onto the plane of the substrate does not overlap with the orthographic projection of the third scan signal line 44 onto the plane of the substrate, and the orthographic projection of the auxiliary power line 59 onto the plane of the substrate does not overlap with the orthographic projection of the second scan signal line 22 onto the plane of the substrate. This can avoid the problem of short circuits in signal line connections caused by excessive electron accumulation and improve the electrical connection reliability of the display substrate.

[0147] In some exemplary embodiments, the auxiliary power cord 59 may include a first portion 59-1 and a second portion 59-2 connected to each other. The first portion 59-1 may be a strip extending along a second direction Y, and may include a first end and a second end positioned opposite each other. The second portion 59-2 may be rectangular, extending along a direction different from both the first direction X and the second direction Y, and may include a first end and a second end positioned opposite each other. The first end of the second portion 59-2 may be connected to the second end of the first portion 59-1, and the second end of the second portion 59-2 may be located away from the second end of the first portion 59-1. In some possible embodiments, the second portion 59-2 may be located on the side of the first portion 59-1 opposite to the first direction X.

[0148] In some exemplary embodiments, there may be an included angle α between the first part 59-1 and the second part 59-2. The included angle α may be greater than 90 degrees and less than 180 degrees, which can avoid stress concentration in the area where the first part 59-1 and the second part 59-2 intersect, and can improve the reliability of the auxiliary power line.

[0149] In some exemplary embodiments, the first auxiliary initial signal line 61, the second auxiliary initial signal line 62, and the third auxiliary initial signal line 63 may all be lines extending along a second direction Y. For example, the first auxiliary initial signal line 61, the second auxiliary initial signal line 62, and the third auxiliary initial signal line 63 may be arranged at equal intervals along a first direction X. The second auxiliary initial signal line 62 may be located between the first auxiliary initial signal line 61 and the third auxiliary initial signal line 63.

[0150] In some exemplary embodiments, the orthographic projection of the first auxiliary initial signal line 61 onto the plane of the substrate at least partially overlaps with the orthographic projection of the nineteenth via V19 onto the plane of the substrate. For example, the orthographic projection of the first auxiliary initial signal line 61 onto the plane of the substrate includes the orthographic projection of the nineteenth via V19 onto the plane of the substrate, and the first auxiliary initial signal line 61 can be connected to the first initial signal line 41 through the nineteenth via V19 to form a mesh structure for transmitting the first initial signal. This not only effectively reduces the resistance of the first initial signal line and reduces the voltage drop of the first initial signal, but also effectively improves the uniformity of the first initial signal in the display substrate, effectively improving display uniformity and enhancing display quality.

[0151] In some exemplary embodiments, the orthographic projection of the second auxiliary initial signal line 62 onto the plane of the substrate at least partially overlaps with the orthographic projection of the twentieth via V20 onto the plane of the substrate. For example, the orthographic projection of the second auxiliary initial signal line 62 onto the plane of the substrate includes the orthographic projection of the twentieth via V20 onto the plane of the substrate, and the second auxiliary initial signal line 62 can be connected to the second initial signal line 42 through the twentieth via V20 to form a mesh structure for transmitting the second initial signal. This not only effectively reduces the resistance of the second initial signal line and reduces the voltage drop of the second initial signal, but also effectively improves the uniformity of the second initial signal in the display substrate, effectively improving display uniformity and enhancing display quality.

[0152] In some exemplary embodiments, the orthographic projection of the third auxiliary initial signal line 63 onto the plane of the substrate at least partially overlaps with the orthographic projection of the fifth via V5 onto the plane of the substrate. For example, the orthographic projection of the third auxiliary initial signal line 63 onto the plane of the substrate includes the orthographic projection of the fifth via V5 onto the plane of the substrate, and the third auxiliary initial signal line 63 can be connected to the third initial signal line 43 through the fifth via V5, forming a mesh structure for transmitting the third initial signal. This not only effectively reduces the resistance of the third initial signal line and reduces the voltage drop of the third initial signal, but also effectively improves the uniformity of the third initial signal in the display substrate, effectively improving display uniformity and enhancing display quality.

[0153] (18) Forming a sixth insulating layer pattern. Forming a sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed, and patterning the sixth insulating film using a patterning process so that the sixth insulating film forms a sixth insulating layer pattern located on the side of the fourth conductive layer pattern away from the substrate, as shown in FIG13. Multiple vias may be provided on the sixth insulating layer.

[0154] In some exemplary embodiments, the plurality of vias in the display substrate may include at least: a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23.

[0155] In some exemplary embodiments, the orthographic projection of the twenty-first via V21 onto the plane of the substrate at least partially overlaps with the orthographic projection of the first connecting electrode 51 onto the plane of the substrate. For example, the orthographic projection of the twenty-first via V21 onto the plane of the substrate may lie within the orthographic projection of the first connecting electrode 51 onto the plane of the substrate. The sixth insulating layer within the twenty-first via V21 is etched away, exposing a portion of the surface of the first connecting electrode 51. The twenty-first via V21 is configured such that subsequently formed data signal lines can be connected to the first connecting electrode 51 through the via.

[0156] In some exemplary embodiments, the orthographic projection of the second-second via V22 onto the plane of the substrate at least partially overlaps with the orthographic projection of the auxiliary power line 59 onto the plane of the substrate. For example, the orthographic projection of the second-second via V22 onto the plane of the substrate may lie within the orthographic projection of the auxiliary power line 59 onto the plane of the substrate. The sixth insulating layer within the second-second via V22 is etched away, exposing a portion of the surface of the auxiliary power line 59. The second-second via V22 is configured such that a subsequently formed first power line can be connected to the auxiliary power line 59 through the via.

[0157] In some exemplary embodiments, the orthographic projection of the second via V22 onto the plane of the substrate at least partially overlaps with the orthographic projection of the second portion 59-2 onto the plane of the substrate. For example, the orthographic projection of the second via V22 onto the plane of the substrate may lie within the orthographic projection of the second portion 59-2 onto the plane of the substrate. The second via V22 is configured such that a subsequently formed first power line can be connected to the second portion 59-2 of the auxiliary power line 59 through the via.

[0158] In some exemplary embodiments, the orthographic projection of the 23rd via V23 onto the plane of the substrate at least partially overlaps with the orthographic projection of the fourth connecting electrode 54 onto the plane of the substrate. For example, the orthographic projection of the 23rd via V23 onto the plane of the substrate may lie within the orthographic projection of the fourth connecting electrode 54 onto the plane of the substrate. The sixth insulating layer within the 23rd via V23 is etched away, exposing a portion of the surface of the fourth connecting electrode 54. The 23rd via V23 is configured such that a subsequently formed anode connecting electrode can be connected to the fourth connecting electrode 54 through the via.

[0159] (19) Forming a fifth conductive layer pattern. Forming a fifth conductive layer pattern may include: depositing a fifth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the fifth conductive thin film through a patterning process so that the fifth conductive thin film forms a fifth conductive layer pattern located on the side of the sixth insulating layer pattern away from the substrate, as shown in Figures 14A and 14B, where Figure 14B is a planar schematic diagram of the fifth conductive layer in Figure 14A. The fifth conductive layer may be referred to as the second source / drain metal (SD2) layer. The fifth conductive layer pattern may at least include a data signal line 71, a first power line 72, an anode connection electrode 73, and a shielding electrode 74.

[0160] In some exemplary embodiments, the data signal line 71 can be a line extending along the second direction Y. The orthographic projection of the data signal line 71 onto the plane of the substrate can at least partially overlap with the orthographic projection of the twenty-first via V21 onto the plane of the substrate. For example, the orthographic projection of the data signal line 71 onto the plane of the substrate can include the orthographic projection of the twenty-first via V21 onto the plane of the substrate. The data signal line 71 can be connected to the first connection electrode 51 through the twenty-first via V21. Since the first connection electrode 51 is connected to the first region of the fourth active layer, the connection between the data signal line 71 and the first region of the fourth active layer is also realized.

[0161] In some exemplary embodiments, the first power line 72 may be rectangular in shape, extending along the second direction Y. The orthographic projection of the first power line 72 onto the plane of the substrate may at least partially overlap with the orthographic projection of the twenty-second via V22 onto the plane of the substrate. For example, the orthographic projection of the first power line 72 onto the plane of the substrate may include the orthographic projection of the twenty-second via V22 onto the plane of the substrate, and the first power line 72 may be connected to the auxiliary power line 59 through the twenty-second via V22.

[0162] In some exemplary embodiments, the orthographic projection of the first power line 72 onto the plane of the substrate does not overlap with the orthographic projection of the first portion 59-1 onto the plane of the substrate, and the orthographic projection of the data signal line 71 onto the plane of the substrate does not overlap with the orthographic projection of the first portion 59-1 onto the plane of the substrate. This can prevent parasitic capacitance from being generated between the first power line and the first portion of the auxiliary power line, and between the data signal line and the first portion of the auxiliary power line, thereby improving the display performance of the display substrate.

[0163] In some exemplary embodiments, the anode connection electrode 73 may be rectangular in shape; for example, the anode connection electrode 73 may be a rounded rectangle. The orthographic projection of the anode connection electrode 73 onto the plane of the substrate at least partially overlaps with the orthographic projection of the twenty-third via V23 onto the plane of the substrate. For example, the orthographic projection of the anode connection electrode 73 onto the plane of the substrate may include the orthographic projection of the twenty-third via V23 onto the plane of the substrate. The anode connection electrode 73 may be connected to the fourth connection electrode 54 through the twenty-third via V23. The anode connection electrode 73 may be configured to be anode-connected to a subsequently formed light-emitting device.

[0164] In some exemplary embodiments, the shielding electrode 74 may be located on one side of the second electrode plate 32 in the second direction Y. The shielding electrode 74 may be rectangular in shape; for example, the shielding electrode 74 may be a rounded rectangle. The orthographic projection of the shielding electrode 74 onto the plane of the substrate at least partially overlaps with the orthographic projection of the second active layer 12 of the second transistor T2 onto the plane of the substrate. For example, the orthographic projection of the shielding electrode 74 onto the plane of the substrate may include the orthographic projection of the second active layer 12 of the second transistor T2 onto the plane of the substrate. For example, the orthographic projection of the shielding electrode 74 onto the plane of the substrate may include the orthographic projection of the second active layer 12 of the second transistor T2 onto the plane of the substrate, and the area of ​​the orthographic projection of the shielding electrode 74 onto the plane of the substrate is larger than the area of ​​the orthographic projection of the second active layer 12 of the second transistor T2 onto the plane of the substrate.

[0165] In some exemplary embodiments, the orthographic projection of the shielding electrode 74 onto the plane of the substrate at least partially overlaps with the orthographic projection of the node between the two gate electrodes of the dual-gate transistor (i.e., the second transistor) onto the plane of the substrate. For example, the orthographic projection of the shielding electrode 74 onto the plane of the substrate may include the orthographic projection of the node between the two gate electrodes of the dual-gate transistor (i.e., the second transistor) onto the plane of the substrate. By utilizing the shielding electrode, embodiments of this disclosure can effectively shield the node between the two gate electrodes of the dual-gate transistor, ensuring the normal operation of the pixel driving circuit and improving the display effect.

[0166] In some exemplary embodiments, the orthographic projection of the shielding electrode 74 onto the plane of the substrate at least partially overlaps with the orthographic projection of the active layer between the two gate electrodes of the dual-gate transistor (i.e., the second transistor) onto the plane of the substrate. For example, the orthographic projection of the shielding electrode 74 onto the plane of the substrate may include the orthographic projection of the active layer between the two gate electrodes of the dual-gate transistor (i.e., the second transistor) onto the plane of the substrate.

[0167] In some exemplary embodiments, the shielding electrode 74 and the first power line 72 can be an integral structure interconnected. Since the first power line has a constant potential, by connecting the shielding electrode to the first power line, the node between the two gate electrodes of the dual-gate transistor can be effectively shielded, ensuring the normal operation of the pixel driving circuit and improving the display effect.

[0168] (20) Forming a seventh insulating layer pattern. Forming a seventh insulating layer pattern may include: depositing a seventh insulating film on the substrate on which the aforementioned pattern is formed, and patterning the seventh insulating film using a patterning process, so that the seventh insulating film forms a seventh insulating layer pattern located on the side of the fifth conductive layer pattern away from the substrate, as shown in FIG15. A plurality of vias are provided on the seventh insulating layer. In some exemplary embodiments, the plurality of vias in the display substrate may include at least a thirty-first via V31.

[0169] In some exemplary embodiments, the orthographic projection of the 31st via V31 onto the plane of the substrate at least partially overlaps with the orthographic projection of the anode connection electrode 73 onto the plane of the substrate. For example, the orthographic projection of the 31st via V31 onto the plane of the substrate may lie within the orthographic projection of the anode connection electrode 73 onto the plane of the substrate. The seventh insulating layer within the 31st via V31 is etched away, exposing a portion of the surface of the anode connection electrode 73. The 31st via V31 is configured such that the anode of a subsequently formed light-emitting device can be connected to the anode connection electrode 73 through the via.

[0170] (21) Forming a sixth conductive layer pattern. Forming a sixth conductive layer pattern may include: depositing a sixth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the sixth conductive thin film using a patterning process, so that the sixth conductive thin film forms a sixth conductive layer pattern located on the side of the seventh insulating layer pattern away from the substrate, as shown in Figures 16A and 16B, where Figure 16B is a planar schematic diagram of the sixth conductive layer in Figure 16A. In embodiments of this disclosure, the sixth conductive layer may also be referred to as an anode layer. The sixth conductive layer pattern may at least include the anode 81 of the light-emitting device.

[0171] In some exemplary embodiments, the orthographic projection of the anode 81 onto the plane of the substrate at least partially overlaps with the orthographic projection of the shielding electrode 74 onto the plane of the substrate. The anode 81 and the shielding electrode 74 can form a parasitic capacitance. The anode 81 can be the anode of the green light-emitting device. During the operation of the display substrate, before the light-emitting signal emits light, the anode of the green light-emitting device is reset through the second initial signal line, forming a negative charge on one plate of the parasitic capacitance, i.e., the anode of the green light-emitting device. When current flows into the first power line, the negative charge on the anode is neutralized first, and then the storage capacitor is charged. This delays the activation of the green light-emitting device, thereby allowing light-emitting devices of different colors to activate synchronously to form a uniform white.

[0172] In some exemplary embodiments, the orthographic projection of the anode 81 onto the plane of the substrate at least partially overlaps with the orthographic projection of the anode connecting electrode 73 onto the plane of the substrate. The orthographic projection of the anode 81 onto the plane of the substrate at least partially overlaps with the orthographic projection of the thirty-first via V31 onto the plane of the substrate. For example, the orthographic projection of the anode 81 onto the plane of the substrate may include the orthographic projection of the thirty-first via V31 onto the plane of the substrate. The anode 81 can be connected to the anode connecting electrode 73 through the thirty-first via V31.

[0173] In some exemplary embodiments, the anode 81 may include a connecting portion 81-1 and an extension portion 81-2 connected together. The connecting portion 81-1 may be elongated, and the extension portion 81-2 may be rectangular. The orthographic projection of the connecting portion 81-1 onto the plane of the substrate may at least partially overlap with the orthographic projection of the thirty-first via V31 onto the plane of the substrate. The orthographic projection of the connecting portion 81-1 onto the plane of the substrate may include the orthographic projection of the thirty-first via V31 onto the plane of the substrate. The connecting portion 81-1 may be connected to the anode connecting electrode 73 through the thirty-first via V31. The orthographic projection of the extension portion 81-2 onto the plane of the substrate may at least partially overlap with the orthographic projection of the shielding electrode 74 onto the plane of the substrate. The extension portion 81-2 and the shielding electrode 74 may form a storage capacitor.

[0174] (22) Forming a pixel definition layer pattern. Forming a pixel definition layer pattern may include: depositing an eighth insulating film on the substrate on which the aforementioned pattern is formed, and patterning the eighth insulating film through a patterning process so that the eighth insulating film forms a pixel definition layer pattern on the side of the sixth conductive layer pattern away from the substrate, as shown in FIG17. The pixel definition layer pattern may include at least one pixel opening region 91. The pixel opening region 91 and the anode 81 may be arranged in a one-to-one correspondence. For example, the orthographic projection of the pixel opening region 91 onto the plane of the substrate may be located within the orthographic projection of the corresponding anode 81 onto the plane of the substrate. Light emitted by the light-emitting device can exit the display substrate through the corresponding pixel opening region.

[0175] The preparation process of this disclosure is well compatible with existing preparation processes. The process is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0176] In some exemplary embodiments, the materials of the first conductive layer, second conductive layer, third conductive layer, fourth conductive layer, fifth conductive layer, and sixth conductive layer can be metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The materials of the first insulating layer, second insulating layer, third insulating layer, fourth insulating layer, fifth insulating layer, sixth insulating layer, and seventh insulating layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), or they can be one or more of epoxy resin, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, furan resin, organosilicon resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, or polyether resin. They can be single-layer, multi-layer, or composite layers. The active layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc. That is, this disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, or organic technology. The structures and fabrication processes described above in the embodiments of this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structures and patterning processes can be modified and added or reduced according to actual needs, and this disclosure does not limit the scope of the invention.

[0177] Existing display substrates suffer from the problem of overlapping or close proximity between "Y"-shaped auxiliary power lines and signal lines. This "Y"-shaped auxiliary power line is prone to short-circuiting after power is applied. In contrast, the auxiliary power line provided in this disclosure, due to its improved shape, reduces the area of ​​overlap or close proximity between the auxiliary power line and signal lines by half compared to the "Y"-shaped auxiliary power line. Therefore, it reduces the probability of short-circuiting and improves display quality.

[0178] This disclosure also provides a display device, which includes the display substrate described in any of the foregoing embodiments. The display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator; this disclosure is not limited thereto.

[0179] While the embodiments disclosed in this invention have been described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. It should be noted that the above embodiments or implementation methods are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the content specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. A display substrate, comprising a substrate, a driving circuit layer disposed on the substrate, and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate; the driving circuit layer comprises at least one first circuit unit, at least one second circuit unit, at least one signal line, at least one auxiliary power supply line, and at least one first power supply line, at least part of the auxiliary power supply lines and the first power supply lines are disposed in groups and electrically connected; the at least one signal line extends along a first direction, the at least one first power supply line extends along a second direction, the first direction intersects the second direction and the plane formed thereby is parallel to the plane in which the substrate lies, and the at least one signal line is located on one side of the at least one auxiliary power supply line along the second direction; a projection of the at least one auxiliary power supply line on the plane in which the substrate lies and a projection of the at least one signal line on the plane in which the substrate lies do not overlap. The first circuit unit comprises a first pixel driving circuit, the second circuit unit comprises a second pixel driving circuit, at least one of the first pixel driving circuits and at least one of the second pixel driving circuits are electrically connected to the same auxiliary power supply line, and the first power supply line is configured to provide a constant level signal to the first pixel driving circuit and the second pixel driving circuit; wherein, The at least one auxiliary power supply line comprises a first portion and a second portion connected to each other; the first portion comprises first and second ends disposed opposite to each other, and the first portion extends along the second direction; the second portion comprises first and second ends disposed opposite to each other, the first end of the second portion is connected to the second end of the first portion, and the second end of the second portion is away from the second end of the first portion; in the plane in which the substrate lies, there is a minimum distance between the second end of the second portion and the at least one signal line, and the minimum distance is greater than or equal to 3 microns. 2.The display substrate of claim 1, wherein, The at least one first power supply line is electrically connected to the second end of the second portion, and a projection of the at least one first power supply line on the plane in which the substrate lies and a projection of the first portion on the plane in which the substrate lies do not overlap. 3.The display substrate of claim 2, wherein, An included angle exists between the first portion and the second portion, and the included angle is greater than 90 degrees and less than 180 degrees. 4.The display substrate of claim 2, wherein, The first pixel driving circuit comprises a shielding electrode and at least one transistor with a double-gate structure; a projection of the shielding electrode on the plane in which the substrate lies and a node between two gate electrodes of the transistor with the double-gate structure on the plane in which the substrate lies at least partially overlap. 5.The display substrate of any one of claims 1 to 4, wherein, The transistor with the double-gate structure comprises a compensation transistor. 6.The display substrate of claim 5, wherein, The shielding electrode and the first power supply line are located in the same conductive layer. 7.The display substrate of claim 5, wherein, The shielding electrode and the first power supply line are an integral structure connected to each other. 8.The display substrate of claim 7, wherein, The light-emitting structure layer comprises at least one light-emitting device, and the at least one light-emitting device comprises an anode, an organic light-emitting layer, and a cathode disposed in sequence; 9.The display substrate of claim 5, wherein, A projection of the shielding electrode on the plane in which the substrate lies and a projection of the anode of the at least one light-emitting device on the plane in which the substrate lies at least partially overlap. The at least one light-emitting device comprises at least one green light-emitting device emitting green light, and a projection of the shielding electrode on the plane in which the substrate lies and a projection of the anode of the at least one green light-emitting device on the plane in which the substrate lies at least partially overlap. 10.The display substrate of claim 9, wherein, ​ 11. The display substrate of any one of claims 1 to 4, wherein, The driving circuit layer comprises at least one first initial signal line extending along the first direction and at least one first auxiliary initial signal line extending along the second direction; the first initial signal line and the first auxiliary initial signal line are connected to form a mesh structure for transmitting a first initial signal. 12.The display substrate of claim 11, wherein, The driving circuit layer comprises at least one second initial signal line extending along the first direction and at least one second auxiliary initial signal line extending along the second direction; the second initial signal line and the second auxiliary initial signal line are connected to form a mesh structure for transmitting a second initial signal. 13.The display substrate of claim 12, wherein, The driving circuit layer comprises at least one third initial signal line extending along the first direction and at least one third auxiliary initial signal line extending along the second direction; the third initial signal line and the third auxiliary initial signal line are connected to form a mesh structure for transmitting a third initial signal.

14. A display device comprising the display substrate according to any one of claims 1 to 13.

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