Display control circuit and method, display substrate, and display device

Abstract

The present disclosure provides a display control circuit and method, a display substrate, and a display device. The display control circuit (100) comprises: at least two shift register circuits and a pixel circuit (13), wherein the at least two shift register circuits include a first shift register (11) and a second shift register (12); the pixel circuit (13) comprises an initialization sub-circuit (130), a storage sub-circuit (131), a drive sub-circuit (132), and a data write sub-circuit (133); a control end of the initialization sub-circuit (130) is connected to a first output end of the first shift register (11), a control end of the data write sub-circuit (133) is connected to a first output end of the second shift register (12), and a shielding sub-circuit is designed in at least one shift register.

Description

Display control circuit, method, display substrate, and display device Cross-references to related applications

[0001] This application claims priority to Chinese patent application No. 202410677208.0, filed on May 29, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure belongs to the field of display control technology, and in particular relates to a display control circuit, method, display substrate and display device. Background Technology

[0003] Partial refresh refers to refreshing a dynamic area of ​​the screen (such as animation) at a high frequency and a static area (such as text) at a low frequency, thereby reducing power consumption. Currently, partial refresh technology is mostly used in LTPO (Low Temperature Polycrystalline Oxide) pixel circuits, but using partial refresh technology on LTPO pixel circuits has the problem of high cost. Summary of the Invention

[0004] The embodiments of this application provide a display control circuit, method, display substrate, and display device, which can realize partial refresh based on LTPS pixel circuit, thereby reducing the implementation cost of partial refresh technology.

[0005] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0006] According to a first aspect of the embodiments of this application, a display control circuit is provided, comprising: at least two sets of shift register circuits, including a first set of shift register circuits and a second set of shift register circuits; the first set of shift register circuits includes a plurality of cascaded first shift registers, and the second set of shift register circuits includes a plurality of cascaded second shift registers; a pixel circuit, including an initialization sub-circuit, a storage sub-circuit, a driving sub-circuit, and a data writing sub-circuit, wherein the initialization sub-circuit is connected to a first node, the storage sub-circuit is connected to both the first node and the second node, the data writing sub-circuit is connected to the second node, and the driving sub-circuit is connected to the first node; wherein the control terminal of the initialization sub-circuit is connected to the first output terminal of the first shift register. Next, the control terminal of the data writing sub-circuit is connected to the first output terminal of the second shift register; the first shift register and the second shift register include a shift register sub-circuit, and at least one of the first shift register and the second shift register further includes: a shielding sub-circuit, the shielding sub-circuit being connected to the shift register sub-circuit; the shift register sub-circuit is used to output a cascaded signal based on the input signal; and the output terminal of the shielding sub-circuit serves as the first output terminal, used to output a control signal based on the shielding signal, wherein when the shielding signal is at a first level, the control signal is at a first level, and when the shielding signal is at a second level, the control signal is the same as the cascaded signal, wherein the first level and the second level are different.

[0007] In some embodiments, the pixel circuit further includes a compensation sub-circuit, a first terminal of which is connected to the first node for writing a compensation voltage to the first node, a second terminal of which is connected to the output terminal of the driving sub-circuit, and a control terminal of which is connected to the first output terminal of the second shift register; and the first shift register and the second shift register include the shielding sub-circuit, wherein the control signal output by the shielding sub-circuit is a row scanning signal.

[0008] In some embodiments, the first shift register and the second shift register are driven by a dual-sided drive.

[0009] In some embodiments, the at least two sets of shift register circuits further include a third set of shift register circuits, the third set of shift register circuits including a plurality of cascaded third shift registers; the initialization sub-circuit includes a first sub-circuit and a second sub-circuit, the input terminal of the first sub-circuit is used to receive an initialization voltage signal, the output terminal is connected to the third node, and the control terminal is connected to the output terminal of the third shift register; the input terminal of the second sub-circuit is connected to the third node, the output terminal is connected to the first node, and the control terminal is connected to the first output terminal of the first shift register; and the second sub-circuit is further used to write a compensation voltage to the first node during the compensation phase.

[0010] In some embodiments, the first shift register includes the shielding sub-circuit, and the control signal output by the shielding sub-circuit is a light emission control signal; and the shift register sub-circuit in the second shift register is further used to output a row scan signal to the control terminal of the data writing sub-circuit.

[0011] In some embodiments, the first shift register and the second shift register include the shielding sub-circuit; the control signal output by the shielding sub-circuit in the first shift register is a light emission control signal; and the control signal output by the shielding sub-circuit in the second shift register is a row scanning signal.

[0012] In some embodiments, the first shift register and the third shift register are driven by a single-sided drive, and the second shift register is driven by a double-sided drive.

[0013] In some embodiments, the pixel circuit further includes a compensation sub-circuit, a first terminal of which is connected to the first node for writing a compensation voltage to the first node, a second terminal of which is connected to the output terminal of the driving sub-circuit, and a control terminal of which is connected to the first output terminal of the second shift register; the second shift register includes a shielding sub-circuit, the control signal output by the shielding sub-circuit is a row scanning signal; and the initialization sub-circuit is connected to the first output terminal of the first shift register and the first output terminal of the previous-level second shift register, respectively, for writing the initialization voltage to the first node under the control of the control signal output by the first output terminal of the first shift register and the control signal output by the first output terminal of the previous-level second shift register.

[0014] In some embodiments, the initialization sub-circuit includes a third sub-circuit and a fourth sub-circuit. The input terminal of the third sub-circuit is used to receive an initialization voltage signal, and its output terminal is connected to the input terminal of the fourth sub-circuit. The output terminal of the fourth sub-circuit is connected to the first node. The control terminal of one of the third sub-circuit and the fourth sub-circuit is connected to the first output terminal of the first shift register, and the control terminal of the other is connected to the first output terminal of the previous-level second shift register.

[0015] In some embodiments, the initialization sub-circuit includes a third sub-circuit and a fourth control sub-circuit. The input terminal of the third sub-circuit is used to receive an initialization voltage signal, the output terminal is connected to the first node, the control terminal is connected to the output terminal of the fourth sub-circuit, and the input terminal of the fourth sub-circuit is connected to the first output terminal of the previous stage second shift register, and the control terminal is connected to the first output terminal of the first shift register.

[0016] In some embodiments, the first shift register is driven by a single-sided drive or a double-sided drive, and the second shift register is driven by a double-sided drive.

[0017] In some embodiments, the at least two sets of shift register circuits further include a third set of shift register circuits, a fourth set of shift register circuits, and a fifth set of shift registers. The third set of shift register circuits includes multiple cascaded third shift registers, the fourth set of shift register circuits includes multiple cascaded fourth shift registers, and the fifth set of shift register circuits includes multiple cascaded fifth shift registers. The data writing sub-circuit includes a fifth sub-circuit and a sixth sub-circuit. The input terminal of the fifth sub-circuit is used to receive a data voltage signal, the output terminal is connected to the second node, and the control terminal is connected to the first output terminal of the second shift register. The input terminal of the sixth sub-circuit is used to receive an initialization voltage signal, the output terminal is connected to the second node, and the control terminal is connected to the output terminal of the third shift register. The initialization sub-circuit includes a seventh sub-circuit. The system comprises an eighth sub-circuit and a ninth sub-circuit. The input terminal of the seventh sub-circuit is used to receive an initialization voltage signal, its output terminal is connected to the fourth node, and its control terminal is connected to the output terminal of the fourth shift register. The input terminal of the eighth sub-circuit is connected to the fourth node, its output terminal is connected to the third node, and its control terminal is connected to the output terminal of the fifth shift register. The input terminal of the ninth sub-circuit is connected to the third node, its output terminal is connected to the first node, and its control terminal is connected to the first output terminal of the first shift register. The first shift register includes a shielding sub-circuit, and the control signal output by the shielding sub-circuit is a light-emitting control signal. The eighth sub-circuit is also used to write a light-emitting control voltage from the fourth node to the light-emitting element during the light-emitting stage. The ninth sub-circuit is also used to write a compensation voltage to the first node during the compensation stage.

[0018] In some embodiments, the transistors in the pixel circuit are all low-temperature polysilicon transistors.

[0019] According to a second aspect of the present disclosure, a display substrate is provided, comprising: a substrate substrate, and a display control circuit as described in the first aspect, the display control circuit being disposed on one side of the substrate substrate.

[0020] According to a third aspect of the present disclosure, a display control method is provided, applied to a display substrate as described in the second aspect, the method comprising: determining a first display area and a second display area of ​​the display substrate; writing a first level to a shielding signal input terminal of a shielding sub-circuit in a shift register corresponding to the first display area; and writing a second level to a shielding signal input terminal of a shielding sub-circuit in a shift register corresponding to the second display area, wherein the first level and the second level are different.

[0021] According to a fourth aspect of the present disclosure, a display device is provided, including a display substrate as described in the second aspect.

[0022] In this disclosure, at least two sets of shift register circuits and pixel circuits are provided in the display control circuit. The at least two sets of shift register circuits include a first shift register and a second shift register. The pixel circuit includes an initialization sub-circuit, a storage sub-circuit, a driving sub-circuit, and a data writing sub-circuit. The control terminal of the initialization sub-circuit is connected to the first output terminal of the first shift register, and the control terminal of the data writing sub-circuit is connected to the first output terminal of the second shift register. Furthermore, a shielding sub-circuit is designed in at least one shift register. This display control circuit design enables partial refresh based on LTPS pixel circuits, reducing the implementation cost of partial refresh technology.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0025] Figure 1 shows a circuit block diagram of a display control circuit according to some embodiments of the present disclosure;

[0026] Figure 2 shows the circuit structure diagram of the LTPS 7T1C pixel circuit in the related technology;

[0027] Figure 3 shows the circuit structure diagram of the LTPS 7T1C pixel circuit that can refresh at a low frequency in full screen.

[0028] Figure 4 shows the circuit structure diagram of the LTPS 8T1C pixel circuit that can refresh at a low frequency in full screen.

[0029] Figure 5 shows an exemplary circuit structure diagram of a shift register that includes a shielded sub-circuit in Figure 1;

[0030] Figure 6 shows the timing diagram of the shift register in Figure 5 during normal output;

[0031] Figure 7 shows the timing diagram of the shift register in Figure 5 with the output masked;

[0032] Figure 8 shows the circuit structure diagram of the shift register driving the 8T1C pixel circuit in Figure 4 in Figure 5;

[0033] Figure 9 shows the timing diagram of the shift register in Figure 5 driving the 8T1C pixel circuit in Figure 4;

[0034] Figure 10 shows an exemplary detailed schematic diagram of the control circuit shown in Figure 1;

[0035] Figure 11 shows an exemplary circuit structure diagram of the pixel circuit in Figure 10;

[0036] Figure 12 shows an exemplary timing diagram for driving the pixel circuit in Figure 11;

[0037] Figure 13 shows an exemplary layout of the display control circuit in Figure 10;

[0038] Figure 14 shows another exemplary timing diagram for driving the pixel circuit in Figure 11;

[0039] Figure 15 shows another exemplary detailed schematic diagram of the control circuit shown in Figure 1;

[0040] Figure 16 shows an exemplary circuit structure diagram of the pixel circuit in Figure 15;

[0041] Figure 17 shows an exemplary layout of the control circuitry shown in Figure 15;

[0042] Figure 18 shows an exemplary timing diagram for driving the pixel circuitry in Figure 16;

[0043] Figure 19 shows another exemplary detailed schematic diagram of the control circuit shown in Figure 1;

[0044] Figure 20 shows an exemplary circuit structure diagram of the pixel circuit in Figure 19;

[0045] Figure 21 shows another exemplary timing diagram for driving the pixel circuit in Figure 16;

[0046] Figure 22 shows an exemplary timing diagram for driving the pixel circuitry in Figure 20;

[0047] Figure 23 shows another exemplary detailed schematic diagram of the control circuit shown in Figure 1;

[0048] Figure 24 shows an exemplary circuit structure diagram of the pixel circuit in Figure 23;

[0049] Figure 25 shows another exemplary circuit structure diagram of the pixel circuit in Figure 23;

[0050] Figure 26 shows another exemplary circuit structure diagram of the pixel circuit in Figure 23;

[0051] Figure 27 shows an exemplary timing diagram for driving the pixel circuit in Figure 23;

[0052] Figure 28 shows an exemplary layout of the display control circuit in Figure 23;

[0053] Figure 29 shows another exemplary detailed schematic diagram of the control circuit shown in Figure 1;

[0054] Figure 30 shows an exemplary circuit structure diagram of the pixel circuit in Figure 29;

[0055] Figure 31 shows a schematic diagram of the structure of a display substrate according to some embodiments of the present disclosure; and

[0056] Figure 32 shows a flowchart of a display control method according to some embodiments of the present disclosure.

[0057] Reference numerals: 20 - Display substrate; 200 - Substrate substrate; 100 - Display control circuit; 11 - First shift register; 12 - Second shift register; 12' - Previous-level second shift register; 13 - Pixel circuit; 130 - Initialization sub-circuit; 1301-1309 - First to Ninth sub-circuits; 131 - Storage sub-circuit; 132 - Driving sub-circuit; 133 - Data writing sub-circuit; 134 - Compensation sub-circuit; 14 - Third shift register; 15 - Fourth shift register; 16 - Fifth shift register; N1-N9 - First to Ninth nodes; EL - Driving light-emitting element; T1-T22 - First to Twenty-second transistor; Cst - First capacitor; C2-C5 - Second to Fifth capacitors. Detailed Implementation

[0058] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0059] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0060] It should also be noted that the source and drain of the transistors used in the embodiments of this disclosure can be symmetrical in structure, so their source and drain can be indistinguishable in physical structure. In the embodiments of this disclosure, in order to distinguish the transistors, except for the gate which serves as the control electrode, one electrode is directly described as the first electrode and the other electrode as the second electrode. Therefore, in the embodiments of this disclosure, the first and second electrodes of all or some transistors can be interchanged as needed.

[0061] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and known components have been omitted.

[0062] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, this disclosure is not limited to these specific embodiments.

[0063] Figure 1 shows a circuit block diagram of a display control circuit according to some embodiments of the present disclosure. As shown in Figure 1, the display control circuit includes: at least two sets of shift register circuits, including a first set of shift register circuits and a second set of shift register circuits; the first set of shift register circuits includes a plurality of cascaded first shift registers 11, and the second set of shift register circuits includes a plurality of cascaded second shift registers 12; a pixel circuit 13, including an initialization sub-circuit 130, a storage sub-circuit 131, a driving sub-circuit 132, and a data writing sub-circuit 133, wherein the initialization sub-circuit 130 is connected to a first node N1, the storage sub-circuit 131 is connected to the first node N1 and the second node N2 respectively, the data writing sub-circuit 133 is connected to the second node N2, and the driving sub-circuit 132 is connected to the first node N1; wherein, the control terminal of the initialization sub-circuit 130 is connected to the first input of the first shift register 11. The control terminal of the data writing sub-circuit 133 is connected to the first output terminal of the second shift register 12. The first shift register 11 and the second shift register 12 include shift register sub-circuits, and at least one of the first shift register 11 and the second shift register 12 further includes a shielding sub-circuit, which is connected to the shift register sub-circuit. The shift register sub-circuit is used to output a cascaded signal (carry) based on the input signal (e.g., GSTV or carry output by the previous shift register sub-circuit). The output terminal of the shielding sub-circuit serves as the first output terminal and is used to output a control signal based on the shielding signal (SU1 or SU2). When the shielding signal is at a first level, the control signal is at a first level, and when the shielding signal is at a second level, the control signal is the same as the cascaded signal.

[0064] In some embodiments, the display control circuit can be applied to a display substrate, such as an active-matrix organic light-emitting diode (AMOLED) display substrate.

[0065] In some embodiments, the light-emitting element EL can be a light-emitting diode, such as an organic light-emitting diode (OLED) or a quantum dot organic light-emitting diode (QLED), etc., and this disclosure does not limit this. The light-emitting element EL can use light-emitting materials of different colors to emit light of different colors, thereby performing color display.

[0066] In some embodiments, the initialization sub-circuit 130 is used to write an initialization voltage to the first node N1, the data writing sub-circuit 133 is used to write a data voltage from the second node N2 to the storage sub-circuit 131, and the driving sub-circuit 132 is used to drive the light-emitting element EL to emit light under the control of the voltage of the first node N1.

[0067] It should be noted that the pixel circuit 13 mentioned above is an LTPS (Low Temperature Poly-Silicon) pixel circuit. The transistors in this pixel circuit are all P-type thin film transistors, which realizes the local refresh technology at low cost.

[0068] It is understandable that for the first-stage shift register sub-circuit in the shift register circuit, since there is no cascaded output signal from the previous stage shift register sub-circuit, it is necessary to write the input signal GSTV to it. For other stages of shift register sub-circuit, the cascaded output signal from the previous stage shift register sub-circuit can be used as the GSTV to drive it.

[0069] It should also be noted that in this embodiment, the first level can be an effective level that turns the transistor on, and the second level can be an ineffective level that turns the transistor off. Taking a P-type thin-film transistor as an example, when the first level is high, the P-type thin-film transistor is off; when the second level is low, the P-type thin-film transistor is on. When the shielding signal is high, the control signal is high, and the shielding effect of the shielding sub-circuit is effective. At this time, the corresponding display area will be refreshed at a low frequency. When the second level is low, the control signal is the same as the cascaded signal, the shielding effect of the shielding sub-circuit is not effective, and the corresponding display area refreshes normally.

[0070] Figure 2 shows the circuit structure diagram of the LTPS 7T1C pixel circuit in the related technology. All transistors in this circuit are P-type low-temperature polysilicon transistors. As shown in Figure 2, the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are controlled by a set of Gate GOA (gate scan driver) circuits. The reset signal is generally the Gate GOA signal of the previous row, that is, while data is being written in the current row, the first node N1 and the fourth node N4 of the next row are reset. The fifth transistor T5 and the sixth transistor T6 are controlled by a set of EM GOA (emissivity control driver) circuits. In this circuit architecture, in order to ensure that the screen is flicker-free at low frequencies, the second node N2 and the fourth node N4 need to be reset during the hold frame stage. However, since the first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 share a set of Gate GOA circuits, when the second node N2 and the fourth node N4 are reset, the second transistor T2 will also turn on, which is equivalent to another data write. Therefore, this circuit architecture cannot switch from high frequency to low frequency.

[0071] Figure 3 shows the circuit structure of the LTPS 7T1C pixel circuit capable of full-screen low-frequency refresh. As shown in Figure 3, the fourth transistor T4 and the seventh transistor T7 are controlled by a set of EM GOA circuits, the first transistor T1 and the second transistor T2 are controlled by a set of Gate GOA circuits, and the fifth transistor T5 and the sixth transistor T6 are controlled by a set of EM GOA circuits. In this circuit architecture, when the second node N2 and the fourth node N4 are reset during the frame holding phase, the second transistor T2 is turned off, which solves the problem of screen flicker at low frequencies. Therefore, this circuit architecture can achieve low-frequency refresh across the entire screen area.

[0072] Figure 4 shows the circuit structure of an LTPS 8T1C pixel circuit capable of full-screen low-frequency refresh. As shown in Figure 4, by adding an eighth transistor T8 connected to the second node N2, the hysteresis of the third transistor T3 can be improved. The reset of the second node N2 is accomplished by the initialization voltage Vinit3. The seventh transistor T7 and the eighth transistor T8 are controlled by a set of EM GOA circuits, the first transistor T1, the second transistor T2, and the fourth transistor T4 are controlled by a set of Gate GOA circuits, and the fifth transistor T5 and the sixth transistor T6 are controlled by a set of EM GOA circuits. This circuit architecture can also achieve low-frequency refresh across the entire screen area.

[0073] The LTPS 7T1C pixel circuit shown in Figure 3 and the LTPS 8T1C pixel circuit shown in Figure 4 can both achieve low-frequency refresh of the entire screen area, but cannot achieve low-frequency refresh of local areas. To achieve local refresh, this embodiment adds a shielding sub-unit to the GOA circuit. This shielding sub-unit shields the data writing to a portion of the area, thereby achieving low-frequency refresh in that portion. Figure 5 shows an exemplary circuit structure diagram of the shift register including the shielding sub-circuit in Figure 1. As shown in Figure 5, taking the first shift register as an example, the shift register includes a shift register sub-circuit 110 and a shielding sub-circuit 111, wherein the shift register sub-circuit 110 can be a Gate... The GOA circuit includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a second capacitor C2, and a third capacitor C3. Specifically, the first terminal of the ninth transistor T9 receives the GSTV signal, its second terminal is connected to the fifth node N5, and its gate receives the GCK signal. The first terminal of the tenth transistor T10 is connected to the sixth node N6, its second terminal receives the GCK signal, and its gate is connected to the fifth node N5. The first terminal of the eleventh transistor T11 receives the VGL signal, its second terminal is connected to the sixth node N6, and its gate receives the GCK signal. The first terminal of the second capacitor C2 receives the VGH signal, and its second terminal is connected to the sixth node N6. The gate of the twelfth transistor T12 is connected to the sixth node N6, its first terminal receives the VGH signal, and its second terminal is connected to the first terminal of the third capacitor C3 and the first terminal of the thirteenth transistor T13, serving as the gate. The output terminal of GOA outputs cascaded signals; the second terminal of the thirteenth transistor T13 is used to output the GCB signal, and its gate is connected to the seventh node N7; the first terminal of the fourteenth transistor T14 is used to receive the VGH signal, and its second terminal is connected to the first terminal of the fifteenth transistor T15 via the eighth node N8, and its gate is connected to the sixth node N6; the second terminal of the fifteenth transistor T15 is connected to the fifth node N5, and its gate is used to receive the GCB signal; the first terminal of the sixteenth transistor T16 is connected to the fifth node N5, its second terminal is connected to the seventh node N7, and its gate is used to receive the VGL signal.

[0074] The shielding unit (SU) 111 may include a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, a twentieth transistor T20, a twenty-first transistor T21, a twenty-second transistor T22, a fourth capacitor C4, and a fifth capacitor C5. The gate of the seventeenth transistor T17 is connected to the sixth node N6. Its first terminal is used to receive the VGH signal, and its second terminal is connected to the first terminal of the fourth capacitor C4 and the first terminal of the eighteenth transistor T18, serving as the output terminal of the shielding unit 111, outputting the control signal Gout. The second terminal of the eighteenth transistor T18 is used to output the GCB signal, and its gate is connected to... The ninth node N9 is connected; the first terminal of the nineteenth transistor T19 is used to receive the VGH signal, the second terminal is connected to the ninth node N9 via the first and second terminals of the twentieth transistor T20, and the gate is connected to the sixth node N6; the gate of the twentieth transistor T20 is used to receive the GCB signal; the first terminal of the twenty-first transistor T21 is connected to the seventh node N7, the second terminal is connected to the ninth node N9 via the fifth capacitor C5, and the gate is used to receive the VGL signal; the first terminal of the twenty-second transistor T22 is used to receive the shielding signal SU, the second terminal is connected to the ninth node N9, and the gate is connected to the second terminal of the twenty-first transistor T21.

[0075] Wherein, GSTV is the row drive clock signal, carry is the cascade signal, Gout is the control signal, GCK is the first gate clock signal, GCB is the second gate clock signal, VGH is high level, and VGL is low level. For P-type low-temperature polysilicon crystals, VGH is the voltage to turn off the gate, and VGL is the voltage to turn on the gate.

[0076] Understandably, in the aforementioned shift register circuit, the shift register sub-circuit 110 serves to output the cascaded signal 'carry' to the next-level shift register sub-circuit, while the shielding sub-circuit 111 serves to output the control signal 'Gout' to the display area. The cascaded signal and the control signal do not interfere with each other. In certain areas, the control shielding signal is at the first level, causing the second transistor T2 and the fourth transistor T4 in the pixel circuit to be turned off, thus maintaining a low refresh rate in this area.

[0077] The aforementioned shift register circuit is based on the 8T2C shift register sub-circuit 110, with the addition of a 6T2C shielding sub-circuit 111. In implementation, the shielding sub-circuit 111 is not limited to the 6T2C circuit design; more thin-film transistors and capacitors can be added to enhance its output capability or improve its functionality. Similarly, the shift register sub-circuit 110 is not limited to 8T2C; the shielding sub-circuit 111 can also be added to 12T3C, 16T3C, and other circuits.

[0078] Figure 6 shows the timing diagram of the shift register in Figure 5 during normal output. In Figure 6, SU is the masking signal. As shown in Figure 6, when GSTV is low, GCK is low, and GCB is high, for the shift register sub-circuit, transistors 9 (T9) and 11 (T11) are turned on, nodes 6 (N6) and 7 (N7) are set low, which in turn turns on transistors 12 (T12) and 13 (T13). At this time, the carry signal is high. For the masking sub-circuit, node 6 (N6) is set low, transistor 16 (T16) is turned on, the Gout signal is high, node 7 (N7) is set low, transistor 17 (T17) is turned on, node 7 (N7) is set low, transistor 22 (T22) is turned on, and the masking signal SU is written to node 9 (N9). Because the masking signal is low at this time, transistor 18 (T18) is turned on, GCB is output, and GCB is high, so the Gout signal remains high.

[0079] Figure 7 shows the timing diagram of the shift register in Figure 5 when the output is masked. As shown in Figure 7, when GSTV is high, GCK is high, and GCB is low, for the shift register sub-circuit, the ninth transistor T9 and the eleventh transistor T11 are turned off, the seventh node N7 and the fifth node N5 maintain the state of the previous moment, which is low, so the tenth transistor T10 is turned on, GCK is written to the sixth node N6, which is high, and the twelfth transistor T12 is turned off. When node 7 is low, transistor 13 (T13) turns on, GCB outputs, and the carry signal is low. For the shielding sub-circuit, node 6 (N6) is high, transistor 17 (T17) turns off, node 7 (N7) is low, transistor 22 (T22) turns on, and the shielding signal SU is written. The level of SU determines whether transistor 18 (T18) turns on. If SU is low, as shown in Figure 6, transistor 18 (T18) turns on normally, GCB outputs, and Gout is low. If SU is high, as shown in Figure 7, transistor 18 (T18) turns off, and Gout maintains its previous state through capacitor C4, outputting a high level, thus achieving the shielding function.

[0080] If a partial refresh design is performed based on the LTPS 8T1C pixel circuit, and a shielding sub-circuit is added to the shift register sub-circuit, the resulting circuit structure is shown in Figure 8. If the second transistor T2, the fourth transistor T4, and the first transistor T1 are still controlled by the same GOA circuit, and the first node N1 of the next row is refreshed while the current row is reset, two phenomena may occur depending on the location of the low-frequency refresh area. First, if the upper half of the screen is a high-frequency refresh area and the lower half is a low-frequency refresh area, and the first node N1 of the first row in the low-frequency refresh area is refreshed, a bright line may appear at the high-low refresh boundary. Second, if the upper half of the screen is a low-frequency refresh area and the lower half is a high-frequency refresh area, since no data is written to the low-frequency refresh area, the first node N1 of the first row in the high-frequency refresh area will not be refreshed, potentially causing screen anomalies. Referring to the timing diagram shown in Figure 9, SU is shielded in the nth row, but the refresh of the first node N1 in the nth row is determined by the data written in the (n-1)th row and cannot be shielded. Therefore, in the local refresh design of LTPS pixel circuits, the key point is that there should be no correlation between uplink and downlink, or the correlation can be shielded through special design.

[0081] The design of the control circuit in this embodiment of the present disclosure enables partial refresh based on LTPS pixel circuit, reducing the implementation cost of partial refresh technology. At the same time, by using different sets of shift registers to control the data writing of the second node and the refresh of the first node, the data writing of the current row will not affect the refresh of the first node N1 of the next row, thereby ensuring the normal display of the screen during the partial refresh process.

[0082] Figure 10 shows an exemplary detailed schematic diagram of the display control circuit in Figure 1. As shown in Figure 10, the pixel circuit also includes a compensation sub-circuit 134. The first terminal of the compensation sub-circuit 134 is connected to the first node N1 for writing a compensation voltage to the first node N1, the second terminal is connected to the output terminal of the drive sub-circuit 132, and the control terminal is connected to the first output terminal of the second shift register 12. The first shift register 11 and the second shift register 12 include a shielding sub-circuit, and the control signal output by the shielding sub-circuit is a row scanning signal.

[0083] Figure 11 shows an exemplary circuit structure diagram of the pixel circuit in Figure 10. Referring to Figures 10 and 11, in some embodiments, the initialization sub-circuit 130 may include a first transistor T1, the storage sub-circuit 131 may include a first capacitor Cst, the compensation sub-circuit 134 may include a second transistor T2, the driving sub-circuit 132 may include a third transistor T3, and the data writing sub-circuit 133 may include a fourth transistor T4. In a specific implementation, the pixel circuit 13 may also include a first light-emitting control sub-circuit (not shown) and a second light-emitting control sub-circuit (not shown). The first light-emitting control sub-circuit includes a fifth transistor T5, the second light-emitting control sub-circuit includes a sixth transistor T6, the initialization sub-circuit 130 may also include a seventh transistor T7, and the data writing sub-circuit 133 may also include an eighth transistor T8. The gate of the first transistor T1 is controlled by the first shift register 11, the gates of the second transistor T2 and the fourth transistor T4 are controlled by the second shift register 12, the gates of the fifth transistor T5 and the sixth transistor T6 can be controlled by the shift register EM1, and the gates of the seventh transistor T7 and the eighth transistor T8 can be controlled by the shift register EM2.

[0084] It should be noted that the sub-circuits of the pixel circuit in Figure 10 are not limited to the above design. The number of thin-film transistors can be reduced, or the output capability of each sub-circuit can be enhanced by adding more thin-film transistors and capacitors.

[0085] Figure 12 shows an exemplary timing diagram for driving the pixel circuit in Figure 11. As shown in Figure 12, in the nth row, the shielding signal SU2 of the shielding sub-circuit of the second shift register switches to a high level, which can shield the data writing in the nth row. The shielding signal SU1 of the shielding sub-circuit of the first shift register can switch to a high level 1H in advance (H is the time required for the data signal to refresh one pixel), shielding the refresh of the first node N1 in the nth row. This ensures the normal display of the image at the boundary between the high-frequency refresh area and the low-frequency refresh area.

[0086] Figure 13 shows an exemplary layout of the display control circuit in Figure 10. As shown in Figure 13, the first shift register (Gate1+SU1) and the second shift register (Gate2+SU2) can be driven by both sides, while shift registers EM1 and EM2 can be driven by one side. This design can reduce the bezel size. In some other embodiments, the four shift registers can also be driven by both sides. Although this approach increases the bezel size, it ensures improved uniformity of display brightness.

[0087] Figure 14 shows another exemplary timing diagram for driving the pixel circuit in Figure 11. As shown in Figure 14, the driving principle of the pixel circuit in Figure 11 is as follows: the shielding signals SU1 and SU2 are set to high level at the beginning of the nth row and remain low level before the (n-1)th row. If the base frequency is 120Hz, the control signal before the (n-1)th row is the same as the cascaded signal, so the shielding effect is not effective, and a refresh is performed every frame. Therefore, the refresh frequency before the (n-1)th row is 120Hz. Starting from the nth row, the control signal is high level, and the shielding effect is effective. This is equivalent to refreshing one frame and maintaining one frame. Therefore, the refresh frequency starting from the nth row is 60Hz.

[0088] Figure 15 shows another exemplary detailed schematic diagram of the control circuit shown in Figure 1. As shown in Figure 15, at least two sets of shift register circuits also include a third set of shift register circuits, which includes multiple cascaded third shift registers 14; the initialization sub-circuit includes a first sub-circuit 1301 and a second sub-circuit 1302. The input of the first sub-circuit 1301 is used to receive the initialization voltage signal Vinit1, the output is connected to the third node N3, and the control terminal is connected to the output of the third shift register 14. The input of the second sub-circuit 1302 is connected to the third node N3, the output is connected to the first node N1, and the control terminal is connected to the first output of the first shift register 11; the second sub-circuit 1302 is also used to write a compensation voltage to the first node N1 during the compensation phase. The first shift register 11 includes a shielding sub-circuit 111, and the control signal output by the shielding sub-circuit 111 is a light emission control signal; the shift register sub-circuit 120 in the second shift register 12 is also used to output a row scan signal to the control terminal of the data writing sub-circuit 133.

[0089] Figure 16 illustrates an exemplary circuit structure diagram of the pixel circuit in Figure 15. Referring to Figures 15 and 16, in some embodiments, the first sub-circuit 1301 may include a first transistor T1, the second sub-circuit 1302 may include a second transistor T2, the storage sub-circuit 131 may include a first capacitor Cst, the driving sub-circuit 132 may include a third transistor T3, and the data writing sub-circuit 133 may include a fourth transistor T4. In a specific implementation, the pixel circuit 13 may also include a first light-emitting control sub-circuit (not shown) and a second light-emitting control sub-circuit (not shown), the first light-emitting control sub-circuit including a fifth transistor T5, the second light-emitting control sub-circuit including a sixth transistor T6, the initialization sub-circuit 130 may also include a seventh transistor T7, and the data writing sub-circuit 133 may also include an eighth transistor T8. The gate of the first transistor T1 is controlled by the third shift register 14, the gate of the second transistor T2 is controlled by the first shift register 11, the gate of the fourth transistor T4 is controlled by the second shift register 12, the gates of the fifth transistor T5 and the sixth transistor T6 can be controlled by the shift register EM1, and the gates of the seventh transistor T7 and the eighth transistor T8 can be controlled by the shift register EM2.

[0090] It is understandable that if the initialization voltage signal Vinit1 is to refresh the first node N1, the first transistor T1 and the second transistor T2 need to be turned on simultaneously. Under the architecture of this pixel circuit, the data writing in this row will not affect the next row. Since the first transistor T1 and the second transistor T2 are controlled by different shift registers, when the second transistor T2 is shielded, the initialization voltage signal Vinit1 cannot be reset to the first node N1. Therefore, the gate of the first transistor T1 does not need to be controlled by a shielding sub-circuit.

[0091] Figure 17 shows an exemplary layout of the display control circuit in Figure 15. Referring to Figures 15 to 17, EM4+SU corresponds to the first shift register 11, Gate corresponds to the second shift register 12, and EM3 corresponds to the third shift register 14. The first and third shift registers are driven by a single-sided drive, while the second shift register is driven by a double-sided drive.

[0092] Figure 18 shows an exemplary timing diagram for driving the pixel circuit in Figure 16. As shown in Figure 18, in the nth row, the shielding signal SU of the shielding sub-circuit of the first shift register switches to a high level, which can shield the refresh of the first node N1 in the nth row, thereby ensuring the normal display of the image at the boundary between the high-frequency refresh area and the low-frequency refresh area.

[0093] Figure 19 shows another exemplary detailed schematic diagram of the control circuit shown in Figure 1. As shown in Figure 19, at least two sets of shift register circuits also include a third set of shift register circuits, which includes multiple cascaded third shift registers 14; the initialization sub-circuit 130 includes a first sub-circuit 1301 and a second sub-circuit 1302. The input of the first sub-circuit 1301 is used to receive an initialization voltage signal, the output is connected to the third node N3, and the control terminal is connected to the output of the third shift register 14. The input of the second sub-circuit 1302 is connected to the third node N3, the output is connected to the first node N1, and the control terminal is connected to the first output of the first shift register 11; the second sub-circuit 1302 is also used to write a compensation voltage to the first node N1 during the compensation phase. The first shift register 11 and the second shift register 12 include shielding sub-circuits; the control signal output by the shielding sub-circuit 111 in the first shift register 11 is a light emission control signal; the control signal output by the shielding sub-circuit 121 in the second shift register 12 is a line scanning signal.

[0094] Figure 20 shows an exemplary circuit structure diagram of the pixel circuit in Figure 19. The pixel circuit architecture in Figure 20 is the same as that in Figure 16, except that a shielding sub-circuit is added to the second shift register 12 to achieve shielding control of the gate of the fourth transistor T4. Figure 21 shows another exemplary timing diagram for driving the pixel circuit in Figure 16, and Figure 22 shows an exemplary timing diagram for driving the pixel circuit in Figure 20. As can be seen from Figures 21 and 22, with this design, the data voltage does not refresh the second node N2 during the hold frame stage in the low-frequency refresh region, whereas in Figure 16, the data voltage refreshes to the second node N2 during the hold frame stage, affecting the source potential of the third transistor T3. Therefore, the circuit structure shown in Figure 20 may have an advantage in low-frequency display performance, but it inevitably leads to an increase in the bezel.

[0095] Figure 23 shows another exemplary detailed schematic diagram of the display control circuit in Figure 1. As shown in Figure 23, the pixel circuit 13 further includes a compensation sub-circuit 134. The first end of the compensation sub-circuit 134 is connected to the first node N1 for writing a compensation voltage to the first node N1. The second end is connected to the output end of the driving sub-circuit 132, and the control end is connected to the first output end of the second shift register 12. The second shift register 12 includes a shielding sub-circuit 121, and the control signal output by the shielding sub-circuit 121 is a row scanning signal. The initialization sub-circuit 130 is connected to the first output end of the first shift register 11 and the first output end of the previous-level second shift register 12', respectively, and is used to write an initialization voltage to the first node N1 under the control of the control signal output by the first output end of the first shift register 11 and the control signal output by the first output end of the previous-level second shift register 12'.

[0096] In some embodiments, the initialization sub-circuit 130 includes a third sub-circuit 1303 and a fourth sub-circuit 1304. The input terminal of the third sub-circuit 1303 is used to receive an initialization voltage signal, and its output terminal is connected to the input terminal of the fourth sub-circuit 1304. The output terminal of the fourth sub-circuit 1304 is connected to the first node N1. The control terminal of one of the third sub-circuit 1303 and the fourth sub-circuit 1304 is connected to the first output terminal of the first shift register 11, and the control terminal of the other is connected to the first output terminal of the previous-level second shift register 12'.

[0097] Figures 24 and 25 illustrate two exemplary circuit structures of the pixel circuit in Figure 23. As shown in Figure 24, the third sub-circuit 1303 may include a first transistor T1, the fourth sub-circuit 1304 may include a ninth transistor T9, the storage sub-circuit 131 may include a first capacitor Cst, the compensation sub-circuit 134 may include a second transistor T2, the driving sub-circuit 132 may include a third transistor T3, and the data writing sub-circuit 133 may include a fourth transistor T4. In a specific implementation, the pixel circuit 13 may also include a first light-emitting control sub-circuit (not shown) and a second light-emitting control sub-circuit (not shown). The first light-emitting control sub-circuit includes a fifth transistor T5, the second light-emitting control sub-circuit includes a sixth transistor T6, the initialization sub-circuit 130 may also include a seventh transistor T7, and the data writing sub-circuit 133 may also include an eighth transistor T8. The gate of the first transistor T1 is controlled by the second shift register 12' of the previous stage. The gates of the second transistor T2 and the fourth transistor T4 are controlled by the second shift register 12. The gate of the ninth transistor T9 is controlled by the first shift register 11. The gates of the fifth transistor T5 and the sixth transistor T6 are controlled by the shift register M1. The gates of the seventh transistor T7 and the eighth transistor T8 are controlled by the shift register M2.

[0098] The difference between Figure 25 and Figure 24 is that the ninth transistor T9 is respectively set at the source or drain of the first transistor T1. In Figure 25, the third sub-circuit 1303 includes the ninth transistor T9 and the fourth sub-circuit 1304 includes the first transistor T1.

[0099] In some embodiments, the initialization sub-circuit 130 includes a third sub-circuit 1303 and a fourth control sub-circuit 1304. The input terminal of the third sub-circuit 1303 is used to receive an initialization voltage signal, the output terminal is connected to the first node N1, the control terminal is connected to the output terminal of the fourth sub-circuit 1304, the input terminal of the fourth sub-circuit 1304 is connected to the first output terminal of the previous stage second shift register 12', and the control terminal is connected to the first output terminal of the first shift register 11.

[0100] Figure 26 shows another exemplary circuit structure diagram of the pixel circuit in Figure 23. As shown in Figure 26, the third sub-circuit 1303 may include a first transistor T1, and the fourth sub-circuit 1304 may include a ninth transistor T9, with the gate of the first transistor T1 controlled by the ninth transistor T9. The difference between Figure 26 and Figure 24 is that the ninth transistor T9 is disposed at the gate of the first transistor T1.

[0101] The three pixel circuits described above each add a ninth transistor T9 to the drain, source, and gate of the first transistor T1 to control whether the initialization voltage Vinit1 is written to the first transistor T1. In these three circuit architectures, the first transistor T1, the second transistor T2, and the fourth transistor T4 are controlled by the second shift register 12, while the refresh of the first node N1 is controlled by the ninth transistor T9. In the low-frequency refresh region, the ninth transistor T9 can be turned off to ensure that the first node N1 is not refreshed.

[0102] Figure 27 shows an exemplary timing diagram for driving the pixel circuit in Figure 23. As shown in Figure 27, in the nth row, the shielding signal SU of the shielding sub-circuit of the second shift register switches to a high level, and the signal output by the first shift register switches to a high level 1H in advance. This can shield the refresh of the first node N1 and the data writing of the second node N2 in the nth row, thereby ensuring the normal display of the image at the boundary between the high-frequency refresh area and the low-frequency refresh area.

[0103] Figure 28 shows an exemplary layout of the display control circuit in Figure 23. Referring to Figures 23 to 28, EM3 corresponds to the first shift register, Gate+SU corresponds to the second shift register, EM1 corresponds to the shift register connected to the fifth transistor T5 and the sixth transistor T6, and EM2 corresponds to the shift register connected to the seventh transistor T7 and the eighth transistor T8. The first shift register is driven by a double-sided drive, the second shift register is driven by a double-sided drive, and shift registers M1 and M2 are driven by a single-sided drive. Of course, other driving methods can also be used. To ensure the uniformity of screen display brightness, the second shift register must be driven by a double-sided drive, while other shift registers can be selected such that one group is driven by a double-sided drive and the other two by a single-sided drive, depending on actual needs.

[0104] Figure 29 shows another exemplary detailed schematic diagram of the control circuit shown in Figure 1. As shown in Figure 29, at least two sets of shift register circuits also include a third set of shift register circuits, a fourth set of shift register circuits, and a fifth set of shift registers. The third set of shift register circuits includes multiple cascaded third shift registers 14, the fourth set of shift register circuits includes multiple cascaded fourth shift registers 15, and the fifth set of shift register circuits includes multiple cascaded fifth shift registers 16. The data writing sub-circuit 133 includes a fifth sub-circuit 1331 and a sixth sub-circuit 1332. The input of the fifth sub-circuit 1331 is used to receive the data voltage signal Vdata, the output is connected to the second node N2, and the control terminal is connected to the first output of the second shift register 12. The input of the sixth sub-circuit 1332 is used to receive the initialization voltage signal Vinit3, the output is connected to the second node N2, and the control terminal is connected to the output of the third shift register 14. The initialization sub-circuit 130 includes a seventh sub-circuit 1307. The eighth sub-circuit 1308 and the ninth sub-circuit 1309 are configured such that the input terminal of the seventh sub-circuit 1307 is used to receive the initialization voltage signal Vinit2, the output terminal is connected to the fourth node N4, and the control terminal is connected to the output terminal of the fourth shift register 15; the input terminal of the eighth sub-circuit 1308 is connected to the fourth node N4, the output terminal is connected to the third node N3, and the control terminal is connected to the output terminal of the fifth shift register 16; the input terminal of the ninth sub-circuit 1309 is connected to the third node N3, the output terminal is connected to the first node N1, and the control terminal is connected to the first output terminal of the first shift register 11; the first shift register 11 includes a shielding sub-circuit 111, and the control signal output by the shielding sub-circuit 111 is a light emission control signal; the eighth sub-circuit 1308 is also used to write the light emission control voltage from the fourth node N4 to the light emission element during the light emission stage; the ninth sub-circuit 1309 is also used to write the compensation voltage to the first node N1 during the compensation stage.

[0105] Figure 30 shows an exemplary circuit structure diagram of the pixel circuit in Figure 29. As shown in Figure 30, the fifth sub-circuit 1331 may include a fourth transistor T4, the sixth sub-circuit 1332 may include an eighth transistor T8, the storage sub-circuit 131 may include a first capacitor Cst, the driving sub-circuit 132 may include a third transistor T3, the seventh sub-circuit 1307 may include a seventh transistor T7, the eighth sub-circuit 1308 may include a sixth transistor T6, and the ninth sub-circuit 1309 may include a second transistor T2. In a specific implementation, the pixel circuit 13 may also include a light-emitting control sub-circuit (not shown), which includes a fifth transistor T5. The gate of the second transistor T2 is controlled by a first shift register 11, the gate of the fourth transistor T4 is controlled by a second shift register 12, and the gates of the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all controlled by different shift registers.

[0106] Understandably, by controlling the fifth transistor T5 and the sixth transistor T6 with different shift registers, the second transistor T2, the sixth transistor T6, and the seventh transistor T7 can be simultaneously turned on in the timing, and the first node N1 can be reset by the initialization voltage Vinit2. Furthermore, controlling the seventh transistor T7 and the eighth transistor T8 with different shift registers also prevents the initialization voltages Vinit2 and Vinit3 from being shorted due to their simultaneous on. This circuit architecture can also prevent the first row of the low-frequency refresh area from being refreshed by the first node N1. It uses fewer thin-film transistors in the pixel circuit but has a larger number of shift registers.

[0107] It should be noted that the pixel circuit in this disclosure can be designed based on a low-frequency LTPS 8T1C pixel circuit or a low-frequency LTPS 7T1C pixel circuit. Those skilled in the art can also design it based on other low-frequency LTPS pixel circuits according to actual needs.

[0108] Figure 31 is a schematic diagram of the structure of a display substrate 20 according to some embodiments of the present disclosure. As shown in Figure 31, the display substrate 20 includes a substrate 200 and a display control circuit 100 provided in any of the embodiments described above. The display control circuit 100 is disposed on one side of the substrate 20. The display control circuit 100 may include shift register circuits 1 to n and a pixel circuit 13. The shift register circuits 1 to n are connected to the pixel circuit 13, and the pixel circuit 13 is connected to the light-emitting element EL to control the light emission of the light-emitting element EL.

[0109] Figure 32 shows a flowchart of a display control method according to some embodiments of the present disclosure. As shown in Figure 32, the display control method is applied to the display substrate provided above, and the method may include the following steps:

[0110] Step S101: Determine the first display area and the second display area of ​​the display substrate;

[0111] Step S102: Write a first level to the shielding signal input terminal of the shielding sub-circuit in the shift register corresponding to the first display area; and

[0112] Step S103: Write a second level to the shielding signal input terminal of the shielding sub-circuit in the shift register corresponding to the second display area, wherein the first level is different from the second level.

[0113] In this embodiment, the first display area refers to the display area that requires low-frequency refresh, and the second display area refers to the display area that requires high-frequency refresh. The specific location and number of the first and second display areas on the display substrate are not limited in this disclosure.

[0114] Assuming the shift register corresponding to the first display area is in row n, the shielding signal written to the shielding sub-circuit before row n is at the second level (e.g., low level). When row n is reached, the shielding signal written to the shielding sub-circuit switches to the first level (e.g., high level), thereby realizing high-frequency refresh of the second display area and low-frequency refresh of the first display area.

[0115] Taking Figure 12 as an example, in the nth row, the shielding signal SU2 of the shielding sub-circuit of the second shift register switches to a high level, which can shield the data writing in the nth row. The shielding signal SU1 of the shielding sub-circuit of the first shift register can switch to a high level 1H in advance to shield the refresh of the first node N1 in the nth row. This can ensure the normal display of the screen at the junction of the high-frequency refresh area and the low-frequency refresh area.

[0116] Taking Figure 18 as an example, in the nth row, the shielding signal SU of the shielding sub-circuit of the first shift register is switched to a high level, which can shield the refresh of the first node N1 in the nth row, thereby ensuring the normal display of the image at the junction of the high-frequency refresh area and the low-frequency refresh area.

[0117] This disclosure also provides a display device, including the display substrate 20 described above. In some embodiments, the display device may be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, wearable device, etc., and this disclosure does not limit this.

[0118] Furthermore, those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of one or more embodiments of this disclosure as described above, which are not provided in detail for the sake of brevity.

[0119] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

Claims

1. A display control circuit, comprising: at least two groups of shift register circuits, including a first group of shift register circuits and a second group of shift register circuits; the first group of shift register circuits includes a plurality of first shift registers arranged in cascade, and the second group of shift register circuits includes a plurality of second shift registers arranged in cascade; a pixel circuit including an initialization sub-circuit, a storage sub-circuit, a driving sub-circuit and a data writing sub-circuit, the initialization sub-circuit is connected to a first node, the storage sub-circuit is connected to the first node and a second node respectively, the data writing sub-circuit is connected to the second node, and the driving sub-circuit is connected to the first node; wherein a control terminal of the initialization sub-circuit is connected to a first output terminal of the first shift register, and a control terminal of the data writing sub-circuit is connected to a first output terminal of the second shift register; the first shift register and the second shift register include a shift register sub-circuit, and at least one of the first shift register and the second shift register further includes a shielding sub-circuit connected to the shift register sub-circuit; the shift register sub-circuit is configured to output a cascade signal based on an input signal; and an output terminal of the shielding sub-circuit serves as the first output terminal and is configured to output a control signal based on a shielding signal, the control signal is a first level when the shielding signal is a first level, and the control signal is the same as the cascade signal when the shielding signal is a second level, wherein the first level is different from the second level.

2. The display control circuit of claim 1, wherein the pixel circuit further includes a compensation sub-circuit, a first terminal of the compensation sub-circuit is connected to the first node and configured to write a compensation voltage to the first node, a second terminal is connected to an output terminal of the driving sub-circuit, and a control terminal is connected to the first output terminal of the second shift register; and the first shift register and the second shift register include the shielding sub-circuit, and the control signal output by the shielding sub-circuit is a row scanning signal.

3. The display control circuit according to claim 2, wherein The driving mode of the first shift register and the second shift register is double-side driving.

4. The display control circuit of claim 1, wherein the at least two groups of shift register circuits further include a third group of shift register circuits, and the third group of shift register circuits includes a plurality of third shift registers arranged in cascade; the initialization sub-circuit includes a first sub-circuit and a second sub-circuit, an input terminal of the first sub-circuit is configured to receive an initialization voltage signal, an output terminal is connected to a third node, and a control terminal is connected to an output terminal of the third shift register, an input terminal of the second sub-circuit is connected to the third node, an output terminal is connected to the first node, and a control terminal is connected to the first output terminal of the first shift register; and the second sub-circuit is further configured to write a compensation voltage to the first node in a compensation phase.

5. The display control circuit of claim 4, wherein The first shift register comprises the shielding sub-circuit, and the control signal output by the shielding sub-circuit is a light-emitting control signal. The shift register sub-circuit in the second shift register is further configured to output a row scanning signal to a control end of the data writing sub-circuit.

6. The display control circuit of claim 4, wherein, The first shift register and the second shift register comprise the shielding sub-circuit. The control signal output by the shielding sub-circuit in the first shift register is a light-emitting control signal. The control signal output by the shielding sub-circuit in the second shift register is a row scanning signal.

7. The display control circuit according to claim 4, wherein The driving mode of the first shift register and the third shift register is single-side driving, and the driving mode of the second shift register is double-side driving.

8. The display control circuit of claim 1, wherein, The pixel circuit further comprises a compensation sub-circuit, a first end of the compensation sub-circuit is connected with the first node, the compensation sub-circuit is configured to write a compensation voltage to the first node, a second end of the compensation sub-circuit is connected with the output end of the driving sub-circuit, and a control end of the compensation sub-circuit is connected with a first output end of the second shift register. The second shift register comprises a shielding sub-circuit, and the control signal output by the shielding sub-circuit is a row scanning signal. The initialization sub-circuit is connected with a first output end of the first shift register and a first output end of a second shift register of a previous stage, respectively, and is configured to write the initialization voltage to the first node under control of a control signal output by the first output end of the first shift register and a control signal output by the first output end of the second shift register of the previous stage.

9. The display control circuit of claim 8, wherein, The initialization sub-circuit comprises a third sub-circuit and a fourth sub-circuit, an input end of the third sub-circuit is configured to receive an initialization voltage signal, an output end of the third sub-circuit is connected with an input end of the fourth sub-circuit, and an output end of the fourth sub-circuit is connected with the first node. A control end of one of the third sub-circuit and the fourth sub-circuit is connected with the first output end of the first shift register, and a control end of the other is connected with the first output end of the second shift register of the previous stage.

10. The display control circuit of claim 8, wherein, The initialization sub-circuit comprises a third sub-circuit and a fourth control sub-circuit, an input end of the third sub-circuit is configured to receive an initialization voltage signal, an output end of the third sub-circuit is connected with the first node, a control end of the third sub-circuit is connected with an output end of the fourth sub-circuit, an input end of the fourth sub-circuit is connected with the first output end of the second shift register of the previous stage, and a control end of the fourth sub-circuit is connected with the first output end of the first shift register. The driving mode of the first shift register is single-side driving or double-side driving, and the driving mode of the second shift register is double-side driving.

11. The display control circuit according to any one of claims 8 to 10, wherein 12. The display control circuit of claim 1, wherein, ​ The at least two groups of shift register circuits further include a third group of shift register circuits, a fourth group of shift register circuits and a fifth group of shift register circuits, the third group of shift register circuits includes a plurality of third shift registers arranged in cascade, the fourth group of shift register circuits includes a plurality of fourth shift registers arranged in cascade, and the fifth group of shift register circuits includes a plurality of fifth shift registers arranged in cascade; The data writing sub-circuit includes a fifth sub-circuit and a sixth sub-circuit, the fifth sub-circuit has an input end for receiving a data voltage signal, an output end connected with the second node, and a control end connected with a first output end of the second shift register, and the sixth sub-circuit has an input end for receiving an initialization voltage signal, an output end connected with the second node, and a control end connected with an output end of the third shift register; The initialization sub-circuit includes a seventh sub-circuit, an eighth sub-circuit and a ninth sub-circuit, the seventh sub-circuit has an input end for receiving an initialization voltage signal, an output end connected with a fourth node, and a control end connected with an output end of the fourth shift register, the eighth sub-circuit has an input end connected with the fourth node, an output end connected with a third node, and a control end connected with an output end of the fifth shift register, and the ninth sub-circuit has an input end connected with the third node, an output end connected with the first node, and a control end connected with a first output end of the first shift register; The first shift register includes a shielding sub-circuit, and the control signal output by the shielding sub-circuit is a light-emitting control signal; The eighth sub-circuit is further configured to write a light-emitting control voltage from the fourth node to the light-emitting element in a light-emitting stage; and The ninth sub-circuit is further configured to write a compensation voltage to the first node in a compensation stage.

13. The display control circuit according to any one of claims 1 to 12, wherein The transistors in the pixel circuit are all low-temperature polysilicon transistors.

14. A display substrate, comprising: a substrate substrate, and the display control circuit in any one of claims 1-13, which is arranged on one side of the substrate substrate.

15. A display control method applied to the display substrate in claim 14, the method comprising: determining a first display area and a second display area of the display substrate; writing a first level to a shielding signal input end of a shielding sub-circuit in a shift register corresponding to the first display area; and writing a second level to the shielding signal input end of the shielding sub-circuit in the shift register corresponding to the second display area, wherein the first level is different from the second level.

16. A display device comprising the display substrate in claim 15. ​

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