Shift register circuit and control method therefor, and gate driver circuit and display apparatus

Abstract

Provided in the present disclosure are a shift register circuit and a control method therefor, and a gate driver circuit and a display apparatus. The shift register circuit comprises: an input sub-circuit, which is electrically connected to an input end, a pull-up node, a first clock signal end and a second clock signal end, and is configured to enable a connection between the input end and the pull-up node on the basis of a signal from the first clock signal end, and enable a connection between the second clock signal end and the pull-up node on the basis of signals from the second clock signal end and the pull-up node; a pull-up sub-circuit, which outputs the signal from the second clock signal end to an output end on the basis of the potential of the pull-up node; a first pull-down control sub-circuit, which controls the potential of a first pull-down node on the basis of signals from a first pull-down control end and the pull-up node; and a first pull-down sub-circuit, which electrically connects a first power signal end to the output end on the basis of a signal from the first pull-down node. The embodiments provided in the present disclosure implement an N-type shift register circuit, thereby improving the stability and reliability of a gate driving signal.

Description

Shift register circuit and its control method, gate drive circuit, display device

[0001] This application claims priority to Chinese Patent Application No. 202410696058.8, filed on May 31, 2024, entitled "Shift Register Circuit and Control Method Thereof, Gate Drive Circuit, Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to a shift register circuit and its control method, a gate driving circuit, and a display device. Background Technology

[0003] With the advancement of display technology, high-resolution, narrow-bezel display panels have become a development trend. To address this, Gate Driver on Array (GOA) technology, which places the display on the array substrate, has emerged. GOA technology replaces external driver chips and offers advantages such as lower cost, fewer processing steps, and higher production capacity.

[0004] If the GOA includes only N-type transistors instead of P-type transistors, this circuit can be applied to oxide display panels. The transistors in such display panels are all low-temperature polycrystalline oxide (LPTO) transistors. Compared with low-temperature polysilicon (LPTS) transistors, LPTO can simplify the process, reduce leakage current, and prevent the degradation of the driving capability of transistors that output low signals during most frames, effectively enhancing the reliability and stability of the gate output signal. Summary of the Invention

[0005] The first aspect of this disclosure provides a shift register circuit, comprising:

[0006] The input sub-circuit, electrically connected to the input terminal, the pull-up node, the first clock signal terminal, and the second clock signal terminal, is configured to enable the connection between the input terminal and the pull-up node based on the signal from the first clock signal terminal, and to enable the connection between the second clock signal terminal and the pull-up node based on the signals from the second clock signal terminal and the pull-up node.

[0007] The pull-up circuit is electrically connected to the pull-up node, the second clock signal terminal, and the output terminal. It is configured to output the signal from the second clock signal terminal to the output terminal based on the potential of the pull-up node.

[0008] The first pull-down control sub-circuit is electrically connected to the first pull-down control terminal, the pull-up node, and the first pull-down node, and is configured to control the potential of the first pull-down node based on the signals from the first pull-down control terminal and the pull-up node.

[0009] The first pull-down sub-circuit is electrically connected to the first pull-down node, the first power signal terminal, and the output terminal, and is configured to enable the connection between the first power signal terminal and the output terminal based on the signal of the first pull-down node.

[0010] Optionally, the input sub-circuit includes: a primary first transistor, a secondary first transistor, a second transistor, and a third transistor.

[0011] The first electrode of the primary transistor is connected to the input terminal, the second electrode is connected to the first node, and the control electrode is connected to the first clock signal terminal.

[0012] The first electrode of the secondary transistor is connected to the first node, the second electrode is connected to the pull-up node, and the control electrode is connected to the first clock signal terminal.

[0013] The first and control terminals of the second transistor are electrically connected to the second clock signal terminal, and the second terminal is electrically connected to the first terminal of the third transistor.

[0014] The second electrode of the third transistor is connected to the first node, and the control electrode is connected to the pull-up node.

[0015] Optionally, the first pull-down control sub-circuit includes: a primary fourth transistor, a secondary fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor; the first pull-down sub-circuit also includes: a seventh transistor (T11).

[0016] The first and control terminals of the primary fourth transistor are electrically connected to the first pull-down control terminal, and the second terminal is electrically connected to the first intermediate node.

[0017] The first electrode of the fourth secondary transistor is connected to the first intermediate node, the second electrode is connected to the second node, and the control electrode is connected to the first pull-down control terminal.

[0018] The first electrode of the fifth transistor is connected to the first pull-down control terminal, the second electrode is connected to the first pull-down node, and the control electrode is connected to the second node.

[0019] The first electrode of the sixth transistor is connected to the second node, the second electrode is connected to the first power signal terminal, and the control electrode is connected to the pull-up node.

[0020] The first terminal of the first capacitor is connected to the second node, and the second terminal is connected to the first pull-down node.

[0021] The first electrode of the seventh transistor is connected to the output terminal, the second electrode is connected to the first power signal terminal, and the control electrode is connected to the first pull-down node.

[0022] Optionally, the pull-up circuit includes: an eighth transistor and a second capacitor.

[0023] The first electrode of the eighth transistor is connected to the second clock signal terminal, the second electrode is connected to the output terminal, and the control electrode is connected to the pull-up node.

[0024] Optionally, the shift register circuit also includes: a ninth transistor,

[0025] The first electrode of the ninth transistor is electrically connected to the control electrode of the eighth transistor, the second electrode is electrically connected to the pull-up node, and the control electrode is electrically connected to the second power supply signal terminal.

[0026] Optionally, the shift register circuit further includes: a first interlock sub-circuit.

[0027] The first interlocking sub-circuit includes a tenth transistor and an eleventh transistor, wherein...

[0028] The first electrode of the tenth transistor is connected to the pull-up node, the second electrode is connected to the third power supply signal terminal, and the control electrode is connected to the first pull-down node.

[0029] The first electrode of the eleventh transistor is connected to the first pull-down node, the second electrode is connected to the third power supply signal terminal, and the control electrode is connected to the pull-up node, or...

[0030] The first interlocking sub-circuit includes a primary tenth transistor, a secondary tenth transistor, and an eleventh transistor.

[0031] The first electrode of the primary tenth transistor is electrically connected to the pull-up node, the second electrode is electrically connected to the second intermediate node and then to the first node, and the control electrode is electrically connected to the first pull-down node.

[0032] The first electrode of the tenth secondary transistor is connected to the second intermediate node, the second electrode is connected to the third power signal terminal, and the control electrode is connected to the first pull-down node.

[0033] The first electrode of the eleventh transistor is connected to the first pull-down node, the second electrode is connected to the third power signal terminal, and the control electrode is connected to the pull-up node.

[0034] Optionally, the shift register circuit also includes:

[0035] The second pull-down control sub-circuit is electrically connected to the third power signal terminal, the pull-up node, and the second pull-down node. It is configured to control the potential of the second pull-down node based on the signals from the second pull-down control terminal and the pull-up node.

[0036] The second pull-down sub-circuit is electrically connected to the second pull-down node, the first power signal terminal, and the output terminal, and is configured to enable the connection between the first power signal terminal and the output terminal based on the signal of the second pull-down node.

[0037] Optionally, the second pull-down control sub-circuit includes: a primary twelfth transistor, a secondary twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a third capacitor; the second pull-down sub-circuit also includes: a fifteenth transistor.

[0038] The first and control terminals of the primary twelfth transistor are electrically connected to the second pull-down control terminal, and the second terminal is electrically connected to the third intermediate node.

[0039] The first electrode of the twelfth secondary transistor is connected to the third intermediate node, the second electrode is connected to the third node, and the control electrode is connected to the first power signal terminal.

[0040] The first electrode of the thirteenth transistor is connected to the second pull-down control terminal, the second electrode is connected to the second pull-down node, and the control electrode is connected to the third node.

[0041] The first electrode of the fourteenth transistor is connected to the third node, the second electrode is connected to the first power signal terminal, and the control electrode is connected to the pull-up node.

[0042] The first terminal of the third capacitor is connected to the third node, and the second terminal is connected to the second pull-down node.

[0043] The first electrode of the fifteenth transistor is connected to the output terminal, the second electrode is connected to the first power signal terminal, and the control electrode is connected to the second pull-down node.

[0044] Optionally, the shift register circuit further includes a second interlock sub-circuit, which includes a primary sixteenth transistor, a secondary sixteenth transistor, and a seventeenth transistor.

[0045] The first electrode of the primary sixteenth transistor is connected to the pull-up node, the second electrode is connected to the fourth intermediate node and then to the first node, and the control electrode is connected to the second pull-down node.

[0046] The first electrode of the sixteenth secondary transistor is connected to the fourth intermediate node, the second electrode is connected to the third power signal terminal, and the control electrode is connected to the second pull-down node.

[0047] The first electrode of the seventeenth transistor is connected to the second pull-down node, the second electrode is connected to the third power signal terminal, and the control electrode is connected to the pull-up node.

[0048] Optionally, the shift register circuit further includes a carry sub-circuit, which includes an eighteenth transistor.

[0049] The first electrode of the eighteenth transistor is connected to the second clock signal terminal, the second electrode is connected to the carry output terminal, and the control electrode is connected to the pull-up node.

[0050] Optionally, the shift register circuit further includes: a first noise reduction sub-circuit, which includes a nineteenth transistor.

[0051] The first electrode of the nineteenth transistor is connected to the carry output terminal, the second electrode is connected to the third power signal terminal, and the control electrode is connected to the first pull-down node.

[0052] Optionally, the shift register circuit further includes: a carry output sub-circuit and a second noise reduction sub-circuit, wherein the carry output sub-circuit includes an eighteenth transistor and the second noise reduction sub-circuit includes a twentieth transistor.

[0053] The first electrode of the eighteenth transistor is connected to the second clock signal terminal, the second electrode is connected to the carry output terminal, and the control electrode is connected to the pull-up node.

[0054] The first electrode of the twentieth transistor is connected to the carry output terminal, the second electrode is connected to the third power signal terminal, and the control electrode is connected to the second pull-down node.

[0055] Optionally, the shift register circuit further includes a reset sub-circuit, electrically connected to the reset control terminal, the first power supply signal terminal, and the pull-up node, configured to enable the connection between the first power supply signal terminal and the pull-up node based on the signal from the reset control terminal.

[0056] A second aspect of this disclosure provides a gate driving circuit, comprising: N cascaded shift register circuits as described above, where N is a natural number greater than 2, wherein...

[0057] The input terminal of the nth stage shift register circuit is electrically connected to the output terminal or carry output terminal of another stage shift register circuit, where n is greater than 1 and less than or equal to N;

[0058] The input terminal of the first-stage shift register circuit is electrically connected to the start signal terminal of the gate drive circuit.

[0059] A third aspect of this disclosure provides a display device including the gate driving circuit described above.

[0060] The fourth aspect of this disclosure provides a control method for the shift register circuit as described above, comprising:

[0061] In the first stage, a high-level signal is provided to the input terminal as the input signal, and the input sub-circuit transmits the input signal to the pull-up node to pull up the potential of the pull-up node;

[0062] In the second stage, the pull-up sub-circuit transmits the signal from the second clock signal terminal to the output terminal under the control of the potential of the pull-up node. Attached Figure Description

[0063] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0064] Figure 1 shows a schematic structural block diagram of the main modules included in a shift register circuit according to an embodiment of the present disclosure;

[0065] Figure 2 is a schematic circuit diagram of a shift register circuit according to an embodiment of the present disclosure;

[0066] Figure 3 is a schematic circuit diagram of a shift register circuit according to another embodiment of the present disclosure;

[0067] Figure 4 shows a schematic timing diagram of each key signal in a shift register circuit according to an embodiment of the present disclosure within a frame time period;

[0068] Figures 5 to 10 show the working principle diagrams of the shift register circuit of the embodiment shown in Figure 3;

[0069] Figure 11 shows a schematic timing diagram of key signals in a shift register circuit according to an embodiment of the present disclosure over two consecutive frame time periods;

[0070] Figure 12 shows a simulation diagram of the output of a shift register circuit according to an embodiment of the present disclosure. Detailed Implementation

[0071] To more clearly illustrate this disclosure, the preferred embodiments and accompanying drawings will be used for further description. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of this disclosure.

[0072] It should be noted that, unless otherwise defined, the technical or scientific terms used in this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "an," "a," or "the," etc., do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "comprising," "including," or similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Furthermore, in this disclosure, electrical connections can be direct connections or connections between transistors that are separated by a single conducting transistor.

[0073] The transistors used in this embodiment can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors are symmetrical, there is no distinction between them. In this embodiment, because all transistors are N-type transistors, to distinguish between the source and drain, the drain is called the first terminal, the source is called the second terminal, and the gate is called the control terminal. When the gate input is high, the source and drain are turned on. In addition, when both the gate and source are at the same high potential, the source and drain are not turned on.

[0074] To achieve at least one of the above objectives, referring to Figure 1, this disclosure provides a shift register circuit, including:

[0075] The input sub-circuit 10 is electrically connected to the input terminal STV, the pull-up node Q, the first clock signal terminal CK1, and the second clock signal terminal CK2. It is configured to enable the connection between the input terminal STV and the pull-up node Q based on the signal of the first clock signal terminal CK1, and to enable the connection between the second clock signal terminal CK2 and the pull-up node Q based on the signals of the second clock signal terminal CK2 and the pull-up node Q.

[0076] Pull-up sub-circuit 20 is electrically connected to pull-up node Q, second clock signal terminal CK2 and output terminal OUT, and is configured to output the signal of second clock signal terminal CK2 to output terminal OUT based on the potential of pull-up node Q;

[0077] The first pull-down control sub-circuit 30 is electrically connected to the first pull-down control terminal GBI1, the pull-up node Q and the first pull-down node QB1, and is configured to control the potential of the first pull-down node QB1 based on the signals of the first pull-down control terminal GBI1 and the pull-up node Q.

[0078] The first pull-down sub-circuit 40 is electrically connected to the first pull-down node QB1, the first power signal terminal VL, and the output terminal OUT, and is configured to enable the connection between the first power signal terminal VL and the output terminal OUT based on the signal of the first pull-down node QB1.

[0079] In this embodiment, by providing an improved input sub-circuit, and writing the input signal to the pull-up node electrically connected to the input of the pull-up sub-circuit based on the signal of the first clock signal terminal, and stabilizing the potential of the pull-up node based on the signals of the second clock signal terminal and the pull-up node, the N-type gate drive circuit composed of the shift register circuit can normally achieve shift output, thereby improving the reliability and stability of the gate drive signal.

[0080] To illustrate the structure and functional advantages of the shift register circuit in the embodiments of this disclosure in detail, specific examples are provided below with detailed descriptions of the specific circuit structure. However, it should be specifically noted that the embodiments of this disclosure are not limited to the specific shift register circuits exemplified below. That is, the input sub-circuit 10, pull-up sub-circuit 20, first pull-down control sub-circuit 30, and first pull-down sub-circuit 40 included in the shift register circuit of this disclosure are essentially the main functional implementation sub-circuits in the shift register circuit, and can guarantee the implementation of basic shift register functions.

[0081] In a specific embodiment, as shown in FIG2, a circuit diagram of a specific circuit that satisfies the block diagram shown in FIG1 is presented. It can be any of N cascaded shift register circuits, where N is an integer greater than or equal to 2.

[0082] Referring to Figures 1 and 2, the shift register circuit includes an input sub-circuit 10, a pull-up sub-circuit 20, a pull-down control sub-circuit 30, and a pull-down circuit 40.

[0083] Specifically, the input sub-circuit 10 is electrically connected to the input terminal STV, the pull-up node Q, the first clock signal terminal CK1, and the second clock signal terminal CK2. It is configured to write the signal of the input terminal STV into the pull-up node Q based on the signal of the first clock signal terminal CK1, and to open the connection between the second clock signal terminal CK2 and the pull-up node Q based on the signals of the second clock signal terminal CK2 and the pull-up node Q, thereby stabilizing the potential of the pull-up node Q.

[0084] Specifically, the input sub-circuit includes: a primary first transistor T1-1, a secondary first transistor T1-2, a second transistor T2, and a third transistor T3. The first electrode of the primary first transistor T1-1 is electrically connected to the input terminal STV, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the first clock signal terminal CK1. The first electrode of the secondary first transistor T1-2 is electrically connected to the first node N1, the second electrode is electrically connected to the pull-up node Q, and the control electrode is electrically connected to the first clock signal terminal CK1. The first electrode and the control electrode of the second transistor T2 are electrically connected to the second clock signal terminal CK2, and the second electrode is electrically connected to the first electrode of the third transistor T3. The second electrode of the third transistor T3 is electrically connected to the first node N1, and the control electrode is electrically connected to the pull-up node Q.

[0085] Referring to Figure 1, the pull-up sub-circuit 20 is electrically connected to the pull-up node Q, the second clock signal terminal CK2, and the output terminal OUT, and is configured to output the signal of the second clock signal terminal CK2 to the output terminal OUT based on the potential of the pull-up node Q.

[0086] During a frame of image driving, when the first clock signal connected to the first clock signal terminal CK1 is high, the primary first transistor T1-1 and the secondary first transistor T1-2 are turned on. If the input signal input to the input terminal STV is high at this time, the high-level signal is written to the pull-up node Q. Afterwards, when the input terminal STV becomes low, the first clock signal terminal CK1 is controlled to be low and the second clock signal terminal CK2 is high. In response to the high-level pull-up node Q and the high-level second clock signal terminal CK2, the second transistor T2 and the third transistor T3 are turned on. The high-level signal connected to the second transistor T2 is used to write a high-level signal to the first node N1, thereby preventing the low-potential input signal from being pulled low by leakage through the primary first transistor T1-1 and pulling down the pull-up node Q.

[0087] Importantly, by providing a second transistor T2, and connecting the first terminal and control terminal of the second transistor T2 to the second clock signal terminal CK2, it is possible to ensure that the first terminal of the third transistor T3 is connected to a high-level signal during the pull-up output period of the pull-up circuit 30. When the pull-up circuit 20 has no effective output due to the low level of the second clock signal terminal CK2, the first terminal of the third transistor T3 has no signal input, thereby making the pull-up node Q stable at a high level during the period when it needs to be high. In addition, by connecting the first terminal of the third transistor T3 to the second transistor T2 controlled by the clock signal, it is also possible to avoid the third transistor T3 being damaged by a large current surge when it is directly connected to a signal terminal that changes between low and high levels, and the transistor is turned on while the first terminal is at a low level.

[0088] Referring again to Figure 1, the first pull-down control sub-circuit 30 is electrically connected to the first pull-down control terminal BGI1, the pull-up node Q, and the first pull-down node QB1. It is configured to control the potential of the first pull-down node QB1 based on the signals of the first pull-down control terminal BGI1 and the pull-up node Q. The first pull-down sub-circuit 40 is electrically connected to the first pull-down node QB1, the first power signal terminal VL, and the output terminal OUT. It is configured to open the connection between the first power signal terminal VL and the output terminal OUT based on the signal of the first pull-down node QB1, thereby using the potential of the first power signal terminal VL to pull down the potential of the output terminal OUT.

[0089] Specifically, referring to FIG2, the first pull-down control sub-circuit 30 includes: primary fourth transistor T4-1, secondary fourth transistor T4-2, fifth transistor T5, sixth transistor T6 and first capacitor C1; the first pull-down sub-circuit 40 includes: seventh transistor T7.

[0090] Specifically, the primary fourth transistor T4-1 has its first electrode and control electrode electrically connected to the first pull-down control terminal BGI1, and its second electrode electrically connected to the first intermediate node. The secondary fourth transistor T4-2 has its first electrode connected to the first intermediate node, its second electrode connected to the second node N2, and its control electrode connected to the first pull-down control terminal BGI1. The fifth transistor T5 has its first electrode connected to the first pull-down control terminal BGI1, its second electrode connected to the first pull-down node QB1, and its control electrode connected to the second node N2. The sixth transistor T6 has its first electrode connected to the second node N2, its second electrode connected to the first power signal terminal VL, and its control electrode connected to the pull-up node Q. The first capacitor C1 has its first electrode connected to the second node N2, and its second electrode connected to the first pull-down node QB1. The seventh transistor T7 has its first electrode connected to the output terminal OUT, its second electrode connected to the first power signal terminal VL, and its control electrode connected to the first pull-down node QB1.

[0091] When the pull-up node Q is high, the sixth transistor T6 is turned on, so that the low-level first power supply signal terminal VL is applied to the control electrode of the fifth transistor T5, thereby turning off the fifth transistor T5. During the period when the signal at the pull-up node Q is high, there is also a period when the first pull-down control terminal GBI1 is high. During the period when both the pull-up node Q and the first pull-down control terminal GBI1 are high, the primary fourth transistor T4-1 and the secondary fourth transistor T4-2 are also turned on. Therefore, when the fifth transistor T5, the primary fourth transistor T4-1, and the secondary fourth transistor T4-2 are all turned on, the control electrode of the fifth transistor T5 can maintain the level of the first power supply signal terminal VL due to the voltage drop caused by the resistance of the primary fourth transistor T4-1 and the secondary fourth transistor T4-2. Therefore, when both the pull-up node Q and the first pull-down control terminal GBI1 are high, the fifth transistor T5 can be well maintained in its off state. The first capacitor C1 can accelerate the turning on and off of the fifth transistor T5 to achieve high-speed driving of the display device by the gate drive circuit. Specifically, by maintaining the low level of the first pull-down node QB1 through the first capacitor C1, the fifth transistor T5 is kept off, and the first pull-down node QB1 is stably kept at a low level, thereby ensuring the turn-off of the seventh transistor T7 and thus ensuring the normal output of the output terminal OUT. By maintaining the high level through the first capacitor C1, the first pull-down node QB1 is quickly pulled high, and the potential of the output terminal OUT is pulled down by the potential of the first power supply signal terminal VL.

[0092] Referring to Figure 2, the pull-up circuit 20 includes an eighth transistor T8 and a second capacitor C2. The first electrode of the eighth transistor T8 is electrically connected to the second clock signal terminal CK2, the second electrode is electrically connected to the output terminal OUT, and the control electrode is electrically connected to the pull-up node Q. When a high-level signal is applied to the control electrode of the eighth transistor T8 and the signal at the second clock signal terminal CK2 is high, the eighth transistor T8 is turned on and outputs the high-level signal of the second clock signal terminal CK2 through the output terminal OUT.

[0093] Optionally, referring to Figure 2, a normally open transistor 50, which is the ninth transistor T9, is also provided between the first pull-up node Q and the control electrode of the eighth transistor T8. The first electrode of the ninth transistor T9 is electrically connected to the control electrode of the eighth transistor T8, i.e., node QF in Figure 2, and the second electrode is electrically connected to the pull-up node Q. The control electrode is electrically connected to the second power supply signal terminal VH. Since the second power supply signal terminal VH is always at a high level, the transistor is normally in the conducting state. However, when the control electrode potential of the eighth transistor T8 becomes 2H-L due to the bootstrap effect of the second capacitor C2 in the pull-up sub-circuit 20, where H is the high level potential of the second clock signal terminal CK2 and L is the low level potential, if this excessively high potential is written to the second electrode of the primary first transistor T1-1 and the secondary first transistor T1-2, the voltage difference between the primary first transistor T1-1 and the secondary first transistor T1-2 will be too large and may cause damage. By setting the ninth transistor T9 such that when the potential of node QF is 2H-L, the potentials of the control electrode and the second electrode of the ninth transistor T9 are both H, the ninth transistor T9 is turned off because Vgs = 0, thus preventing 2H-L from being written to the second electrode of the primary first transistor T1-1 and the secondary first transistor T1-2, thereby protecting the transistors in the input sub-circuit 10.

[0094] Optionally, referring to FIG2, the shift register circuit further includes a first interlock sub-circuit 60, which includes a tenth transistor T10 and an eleventh transistor T11. The tenth transistor T10 has its first electrode connected to the pull-up node Q, its second electrode connected to the third power supply signal terminal VL2, and its control electrode connected to the first pull-down node QB1. Similarly, the eleventh transistor T11 has its first electrode connected to the first pull-down node QB1, its second electrode connected to the third power supply signal terminal VL2, and its control electrode connected to the pull-up node Q.

[0095] When the first pull-down node QB1 is high, the tenth transistor T10 is turned on, applying the low level of the third power supply signal terminal VL2 to the pull-up node Q. When the pull-up node Q is high, the eleventh transistor T11 is turned on, applying the low level of the third power supply signal terminal VL2 to the first pull-down node QB1. Therefore, the presence of the tenth transistor T10 and the eleventh transistor T11 ensures that the pull-up node Q and the first pull-down node QB1 are not both high or both low simultaneously.

[0096] Optionally, referring to Figure 2, the shift register circuit further includes a carry sub-circuit 70, which includes an eighteenth transistor T18. The first electrode of the eighteenth transistor T18 is electrically connected to the second clock signal terminal CK2, the second electrode is electrically connected to the carry output terminal CR, and the control electrode is electrically connected to the pull-up node Q. When the eighteenth transistor T18 receives a high-level signal and the second clock signal terminal CK2 is high, the high level is carried over to the input terminal STV of the next-stage shift register circuit, thereby realizing the shift register function.

[0097] Of course, when the shift register circuit includes normally open transistor 50, the control electrode of the eighteenth transistor T18 is directly electrically connected to the first electrode of the ninth transistor T9.

[0098] Optionally, the shift register circuit further includes a first noise reduction sub-circuit 80, which includes a nineteenth transistor T19. The first electrode of the nineteenth transistor T19 is electrically connected to the carry output terminal CR, the second electrode is electrically connected to the third power supply signal terminal VL2, and the control electrode is electrically connected to the first pull-down node QB1. When the first pull-down node QB1 is active, the nineteenth transistor T19 is turned on, and the potential of the third power supply signal terminal VL2 is used to pull down the carry output terminal CR to reduce noise at the carry output terminal CR.

[0099] Considering that the transistor in the first pull-down sub-circuit 30 is a transistor that outputs a low-level signal during most frames, in order to prevent the deterioration of the driving capability of the first pull-down sub-circuit, it is considered to add another pull-down sub-circuit and make it operate alternately with the first pull-down sub-circuit.

[0100] In some alternative embodiments, referring to FIG3, the shift register circuit further includes: a second pull-down control sub-circuit and a second pull-down sub-circuit.

[0101] The second pull-down control sub-circuit is electrically connected to the second pull-down control terminal BGI2, the pull-up node Q, and the second pull-down node QB2. It is configured to control the potential of the second pull-down node QB2 based on the signals of the second pull-down control terminal BGI2 and the pull-up node Q. The second pull-down sub-circuit is electrically connected to the second pull-down node QB2, the first power signal terminal VL, and the output terminal OUT. It is configured to enable the connection between the first power signal terminal VL and the output terminal OUT based on the signal of the second pull-down node QB2, thereby using the potential of the first power signal terminal VL to pull down the potential of the output terminal OUT.

[0102] Specifically, referring to FIG3, the second pull-down control sub-circuit includes: primary twelfth transistor T12-1, secondary twelfth transistor T12-2, thirteenth transistor T13, fourteenth transistor T14 and third capacitor C3, and the second pull-down sub-circuit includes: fifteenth transistor T15. The primary twelfth transistor T12-1 has its first and control electrodes connected to the second pull-down control terminal BGI2, and its second electrode connected to the third intermediate node. The secondary twelfth transistor T12-1 has its first electrode connected to the third intermediate node, its second electrode connected to the third node N3, and its control electrode connected to the first power supply signal terminal VL. The thirteenth transistor T13 has its first electrode connected to the second pull-down control terminal BGI2, its second electrode connected to the second pull-down node QB2, and its control electrode connected to the third node N3. The fourteenth transistor T14 has its first electrode connected to the third node N3, its second electrode connected to the first power supply signal terminal VL, and its control electrode connected to the pull-up node Q. The third capacitor C3 has its first electrode connected to the third node N3, and its second electrode connected to the second pull-down node QB2. The fifteenth transistor T15 has its first electrode connected to the output terminal OUT, its second electrode connected to the first power supply signal terminal VL, and its control electrode connected to the second pull-down node QB2.

[0103] When the pull-up node Q is high, the fourteenth transistor T14 is turned on, so that the low-level first power supply signal terminal VL is applied to the control electrode of the thirteenth transistor T13, thereby turning off the thirteenth transistor T13. During the period when the signal at the pull-up node Q is high, there is also a period when the second pull-down control terminal GBI2 is high. During the period when both the pull-up node Q and the second pull-down control terminal GBI2 are high, the primary twelfth transistor T12-1 and the secondary twelfth transistor T12-2 are also turned on. Therefore, when the thirteenth transistor T13, the primary twelfth transistor T12-1, and the secondary twelfth transistor T12-2 are all turned on, the control electrode of the thirteenth transistor T13 can maintain the level of the first power supply signal terminal VL due to the voltage drop caused by the resistance of the primary twelfth transistor T12-1 and the secondary twelfth transistor T12-2. Therefore, when both the pull-up node Q and the first pull-down control terminal GBI1 are high, the fifth transistor T5 can be kept off. The first capacitor C1 accelerates the turn-on and turn-off of the fifth transistor T5 to achieve high-speed driving of the display device by the gate drive circuit. Specifically, by maintaining the low level of the second pull-down node QB2 through the first capacitor C1, the thirteenth transistor T13 is kept off, so that the second pull-down node QB2 is stably kept at a low level, thereby ensuring the turn-off of the fifteenth transistor T15, and thus ensuring the normal output of the output terminal OUT. By maintaining a high level through the third capacitor C3, the second pull-down node QB2 is quickly pulled high, and the potential of the output terminal OUT is pulled down by the potential of the first power signal terminal VL.

[0104] Referring again to Figure 3, which shows another form of the first interlocking sub-circuit, as shown in Figure 3, in this example, the first interlocking sub-circuit includes a primary tenth transistor T10-1, a secondary tenth transistor T10-2, and an eleventh transistor T11. The primary tenth transistor T10-1 has its first electrode electrically connected to the pull-up node Q, its second electrode electrically connected to the second intermediate node and then to the first node N1, and its control electrode electrically connected to the first pull-down node QB1. The secondary tenth transistor T10-2 has its first electrode electrically connected to the second intermediate node, its second electrode electrically connected to the third power supply signal terminal VL2, and its control electrode electrically connected to the first pull-down node QB1. The eleventh transistor T11 has its first electrode electrically connected to the first pull-down node QB1, its second electrode electrically connected to the third power supply signal terminal VL2, and its control electrode electrically connected to the pull-up node Q.

[0105] The difference between this structure and the first interlock sub-circuit 60 shown in Figure 2 is that it utilizes two transistors connected in series with their source and drain connected to their electrodes, and connects their intermediate node to the first node N1. This allows the second transistor T2 and the third transistor T3 in the input sub-circuit 10 to stabilize the first pull-down node QB1, thus preventing leakage current from the primary tenth transistor T10-1 and the secondary tenth transistor T10-2 from pulling down the first pull-down node QB1. Correspondingly, this configuration prevents leakage current from a single tenth transistor T10 from pulling down the potential of the first pull-down node QB1.

[0106] Of course, this structure can also be directly applied to the example in Figure 2, thereby directly replacing the second transistor 2 in Figure 2 to form an optional embodiment. In addition, the primary tenth transistor T10-1 and the secondary tenth transistor T10-2 in Figure 3 can also be replaced by a tenth transistor T10 in Figure 2, which will not be elaborated here.

[0107] Optionally, considering that in the example shown in Figure 3, the second pull-down control sub-circuit and the second pull-down circuit work alternately with the first pull-down control sub-circuit and the first pull-down sub-circuit, it is more preferable that an interlocking sub-circuit is also required when the second pull-down control sub-circuit and the second pull-down circuit are working.

[0108] Referring to Figure 3, the shift register circuit further includes a second interlock sub-circuit, which includes a primary sixteenth transistor, a secondary sixteenth transistor T16-2, and a seventeenth transistor T17. The first electrode of the primary sixteenth transistor T16-1 is electrically connected to the pull-up node Q, the second electrode is electrically connected to the fourth intermediate node and then to the first node N1, and the control electrode is electrically connected to the second pull-down node QB2. The first electrode of the secondary sixteenth transistor T16-2 is electrically connected to the fourth intermediate node, the second electrode is electrically connected to the third power supply signal terminal VL2, and the control electrode is electrically connected to the second pull-down node QB2. The first electrode of the seventeenth transistor T17 is electrically connected to the second pull-down node QB2, the second electrode is electrically connected to the third power supply signal terminal VL2, and the control electrode is electrically connected to the pull-up node Q. This structure forms an interlock between the pull-up node Q and the second pull-down node QB2, preventing both from being simultaneously high or simultaneously low.

[0109] Furthermore, by utilizing the stabilizing effect of the second transistor T2 and the third transistor T3 in the input sub-circuit 10 on the first node N1 through the primary sixteenth transistor T16-1 and the secondary sixteenth transistor T16-2, the second pull-down node QB2 can be stabilized, thereby preventing leakage current from the primary sixteenth transistor T16-1 and the secondary sixteenth transistor T16-2 from pulling down the second pull-down node QB2. This configuration prevents leakage current from a single transistor from pulling down the potential of the second pull-down node QB2.

[0110] Alternatively, referring to Figure 3, corresponding to the added second pull-down control sub-circuit and second pull-down circuit, the shift register circuit also includes a corresponding second noise reduction sub-circuit. The second noise reduction sub-circuit includes a twentieth transistor T20, the first electrode of which is electrically connected to the carry output terminal CR, the second electrode of which is electrically connected to the third power supply signal terminal VL2, and the control electrode of which is electrically connected to the second pull-down node QB2.

[0111] Additionally, referring to Figure 3, the shift register circuit may further include a reset sub-circuit, electrically connected to the reset control terminal RST, the first power supply signal terminal VL, and the pull-up node Q, configured to open the connection between the first power supply signal terminal VL and the pull-up node Q based on the signal from the reset control terminal RST, thereby using the potential of the first power supply signal terminal VL to pull down the potential of the pull-up node Q. Optionally, the reset sub-circuit may include a primary twenty-first transistor T21-1 and a secondary twenty-first transistor T21-2. The first electrode of the primary twenty-first transistor T21-1 is electrically connected to the pull-up node Q, the second electrode is electrically connected to the fifth intermediate node, and the control electrode is electrically connected to the reset control terminal RST. The first electrode of the secondary twenty-first transistor T21-2 is electrically connected to the fifth intermediate node, the second electrode is electrically connected to the first power supply signal terminal VL, and the control electrode is electrically connected to the reset control terminal RST.

[0112] To further understand the structure and function of the shift register circuit of the present disclosure, the working principle of the circuit structure shown in Figure 3 in each time period is described below with reference to the timing diagram of one frame of image shown in Figure 4, and in conjunction with Figures 5 to 10.

[0113] It should be noted that in the diagram, the thick solid lines represent high potentials, the thin solid lines represent low potentials, the transistors circled by the dashed lines are conducting transistors, and the other transistors are off transistors.

[0114] During the frame time, the first pull-down control terminal BGI1 remains high and the second pull-down control terminal BGI2 remains low. The second pull-down control sub-circuit and the second pull-down circuit do not participate in the operation during the frame time, and the relevant transistors are all in the off state, and the corresponding lines are all at low level.

[0115] Referring to Figure 5, during the t1 time period, the signal of the first clock signal terminal CK1 is at a high level, the signal of the second clock signal terminal CK2 is at a low level, and the signal of the input terminal STV is at a low level.

[0116] Because the signal at the first clock signal terminal CK1 is high, the primary first transistor T1-1 and the secondary first transistor T1-2 are turned on, writing the low-level signal at the input terminal STV into the pull-up node Q. Because the first pull-down control terminal GBI1 changes from low to high, the primary fourth transistor T4-1, the secondary fourth transistor T4-2, and the fifth transistor T5 are turned on, writing the high level to the lower and upper plates of the first capacitor C1. The first pull-down node QB1 becomes high as the plates of the first capacitor C1 change, and the primary tenth transistor T10-1, the secondary tenth transistor T10-2, and the nineteenth transistor T19 are turned on. Additionally, because the second power supply signal terminal VH is a constant high level, the ninth transistor T9 is turned on.

[0117] It should be noted that at the instant the second pull-down control terminal GBI2 changes from high level to low level, the second pull-down node QB2 is actually high level, thus turning on the primary sixteenth transistor T16-1, the secondary sixteenth transistor T16-2, and the twentieth transistor T20, but turning them off in the subsequent period.

[0118] Referring to Figure 6, during time period t2, the signal at the second clock signal terminal CK2 is high, the signal at the first clock signal terminal CK1 is low, and the signal at the input terminal STV is low. During this time period, although the signal at the second clock signal terminal CK2 is high, the eighth transistor T8 remains off because the potential of the pull-up node Q is low and the potential of the first capacitor C1 is maintained. The signals at the output terminal OUT and the carry output terminal CR are both low.

[0119] Referring to Figure 7, during the t3 period, the signal at the first clock signal terminal CK1 is at a high level, the signal at the second clock signal terminal CK2 is at a low level, and the input terminal STV writes a high-level signal.

[0120] The high-level signal at the input terminal STV is written to the pull-up node Q as the primary first transistor T1-1 and the secondary first transistor T1-2 are turned on by the first clock signal terminal CK1, and then written to the node QF via the ninth transistor T9. As a result, the eighteenth transistor T18 and the eighth transistor T8 are turned on. However, since the signal at the second clock signal terminal CK2 is low at this time, the signals at the output terminal OUT and the carry output terminal CR are still low. However, during this period, the second capacitor C2 is charged by the high-level signal at the node QF.

[0121] Additionally, during this time period, because the pull-up node Q is at a high level, the eleventh transistor T11 in the first interlocking sub-circuit is turned on, thereby using the potential of the third power supply signal terminal VL2 to pull down the first pull-down node QB1, thus turning off the nineteenth transistor T19 and the seventh transistor T7. At the same time, the plate potential of the first capacitor C1 is at a low level, and the fifth transistor T5 is turned off.

[0122] Referring to Figure 8, during the t4 period, the signal at the second clock signal terminal CK2 is at a high level, the signal at the first clock signal terminal CK1 is at a low level, and the input terminal STV is at a low level.

[0123] Because the signal at the second clock signal terminal CK2 is high and the control terminals of the eighth transistor T8 and the eighteenth transistor T18 are still high, the output terminal OUT and the carry output terminal CR output high-level signals, thereby realizing the shift register function.

[0124] It should be noted that during this period, the second capacitor C2 continues to charge. Due to its bootstrap effect, the potential of the upper plate changes from H during period t3 to HL-L. If the excessively high potential 2H-L is written to the drain of the primary transistor T1-1 and the secondary transistor T1-2, the voltage difference of the transistors will be too large and may be damaged. Therefore, by setting the ninth transistor T9, since the potentials of the control electrode and source of the ninth transistor T9 are both H, Vgs = 0 and it cannot conduct, so the potential 2H-L at the drain cannot pass, thus protecting the primary transistor T1-1 and the secondary transistor T1-2. In addition, since the signal at the input terminal STV is low and the pull-up node Q is high at this time, if a separate transistor T1 is set, this transistor may leak current, causing the potential of the pull-up node Q to drop, which may result in insufficient activation of the eighth transistor T8 and the eighteenth transistor T18, leading to problems with the output waveform and affecting the driving capability. By setting the primary first transistor T1-1 and the secondary first transistor T1-2, and connecting the intermediate node to the first node N1 and electrically connecting it to the second terminal of the third transistor T3 and the second transistor T2, the high potential of the second clock signal terminal CK2 is written to the first node N1, preventing the low potential of the input terminal STV from leaking to the pull-up node Q.

[0125] Referring to Figure 9, during the time period t5, the signal at the first clock signal terminal CK1 is at a high level, the signal at the second clock signal terminal CK2 is at a low level, and the input terminal STV is at a low level.

[0126] The primary transistor T1-1 and the secondary transistor T1-2, when their input terminal STV is low, write a low level to the pull-up node Q, turning off the eighth transistor T8 and the eighteenth transistor T18. Because the pull-up node Q becomes level, the sixth transistor T6 turns off, and both the upper and lower plates of the first capacitor C1 become high, causing the first pull-down node BQ1 to become high. This turns on the nineteenth transistor T19 and the seventh transistor T7, thus using the potentials of the first power supply signal terminal VL and the third power supply signal terminal VL2 to pull down the output terminal OUT and the carry output terminal CR.

[0127] Referring to Figure 10, during the time period t6, the signal at the second clock signal terminal CK2 is at a high level, the signal at the first clock signal terminal CK1 is at a low level, and the input terminal STV is at a low level.

[0128] The first clock signal terminal CK1 turns off the primary first transistor T1-1 and the secondary first transistor T1-2, but has no effect on the pull-up node Q, node QF, and the first pull-down node QB1. Therefore, the output remains unchanged. As time goes by, since the input terminal STV does not change, the output terminal will not change.

[0129] Additionally, it should be noted that, referring to Figure 11, for two consecutive frames, the only difference is that the level of the first pull-down control terminal GBI1 becomes high and the level of the second pull-down control terminal GBI2 becomes low. As for the circuit, the transistors and signal lines in the second pull-down control sub-circuit and the second pull-down sub-circuit at the corresponding positions of the first pull-down control sub-circuit and the first pull-down sub-circuit undergo corresponding changes, which will not be elaborated here.

[0130] Figure 12 further shows the output simulation diagram of the shift register circuit using the embodiments of this disclosure. In the figure, the first row of signals represents the input signal IN of the input terminal STV, the second row represents the clock signal CK of the first clock signal terminal CK1, the third row represents the clock signal CB of the second clock signal terminal CK2, and the fourth row represents the output signal of the output terminal OUT. As can be seen from the simulation diagram, the clock signal CB is a clock signal with a changing level. In the next time period after the input signal IN becomes high, the output signal changes from low to high and the output waveform is consistent with the clock signal CB at this time, thus realizing the shift register function.

[0131] This disclosure provides a gate driving circuit comprising N cascaded shift register circuits of any of the above types, where N is a natural number greater than 2.

[0132] The input terminal of the nth stage shift register circuit is electrically connected to the output terminal or carry output terminal of another stage shift register circuit, where n is greater than 1 and less than or equal to N;

[0133] The input terminal of the first-stage shift register circuit is electrically connected to the start signal terminal of the gate drive circuit.

[0134] In addition, the carry output terminal of the nth stage shift register circuit is electrically connected to the input terminal STV of the (n+1)th stage shift register circuit, the reset signal terminal of the mth stage shift register circuit is electrically connected to the output terminal of another stage shift register circuit, where m is greater than or equal to 1 and less than N, and the reset signal terminal of the Nth stage shift register circuit is electrically connected to the cutoff signal terminal of the gate drive circuit.

[0135] Optionally, the other shift register circuit that serves as the carry circuit of the nth-stage shift register circuit can be the next-next-stage shift register circuit or a shift register circuit at a certain interval. For example, the nth-stage shift register circuit can be cascaded with the shift register circuit located two stages before it, such as the (n-1)th-stage shift register circuit, or it can be cascaded with the shift register circuit located three stages before it, such as the (n-2)th-stage shift register circuit. Of course, this is just an example, and this disclosure is not limited to specific cascading methods, thereby enabling flexible cascading methods as needed.

[0136] Alternatively, the reset method is not limited to two adjacent shift register circuits. For example, the connection between the reset control terminal of the m-th shift register circuit and the output terminal of the (m+1)-th shift register circuit can be enabled, or it can be electrically connected to the output terminal of the (m+2)-th shift register circuit to achieve more flexible reset control. Of course, the specific number of stages used for reset is not limited.

[0137] This configuration ensures that all transistors in the gate drive circuit are N-type transistors, excluding P-type transistors. This simplifies the manufacturing process, prevents current leakage in the gate drive circuit, and prevents flickering caused by current leakage. It also improves the reliability and stability of the gate drive signal, thereby enhancing the display effect of the display product.

[0138] A third aspect of this disclosure provides a display device including a gate driving circuit according to embodiments of this disclosure.

[0139] In this embodiment, the gate drive circuit, which includes all N-type transistors, simplifies the manufacturing process of the display device and reduces manufacturing costs. At the same time, the gate drive circuit prevents leakage problems, improves the reliability and stability of the gate drive signal, and thus improves the driving capability and display effect of the display device.

[0140] It is worth noting that the gate driving circuit with the embodiments of this disclosure can be applied to various forms of display devices. Those skilled in the art should understand that all display devices based on the gate driving circuit operating mode of this disclosure are within the protection scope of this disclosure.

[0141] A fourth aspect of this disclosure provides a control method for a shift register circuit utilizing embodiments of this disclosure, comprising:

[0142] In the first stage, a high-level signal is provided to the input terminal as an input signal, and the input sub-circuit transmits the input signal to the pull-up node to pull up the potential of the pull-up node;

[0143] In the second stage, the pull-up sub-circuit transmits the signal from the second clock signal terminal to the output terminal under the control of the potential of the pull-up node.

[0144] The above method, by configuring all transistors in the gate drive circuit as N-type transistors, simplifies the manufacturing process, prevents current leakage in the gate drive circuit, and prevents flickering caused by current leakage, thereby improving the display effect of the display product. The specific implementation of this embodiment is the same as the previous embodiment, and will not be repeated here.

[0145] This disclosure addresses existing problems by providing a shift register circuit and its control method, a gate drive circuit, and a display device. By providing an improved input sub-circuit, and writing the input signal to a pull-up node electrically connected to the input of the pull-up sub-circuit based on the signal from the first clock signal terminal, and stabilizing the potential of the pull-up node based on the signals from the second clock signal terminal and the pull-up node, the N-type gate drive circuit constructed by the shift register circuit can normally achieve shift output. This improves the reliability and stability of the gate drive signal, simplifies the manufacturing of display products, and has broad application prospects.

[0146] Obviously, the above embodiments of this disclosure are merely examples for clearly illustrating this disclosure, and are not intended to limit the implementation of this disclosure. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. Any obvious variations or modifications derived from the technical solutions of this disclosure are still within the protection scope of this disclosure.

Claims

1. A shift register circuit, characterized in that, include: An input sub-circuit is electrically connected to an input terminal, a pull-up node, a first clock signal terminal, and a second clock signal terminal. It is configured to enable the connection between the input terminal and the pull-up node based on the signal of the first clock signal terminal, and to enable the connection between the second clock signal terminal and the pull-up node based on the signals of the second clock signal terminal and the pull-up node. A pull-up sub-circuit is electrically connected to the pull-up node, the second clock signal terminal, and the output terminal, and is configured to output the signal of the second clock signal terminal to the output terminal based on the potential of the pull-up node; The first pull-down control sub-circuit is electrically connected to the first pull-down control terminal, the pull-up node, and the first pull-down node, and is configured to control the potential of the first pull-down node based on the signals of the first pull-down control terminal and the pull-up node; as well as, The first pull-down sub-circuit is electrically connected to the first pull-down node, the first power signal terminal, and the output terminal, and is configured to enable the connection between the first power signal terminal and the output terminal based on the signal from the first pull-down node.

2. The shift register circuit according to claim 1, characterized in that, The input sub-circuit includes: a primary first transistor, a secondary first transistor, a second transistor, and a third transistor. The first electrode of the primary transistor is electrically connected to the input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal terminal. The first electrode of the secondary first transistor is connected to the first node, the second electrode is connected to the pull-up node, and the control electrode is connected to the first clock signal terminal. The first terminal and control terminal of the second transistor are electrically connected to the second clock signal terminal, and the second terminal is electrically connected to the first terminal of the third transistor. The second electrode of the third transistor is electrically connected to the first node, and the control electrode is electrically connected to the pull-up node.

3. The shift register circuit according to claim 1, characterized in that, The first pull-down control sub-circuit includes: a primary fourth transistor, a secondary fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor; the first pull-down sub-circuit also includes: a seventh transistor. The first and control terminals of the primary fourth transistor are electrically connected to the first pull-down control terminal, and the second terminal is electrically connected to the first intermediate node. The first electrode of the secondary fourth transistor is connected to the first intermediate node, the second electrode is connected to the second node, and the control electrode is connected to the first pull-down control terminal. The first electrode of the fifth transistor is connected to the first pull-down control terminal, the second electrode is connected to the first pull-down node, and the control electrode is connected to the second node. The first electrode of the sixth transistor is electrically connected to the second node, the second electrode is electrically connected to the first power signal terminal, and the control electrode is electrically connected to the pull-up node. The first terminal of the first capacitor is electrically connected to the second node, and the second terminal is electrically connected to the first pull-down node. The first electrode of the seventh transistor is electrically connected to the output terminal, the second electrode is electrically connected to the first power signal terminal, and the control electrode is electrically connected to the first pull-down node.

4. The shift register circuit according to claim 1, characterized in that, The pull-up sub-circuit includes: an eighth transistor and a second capacitor. The first electrode of the eighth transistor is electrically connected to the second clock signal terminal, the second electrode is electrically connected to the output terminal, and the control electrode is electrically connected to the pull-up node.

5. The shift register circuit according to claim 4, characterized in that, Also includes: The ninth transistor, The first electrode of the ninth transistor is electrically connected to the control electrode of the eighth transistor, the second electrode is electrically connected to the pull-up node, and the control electrode is electrically connected to the second power signal terminal.

6. The shift register circuit according to claim 2, characterized in that, Also includes: First interlocking sub-circuit, The first interlock sub-circuit includes a tenth transistor and an eleventh transistor, wherein, The first electrode of the tenth transistor is connected to the pull-up node, the second electrode is connected to the third power signal terminal, and the control electrode is connected to the first pull-down node. The first electrode of the eleventh transistor is electrically connected to the first pull-down node, the second electrode is electrically connected to the third power signal terminal, and the control electrode is electrically connected to the pull-up node, or The first interlock sub-circuit includes a primary tenth transistor, a secondary tenth transistor, and an eleventh transistor. The first electrode of the primary tenth transistor is electrically connected to the pull-up node, the second electrode is electrically connected to the second intermediate node and then to the first node, and the control electrode is electrically connected to the first pull-down node. The first electrode of the secondary tenth transistor is connected to the second intermediate node, the second electrode is connected to the third power signal terminal, and the control electrode is connected to the first pull-down node. The first electrode of the eleventh transistor is electrically connected to the first pull-down node, the second electrode is electrically connected to the third power signal terminal, and the control electrode is electrically connected to the pull-up node.

7. The shift register circuit according to claim 2, characterized in that, Also includes: The second pull-down control sub-circuit is electrically connected to the second pull-down control terminal, the pull-up node, and the second pull-down node, and is configured to control the potential of the second pull-down node based on the signals from the second pull-down control terminal and the pull-up node. The second pull-down sub-circuit is electrically connected to the second pull-down node, the first power signal terminal, and the output terminal, and is configured to enable the connection between the first power signal terminal and the output terminal based on the signal of the second pull-down node.

8. The shift register circuit according to claim 7, characterized in that, The second pull-down control sub-circuit includes: a primary twelfth transistor, a secondary twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a third capacitor; the second pull-down sub-circuit also includes: a fifteenth transistor. The first and control terminals of the primary twelfth transistor are electrically connected to the second pull-down control terminal, and the second terminal is electrically connected to the third intermediate node. The first electrode of the twelfth secondary transistor is electrically connected to the third intermediate node, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the first power signal terminal. The first electrode of the thirteenth transistor is electrically connected to the second pull-down control terminal, the second electrode is electrically connected to the second pull-down node, and the control electrode is electrically connected to the third node. The first electrode of the fourteenth transistor is electrically connected to the third node, the second electrode is electrically connected to the first power signal terminal, and the control electrode is electrically connected to the pull-up node. The first electrode of the third capacitor is electrically connected to the third node, and the second electrode is electrically connected to the second pull-down node. The first electrode of the fifteenth transistor is electrically connected to the output terminal, the second electrode is electrically connected to the first power signal terminal, and the control electrode is electrically connected to the second pull-down node.

9. The shift register circuit according to claim 7, characterized in that, Also includes: The second interlocking sub-circuit includes: a primary sixteenth transistor, a secondary sixteenth transistor, and a seventeenth transistor. The first electrode of the primary sixteenth transistor is electrically connected to the pull-up node, the second electrode is electrically connected to the fourth intermediate node and then to the first node, and the control electrode is electrically connected to the second pull-down node. The first electrode of the sixteenth secondary transistor is electrically connected to the fourth intermediate node, the second electrode is electrically connected to the third power signal terminal, and the control electrode is electrically connected to the second pull-down node. The first electrode of the seventeenth transistor is electrically connected to the second pull-down node, the second electrode is electrically connected to the third power signal terminal, and the control electrode is electrically connected to the pull-up node.

10. The shift register circuit according to claim 1, characterized in that, Also includes: Carry sub-circuit, the carry sub-circuit including the eighteenth transistor, The first electrode of the eighteenth transistor is electrically connected to the second clock signal terminal, the second electrode is electrically connected to the carry output terminal, and the control electrode is electrically connected to the pull-up node.

11. The shift register circuit according to claim 10, characterized in that, Also includes: The first noise reduction sub-circuit includes a nineteenth transistor. The first electrode of the nineteenth transistor is connected to the carry output terminal, the second electrode is connected to the third power signal terminal, and the control electrode is connected to the first pull-down node.

12. The shift register circuit according to claim 7, characterized in that, Also includes: The system includes a carry-out sub-circuit and a second noise reduction sub-circuit, wherein the carry-out sub-circuit includes an eighteenth transistor and the second noise reduction sub-circuit includes a twentieth transistor. The first electrode of the eighteenth transistor is connected to the second clock signal terminal, the second electrode is connected to the carry output terminal, and the control electrode is connected to the pull-up node. The first electrode of the twentieth transistor is connected to the carry output terminal, the second electrode is connected to the third power signal terminal, and the control electrode is connected to the second pull-down node.

13. The shift register circuit according to claim 1, characterized in that, Also includes: A reset sub-circuit is electrically connected to the reset control terminal, the first power signal terminal, and the pull-up node, and is configured to enable the connection between the first power signal terminal and the pull-up node based on the signal from the reset control terminal.

14. A gate driving circuit, characterized in that, include: N cascaded shift register circuits as described in any one of claims 1-13, where N is a natural number greater than 2, where The input terminal of the nth stage shift register circuit is electrically connected to the output terminal or carry output terminal of another stage shift register circuit, where n is greater than 1 and less than or equal to N; The input terminal of the first-stage shift register circuit is electrically connected to the start signal terminal of the gate drive circuit.

15. A display device, characterized in that, Includes the gate drive circuit as described in claim 14.

16. A control method for a shift register circuit as described in any one of claims 1-13, characterized in that, include: In the first stage, a high-level signal is provided to the input terminal as an input signal, and the input sub-circuit transmits the input signal to the pull-up node to pull up the potential of the pull-up node; In the second stage, the pull-up sub-circuit transmits the signal from the second clock signal terminal to the output terminal under the control of the potential of the pull-up node.

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