Fault localization method and device

Abstract

The present application provides a fault localization method and device, applied to a receiving end device. The receiving end device can determine a first reconfigured link to be detected, wherein the first reconfigured link is a link obtained by reconfiguring a first sublink in a faulty first link and some of links in a fault-free second link. The first link, the second link, and the first reconfigured link are all links from a transmitting end device to the receiving end device, and the transmitting end device and the receiving end device communicate through an optical fiber link. Specifically, the first reconfigured link is a link formed by replacing a corresponding link in the second link with the first sublink. After determining the first reconfigured link, the receiving end device can perform fault detection on the first reconfigured link, and on the basis of a fault detection result of the first reconfigured link, the receiving end device localizes whether a fault location of the first link comprises the first sublink. Thus, by means of the present solution, a fault location of a first link can be localized when a fault occurs in the first link.

Description

A fault locating method and device

[0001] The present application claims priority from the Chinese Patent Application No. 202410696787.3 filed on May 30, 2024, and entitled "A fault locating method and device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of communication, in particular to a fault locating method and device. BACKGROUND

[0003] When data is transmitted in a communication network, if a communication link fails, it may affect the normal transmission of data, and accordingly, some negative effects will be brought. For example, in the scenario where the application of artificial intelligence (AI) technology is becoming more and more widespread, AI training data can be transmitted in a communication network, and once the communication link fails, it may cause abnormal transmission of AI training data, and accordingly, it will affect the accuracy and efficiency of AI training.

[0004] When the communication link fails, it is particularly important to locate the fault. The so-called fault locating can be understood as determining the fault point in the link that specifically causes the fault.

[0005] How to accurately locate the fault of the link that fails is a problem that needs to be solved at present. SUMMARY

[0006] The present application provides a fault locating method and device, which can locate the fault point in the link that specifically causes the fault after the link fails.

[0007] In a first aspect, an embodiment of the present application provides a fault locating method, which can be applied to a receiving end device. The receiving end device can determine a first recombined link to be detected, which is a link recombined by a first sub-link in a first link with a fault and a part of a second link without a fault. The first link, the second link and the first recombined link are all links from a sending end device to the receiving end device, and the sending end device and the receiving end device communicate through an optical fiber link. Specifically, the first recombined link is a link formed by replacing a corresponding link in the second link with the first sub-link. After determining the first recombined link, the receiving end device can perform fault detection on the first recombined link. Since the second link is fault-free, the fault detection result of the first recombined link can represent whether the first sub-link has a fault. Therefore, the receiving end device can determine whether the fault position of the first link includes the first sub-link according to the fault detection result of the first recombined link. As can be seen, by using the scheme of the embodiment of the present application, the fault position of the first link can be located after the first link has a fault.

[0008] In a possible implementation, the receiving end device can send a first frame including first indication information to the sending end device. The first indication information is used to indicate that fault locating is performed on the first sub-link. As an example, the foregoing first indication information can be used to indicate a stage of performing fault locating on the first link. Different stages require locating different sub-links, and each stage has a first sub-link corresponding to the stage. The receiving end device sends the first frame to the sending end device, so that the sending end device determines the stage of performing fault locating, so as to enable the sending end to perform corresponding measures to cooperate with the fault locating performed on the first sub-link.

[0009] In a possible implementation, the sending end device includes a first physical layer (physical, PHY) chip, the first sub-link is a link between the first PHY chip and a first mapping module, and the first mapping module is used to connect the first PHY chip and a sending end optical module. In this scenario, the first indication information triggers the first mapping module to switch the first sub-link to a second sub-link in the second link, so as to obtain the foregoing first recombined link, where the second sub-link is a link from the first mapping module to the receiving end device. In this scenario, the first recombined link includes the second sub-link in addition to the first sub-link.

[0010] In a possible implementation, the sending-end device comprises a first PHY chip, and the receiving-end device comprises the second PHY chip. The first sub-link is a link from a first mapping module to a second mapping module, the first mapping module being configured to connect the first PHY chip and the sending-end optical module, and the second mapping module being configured to connect the second PHY chip and the receiving-end optical module. In this scenario, the first indication information triggers the first mapping module to switch a third sub-link in the second link to the first sub-link, and triggers the second mapping module to switch the first sub-link to a fourth sub-link in the second link, so as to obtain the first recombined link. The third sub-link is a link between the first PHY chip and the first mapping module, and the fourth sub-link is a link between the second mapping module and the second PHY chip. In this scenario, the first recombined link comprises the first sub-link, the third sub-link, and the fourth sub-link.

[0011] In a possible implementation, the first sub-link is a link between the second mapping module and the second PHY chip. In this scenario, the first indication information triggers the second mapping module to switch a fifth sub-link of the second link to the first sub-link, so as to obtain the first recombined link. The fifth sub-link is a link from the sending-end device to the second mapping module. In this scenario, the first recombined link comprises the first sub-link and the fifth sub-link.

[0012] In a possible implementation, the first frame can comprise at least one information field, and the first indication information can be carried in any one of the at least one information field. As a specific example, the at least one information field comprises a control field, and the first indication information is carried in the control field of the first frame.

[0013] In a possible implementation, the at least one information field further includes a state field. In an example, the state field of the first frame can be used to indicate that the receiving end device has completed a first preparation operation required for completing a current fault locating phase. In other words, the state field of the first frame can be used to indicate that the receiving end device has completed a first preparation operation of performing fault locating on the first sub-link. The first preparation operation can include a mapping relationship switching operation required for the second mapping module corresponding to the receiving end device to complete between the system-side channel unit and the line-side channel unit, so as to obtain the first recombined link after the mapping relationship switching operation is performed. As described above, the first preparation operation includes that the second mapping module corresponding to the receiving end device switches the first sub-link to a fourth sub-link in the second link, the fourth sub-link being a link between the second mapping module and a second PHY chip included in the receiving end device; or the second mapping module switches a fifth sub-link of the second link to the first sub-link, the fifth sub-link being a link from the sending end device to the second mapping module.

[0014] In a possible implementation, the receiving end device performs fault detection on the first recombined link. In a specific implementation, the receiving end device performs fault detection on the first recombined link based on a second frame sent by the sending end device to the receiving end device through the first recombined link. That is, the sending end device can send the second frame to the receiving end device through the first recombined link. Correspondingly, the receiving end device can perform fault detection on the first recombined link through the second frame.

[0015] In a possible implementation, the second frame can include a test data stream, and the receiving end device can determine whether the first recombined link is faulty based on a bit error rate of the test data stream transmitted on the first recombined link. For example, the receiving end device can determine that the first recombined link is faulty when the bit error rate is greater than or equal to a preset bit error rate threshold. The receiving end device can determine that the first recombined link is not faulty when the bit error rate is less than the preset bit error rate threshold. In a specific example, the test data stream can be a pseudo random binary sequence (PRBS). In other words, the second frame includes a PRBS, and a bit error rate of the PRBS transmitted on the first recombined link is used to determine the fault detection result.

[0016] In a possible implementation, the second frame can include a control field, and the control field of the second frame carries second indication information, the second indication information indicating whether the first sub-link is included in locating a fault position of the first link.

[0017] In a possible implementation, the second frame can also include a status field, the status field of the second frame being used to indicate that the sending-end device has completed the second preparation operation of performing fault positioning on the first sub-link. The second preparation operation can include a mapping relationship switching operation between the system-side channel unit and the line-side channel unit required to be completed by the first mapping module corresponding to the sending-end device, so as to obtain the first recombined link after the mapping relationship switching operation is performed. As described above, the second preparation operation includes: the first mapping module corresponding to the sending-end device switches the first sub-link to a second sub-link in the second link, the second sub-link being a link from the first mapping module to the receiving-end device; or, the first mapping module switches a third sub-link in the second link to the first sub-link, the third sub-link being a link between the first PHY chip and the first mapping module, and the sending-end device including the first PHY chip.

[0018] In a possible implementation, the sending-end device is a sending-end network device, and the first mapping module is located in the sending-end network device. In this scenario, when the first sub-link is a link between the first PHY chip and the first mapping module, if the fault of the first sub-link is located, it indicates that the sending-end network device has a fault.

[0019] In a possible implementation, the first mapping module is located in the sending-end optical module.

[0020] In a possible implementation, the first mapping module can perform the second preparation operation of locating whether the fault position of the first link includes the first sub-link based on a channel switching instruction sent by the first PHY chip. As an example, the first PHY chip can send a channel switching instruction to the first mapping module, the channel switching instruction being used to indicate a value of a register, and further, the first mapping module can complete the second preparation operation based on the value of the register indicated by the channel switching instruction. The value of the register mentioned herein is used to indicate the mapping relationship between the system-side channel unit and the line-side channel unit of the first mapping module.

[0021] In a possible implementation, the receiving-end device is a receiving-end network device, and the second mapping module is located in the receiving-end network device. In this scenario, when the first sub-link is a link between the second PHY chip and the second mapping module, if the fault of the first sub-link is located, it indicates that the receiving-end network device has a fault.

[0022] In a possible implementation, the second mapping module is located in the receiving-end optical module.

[0023] In a possible implementation, the second mapping module is configured to perform a first preparation operation of fault positioning on the first sub-link based on the channel switching instruction sent by the second PHY chip.

[0024] In a possible implementation, the first mapping module can be a first chip, for example, the first mapping module is a chip different from the first PHY chip in the sending-end network device.

[0025] In a possible implementation, the first mapping module can be a first functional circuit, for example, the first mapping module is a functional circuit in the first PHY chip.

[0026] In a possible implementation, the second mapping module can be a second chip, for example, the second mapping module is a chip different from the second PHY chip in the receiving-end network device.

[0027] In a possible implementation, the second mapping module can be a second functional circuit, for example, the second mapping module is a functional circuit in the second PHY chip.

[0028] In a possible implementation, since in the first recombined link, only the first sub-link comes from the faulty first link, and the other sub-links all come from the non-faulty second link. In other words, in the first recombined link, except that whether the first sub-link is faulty is not clear, the other sub-links can be determined to be non-faulty. Therefore, the fault detection result of the first recombined link is also the fault detection result of the first sub-link. That is, if the fault detection result of the first recombined link is that the first recombined link is faulty, it indicates that the first sub-link is faulty. If the fault detection result of the first recombined link is that the first recombined link is non-faulty, it indicates that the first sub-link is non-faulty. Therefore, when the receiving-end device “locates whether the fault position of the first link includes the first sub-link according to the fault detection result of the first recombined link”, if the fault detection result indicates that the first recombined link is faulty, the receiving-end device locates that the fault position of the first link includes the first sub-link; if the fault detection result indicates that the first recombined link is non-faulty, the receiving-end device locates that the fault position of the first link does not include the first sub-link.

[0029] In a second aspect, the present application provides a fault locating device, applied to a receiving end device, the device comprising: a determining unit configured to determine a first recombination link to be detected, the first recombination link comprising a first sub-link, the first sub-link belonging to a first link with a fault, the first recombination link being a link formed by replacing a corresponding link in a second link without a fault by the first sub-link, the first link, the second link and the first recombination link all being links from a sending end device to the receiving end device, the sending end device and the receiving end device communicating through an optical fiber link; and a processing unit configured to: perform fault detection on the first recombination link; and locate whether the fault position of the first link includes the first sub-link according to a fault detection result of the first recombination link.

[0030] In a possible implementation, the determining unit specifically comprises a sending unit, and the sending unit is configured to send a first frame to the sending end device, the first frame comprising first indication information, the first indication information indicating that fault locating is performed on the first sub-link.

[0031] In a possible implementation, the sending end device comprises a first physical layer (PHY) chip, the first sub-link being a link between the first PHY chip and a first mapping module, the first mapping module being configured to connect the first PHY chip and a sending end optical module, and the first indication information triggers the first mapping module to switch the first sub-link to a second sub-link in the second link, the second sub-link being a link from the first mapping module to the receiving end device, and the first recombination link further comprising the second sub-link.

[0032] In a possible implementation, the first sub-link is a link from a first mapping module to a second mapping module, the first mapping module being configured to connect a first PHY chip and a sending end optical module, the second mapping module being configured to connect a second PHY chip and a receiving end optical module, the sending end device comprising the first PHY chip, and the receiving end device comprising the second PHY chip, the first indication information triggering the first mapping module to switch a third sub-link in the second link to the first sub-link and triggering the second mapping module to switch the first sub-link to a fourth sub-link in the second link, the first recombination link further comprising the third sub-link and the fourth sub-link, the third sub-link being a link between the first PHY chip and the first mapping module, and the fourth sub-link being a link between the second mapping module and the second PHY chip.

[0033] In a possible implementation, the first sub-link is a link between a second mapping module and a second PHY chip, the receiving end device comprises the second PHY chip, and the second mapping module is configured to connect the second PHY chip and a receiving end optical module; the first indication information triggers the second mapping module to switch a fifth sub-link of the second link to the first sub-link, and the first recombined link further comprises the fifth sub-link, and the fifth sub-link is a link from the sending end device to the second mapping module.

[0034] In a possible implementation, the first indication information is carried in a control field of the first frame.

[0035] In a possible implementation, the first frame further comprises a state field, and the state field of the first frame indicates that the receiving end device has completed a first preparation operation of performing fault positioning on the first sub-link, wherein the first preparation operation comprises: a second mapping module corresponding to the receiving end device switching the first sub-link to a fourth sub-link in the second link, the fourth sub-link being a link between the second mapping module and a second PHY chip included in the receiving end device; or the second mapping module switching a fifth sub-link of the second link to the first sub-link, the fifth sub-link being a link from the sending end device to the second mapping module.

[0036] In a possible implementation, the processing unit is configured to perform fault detection on the first recombined link based on a second frame sent by the sending end device to the receiving end device through the first recombined link.

[0037] In a possible implementation, the second frame comprises a pseudo-random binary sequence (PRBS), and a bit error rate of the PRBS transmitted on the first recombined link is used to determine the fault detection result.

[0038] In a possible implementation, the second frame further comprises a control field, and the control field of the second frame comprises second indication information, the second indication information indicating whether the first sub-link is included in positioning a fault position of the first link.

[0039] In a possible implementation, the second frame further comprises a state field, and the state field of the second frame indicates that the sending end device has completed a second preparation operation of performing fault positioning on the first sub-link, and the second preparation operation comprises: a first mapping module corresponding to the sending end device switches the first sub-link to a second sub-link in the second link, and the second sub-link is a link of the first mapping module to the receiving end device; or, the first mapping module switches a third sub-link in the second link to the first sub-link, and the third sub-link is a link between a first PHY chip and the first mapping module, and the sending end device comprises the first PHY chip.

[0040] In a possible implementation, the sending end device is a sending end network device, and the first mapping module is located in the sending end network device.

[0041] In a possible implementation, the first mapping module is located in the sending end optical module.

[0042] In a possible implementation, the first mapping module is configured to perform, based on a channel switching instruction sent by the first PHY chip, a second preparation operation of locating whether the fault position of the first link comprises the first sub-link.

[0043] In a possible implementation, the receiving end device is a receiving end network device, and the second mapping module is located in the receiving end network device.

[0044] In a possible implementation, the second mapping module is located in a receiving end optical module.

[0045] In a possible implementation, the second mapping module is configured to perform, based on a channel switching instruction sent by the second PHY chip, a first preparation operation of locating whether the fault position of the first link comprises the first sub-link.

[0046] In a possible implementation, the first mapping module comprises a first chip or a first functional circuit, and / or the second mapping module comprises a second chip or a second functional circuit.

[0047] In a possible implementation, the processing unit is configured to: if the fault detection result indicates that the first recombined link has a fault, locate that the fault position of the first link comprises the first sub-link; or, if the fault detection result indicates that the first recombined link has no fault, locate that the fault position of the first link does not comprise the first sub-link.

[0048] In a third aspect, an embodiment of the present application provides a communication device, comprising a processor and a memory;

[0049] The memory is configured to store instructions, and the processor is configured to execute the instructions to enable the communication device to perform the method in the first aspect and any one of the implementations of the first aspect.

[0050] In a fourth aspect, an embodiment of the present application provides a communication device, comprising a communication interface and a processor connected to the communication interface, the communication interface is configured to perform the transceiving operation in the method in the first aspect and any one of the implementations of the first aspect, and the processor is configured to perform other operations in the method in the first aspect and any one of the implementations of the first aspect except the transceiving operation.

[0051] In a fifth aspect, an embodiment of the present application provides a chip, comprising an interface circuit and a processing circuit, the chip is configured to perform the method in the first aspect and any one of the implementations of the first aspect; the interface circuit is configured to receive and / or send data, and the processing circuit is configured to process data.

[0052] In one specific example, the interface circuit is configured to determine a first recombination link to be detected, the first recombination link comprises a first sub-link, the first sub-link belongs to a first link in failure, the first recombination link is formed by replacing a corresponding link in a second link without failure by the first sub-link, the first link, the second link and the first recombination link are all links from a sending end device to a receiving end device, and the sending end device and the receiving end device communicate through an optical fiber link; and the processing circuit is configured to perform failure detection on the first recombination link, and determine whether the failure position of the first link includes the first sub-link according to a failure detection result of the first recombination link.

[0053] In a sixth aspect, an embodiment of the present application provides a computer readable storage medium, comprising instructions or a computer program, when the instructions or the computer program are executed on a processor, the method in the first aspect and any one of the implementations of the first aspect is implemented.

[0054] In a seventh aspect, an embodiment of the present application provides a computer program product, comprising a computer program product, when the computer program product is executed on a processor, the method in the first aspect and any one of the implementations of the first aspect is implemented. BRIEF DESCRIPTION OF DRAWINGS

[0055] FIG. 1a is a schematic diagram of an exemplary application scenario according to an embodiment of the present application;

[0056] FIG. 1b is another schematic diagram of an exemplary application scenario according to an embodiment of the present application;

[0057] FIG. 1c is a schematic diagram of another exemplary application scenario provided by the embodiment of the present application;

[0058] FIG. 2a is a schematic diagram of an exemplary application scenario provided by the embodiment of the present application;

[0059] FIG. 2b is a schematic diagram of another exemplary application scenario provided by the embodiment of the present application;

[0060] FIG. 2c is a schematic diagram of another exemplary application scenario provided by the embodiment of the present application;

[0061] FIG. 3 is a schematic diagram of a process of a fault locating method provided by the embodiment of the present application;

[0062] FIG. 4a is a schematic diagram of a first recombination link provided by the embodiment of the present application;

[0063] FIG. 4b is a schematic diagram of another first recombination link provided by the embodiment of the present application;

[0064] FIG. 4c is a schematic diagram of another first recombination link provided by the embodiment of the present application;

[0065] FIG. 4d is a schematic diagram of an exemplary application scenario provided by the embodiment of the present application;

[0066] FIG. 5a is a schematic diagram of an exemplary application scenario provided by the embodiment of the present application;

[0067] FIG. 5b is a schematic diagram of a process of a fault locating method provided by the embodiment of the present application;

[0068] FIG. 5c is a schematic diagram of a process of a fault locating method provided by the embodiment of the present application;

[0069] FIG. 5d is a schematic diagram of a process of a fault locating method provided by the embodiment of the present application;

[0070] FIG. 6a is a schematic diagram of another exemplary application scenario provided by the embodiment of the present application;

[0071] FIG. 6b is a schematic diagram of another exemplary application scenario provided by the embodiment of the present application;

[0072] FIG. 6c is a schematic diagram of another exemplary application scenario provided by the embodiment of the present application;

[0073] FIG. 7 is a schematic diagram of a structure of a fault locating apparatus provided by the embodiment of the present application;

[0074] FIG. 8 is a schematic diagram of a structure of a communication apparatus provided by the embodiment of the present application;

[0075] FIG. 9 is a schematic diagram of a structure of a communication device provided by the embodiment of the present application;

[0076] FIG. 10 is a structural schematic diagram of a chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0077] The present application provides a fault positioning method and device, which can locate the fault point in the link after the link fault occurs.

[0078] To facilitate understanding of the present application, the application scenario of the present application is first introduced.

[0079] Referring to FIG. 1a, which is a schematic diagram of an exemplary application scenario provided in an embodiment of the present application.

[0080] As shown in FIG. 1a:

[0081] The network device 1 includes a PHY chip 1, an electrical signal processing unit 1, and an optical module 1, wherein the electrical signal processing unit 1 is used to connect the PHY chip 1 and the optical module 1, one side of the electrical signal processing unit 1 used to connect the PHY chip 1 is the system side, and one side of the electrical signal processing unit 1 used to connect the optical module 1 is the line side. The optical module 1 includes an optical transmitting unit used to transmit signals to an optical fiber and an optical receiving unit used to receive signals from the optical fiber. In one example, the electrical signal processing unit 1 can be located in the network device 1. For example, the electrical signal processing unit 1 can be another chip (for example, a clock data recovery (CDR) chip) located in the network device 1 and different from the PHY chip 1. For another example, the electrical signal processing unit 1 can be a functional circuit located in the network device 1, for example, a functional circuit located in the PHY chip 1. In yet another example, the electrical signal processing unit 1 can be located in the optical module 1, for example, the electrical signal processing unit 1 can be a digital signal processor (DSP) in the optical module 1.

[0082] The network device 2 includes a PHY chip 2, an electrical signal processing unit 2, and an optical module 2, wherein the electrical signal processing unit 2 is used to connect the PHY chip 2 and the optical module 2, one side of the electrical signal processing unit 2 used to connect the PHY chip 2 is the system side, and one side of the electrical signal processing unit 2 used to connect the optical module 2 is the line side. The optical module 2 includes an optical transmitting unit used to transmit signals to an optical fiber and an optical receiving unit used to receive signals from the optical fiber. In one example, the electrical signal processing unit 2 can be located in the network device 2. For example, the electrical signal processing unit 2 can be another chip located in the network device 2 and different from the PHY chip 2. For another example, the electrical signal processing unit 2 can be a functional circuit located in the network device 2, for example, a functional circuit located in the PHY chip 2. In yet another example, the electrical signal processing unit 2 can be located in the optical module 2.

[0083] In some scenarios, the electrical signal processing unit can also be referred to as a mapping module. For example, the electrical signal processing unit 1 can be referred to as a first mapping module, and the electrical signal processing unit 2 can be referred to as a second mapping module. For this case, "electrical signal processing unit 1" and "first mapping module" refer to the same object, and the two can be used alternately. Correspondingly, "electrical signal processing unit 2" and "second mapping module" refer to the same object, and the two can be used alternately.

[0084] Currently, when a link fails, the specific fault point can be located by using loopback technology. The link mentioned here can be, for example, the link between the network device 1 and the network device 2, or the link between the optical module 1 and the network device 2, or the link between the network device 1 and the optical module 2.

[0085] Taking the link failure between the network device 1 and the network device 2 as an example, the implementation of locating the specific fault point by using loopback technology is introduced.

[0086] Currently, loopback can be configured at different positions in the link under offline conditions to realize fault location of different link areas. Further, the fault area is finally determined in combination with the fault location corresponding to each position. As shown in FIG. 1a:

[0087] The A1 and B1 positions support the configuration of loopback. For the PHY chip (such as the PHY chip 1 and the PHY chip 2), there is a specific signal path in the chip that is exclusively used for loopback. When the working mode of the PHY chip is configured as a loopback mode, the PHY chip guides the sending end signal to the receiving end through the specific path in the chip itself, forming a closed loop in the PHY chip, and ensuring the correct transmission of data in the PHY chip.

[0088] The electrical signal processing unit (such as the electrical signal processing unit 1 and the electrical signal processing unit 2) also supports the configuration of loopback. The electrical signal processing unit can support the loopback corresponding to the system side and the loopback corresponding to the line side. The loopback corresponding to the system side corresponds to A2 and B2 in FIG. 1a, and the loopback corresponding to the line side corresponds to A3 and B3 in FIG. 1a.

[0089] In one specific example, the service data signal loopback can be configured at the A2 position, and if service interruption occurs, it can be determined that the fault position includes the link between the network device 1 and the electrical signal processing unit 1. If no service interruption occurs after the service data signal loopback is configured at the A2 position, the loopback configuration at the A2 position is cancelled and the service data signal loopback is configured at the B3 position. If service interruption occurs after the service data signal loopback is configured at the B3 position, it can be determined that the fault position includes the link between the A2 position and the B3 position, that is, it can be determined that the optical module or the optical fiber link is faulty. If no service interruption occurs after the service data signal loopback is configured at the B3 position, it can be determined that the fault position includes the link between the electrical signal processing unit 2 and the network device 2.

[0090] The loopback technology is often used to locate the fault position, and multiple positions need to be configured with loopback to locate the specific fault point. For example, in the above example, loopback needs to be configured at two positions A2 and B3. It is difficult to locate the fault position only by configuring loopback at one position. Moreover, loopback needs to be configured manually by personnel, and cannot be automatically operated, which makes it difficult to locate the fault position in time after the fault occurs. That is, the loopback technology cannot efficiently locate the fault.

[0091] Moreover, the loopback technology cannot accurately locate the fault. For example, for some specific faults, the loopback technology cannot reproduce the fault scene, so that the fault cannot be accurately located. Now an example is given in combination with the scene shown in FIG. 1b. FIG. 1b is another exemplary application scenario provided by the embodiment of the application.

[0092] The PHY chip includes a sending part and a receiving part. In general, the signal received by the receiving part passes through functions such as analog-to-digital conversion, signal equalization, and decision in sequence. Different manufacturers of PHY chips have different designs in the decision function. The default configuration of the decision threshold value by the manufacturer can be a fixed threshold value or an adaptive threshold value. When the decision threshold value in the PHY chip is set to a fixed threshold mode and does not match the received signal, it can cause link interruption.

[0093] For example, in the example shown in FIG. 1b, the PHY chip from the A manufacturer sets the decision mode to a fixed threshold mode in the receiving part. Therefore, when the PHY chip from the A manufacturer receives data from the PHY chip from the B manufacturer, the set value of the decision threshold value does not match the level of the received signal, which can cause the link to be interrupted. That is, because the decision mode of the chip from the A manufacturer is not reasonable, the link is faulty.

[0094] If the loopback technology is used for online fault localization, for example, a loopback is performed at the location of the electrical signal processing unit 1, as shown by the green arrow line in FIG. 1c. FIG. 1c is another exemplary application scenario provided by an embodiment of the present application. Since the signal sent by the same chip is matched with the decision mode of the chip itself, the loopback test result is passed, and thus the fault localization result indicates that the PHY chip from the A manufacturer is fault-free, which is inaccurate.

[0095] Based on this, the embodiments of the present application provide a fault localization method and device, which can accurately and efficiently perform fault localization.

[0096] Before introducing the scheme provided by the embodiments of the present application, the application scenario of the embodiments of the present application is introduced first. The scheme provided by the embodiments of the present application can be applied to the scenario shown in FIG. 1a. In one example, the internal structures of the PHY chip 1, the electrical signal processing unit 1 and the optical module 1 shown in FIG. 1a can be as shown in FIG. 2a. In another example, the internal structures of the PHY chip 2, the electrical signal processing unit 2 and the optical module 2 shown in FIG. 1a can also be as shown in FIG. 2a. FIG. 2a is an exemplary application scenario provided by an embodiment of the present application.

[0097] In FIG. 2a, the PHY chip can correspond to the PHY chip 1 or the PHY chip 2 shown in FIG. 1a, the electrical signal processing unit can correspond to the electrical signal processing unit 1 or the electrical signal processing unit 2 shown in FIG. 1a, and the optical module can correspond to the optical module 1 or the optical module 2 shown in FIG. 1a. In one example, when the PHY chip shown in FIG. 2a corresponds to the PHY chip 1 shown in FIG. 1a, the electrical signal processing unit shown in FIG. 2a can correspond to the electrical signal processing unit 1 shown in FIG. 1a, and the optical module shown in FIG. 2a can correspond to the optical module 1 shown in FIG. 1a. In another example, when the PHY chip shown in FIG. 2a corresponds to the PHY chip 2 shown in FIG. 1a, the electrical signal processing unit shown in FIG. 2a can correspond to the electrical signal processing unit 2 shown in FIG. 1a, and the optical module shown in FIG. 2a can correspond to the optical module 2 shown in FIG. 1a.

[0098] As shown in FIG. 2a, the electrical signal processing unit includes a system side channel unit, a mapping switching unit and a line side channel unit, wherein: the system side refers to the side of the electrical signal processing unit closer to the PHY chip, and the line side refers to the side of the electrical signal processing unit closer to the optical module. That is, the system side channel unit is a channel unit for communicating with the PHY chip, and the line side channel unit is a resource for communicating with the optical module. The dashed arrow in the figure indicates that there can be other link parts between the electrical signal processing unit and the PHY chip, and there can be other link parts between the electrical signal processing unit and the optical module.

[0099] The number of electrical signal transmitting units (M Host TX) in the system-side channel unit is not less than two, and four are shown in FIG. 2a;

[0100] The number of electrical signal receiving units (M Host RX) in the system-side channel unit is not less than two, and four are shown in FIG. 2a;

[0101] The number of electrical signal transmitting units (Line TX) in the line-side channel unit is not less than two, and four are shown in FIG. 2a;

[0102] The number of electrical signal receiving units (Line RX) in the line-side channel unit is not less than two, and four are shown in FIG. 2a.

[0103] The mapping switching unit supports cross-connection (or mapping) of any one of the electrical signal transmitting units in the system-side channel unit to any one of the electrical signal receiving units in the line-side channel unit, and supports cross-connection (or mapping) of any one of the electrical signal receiving units in the system-side channel unit to any one of the electrical signal transmitting units in the line-side channel unit.

[0104] The PHY chip can also be referred to as a service chip, and has service forwarding and packet processing functions. The PHY chip includes electrical signal transmitting units (C Host TX) and electrical signal receiving units (C Host RX).

[0105] In the present application, after a first link from a sending device to a receiving device fails, the receiving device can perform fault detection on a first recombined link, wherein the first recombined link is a link recombined from a first sub-link in the failed first link and part of a second link that is not faulty. The second link is also a link from the sending device to the receiving device. Since the second link is not faulty, the fault detection result of the first recombined link can represent whether the first sub-link is faulty. Therefore, the receiving device can determine whether the fault position of the first link includes the first sub-link according to the fault detection result of the first recombined link.

[0106] Regarding the first link, the second link, and the first sub-link, they can be understood in combination with FIGS. 2b and 2c.

[0107] Referring to FIG. 2b, FIG. 2b is a schematic diagram of another exemplary application scenario provided by an embodiment of the present application. As shown in FIG. 2b:

[0108] The PHY chip 1 of the network device 1 includes two electrical signal transmitting units and two electrical signal receiving units, which are electrical signal transmitting unit 1, electrical signal transmitting unit 2, electrical signal receiving unit 1, and electrical signal receiving unit 2.

[0109] The system-side channel unit of the electrical signal processing unit 1 includes two system-side electrical signal receiving units (system-side electrical signal receiving unit 1 and system-side electrical signal receiving unit 2), and two system-side electrical signal transmitting units (system-side electrical signal transmitting unit 1 and system-side electrical signal transmitting unit 2). The line-side channel unit of the electrical signal processing unit 1 includes two line-side electrical signal receiving units (line-side electrical signal receiving unit 1 and line-side electrical signal receiving unit 2), and two line-side electrical signal transmitting units (line-side electrical signal transmitting unit 1 and line-side electrical signal transmitting unit 2). The connection relationship between the system-side channel unit and the line-side channel unit of the electrical signal processing unit 1 is shown in FIG. 2b, which will not be described in detail here.

[0110] The optical module 1 includes two optical transmitting units (optical transmitting unit 1 and optical transmitting unit 2), and two optical receiving units (optical receiving unit 1 and optical receiving unit 2). The connection relationship between the units of the optical module 1 and the line-side channel unit of the electrical signal processing unit 1 is shown in FIG. 2b, which will not be described in detail here.

[0111] The PHY chip 2 of the network device 2 includes two electrical signal transmitting units and two electrical signal receiving units, which are electrical signal transmitting unit 1, electrical signal transmitting unit 2, electrical signal receiving unit 1, and electrical signal receiving unit 2.

[0112] The system-side channel unit of the electrical signal processing unit 2 includes two system-side electrical signal receiving units (system-side electrical signal receiving unit 1 and system-side electrical signal receiving unit 2), and two system-side electrical signal transmitting units (system-side electrical signal transmitting unit 1 and system-side electrical signal transmitting unit 2). The line-side channel unit of the electrical signal processing unit 2 includes two line-side electrical signal receiving units (line-side electrical signal receiving unit 1 and line-side electrical signal receiving unit 2), and two line-side electrical signal transmitting units (line-side electrical signal transmitting unit 1 and line-side electrical signal transmitting unit 2). The connection relationship between the system-side channel unit and the line-side channel unit of the electrical signal processing unit 2 is shown in FIG. 2b, which will not be described in detail here.

[0113] The optical module 2 includes two optical transmitting units (optical transmitting unit 1 and optical transmitting unit 2), and two optical receiving units (optical receiving unit 1 and optical receiving unit 2). The connection relationship between the units of the optical module 2 and the line-side channel unit of the electrical signal processing unit 2 is shown in FIG. 2b, which will not be described in detail here.

[0114] The optical module 1 and the optical module 2 can be connected through an optical fiber. The connection relationship between the units of the optical module 1 and the units of the optical module 2 is shown in FIG. 2b, which will not be described in detail here.

[0115] As shown in FIG. 2b, there are 4 links between the PHY chip 1 and the PHY chip 2, wherein: the link 1 and the link 3 are links from the PHY chip 1 to the PHY chip 2, and the link 2 and the link 4 are links from the PHY chip 2 to the PHY chip 1. If the PHY 1 is taken as a sending end and the PHY 2 is taken as a receiving end, the link 1 and the link 3 can be called sending links, and the link 2 and the link 4 can be called receiving links. In an example, the link 1 and the link 2 constitute a group of transceiving links, and the link 3 and the link 4 also constitute a group of transceiving links.

[0116] FIG. 2c shows another example application scenario provided by an embodiment of the present application. The application scenario shown in FIG. 2c is the same as the application scenario shown in FIG. 2b, and the difference lies in that in FIG. 2c, the optical transmitting unit in the optical module is refined into two parts including a drive and a transmitter optical subassembly (TOSA), and the optical receiving unit in the optical module is refined into two parts including a trans-impedance amplifier (TIA) and a receiver optical subassembly (ROSA).

[0117] As shown in FIG. 2c, the link 1 can include 3 sub-links, corresponding to the sub-link 1, the sub-link 2 and the sub-link 3 shown in FIG. 2c respectively.

[0118] The link 3 also includes 3 sub-links, corresponding to the sub-link 1', the sub-link 2' and the sub-link 3' shown in FIG. 2c respectively. Wherein:

[0119] The sub-link 1' and the sub-link 1 correspond to each other, and both are links from the PHY chip 1 to the electrical signal processing unit 1.

[0120] The sub-link 2' and the sub-link 2 correspond to each other, and both are links from the electrical signal processing unit 1 to the electrical signal processing unit 2.

[0121] The sub-link 3' and the sub-link 3 correspond to each other, and both are links from the electrical signal processing unit 2 to the PHY chip 2.

[0122] In the scenario 1, the sending end device is the network device 1, and the receiving end device is the network device 2. At this time, the first link can be, for example, the link 1 shown in FIG. 2b or FIG. 2c, and the second link can be, for example, the link 3 shown in FIG. 2b or FIG. 2c. Correspondingly, the first sub-link can be any one of the sub-link 1, the sub-link 2 and the sub-link 3.

[0123] In scenario 2, the sending end device is the network device 1, and the receiving end device is the optical module 2. At this time, the first link may, for example, be the part of the link 1 shown in FIG. 2b or FIG. 2c from the network device 1 to the optical module 2, and the second link may, for example, be the part of the link 3 shown in FIG. 2b or FIG. 2c from the network device 1 to the optical module 2. Correspondingly, the first sub-link may be the sub-link 1. For the scenario in which the electrical signal processing unit is located in the optical module 2, the first sub-link may also be the sub-link 2.

[0124] In scenario 3, the sending end device is the optical module 1, and the receiving end device is the network device 2. At this time, the first link may, for example, be the part of the link 1 shown in FIG. 2b or FIG. 2c from the optical module 1 to the network device 2, and the second link may, for example, be the part of the link 3 shown in FIG. 2b or FIG. 2c from the optical module 1 to the network device 2. Correspondingly, the first sub-link may be the sub-link 3. For the scenario in which the electrical signal processing unit 1 is located in the optical module 1, the first sub-link may also be the sub-link 2.

[0125] Next, taking the scenario shown in FIG. 2c as an example, the method for fault positioning provided in the embodiments of the present application is introduced in combination with the flow chart shown in FIG. 3. FIG. 3 is a flow chart of a method for fault positioning provided in the embodiments of the present application.

[0126] The method shown in FIG. 3 can be applied to a receiving end device. The receiving end device may, for example, be the network device 2 or the optical module 2 shown in FIG. 2c. The receiving end device can locate the cause of the fault of the first link between the sending end device and the receiving end device. As described above, when the receiving end device is the network device 2, the sending end device may be the network device 1 or the optical module 1; when the receiving end device is the optical module 2, the sending end device is the network device 1.

[0127] The method shown in FIG. 3 can include the following S101-S103.

[0128] S101: The receiving end device determines a first recombination link to be detected, the first recombination link including a first sub-link, the first sub-link belonging to a first link with a fault, the first recombination link being a link formed by replacing a corresponding link in a second link without a fault by the first link, the first link, the second link, and the first recombination link all being links from the sending end device to the receiving end device, and the sending end device and the receiving end device communicating through an optical fiber link.

[0129] In the embodiments of the present application, if the sending end device is the network device 1, and the receiving end device is the network device 2, the first link may correspond to the link 1 shown in FIG. 2c, and the second link may correspond to the link 2 in FIG. 2c. For this case:

[0130] In one example, the first sub-link can be sub-link 1 in FIG. 2c. Correspondingly, the first recombined link can be a link formed by replacing sub-link 1' in link 2 with sub-link 1. For this case, the first recombined link can be understood with reference to FIG. 4a, which is a schematic diagram of a first recombined link according to an embodiment of the present application. The link schematically shown by the red arrow in FIG. 4a is the first recombined link.

[0131] In another example, the first sub-link can be sub-link 2 in FIG. 2c. Correspondingly, the first recombined link can be a link formed by replacing sub-link 2' in link 2 with sub-link 2. For this case, the first recombined link can be understood with reference to FIG. 4b, which is another schematic diagram of a first recombined link according to an embodiment of the present application. The link schematically shown by the red arrow in FIG. 4b is the first recombined link.

[0132] In another example, the first sub-link can be sub-link 3 in FIG. 2c. Correspondingly, the first recombined link can be a link formed by replacing sub-link 3' in link 2 with sub-link 3. For this case, the first recombined link can be understood with reference to FIG. 4c, which is another schematic diagram of a first recombined link according to an embodiment of the present application. The link schematically shown by the red arrow in FIG. 4c is the first recombined link.

[0133] In the embodiments of the present application, if the sending-end device is network device 1 and the receiving-end device is optical module 2, the first link can correspond to the part of link 1 in FIG. 2c from network device 1 to optical module 2, and the second link can correspond to the part of link 2 in FIG. 2c from network device 1 to optical module 2. For this case:

[0134] In one example, the first sub-link can be sub-link 1 in FIG. 2c. Correspondingly, the first recombined link can be a link formed by replacing sub-link 1' in link 2 with sub-link 1. For this case, the first recombined link can be the part of the link schematically shown by the red arrow in FIG. 4a from network device 1 to optical module 2.

[0135] In the embodiments of the present application, if the sending-end device is optical module 1 and the receiving-end device is network device 2, the first link can correspond to the part of link 1 in FIG. 2c from optical module 1 to network device 2, and the second link can correspond to the part of link 2 in FIG. 2c from optical module 1 to network device 2. For this case:

[0136] In one example, the first sub-link can be sub-link 3 in FIG. 2c. Correspondingly, the first recombined link can be a link formed by replacing sub-link 3' in link 2 with sub-link 3. For this case, the first recombined link can be the part of the link schematically shown by the red arrow in FIG. 4c from optical module 1 to network device 2.

[0137] In one example, the receiving end device can perform fault localization on the first link after determining the first link failure. Specifically, the receiving end device can perform S101-S103 to perform fault localization on the first link.

[0138] In the embodiments of the present application, the receiving end device can determine a plurality of sub-links included in the first link after determining the first link failure, and select one of the plurality of sub-links as the first sub-link. The embodiments of the present application do not specifically limit the specific implementation manner of the receiving end device determining the first link failure. For example, the receiving end device can determine the first link failure when the error rate corresponding to the first link is higher than a certain threshold. In addition, the receiving end device can also select one of the other links other than the first link from the other links from the sending end device to the receiving end device as the second link. Further, the first reorganized link formed by replacing the corresponding link in the second link with the first sub-link is determined.

[0139] In one example, when the first link includes a plurality of sub-links, the receiving end device can respectively determine whether the fault position of the first link includes each of the plurality of sub-links. For example, when the first link corresponds to the link 1 shown in FIG. 2c, the receiving end device can respectively determine whether the fault position of the first link includes the sub-link 1 (at this time, the sub-link 1 is the first sub-link), whether the fault position of the first link includes the sub-link 2 (at this time, the sub-link 2 is the first sub-link), and whether the fault position of the first link includes the sub-link 3 (at this time, the sub-link 3 is the first sub-link). In other words, the fault position of the first link can include multiple stages, for example, in the above example, the fault position of the first link can include 3 stages.

[0140] For convenience of description, determining whether the fault position of the first link includes the sub-link 1 is called stage 1, determining whether the fault position of the first link includes the sub-link 3 is called stage 2, and determining whether the fault position of the first link includes the sub-link 2 is called stage 3.

[0141] In one example, the receiving end device can send the first frame to the sending end device, and the first frame includes the first indication information. The first indication information can be used to indicate the current stage of fault locating for the first link. Different stages require locating different sub-links, and each stage has a corresponding first sub-link. For example, the first sub-link corresponding to the aforementioned stage 1 is sub-link 1, the first sub-link corresponding to the aforementioned stage 2 is sub-link 3, and the first sub-link corresponding to the aforementioned stage 3 is sub-link 2. Since the stage and the first sub-link have a one-to-one correspondence, the aforementioned first indication information can be used to indicate that fault locating is performed on the first sub-link. The fault locating on the first sub-link can also be understood as locating whether the fault position of the first link includes the first sub-link.

[0142] In one example, the receiving end device can send the first frame to the sending end device through the third link. The third link can be any link from the receiving end device to the sending end device. In a specific example, the third link and the first link can be a set of transceiving links between the sending end device and the receiving end device. For example, the first link corresponds to link 1 shown in FIG. 2c, and the third link can correspond to link 2 shown in FIG. 2c.

[0143] In one example, if the first sub-link is link 1 shown in FIG. 2c, the first indication information can be used to trigger the electrical signal processing unit 1 to switch the first sub-link to a second sub-link in the second link, so as to replace the corresponding sub-link 1' in the second link with the sub-link 1, thereby obtaining a first reorganized link that retains the first sub-link but avoids other sub-links in the first link. For this case, the first reorganized link includes the first sub-link and the second sub-link. In other words, in the first reorganized link, only the first sub-link comes from the faulty first link, and the other part (i.e., the second sub-link) comes from the non-faulty second link. In this scenario, the second sub-link is the link from the electrical signal processing unit 1 to the receiving end device. For example, when the receiving end device is the network device 2, the second sub-link is the link from the electrical signal processing unit 1 to the network device 2. For another example, when the receiving end device is the optical module 2, the second sub-link is the link from the electrical signal processing unit 1 to the optical module 2. For understanding, reference can be made to FIG. 4a. In this scenario, after receiving the first indication information, the electrical signal processing unit 1 can map its M Host RX1 to Line TX2, so as to switch the first sub-link to the second sub-link in the second link.

[0144] In one example, if the first sub-link is the link 2 shown in FIG. 2c, the first indication information can be used to trigger the electrical signal processing unit 1 to switch the third sub-link in the second link to the first sub-link, and trigger the electrical signal processing unit 2 to switch the first sub-link to the fourth sub-link in the second link, so as to achieve the purpose of replacing the corresponding sub-link 1' in the second link with the sub-link 1, thereby obtaining a first reorganized link which retains the first sub-link but avoids other sub-links in the first link except the first sub-link. For this case, the first reorganized link can include the first sub-link, the third sub-link and the fourth sub-link. In other words, in the first reorganized link, only the first sub-link comes from the faulty first link, and the other parts (i.e. the third sub-link and the fourth sub-link) come from the non-faulty second link. In this scenario, the third sub-link is the link between the PHY chip 1 and the electrical signal processing unit 1, and the fourth sub-link is the link between the electrical signal processing unit 2 and the PHY chip 2. It can be understood with reference to FIG. 4b that in this scenario, after receiving the first indication information, the electrical signal processing unit 2 can map its M Host TX2 to Line RX1 to achieve the switching of the first sub-link to the fourth sub-link in the second link. In addition, after receiving the first indication information, the electrical signal processing unit 1 can map its M Host RX2 to Line TX1 to achieve the switching of the third sub-link in the second link to the first sub-link.

[0145] In one example, if the first sub-link is the sub-link 3 of the link 2 in FIG. 2c, the first indication information can be used to trigger the electrical signal processing unit 2 to switch the fifth sub-link in the second link to the first sub-link, or the first indication information can be used to trigger the electrical signal processing unit 2 to switch the first sub-link to the fifth sub-link in the second link, so as to replace the corresponding sub-link 1' in the second link with the sub-link 1, thereby obtaining a first reorganized link which retains the first sub-link but avoids other sub-links in the first link. For this case, the first reorganized link includes the first sub-link and the fifth sub-link, in other words, in the first reorganized link, only the first sub-link comes from the faulty first link, and the other part (i.e., the fifth sub-link) comes from the non-faulty second link. In this scenario, the fifth sub-link is the link from the sending end device to the electrical signal processing unit 2. For example, when the sending end device is the network device 1, the fifth sub-link is the link from the network device 1 to the electrical signal processing unit 2. For another example, when the sending end device is the optical module 1, the fifth sub-link is the link from the optical module 1 to the electrical signal processing unit 2. For understanding, reference can be made to FIG. 4c. In this scenario, after receiving the first indication information, the electrical signal processing unit 2 can map the M Host TX1 of itself to the Line RX2, so as to switch the first sub-link to the fifth sub-link in the second link (or switch the fifth sub-link to the first sub-link).

[0146] In one example, the first frame can include at least one information field, and the first indication information can be carried in any one of the at least one information field. As a specific example, the at least one information field includes a control field, and the first indication information is carried in the control field of the first frame. In one possible implementation, the first indication information can be carried in two bits in the control field. Assuming that the first indication information is carried in the X+1 bit and the X bit of the control field, the specific meanings of the X+1 bit and the X bit can be understood from the following Table 1.

[0147] Table 1

[0148] In Table 1:

[0149] “Diagnosis of failure of the network device at the opposite end”, corresponding to the aforementioned stage 1, for example in FIG. 2c, in this stage, it is determined whether the failure position of the link 1 includes the sub-link 1.

[0150] “Diagnosis of failure of the network device at the opposite end”, corresponding to the aforementioned stage 1, for example in FIG. 2c, in this stage, it is determined whether the failure position of the link 1 includes the sub-link 1.

[0151] "Optical module or optical link fault diagnosis", corresponding to the aforementioned stage 3, taking Fig. 2c as an example, in this stage, it is determined whether the fault position of the link 1 includes the sub-link 2.

[0152] It should be noted that the content shown in Table 1 is only shown for the convenience of understanding the present scheme, and does not constitute a limitation on the embodiments of the present application. The value of X+1:X and its corresponding meaning can not be limited to the case shown in Table 1.

[0153] In one example, the aforementioned at least one information field can further include a status field. In one example, the status field of the first frame can be used to indicate that the receiving end device has completed the first preparation operation required by the stage of the current fault positioning. In other words, the status field of the first frame can be used to indicate that the receiving end device has completed the first preparation operation of performing fault positioning on the first sub-link. The first preparation operation can include the mapping relationship switching operation required by the system side channel unit and the line side channel unit of the corresponding electrical signal processing unit 2 of the receiving end device, so as to obtain the first reorganized link after performing the mapping relationship switching operation. As previously described, in the case where the first sub-link corresponds to the link 2 shown in Fig. 2c, the first preparation operation can include switching the first sub-link to the fourth sub-link in the second link by the electrical signal processing unit 2. In the case where the first sub-link corresponds to the link 3 shown in Fig. 2c, the first preparation operation can include switching the fifth sub-link of the second link to the first sub-link by the electrical signal processing unit 2.

[0154] In one example, the completion of the aforementioned first preparation operation can be indicated by one or more bits of the status field of the first frame. In one possible implementation, the completion of the aforementioned first preparation operation can be implemented by one bit in the status field. Assuming that the completion of the aforementioned first preparation operation is indicated by the Yth bit of the control field, the specific meaning of the Yth bit can be understood by Table 2 below.

[0155] Table 2

[0156] As shown in Table 1, if the value of the Yth bit of the status field of the first frame is 1, it indicates that the receiving end device has completed the aforementioned first preparation operation, and if the value of the Yth bit of the status field of the first frame is 0, it indicates that the receiving end device has not completed the first preparation operation.

[0157] In one example, the receiving end device may, for example, send the first frame to the sending end device after the completion of the first preparation operation.

[0158] In the embodiments of the present application, the first frame can be a frame with a certain structure. In a specific example, the first frame can be a training frame. In addition to including a control field and a status field, the training frame can further include an identification bit for identifying the training frame, which can be, for example, a specific 4 pulse amplitude modulation (PAM4) symbol sequence composed of 16 consecutive "3"s and 16 consecutive "0"s.

[0159] In one example, the electrical signal processing unit 2 can include a register, a value of the register being used to indicate a mapping relationship between the system-side channel unit and the line-side channel unit of the electrical signal processing unit 2. The electrical signal processing unit 2 can adjust the value of the register itself to adjust the mapping relationship between the system-side channel unit and the line-side channel unit thereof. In other words, the electrical signal processing unit 2 can adjust the value of the aforementioned register itself to complete the aforementioned first preparation operation.

[0160] In yet another example, the electrical signal processing unit 2 can also adjust the mapping relationship between the system-side channel unit and the line-side channel unit thereof based on a value of a register set by the PHY chip 2. In other words, the electrical signal processing unit 2 can complete the aforementioned first preparation operation based on the value of the register set by the PHY chip 2. As an example, the PHY chip 2 can send a channel switching instruction to the electrical signal processing unit 2, the channel switching instruction being used to indicate the value of the aforementioned register, and further, the electrical signal processing unit 2 can complete the aforementioned first preparation operation based on the value of the register indicated by the aforementioned channel switching instruction. As previously described, the receiving end device can select one of the other links other than the first link from the sending end device to the receiving end device as the second link. In the embodiments of the present application, the receiving end device can also notify the sending end device of the second link selected by itself, so that the sending end device can perform the second preparation operation of performing fault localization on the first sub-link to obtain the first reorganized link.

[0161] In one example, the receiving end device can notify the sending end device of the information of the second link through the status field of the aforementioned first frame, so that the sending end device can determine the second link. For example, the information of the second link can be carried by at least two bits in the status field. For example, the two bits can be used to carry the channel number corresponding to the second link, for example, when the channel number is 3, it means that the second link is the third link from the sending end device to the receiving end device, and for another example, when the channel number is 5, it means that the second link is the fifth link from the sending end device to the receiving end device.

[0162] In yet another example, the receiving end device can send a third frame to the sending end device through a fourth link, and neither the state field nor the control field in the third frame carries valid information. For example, the values of the X+1th bit and the Xth bit of the control field of the third frame are both 0, and the value of the Yth bit of the state field of the third frame is also 0. The fourth link and the second link are a set of transceiving links between the sending end device and the receiving end device. After receiving the third frame, the sending end device can determine that the third frame is used to announce the reference link (i.e., the second link) participating in the fault positioning, and therefore, the sending end device can determine another link that forms a set of transceiving links with the fourth link as the second link.

[0163] In another example, the sending end device can also select a second link from a plurality of links from the sending end device to the receiving end device in the manner that the receiving end device selects the second link. For example, each of the plurality of links from the sending end device to the receiving end device has a number, and the sending end device and the receiving end device can select a link with a number closest to that of the first link as the second link. For example, the numbers of the plurality of links are 1, 3, 5, and 7, and the number of the first link is 1, and therefore, the sending end device and the receiving end device both select the link with the number 3 as the second link.

[0164] In one example, after the sending end device determines the second link, the sending end device can stop sending service data on the second link, so as to subsequently perform fault positioning on the first link by using the second link.

[0165] Regarding the second preparation operation, it should be noted that the second preparation operation can include a mapping relationship switching operation between the system-side channel unit and the line-side channel unit required to be completed by the corresponding electrical signal processing unit 1 of the sending end device, so as to obtain the first reorganized link after performing the mapping relationship switching operation. As described above, in the case that the first sub-link corresponds to the link 1 shown in FIG. 2c, the second preparation operation can include switching the first sub-link to the second sub-link in the second link by the electrical signal processing unit 1. In the case that the first sub-link corresponds to the link 3 shown in FIG. 2c, the second preparation operation can include switching the third sub-link of the second link to the first sub-link by the electrical signal processing unit 1.

[0166] In one example, the electrical signal processing unit 1 can include a register, a value of the register being used to indicate a mapping relationship between the system-side lane units and the line-side lane units of the electrical signal processing unit 1. The electrical signal processing unit 1 can adjust the value of the register by itself to adjust the mapping relationship between the system-side lane units and the line-side lane units of the electrical signal processing unit 1. In other words, the electrical signal processing unit 1 can adjust the value of the aforementioned register by itself to complete the aforementioned second preparation operation.

[0167] In yet another example, the electrical signal processing unit 1 can also adjust the mapping relationship between the system-side lane units and the line-side lane units of the electrical signal processing unit 1 based on a value of a register set by the PHY chip 1. In other words, the electrical signal processing unit 1 can complete the aforementioned second preparation operation based on the value of the register set by the PHY chip 1. As one example, the PHY chip 1 can send a lane switching instruction to the electrical signal processing unit 1, the lane switching instruction being used to indicate the value of the aforementioned register, and further, the electrical signal processing unit 1 can complete the aforementioned second preparation operation based on the value of the register indicated by the aforementioned lane switching instruction.

[0168] As known from the foregoing description, in the scenario where the receiving end device is a receiving end network device and the sending end device is a sending end network device, the first frame sent by the receiving end network device to the sending end network device experiences a path of: PHY chip 2 → electrical signal processing unit 2 → electrical signal processing unit 1 → PHY chip 1.

[0169] In one example, the aforementioned first preparation operation can include operations performed by the PHY chip 2 in addition to the operations performed by the electrical signal processing unit 2. Similarly, the aforementioned second preparation operation can include operations performed by the PHY chip 1 in addition to the operations performed by the electrical signal processing unit 1. As an example, after the PHY chip 2 has performed the operations required to be performed by the PHY chip 2, the PHY chip 2 can send a first frame to the electrical signal processing unit 2, the status field of the first frame indicating that the PHY chip 2 has completed the operations required to be performed by the PHY chip 2. Further, after the electrical signal processing unit 2 receives the first frame, the electrical signal processing unit 2 can parse the first frame, and based on the status field of the first frame, the electrical signal processing unit 2 determines that the PHY chip 2 has completed the operations required to be performed by the PHY chip 2, and then the electrical signal processing unit 2 performs the operations required to be performed by the electrical signal processing unit 2 in combination with the control field of the first frame. Moreover, after the electrical signal processing unit 2 has completed the operations required to be performed by the electrical signal processing unit 2, the electrical signal processing unit 2 further sends the first frame to the electrical signal processing unit 1. Similarly, after the electrical signal processing unit 1 receives the first frame, the electrical signal processing unit 1 can parse the first frame, and based on the status field of the first frame, the electrical signal processing unit 1 determines that the electrical signal processing unit 2 has completed the operations required to be performed by the electrical signal processing unit 2, and then the electrical signal processing unit 1 performs the operations required to be performed by the electrical signal processing unit 1 in combination with the control field of the first frame. Moreover, after the electrical signal processing unit 1 has completed the operations required to be performed by the electrical signal processing unit 1, the electrical signal processing unit 1 further sends the first frame to the PHY chip 1, so that the PHY chip 1 continues to perform the operations required to be performed by the PHY chip 1.

[0170] In one example, if the electrical signal processing unit 2 has not completed the operations required to be performed by the electrical signal processing unit 2, in one example, the electrical signal processing unit 2 can discard the first frame. In another example, the electrical signal processing unit 2 can also modify the status field of the first frame, so that the modified status field indicates that the electrical signal processing unit 2 has not completed the operations required to be performed by the electrical signal processing unit 2, and further sends the first frame to the electrical signal processing unit 1. In this scenario, after the electrical signal processing unit 1 receives the first frame, the electrical signal processing unit 1 can parse the first frame, and based on the status field of the first frame, the electrical signal processing unit 1 determines that the electrical signal processing unit 2 has not completed the operations required to be performed by the electrical signal processing unit 2, and then the electrical signal processing unit 1 directly sends the first frame to the PHY chip 1, without performing the step of performing the operations required to be performed by the electrical signal processing unit 1 in combination with the control field of the first frame. Similarly, after the PHY chip 1 receives the first frame, the PHY chip 1 can parse the first frame, and based on the status field of the first frame, the PHY chip 1 determines that the electrical signal processing unit 1 has not completed the operations required to be performed by the electrical signal processing unit 1, and then the PHY chip 1 also does not perform the step of performing the operations required to be performed by the PHY chip 1 in combination with the control field of the first frame.

[0171] S102: The receiving end device performs fault detection on the first recombination link.

[0172] After determining the first recombination link, the receiving-end device can perform fault detection on the first recombination link.

[0173] In one example, the receiving-end device can perform fault detection on the first recombination link based on a second frame sent by the sending-end device to the receiving-end device through the first recombination link. That is, after the sending-end device completes the aforementioned second preparation operation, the sending-end device can send a second frame to the receiving-end device through the first recombination link. Similar to the first frame, the second frame can be a frame with a certain structure, and in one specific example, the second frame can be a training frame.

[0174] In one example, the second frame can include a test data stream, and the receiving-end device can determine whether the first recombination link is faulty based on an error rate of the test data stream transmitted on the first recombination link. For example, the receiving-end device can determine that the first recombination link is faulty when the error rate is greater than or equal to a preset error rate threshold. When the error rate is less than the preset error rate threshold, the receiving-end device can determine that the first recombination link is not faulty. In one specific example, the test data stream can be a PRBS.

[0175] Similar to the first frame, the second frame can also include a control field, and the control field of the second frame carries second indication information indicating whether the fault location of the first link includes the first sub-link. The second frame carries the second indication information in the same way as the first frame carries the first indication information. Therefore, for the second indication information, please refer to the description of the first indication information above, which will not be repeated here.

[0176] Similar to the first frame, the second frame can also include a status field, and the status field of the second frame is used to indicate that the sending-end device has completed the aforementioned second preparation operation. For the second preparation operation, please refer to the description above, which will not be repeated here. For the description of the status field of the second frame indicating that the sending-end device has completed the aforementioned second preparation operation, please refer to the description of the status field of the first frame indicating that the receiving-end device has completed the aforementioned first preparation operation, which will not be repeated here.

[0177] In addition, in the case where the second frame is a training frame, the second frame can also include an identification bit for identifying the training frame. For the identification bit, please refer to the specific description above, which will not be repeated here.

[0178] In yet another example, the receiving end device may, for example, detect a loss of signal (LOS) or loss of lock (LOL) alarm of the first recombination link to perform fault detection on the first recombination link. For example, when the first recombination link has a LOS or LOL alarm, it is determined that the first recombination link is faulty.

[0179] In another example, the receiving end device determines the eye height and / or noise of the electrical signal received through the first recombination link, and when the eye height and / or noise is greater than or equal to a preset threshold, it is determined that the first recombination link is faulty.

[0180] In yet another example, the receiving end device may, for example, detect the optical power and / or signal-to-noise ratio (SNR) of the optical signal received through the first recombination link, and when the optical power and / or SNR is lower than a preset threshold, it is determined that the first recombination link is faulty.

[0181] S103: The receiving end device determines whether the fault position of the first link includes the first sub-link according to the fault detection result of the first recombination link.

[0182] As described above, in the plurality of sub-links included in the first recombination link, only the first sub-link comes from the faulty first link, and the other sub-links come from the non-faulty second link. In other words, in the first recombination link, except that it is not yet clear whether the first sub-link is faulty, it can be determined that the other sub-links are non-faulty. Therefore, the fault detection result of the first recombination link is also the fault detection result of the first sub-link. That is, if the fault detection result of the first recombination link indicates that the first recombination link is faulty, it means that the first sub-link is faulty. If the fault detection result of the first recombination link indicates that the first recombination link is non-faulty, it means that the first sub-link is non-faulty. Therefore, in the implementation of S103, if the fault detection result indicates that the first recombination link is faulty, the receiving end device determines that the fault position of the first link includes the first sub-link; if the fault detection result indicates that the first recombination link is non-faulty, the receiving end device determines that the fault position of the first link does not include the first sub-link.

[0183] As described above, by using the scheme of the embodiments of the present application, after the first link fails, the receiving end device and the sending end device can exchange information (such as the first frame and the second frame described above) to realize the positioning of the fault position of the first link. Without manual intervention, compared with the way of configuring a loopback, the efficiency of fault positioning by the present scheme is lower.

[0184] Further, the scheme can perform the fault locating method of the scheme on each sub-link of the fault link, so that the range of fault locating can cover the entire fault link (i.e., the first link).

[0185] In addition, in the scheme of performing fault detection on the first recombination link through the second frame, since the sending end device and the receiving end device involved in the information interaction in the process of fault detection are the original devices, the problem that the loopback technology is difficult to reproduce the fault scene in some specific scenarios, thereby leading to inaccurate fault detection results can be avoided. That is, the scheme of the embodiment of the application has more accurate fault locating results. For example, reference can be made to FIG. 4d for understanding. FIG. 4d is a schematic diagram of an exemplary application scenario provided by the embodiment of the application.

[0186] FIG. 4d shows the application of the scheme to the fault scenario shown in FIG. 1b. In the scenario shown in FIG. 4d, the network device 1 can correspond to the sending end device in the above embodiment, and correspondingly, the network device 2 can correspond to the receiving end device in the above embodiment. Correspondingly, the link shown by the red arrow in FIG. 4d is the first recombination link, and the network device 2 sends the second frame to the network device 1 through the first recombination link. When the second frame from the PHY chip of manufacturer B is received by the PHY chip of manufacturer A, the setting value of the decision threshold and the level of the received signal are not adapted, which can cause the link to be interrupted. That is, the network device 1 can determine that the first recombination link is faulty, and correspondingly, the network device 1 can determine that the first sub-link (i.e., the link between the PHY chip of manufacturer A and the electrical signal processing unit 1 in FIG. 4d) in the first recombination link is faulty, thereby accurately locating the fault. For details in FIG. 4d that are not shown in FIG. 1b, for example, details in the optical module 1, the optical module 2, and the electrical signal processing unit 1, reference can be made to the related description in the foregoing description of other figures, which will not be repeated here.

[0187] The scheme of the embodiment of the application is introduced above. Next, the scheme of the embodiment of the application will be described in combination with a specific scenario.

[0188] Referring to FIG. 5a, which is a schematic diagram of an exemplary application scenario provided by the embodiment of the application.

[0189] The application scenario shown in FIG. 5a is a variation of the application scenario shown in FIG. 2c, in which the electrical signal processing unit 1 is in the optical module 1 and the electrical signal processing unit 2 is in the optical module 2. The optical module 1 and the optical module 2 shown in FIG. 5a can be common optical modules including an optical digital signal processing (oDSP) chip. The oDSP chip can include an electrical signal processing unit. That is, the oDSP of the optical module 1 includes the electrical signal processing unit 1, and the oDSP of the optical module 2 includes the electrical signal processing unit 2.

[0190] In addition, although not shown in FIG. 5a, the common optical module also includes a micro controller unit (MCU). The network device (for example, the network device 1 and the network device 2) can include a central processing unit (CPU) in addition to the PHY chip. The first side of the aforementioned oDSP chip is used to connect the PHY chip, which can be referred to as the host side. The second side of the oDSP chip is used to connect the TOSA / ROSA of the optical module, which can be referred to as the media side. The host side and the media side are not limited in the embodiments of the present application. The first side is used to communicate with the PHY chip through an electrical channel. For example, the serializer / deserializer (serdes) located on the first side of the oDSP chip communicates with the serdes (not shown in FIG. 5a) located on the PHY chip through an electrical channel. The second side is used to communicate with the TOSA / ROSA through an electrical channel. In one implementation, the TOSA / ROSA in the optical module 1 is connected to the TOSA / ROSA in the optical module 2 through an optical channel.

[0191] The MCU of the optical module is connected to the CPU of the host side device (i.e., the network device) through a management interface. After the optical module is powered on, whether the optical module has the ability of linear operation and the current working mode adopted by the optical module can be reported to the host side device through the management interface. For example, the management interface can be an inter-integrated circuit (IIC) interface, and the management protocol based on the management interface can be a common management interface specification (CMIS).

[0192] In the scenario shown in FIG. 5a, after the network device 2 determines that the link 1 is faulty, the PHY chip 2 corresponding to the physical coding sublayer (PCS) generates a local fault sequence and sends it to the local media access control (MAC) layer. After the MAC of the network device 2 receives the local fault sequence, it can stop sending service data on the service 2 and generate a remote fault sequence and send it to the PHY chip 1 of the network device 1. After the PHY chip 1 receives the remote fault sequence, it determines that the link is faulty and stops sending service data on the link 1.

[0193] Further, the PHY chip 2 triggers a fault locating process.

[0194] First, the PHY chip 2 triggers stage 1 of the fault locating process. Stage 1 is used to determine whether the location of the link fault includes the sub-link 1. The specific process can be understood in combination with FIG. 5b. FIG. 5b is a process schematic diagram of a fault locating method provided by an embodiment of the present application. The fault locating process shown in FIG. 5b can include the following steps:

[0195] 1. The PHY chip 2 sends a first training frame to the electrical signal processing unit 2.

[0196] The PHY chip 2 sends the first training frame to the electrical signal processing unit 2 through the C Host TX 1. The X:X+1 bit position of the control field of the first training frame is 01, indicating that the current diagnosis stage is stage 1; the Y bit position of the state field is 1, indicating that the PHY chip 2 has completed the diagnosis preparation process. 2. The electrical signal processing unit 2 identifies the first training frame and sends it to the electrical signal processing unit 1.

[0197] After the electrical signal processing unit 2 identifies that the control field X:X+1 bit is 01, it determines that the current diagnosis stage is stage 1, and determines that the mapping relationship between its own system side channel unit and line side channel unit in this stage does not need to be changed. The electrical signal processing unit 2 sends the first training frame to the electrical signal processing unit 1 through the Line TX 1, and keeps the control field X:X+1 bit content and the Y bit content of the state field of the first training frame unchanged.

[0198] 3. The electrical signal processing unit 1 identifies the first training frame and maps its own M Host RX1 to the Line TX2 to form the first recombination path corresponding to the red arrow in FIG. 5b. Moreover, the electrical signal processing unit 1 continues to send the first training frame to the PHY chip 1.

[0199] The electrical signal processing unit 1 identifies that the control field X:X+1 bit is 01, determines that the current fault diagnosis stage is stage 1, and thus maps MHost RX 1 to Line TX 2. For example, the electrical signal processing unit 1 can learn from a pre-stored mapping table that mapping switching needs to be performed in stage 1, and MHost RX 1 needs to be mapped to Line TX 2.

[0200] After completing the foregoing mapping switching, the electrical signal processing unit 1 sends a first training frame to the PHY chip 1 through MHost TX 1, and keeps the contents of the training frame control field and the state field unchanged.4.The PHY chip 1 identifies the first training frame, and transmits a second training frame containing a known test data stream through the first recombination link.

[0201] The PHY chip 1 identifies that the control field X:X+1 bit is 01, and determines that the current fault diagnosis stage is stage 1. The PHY chip 1 specifies that CHost TX 1 transmits a second training frame containing PRBS, keeps the content of the training frame control field unchanged, and sets the state field Y bit to 1, indicating that the PHY chip 1 has completed the diagnosis preparation process.

[0202] Before the PHY chip 1 transmits the second training frame through the first recombination link, the PHY chip 1 also sends a control message to the electrical signal processing unit 1 through the IIC interface based on the CMIS protocol, so that the electrical signal processing unit 1 stops MHost RX 2 drive+TOSA, to avoid MHost RX 2 and MHost RX 1 driving the same drive+TOSA at the same time.5.The electrical signal processing unit 1 and the electrical signal processing unit 2 identify the content of the second training frame and forward it, and the PHY chip 2 identifies the second training frame and determines the fault detection result based on the test data stream in the second training frame.

[0203] In one example, the process of determining the fault detection result based on the test data stream in the second training frame by the PHY chip 2 lasts for T seconds, and if a link fault occurs during the diagnosis process, it is determined that sublink 1 has a fault. If no link fault occurs during the diagnosis process, it is determined that sublink 1 has no fault.

[0204] If the PHY chip 2 does not receive a second training frame with control field X:X+1 bit as 01 at all within T seconds, it also determines that sublink 1 has a fault.

[0205] After determining the fault detection result corresponding to stage 1, the PHY chip 2 triggers stage 2 of fault positioning. Stage 2 is used to determine whether the location of the link fault includes sublink 3. The specific process can be understood in combination with FIG. 5c. FIG. 5c is a process schematic diagram of a fault positioning method provided by an embodiment of the present application. The fault positioning process shown in FIG. 5c can include the following steps:

[0206] 6. The PHY chip 2 sends the first training frame to the electrical signal processing unit 2.

[0207] The PHY chip 2 sends the first training frame to the electrical signal processing unit 2 through the C Host TX 1, and the X:X+1 bit position of the control field of the first training frame is 10, indicating that the current diagnosis stage is stage 2; the Y bit position of the state field is 1, indicating that the PHY chip 2 has completed the diagnosis preparation process.

[0208] 7. The electrical signal processing unit 2 identifies the first training frame and sends the first training frame to the electrical signal processing unit 1.

[0209] After the electrical signal processing unit 2 identifies that the control field X:X+1 bit is 10, it is determined that the current diagnosis stage is stage 2, and it is determined that in this stage, it needs to map the M Host TX1 to the Line RX2, so the electrical signal processing unit 2 maps its own M Host TX1 to the Line RX2 to form the first recombination path corresponding to the red arrow in FIG. 5c. The electrical signal processing unit 2 sends the first training frame to the electrical signal processing unit 1 through the Line TX 1, and keeps the control field X:X+1 bit content and the Y bit content of the state field of the first training frame unchanged.

[0210] In addition, the PHY chip 2 also sends a control message to the electrical signal processing unit 2 through the IIC interface based on the CMIS protocol, so that the electrical signal processing unit 2 stops driving the TIA+ROSA of the M Host TX2, so as to avoid the M Host TX2 and the M Host TX1 driving the same TIA+ROSA at the same time.

[0211] 8. The electrical signal processing unit 1 identifies the first training frame and determines that the mapping relationship of the system side channel unit and the line side channel unit of itself needs to remain in the initial state. Since the M Host RX1 of the electrical signal processing unit 1 itself is mapped to the Line TX2 during stage 1, in this stage, the electrical signal processing unit 1 can map its own M Host RX1 to the Line TX1 and map its own M Host RX2 to the Line TX2. Moreover, the electrical signal processing unit 1 continues to send the first training frame to the PHY chip 1.

[0212] 9. The PHY chip 1 identifies the first training frame and transmits a second training frame containing a known test data stream through the first recombination link.

[0213] PHY chip 1 identifies that the control field X:X+1 bits are 10, and determines that the current fault diagnosis stage is stage 2. PHY chip 1 instructs C Host TX 2 to transmit a second training frame containing PRBS, and keeps the control field content of the training frame unchanged, and sets the state field Y bit position to 1, which represents that PHY chip 1 has completed the diagnosis preparation process.

[0214] 10. The telecommunication signal processing unit 1 and the telecommunication signal processing unit 2 identify the second training frame content and forward, and PHY chip 2 identifies the second training frame, and determines the fault detection result based on the test data stream in the second training frame.

[0215] In one example, PHY chip 2 determines the fault detection result based on the test data stream in the second training frame for T seconds, and determines that the sub-link 3 is faulty if a link fault occurs during the diagnosis process. If no link fault occurs during the diagnosis process, it is determined that the sub-link 3 is not faulty.

[0216] If PHY chip 2 does not receive the second training frame with the control field X:X+1 bits being 10 at all within T seconds, it also determines that the sub-link 3 is faulty.

[0217] After the fault detection result corresponding to stage 2 is determined, PHY chip 2 triggers stage 3 of fault positioning. Stage 3 is used to determine whether the position of the link fault includes sub-link 2. The specific process can be understood in combination with FIG. 5d. FIG. 5d is a process schematic diagram of a fault positioning method provided by an embodiment of the present application. The fault positioning process shown in FIG. 5d can include the following steps:

[0218] 11. PHY chip 2 sends a first training frame to the telecommunication signal processing unit 2.

[0219] PHY chip 2 sends the first training frame to the telecommunication signal processing unit 2 through C Host TX 1, and the X:X+1 bits of the control field of the first training frame are 11, indicating that the current diagnosis stage is stage 3; and the Y bit of the state field is 1, indicating that PHY chip 2 has completed the diagnosis preparation process.

[0220] 12. The telecommunication signal processing unit 2 identifies the first training frame and sends the first training frame to the telecommunication signal processing unit 1.

[0221] After the electrical signal processing unit 2 identifies that the control field X:X+1 bits are 11, it determines that the current diagnosis stage is stage 3, and determines that it needs to map M Host TX2 to Line RX1 at this stage. Therefore, the electrical signal processing unit 2 maps its M Host TX2 to Line RX1 to form the first recombination path corresponding to the red arrow in FIG. 5d. The electrical signal processing unit 2 sends the first training frame to the electrical signal processing unit 1 through Line TX 1, keeping the control field X:X+1 bits and the Y bits of the status field unchanged.

[0222] In addition, the PHY chip 2 also sends a control message to the electrical signal processing unit 2 through the IIC interface based on the CMIS protocol, so that the electrical signal processing unit 2 stops M Host TX1 from driving the TIA+ROSA, so as to avoid M Host TX1 and M Host TX2 driving the same TIA+ROSA at the same time.

[0223] 13. The electrical signal processing unit 1 identifies the first training frame and sends the first training frame to the PHY chip 1.

[0224] After the electrical signal processing unit 1 identifies that the control field X:X+1 bits are 11, it determines that the current diagnosis stage is stage 3, and determines that it needs to map M Host RX2 to Line TX1 at this stage. Therefore, the electrical signal processing unit 1 maps M Host RX2 to Line TX1. And the electrical signal processing unit 1 continues to send the first training frame to the PHY chip 1.

[0225] 14. The PHY chip 1 identifies the first training frame and transmits a second training frame containing a known test data stream through the first recombination link.

[0226] After the PHY chip 1 identifies that the control field X:X+1 bits are 11, it determines that the current fault diagnosis stage is stage 3. The PHY chip 1 specifies that C Host TX 2 transmits a second training frame containing PRBS, keeps the control field unchanged, and sets the Y bits of the status field to 1, indicating that the PHY chip 1 has completed the diagnosis preparation process.

[0227] Before the PHY chip 1 transmits the second training frame through the first recombination link, the PHY chip 1 also sends a control message to the electrical signal processing unit 1 through the IIC interface based on the CMIS protocol, so that the electrical signal processing unit 1 stops M Host RX1 from driving the drive+TOSA, so as to avoid M Host RX1 and M Host RX2 driving the same drive+TOSA at the same time.

[0228] 15. The electrical signal processing unit 1 and the electrical signal processing unit 2 identify the second training frame content and forward, the PHY chip 2 identifies the second training frame, and determines the fault detection result based on the test data stream in the second training frame.

[0229] In one example, the PHY chip 2 determines the fault detection result based on the test data stream in the second training frame for T seconds, and determines that the sub-link 2 is faulty if a link fault condition occurs in the diagnosis process. If no link fault condition occurs in the diagnosis process, it is determined that the sub-link 2 is not faulty.

[0230] If the PHY chip 2 does not receive the second training frame with the control domain X:X+1 bit being 11 at all within T seconds, it also determines that the sub-link 2 is faulty.

[0231] At this point, the three-stage fault positioning process is completed, and the PHY chip 2 can determine the specific fault position of the link 1.

[0232] FIGS. 6a, 6b and 6c are schematic diagrams of another three exemplary application scenarios provided by the embodiments of the present application.

[0233] The application scenarios shown in FIGS. 6a, 6b and 6c are all variations of the application scenario shown in FIG. 2c.

[0234] In FIG. 6a, it is specified that the electrical signal processing unit 1 is in the network device 1, and the electrical signal processing unit 2 is in the network device 2.

[0235] In FIG. 6b, it is specified that the electrical signal processing unit 1 is in the optical module 1, and the electrical signal processing unit 2 is in the network device 2.

[0236] In FIG. 6c, it is specified that the electrical signal processing unit 1 is in the network device 1, and the electrical signal processing unit 2 is in the optical module 2.

[0237] For the three application scenarios of FIGS. 6a to 6c, if the link 1 is faulty, the corresponding fault positioning process is the same as that of FIG. 5a, and therefore, the specific fault positioning process can be referred to the foregoing description of FIGS. 5b to 5d, which is not repeated here.

[0238] Referring to FIG. 7, which is a structural schematic diagram of a fault positioning apparatus provided by the embodiments of the present application. The fault positioning apparatus 700 shown in FIG. 7 can be applied to the receiving end apparatus mentioned in the foregoing method embodiments, and is used to execute the fault positioning method executed by the receiving end apparatus provided by the foregoing method embodiments.

[0239] As shown in FIG. 7, the fault positioning apparatus 700 includes a determination unit 701 and a processing unit 702.

[0240] The determining unit 701 is configured to determine a first recombination link to be detected, the first recombination link comprising a first sub-link, the first sub-link belonging to a first link in failure, the first recombination link being a link formed by replacing a corresponding link in a second link without failure by the first sub-link, the first link, the second link and the first recombination link all being links from a sending end device to a receiving end device, the sending end device and the receiving end device communicating through an optical fiber link.

[0241] The processing unit 702 is configured to perform failure detection on the first recombination link, and locate whether the failure position of the first link includes the first sub-link according to a failure detection result of the first recombination link.

[0242] In a possible implementation, the determining unit 701 specifically comprises a sending unit, and the sending unit is configured to send a first frame to the sending end device, the first frame comprising first indication information, the first indication information indicating that failure positioning is performed on the first sub-link.

[0243] In a possible implementation, the sending end device comprises a first physical layer (PHY) chip, the first sub-link is a link between the first PHY chip and a first mapping module, the first mapping module being configured to connect the first PHY chip and a sending end optical module, and the first indication information triggers the first mapping module to switch the first sub-link to a second sub-link in the second link, the second sub-link being a link from the first mapping module to the receiving end device, and the first recombination link further comprising the second sub-link.

[0244] In a possible implementation, the first sub-link is a link from a first mapping module to a second mapping module, the first mapping module being configured to connect a first PHY chip and a sending end optical module, the second mapping module being configured to connect a second PHY chip and a receiving end optical module, the sending end device comprising the first PHY chip, and the receiving end device comprising the second PHY chip, the first indication information triggering the first mapping module to switch a third sub-link in the second link to the first sub-link, and triggering the second mapping module to switch the first sub-link to a fourth sub-link in the second link, the first recombination link further comprising the third sub-link and the fourth sub-link, the third sub-link being a link between the first PHY chip and the first mapping module, and the fourth sub-link being a link between the second mapping module and the second PHY chip.

[0245] In a possible implementation, the first sub-link is a link between a second mapping module and a second PHY chip, the receiving end device includes the second PHY chip, and the second mapping module is configured to connect the second PHY chip and a receiving end optical module; the first indication information triggers the second mapping module to switch a fifth sub-link of the second link to the first sub-link, and the first recombined link further includes the fifth sub-link, and the fifth sub-link is a link from the sending end device to the second mapping module.

[0246] In a possible implementation, the first indication information is carried in a control field of the first frame.

[0247] In a possible implementation, the first frame further includes a state field, and the state field of the first frame indicates that the receiving end device has completed a first preparation operation of performing fault positioning on the first sub-link, where the first preparation operation includes: a second mapping module corresponding to the receiving end device switching the first sub-link to a fourth sub-link in the second link, the fourth sub-link being a link between the second mapping module and a second PHY chip included in the receiving end device; or the second mapping module switching a fifth sub-link of the second link to the first sub-link, the fifth sub-link being a link from the sending end device to the second mapping module.

[0248] In a possible implementation, the processing unit 702 is configured to perform fault detection on the first recombined link based on a second frame sent by the sending end device to the receiving end device through the first recombined link.

[0249] In a possible implementation, the second frame includes a pseudo-random binary sequence (PRBS), and a bit error rate of the PRBS transmitted on the first recombined link is used to determine the fault detection result.

[0250] In a possible implementation, the second frame further includes a control field, and the control field of the second frame includes second indication information, where the second indication information indicates whether the first sub-link is included in locating a fault position of the first link.

[0251] In a possible implementation, the second frame further comprises a state field, and the state field of the second frame indicates that the sending end device has completed a second preparation operation of performing fault positioning on the first sub-link, and the second preparation operation comprises: a first mapping module corresponding to the sending end device switches the first sub-link to a second sub-link in the second link, and the second sub-link is a link of the first mapping module to the receiving end device; or, the first mapping module switches a third sub-link in the second link to the first sub-link, and the third sub-link is a link between a first PHY chip and the first mapping module, and the sending end device comprises the first PHY chip.

[0252] In a possible implementation, the sending end device is a sending end network device, and the first mapping module is located in the sending end network device.

[0253] In a possible implementation, the first mapping module is located in the sending end optical module.

[0254] In a possible implementation, the first mapping module is configured to perform, based on a channel switching instruction sent by the first PHY chip, a second preparation operation of locating whether the fault position of the first link comprises the first sub-link.

[0255] In a possible implementation, the receiving end device is a receiving end network device, and the second mapping module is located in the receiving end network device.

[0256] In a possible implementation, the second mapping module is located in a receiving end optical module.

[0257] In a possible implementation, the second mapping module is configured to perform, based on a channel switching instruction sent by the second PHY chip, a first preparation operation of locating whether the fault position of the first link comprises the first sub-link.

[0258] In a possible implementation, the first mapping module comprises a first chip or a first functional circuit, and / or the second mapping module comprises a second chip or a second functional circuit.

[0259] In a possible implementation, the processing unit 702 is configured to: if the fault detection result indicates that the first recombined link has a fault, locate that the fault position of the first link comprises the first sub-link; or if the fault detection result indicates that the first recombined link has no fault, locate that the fault position of the first link does not comprise the first sub-link.

[0260] In addition, the embodiment of the present application further provides a communication device 800, as shown in FIG. 8, which is a structural schematic diagram of a communication device provided by the embodiment of the present application. The communication device 800 comprises a communication interface 801 and a processor 802 connected with the communication interface 801. The communication device 800 can be applied to the receiving end device mentioned in the above embodiment, and is used for executing the method executed by the receiving end device in the above embodiment.

[0261] The communication interface 801 is used for executing the receiving and / or sending operation in the method executed by the receiving end device. The processor 802 is used for executing the other operation in the method executed by the receiving end device except the receiving and / or sending operation. For example, the communication interface 801 is used for sending the first frame to the sending end device, wherein the first frame comprises the first indication information, and the first indication information indicates that the fault positioning is performed on the first sub-link; and the processor 802 is used for performing the fault detection on the first recombination link, and positioning whether the fault position of the first link comprises the first sub-link according to the fault detection result of the first recombination link.

[0262] In addition, the embodiment of the present application further provides a communication device 900, as shown in FIG. 9, which is a structural schematic diagram of a communication device provided by the embodiment of the present application. The communication device 900 can be used for executing the fault positioning method in the above embodiment.

[0263] As shown in FIG. 9, the communication device 900 can comprise a processor 910, a communication interface 920, and a memory 930 coupled with the processor 910.

[0264] The processor mentioned in the present application can be one or more processors. When the processor is multiple, the types of the processors can be the same or different. The processor can be, for example, a CPU, a network processor (NP) or a combination of the CPU and the NP. The processor can also be one or more processing circuits. The processor can also be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0265] The memory 930 mentioned in the present application can include volatile memory such as random-access memory (RAM); the memory can also include non-volatile memory such as read-only memory (ROM), flash memory, a hard disk drive (HDD), or a solid-state drive (SSD); the memory 930 can also include a combination of the above-mentioned kinds of memory. The memory 930 can refer to one memory or can include multiple memories. In an embodiment, the memory 930 stores computer-readable instructions, which include a plurality of software modules, such as a sending module 931, a processing module 932, and a receiving module 933. The processor 910 executes each software module and performs corresponding operations according to the instructions of each software module. In the present embodiment, the operation performed by one software module actually refers to the operation performed by the processor 910 according to the instructions of the software module.

[0266] When the communication device 900 is used to perform the above fault locating method, the communication interface 920 is configured to perform the receiving and / or sending operations in the fault locating method. The processor 910 is configured to perform operations other than the receiving and / or sending operations in the fault locating method. For example, the communication interface 920 is configured to send, to the sending end device, a first frame including first indication information indicating that fault locating is performed on a first sub-link; and the processor 910 is configured to perform fault detection on a first recombination link and locate whether the fault position of the first link includes the first sub-link according to a fault detection result of the first recombination link.

[0267] Referring to FIG. 10, which is a structural schematic diagram of a chip provided by an embodiment of the present application. The chip 1000 shown in FIG. 10 includes an interface circuit 1001 and a processing circuit 1002. The interface circuit 1001 is configured to receive and / or send data, and the processing circuit 1002 is configured to perform data processing.

[0268] In one example, the chip 1000 can be applied to the above receiving end device to perform the method performed by the receiving end device provided by the above method embodiments.

[0269] In one specific example, the interface circuit 1001 is configured to determine a first recombination link to be detected, the first recombination link comprising a first sub-link, the first sub-link belonging to a first link that is faulty, the first recombination link being formed by replacing a corresponding link in a second link that is fault-free by the first sub-link, the first link, the second link and the first recombination link being links from a sending device to the receiving device, the sending device and the receiving device being in communication through fiber links; and the processing circuit 1002 is configured to perform fault detection on the first recombination link, and determine whether the fault location of the first link includes the first sub-link according to a result of the fault detection on the first recombination link.

[0270] For the specific steps performed by the interface circuit 1001 and the processing circuit 1002, reference can be made to the description of the method for performing fault location by the receiving device, which will not be repeated here.

[0271] The present application also provides a computer readable storage medium, which stores instructions or a computer program, when the instructions or the computer program are executed on a processor, any one or more operations of the method described in the foregoing embodiments can be implemented.

[0272] The present application also provides a computer program product, which comprises a computer program, when the computer program is executed on a processor, any one or more operations of the method described in the foregoing embodiments can be implemented.

[0273] The terms "first", "second", "third", "fourth" and the like in the description and claims of the present application and in the above drawings (if any) are used to distinguish between similar objects, not necessarily described in a particular order or sequence. It should be understood that the data thus used can be interchanged, where appropriate, so that the embodiments described herein can be carried out in a different order than the one illustrated or described herein. Furthermore, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, processes, methods, systems, products, or devices that comprise a list of steps or units are not necessarily limited to those clearly listed, but can include other steps or units not clearly listed or inherent to such processes, methods, products, or devices.

[0274] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0275] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the division of the above-described device embodiment is merely a logical division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between different units, can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0276] The units described as separated components can or can not be physically separated, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purposes of the embodiments of the present application.

[0277] In addition, each service unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present alone, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software service unit.

[0278] If the integrated unit is realized in the form of a software service unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the present application, the essential part or contribution to the prior art, or all or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various program code storage media.

[0279] Those skilled in the art should understand that, in one or more examples described above, the described services of the present application can be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the services can be stored in or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.

[0280] The above detailed description sets forth the purposes, technical solutions, and beneficial effects of the present application. It should be understood that the above is merely a specific implementation of the present application.

[0281] The above examples are merely used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that the technical solutions recorded in the foregoing examples can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A fault location method, characterized in that, The method includes: The receiving device determines the first reassembled link to be detected. The first reassembled link includes a first sub-link. The first sub-link is a faulty first link. The first reassembled link is a link formed by replacing the corresponding link in the faultless second link with the first sub-link. The first link, the second link, and the first reassembled link are all links from the transmitting device to the receiving device. The transmitting device and the receiving device communicate through an optical fiber link. The receiving device performs fault detection on the first reconnection link; The receiving device determines whether the fault location of the first link includes the first sub-link based on the fault detection result of the first reconnection link.

2. The method according to claim 1, characterized in that, The receiving device determines the first reassembly link to be detected, including: The receiving device sends a first frame to the sending device, the first frame including first indication information, the first indication information indicating that fault location should be performed on the first sub-link.

3. The method according to claim 2, characterized in that, The transmitting device includes a first physical layer PHY chip, the first sub-link is the link between the first PHY chip and the first mapping module, and the first mapping module is used to connect the first PHY chip and the transmitting optical module. The first indication information triggers the first mapping module to switch the first sub-link to the second sub-link in the second link. The second sub-link is the link from the first mapping module to the receiving device. The first reconnection link also includes the second sub-link.

4. The method according to claim 2, characterized in that, The first sub-link is the link from the first mapping module to the second mapping module. The first mapping module is used to connect the first PHY chip and the transmitting optical module. The second mapping module is used to connect the second PHY chip and the receiving optical module. The transmitting device includes the first PHY chip, and the receiving device includes the second PHY chip. The first indication information triggers the first mapping module to switch the third sub-link in the second link to the first sub-link, and triggers the second mapping module to switch the first sub-link to the fourth sub-link in the second link. The first reconnected link also includes the third sub-link and the fourth sub-link. The third sub-link is the link between the first PHY chip and the first mapping module, and the fourth sub-link is the link between the second mapping module and the second PHY chip.

5. The method according to claim 2, characterized in that, The first sub-link is the link between the second mapping module and the second PHY chip. The receiving device includes the second PHY chip, and the second mapping module is used to connect the second PHY chip and the receiving optical module. The first indication information triggers the second mapping module to switch the fifth sub-link of the second link to the first sub-link. The first reconnected link also includes the fifth sub-link, which is the link from the sending device to the second mapping module.

6. The method according to any one of claims 2-5, characterized in that, The first indication information is carried through the control field of the first frame.

7. The method according to claim 6, characterized in that, The first frame also includes a state field, which indicates that the receiving device has completed a first preparatory operation for fault location of the first sub-link, wherein the first preparatory operation includes: The second mapping module corresponding to the receiving device switches the first sub-link to the fourth sub-link in the second link, wherein the fourth sub-link is the link between the second mapping module and the second PHY chip included in the receiving device; or... The second mapping module switches the fifth sub-link of the second link to the first sub-link, where the fifth sub-link is the link from the sending device to the second mapping module.

8. The method according to any one of claims 1-7, characterized in that, The receiving device performs fault detection on the first reassembly link, including: The receiving device performs fault detection on the first reconnection link based on the second frame sent by the sending device to the receiving device through the first reconnection link.

9. The method according to claim 8, characterized in that, The second frame includes a pseudo-random binary sequence (PRBS), the bit error rate of which is transmitted on the first reassembly link, and is used to determine the fault detection result.

10. The method according to claim 9, characterized in that, The second frame also includes a control field, which includes second indication information indicating whether locating the fault location of the first link includes the first sub-link.

11. The method according to claim 9 or 10, characterized in that, The second frame also includes a status field, which indicates that the transmitting device has completed a second preparatory operation for fault location of the first sub-link. The second preparatory operation includes: The first mapping module corresponding to the transmitting device switches the first sub-link to the second sub-link in the second link, where the second sub-link is the link from the first mapping module to the receiving device; or... The first mapping module switches the third sub-link in the second link to the first sub-link. The third sub-link is the link between the first PHY chip and the first mapping module. The transmitting device includes the first PHY chip.

12. The method according to claim 3 or 4, characterized in that, The transmitting device is a transmitting network device, and the first mapping module is located in the transmitting network device.

13. The method according to claim 3 or 4, characterized in that, The first mapping module is located in the transmitting optical module.

14. The method according to claim 12 or 13, characterized in that, The first mapping module is used to perform a second preparation operation to determine whether the fault location of the first link includes the first sub-link, based on the channel switching command sent by the first PHY chip.

15. The method according to claim 4 or 5, characterized in that, The receiving device is a receiving network device, and the second mapping module is located in the receiving network device.

16. The method according to claim 4 or 5, characterized in that, The second mapping module is located in the optical module at the receiving end.

17. The method according to claim 15 or 16, characterized in that, The second mapping module is used to perform a first preparation operation to locate whether the fault location of the first link includes the first sub-link, based on the channel switching command sent by the second PHY chip.

18. The method according to any one of claims 2-7, characterized in that, The first mapping module includes: a first chip or a first functional circuit; and / or, The second mapping module includes: a second chip or a second functional circuit.

19. The method according to any one of claims 1-18, characterized in that, The receiving device determines whether the fault location of the first link includes the first sub-link based on the fault detection result of the first reconnection link, including: If the fault detection result indicates that the first reconnection link is faulty, then the receiving device locates the fault location of the first link including the first sub-link; or, If the fault detection result indicates that there is no fault in the first reconnection link, then the fault location of the first link located by the receiving device does not include the first sub-link.

20. A chip, characterized in that, The chip, used in a receiving device, includes: An interface circuit is used to determine the first reassembled link to be detected. The first reassembled link includes a first sub-link. The first sub-link is a faulty first link. The first reassembled link is a link formed by replacing the corresponding link in the fault-free second link with the first sub-link. The first link, the second link, and the first reassembled link are all links from the transmitting device to the receiving device. The transmitting device and the receiving device communicate through an optical fiber link. The processing circuit is used to: perform fault detection on the first reconnected link; and, based on the fault detection result of the first reconnected link, determine whether the fault location of the first link includes the first sub-link.

21. The chip according to claim 20, characterized in that, The interface circuit is used for: A first frame is sent to the transmitting device, the first frame including first indication information, the first indication information indicating that fault location is performed on the first sub-link.

22. The chip according to claim 21, characterized in that, The transmitting device includes a first physical layer PHY chip, the first sub-link is the link between the first PHY chip and the first mapping module, and the first mapping module is used to connect the first PHY chip and the transmitting optical module. The first indication information triggers the first mapping module to switch the first sub-link to the second sub-link in the second link. The second sub-link is the link from the first mapping module to the receiving device. The first reconnection link also includes the second sub-link.

23. The chip according to claim 21, characterized in that, The first sub-link is the link from the first mapping module to the second mapping module. The first mapping module is used to connect the first PHY chip and the transmitting optical module. The second mapping module is used to connect the second PHY chip and the receiving optical module. The transmitting device includes the first PHY chip, and the receiving device includes the second PHY chip. The first indication information triggers the first mapping module to switch the third sub-link in the second link to the first sub-link, and triggers the second mapping module to switch the first sub-link to the fourth sub-link in the second link. The first reconnected link also includes the third sub-link and the fourth sub-link. The third sub-link is the link between the first PHY chip and the first mapping module, and the fourth sub-link is the link between the second mapping module and the second PHY chip.

24. The chip according to claim 21, characterized in that, The first sub-link is the link between the second mapping module and the second PHY chip. The receiving device includes the second PHY chip, and the second mapping module is used to connect the second PHY chip and the receiving optical module. The first indication information triggers the second mapping module to switch the fifth sub-link of the second link to the first sub-link. The first reconnected link also includes the fifth sub-link, which is the link from the sending device to the second mapping module.

25. The chip according to any one of claims 20-24, characterized in that, The processing circuit is used for: Based on the second frame sent by the transmitting device to the receiving device through the first reconnection link, fault detection is performed on the first reconnection link.

Images