Shift register unit and control method therefor, and gate driver circuit and display device

Abstract

Provided in the present disclosure are a shift register unit and a control method therefor, and a gate driver circuit and a display device. An output circuit in the shift register unit is connected to a first high-potential power supply end and an output end, and is configured to output the potential of the first high-potential power supply end to the output end; and a first switching circuit in the shift register unit is connected to the output circuit and is also connected to a switching signal end, and is configured to control, on the basis of a switching signal provided by the switching signal end, the output circuit to turn off the output of the potential of the first high-potential power supply end. In this way, the output of an abnormal high potential can be effectively avoided.

Description

Shift register unit and its control method, gate drive circuit and display device

[0001] This disclosure claims priority to Chinese Patent Application No. 202410704183.9, filed on May 31, 2024, entitled "Shift Register Unit, Circuit Control Method, Driving Substrate and Display Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiments of this disclosure relate to the technical field of circuit control, and more particularly to a shift register unit and its control method, a gate driving circuit, and a display device. Background Technology

[0003] The shift register unit outputs an abnormal level to the pixel drive circuit, which causes the pixel to light up due to the abnormal level, forming a bright spot on the display device.

[0004] Therefore, a solution is needed to eliminate abnormal output levels of shift register units. Summary of the Invention

[0005] The purpose of this disclosure is to provide a shift register unit and its control method, gate driving circuit and display device.

[0006] For the purposes described above, this disclosure provides a shift register unit, including:

[0007] An output circuit, connected to a first high-potential power supply terminal and an output terminal, is configured to output the potential of the first high-potential power supply terminal to the output terminal;

[0008] A first switching circuit, connected to the output circuit and connected to a switching signal terminal, is configured to control the output circuit to turn off the potential output of the first high-potential power supply terminal according to the switching signal provided by the switching signal terminal.

[0009] Optionally, the output circuit is further connected to the first node, the second node and the first low-potential power supply terminal respectively, and is configured to control the connection and disconnection between the first high-potential power supply terminal and the output terminal according to the potential of the first node, and control the connection and disconnection between the first low-potential power supply terminal and the output terminal according to the potential of the second node.

[0010] The first switching circuit is also connected to the first node and is configured to control the potential of the first node according to the switching signal.

[0011] Optionally, the first switching circuit includes a first switching unit and a second switching unit;

[0012] The first switching unit is connected to the switching signal terminal, the second low-potential power supply terminal, and the third node respectively, and is configured to output the potential of the second low-potential power supply terminal to the third node according to the switching signal;

[0013] The second switching unit is connected to the first node, the third node, and the second high-potential power supply terminal, respectively, and is configured to output the potential of the second high-potential power supply terminal to the first node according to the potential of the second low-potential power supply terminal output by the first switching unit to the third node, so that the output circuit controls the first high-potential power supply terminal to disconnect from the output terminal.

[0014] Optionally, the first switching unit includes a first transistor, and the second switching unit includes a second transistor;

[0015] Wherein, the gate of the first transistor is connected to the switching signal terminal, the first electrode is connected to the second low-potential power supply terminal, and the second electrode is connected to the third node;

[0016] The gate of the second transistor is connected to the third node, the first terminal is connected to the second high-potential power supply terminal, and the second terminal is connected to the first node.

[0017] Optionally, the first switching circuit includes a first switching unit and a second switching unit;

[0018] The first switching unit is connected to the switch signal terminal, the fourth node and the first node respectively, and is configured to control the connection and disconnection between the fourth node and the first node according to the switch signal;

[0019] The second switching unit is connected to the first node, the third node, and the second high-potential power supply terminal, respectively, and is configured to control the connection and disconnection between the second high-potential power supply terminal and the first node according to the potential of the third node.

[0020] Optionally, the first switching unit includes a third transistor, and the second switching unit includes a second transistor;

[0021] The gate of the third transistor is connected to the switching signal terminal, the first terminal is connected to the fourth node, and the second terminal is connected to the first node.

[0022] The gate of the second transistor is connected to the third node, the first terminal is connected to the second high-potential power supply terminal, and the second terminal is connected to the first node.

[0023] Optionally, the output circuit includes: a fourth transistor, a fifth transistor, and a first capacitor;

[0024] The gate of the fourth transistor is connected to the first node, the first terminal is connected to the first high-potential power supply terminal, and the second terminal is connected to the output terminal.

[0025] The gate of the fifth transistor is connected to the second node, the first terminal is connected to the first low-potential power supply terminal, and the second terminal is connected to the output terminal.

[0026] One end of the first capacitor is connected to the first high-potential power supply terminal, and the other end is connected to the first node.

[0027] Optionally, it also includes:

[0028] An input circuit, connected to a first clock signal terminal, an input signal terminal, and a second node, is configured to control the connection and disconnection between the input signal terminal and the second node based on the potential of the first clock signal terminal.

[0029] Optionally, the input circuit includes a sixth transistor;

[0030] The gate of the sixth transistor is connected to the first clock signal terminal, the first terminal is connected to the input signal terminal, and the second terminal is connected to the second node.

[0031] Optionally, the input circuit further includes: a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

[0032] The seventh transistor has its gate connected to a third low-potential power supply terminal, its first terminal connected to a third node, and its second terminal connected to the second node. The second terminal of the sixth transistor is connected to the second node through the seventh transistor.

[0033] The eighth transistor has its gate connected to the first clock signal terminal, its first terminal connected to the input signal terminal, and its second terminal connected to the first terminal of the ninth transistor.

[0034] The ninth transistor has its gate connected to the fourth low-potential power supply terminal and its second terminal connected to the fifth node.

[0035] The tenth transistor has its gate and first electrode connected to the fifth node, and its second electrode connected to the second node.

[0036] Optionally, it may also include a second switching circuit and a third switching circuit;

[0037] The second switching circuit is connected to the first clock signal terminal, the second clock signal terminal, the third node, the fifth node, and the sixth node, respectively, and is configured to control the potential of the sixth node according to the potential of the first clock signal terminal and the potential of the third node, and to control the potential of the fifth node according to the potential of the sixth node.

[0038] The third switching circuit, which is connected to the sixth node, the second clock signal terminal, and the first node respectively, is configured to control the potential of the first node based on the potential of the sixth node and the potential of the second clock signal terminal.

[0039] Optionally, the second switching circuit includes:

[0040] The eleventh transistor has its gate connected to the first clock signal terminal, its first terminal connected to the fifth low-potential power supply terminal, and its second terminal connected to the sixth node.

[0041] The twelfth transistor has its gate connected to the third node, its first terminal connected to the first clock signal terminal, and its second terminal connected to the sixth node;

[0042] The thirteenth transistor has its gate connected to the fifth node, its first terminal connected to the second clock signal terminal, and its second terminal connected to the seventh node.

[0043] The fourteenth transistor has its gate connected to the sixth node, its first terminal connected to the third high-potential power supply terminal, and its second terminal connected to the seventh node.

[0044] The second capacitor is connected between the fifth node and the seventh node.

[0045] Optionally, the third switching circuit includes:

[0046] The fifteenth transistor has its gate connected to the sixth low-potential power supply terminal, its first terminal connected to the sixth node, and its second terminal connected to the eighth node.

[0047] The sixteenth transistor has its gate connected to the eighth node, its first terminal connected to the second clock signal terminal, and its second terminal connected to the fourth node.

[0048] The seventeenth transistor has its gate connected to the second clock signal terminal, its first terminal connected to the fourth node, and its second terminal connected to the first node.

[0049] The third capacitor is connected between the eighth node and the fourth node.

[0050] Optionally, the transistors included in the shift register unit are all P-type transistors.

[0051] Based on the same inventive concept, this disclosure also provides a control method for a shift register unit, the shift register unit including an output circuit and a first switching circuit, the output circuit being connected to a first high-potential power supply terminal and an output terminal, and the first switching circuit being connected to the output circuit and a switching signal terminal, the method including:

[0052] The potential of the switch signal provided by the switch signal terminal is controlled so that the first switch circuit controls the output circuit to turn off the potential output of the first high potential power supply terminal according to the switch signal.

[0053] Optionally, controlling the potential of the switch signal provided by the switch signal terminal includes: when the display device is powered on, controlling the potential of the switch signal provided by the switch signal terminal to be a low potential.

[0054] Based on the same inventive concept, this disclosure also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the control method of the shift register unit as described in any of the above claims.

[0055] Based on the same inventive concept, this disclosure also provides a gate driving circuit, which includes a plurality of cascaded shift register units as described above.

[0056] Based on the same inventive concept, this disclosure also provides a display device, which includes a plurality of pixels and a gate driving circuit as described above. The gate driving circuit is connected to the plurality of pixels and is used to transmit gate driving signals to the plurality of pixels to drive the plurality of pixels to emit light.

[0057] Optionally, each of the plurality of pixels includes a pixel circuit and a light-emitting unit, wherein the transistor in the pixel circuit for receiving the gate drive signal is an N-type transistor.

[0058] Optionally, the pixel circuit in the pixel is a low-temperature polycrystalline oxide (LTPO) pixel circuit. Attached Figure Description

[0059] To more clearly illustrate the technical solutions in this disclosure or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0060] Figure 1 is a circuit diagram of the pixel driving circuit according to an embodiment of the present disclosure;

[0061] Figure 2 is a first timing diagram of the shift register unit according to an embodiment of the present disclosure;

[0062] Figure 3 is a second timing diagram of the shift register unit according to an embodiment of the present disclosure;

[0063] Figure 4 is a first circuit diagram of the shift register unit according to an embodiment of the present disclosure;

[0064] Figure 5 is a second circuit diagram of the shift register unit according to an embodiment of this disclosure;

[0065] Figure 6 is a third circuit diagram of the shift register unit according to an embodiment of this disclosure;

[0066] Figure 7 is a fourth circuit diagram of the shift register unit according to an embodiment of this disclosure;

[0067] Figure 8 is a fifth circuit diagram of the shift register unit according to an embodiment of this disclosure;

[0068] Figure 9 is a third timing diagram of the shift register unit according to an embodiment of this disclosure;

[0069] Figure 10 is a sixth circuit diagram of the shift register unit according to an embodiment of this disclosure;

[0070] Figure 11 is a seventh circuit diagram of the shift register unit according to an embodiment of this disclosure;

[0071] Figure 12 is a first flowchart of the control method of the shift register unit according to an embodiment of the present disclosure;

[0072] Figure 13 is a second flowchart of the control method of the shift register unit according to an embodiment of the present disclosure;

[0073] Figure 14 is a circuit diagram of the gate driving circuit according to an embodiment of the present disclosure;

[0074] Figure 15 is a schematic diagram of the structure of a display device according to an embodiment of the present disclosure. Detailed Implementation

[0075] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0076] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0077] As described in the background section, the relevant shift register units are still difficult to meet the needs of actual circuit driving.

[0078] In the process of implementing this disclosure, the applicant discovered that the main problem with the relevant shift register unit is that, for other shift register units, when the connected high-potential power supply terminal and low-potential power supply terminal are powered on, an abnormal potential will be output in the first frame. After being output from the shift register unit, this abnormal potential will be written to the pixel driving circuit, thus causing a flashing point during display.

[0079] For example, in the pixel driving circuit shown in Figure 1, the high potential output by the shift register unit is written to the gate of Tx (N-type field-effect transistor x). When the gate of Tx is shorted to the Nx node, the high potential of the Tx gate is written to the Nx node. After the potential of the Nx node is pulled high, as shown in Figure 1, the high potential is applied to the anode of the light-emitting unit through Tm (field-effect transistor m), thereby causing the display device to have a bright spot. Here, the light-emitting unit is a light-emitting diode (LED) or an organic light-emitting diode (OLED).

[0080] As shown in the timing diagrams in Figures 2 and 3, it can be seen that after the shift register unit is powered on, i.e., after time t1, when the high and low potentials of the two clock signal terminals CK and CB begin to alternate, the output voltage of the shift register unit's output terminal OUT becomes abnormally high. Furthermore, as can be seen from Figures 2 and 3, regardless of whether the timing of the two clock signal terminals CK and CB is set to the high potential shown in Figure 2 or the no-pulse signal shown in Figure 3 (i.e., floating potential), the output terminal OUT will always become abnormally high when the high and low potentials of the two clock signal terminals begin to alternate (i.e., at time t3 as shown in Figures 1 and 2).

[0081] Based on this, embodiments of this disclosure provide a shift register unit that, based on control of the output circuit, enables the output circuit to promptly shut off the potential output of the high-potential power supply terminal. Embodiments of this disclosure are described in detail below with reference to the accompanying drawings.

[0082] Referring to FIG4, a shift register unit 1 according to an embodiment of the present disclosure includes:

[0083] The output circuit 101 is connected to the first high-potential power supply terminal VGH1 and the output terminal OUT, and is configured to output the potential of the first high-potential power supply terminal VGH1 to the output terminal OUT.

[0084] The first switching circuit 102 is connected to the output circuit 101 and to the switching signal terminal CX. It is configured to control the output circuit 101 to turn off the potential output of the first high potential power supply terminal VGH1 according to the switching signal provided by the switching signal terminal CX.

[0085] In this embodiment, as shown in FIG4, the output circuit 101 is connected to the first high-potential power supply terminal VGH1. After the high-potential power supply terminal (including the first high-potential power supply terminal VGH1) of the shift register unit 1 is powered on, the output circuit 101 can output the potential (i.e., high potential) of the first high-potential power supply terminal VGH1. The potential VGH1 of the first high-potential power supply terminal may be output when not needed, thus becoming an abnormally high potential, and written to the pixel driving circuit shown in FIG1, thereby lighting up the pixel.

[0086] In this embodiment of the present disclosure, the first switching circuit 102 can be turned on when the switching signal at the connected switching signal terminal CX is at a low potential. After the first switching circuit 102 is turned on, the output of the output circuit 101 can be controlled. Specifically, when the output circuit 101 outputs the potential of the first high potential power supply terminal VGH1, the potential output of the first high potential power supply terminal VGH1 is turned off.

[0087] It can be seen that by turning off the potential output of the first high-potential power supply terminal VGH1, the pixels of the pixel driving circuit can be prevented from being lit by abnormally high potentials, that is, the flashing points of the display device are avoided.

[0088] Optionally, referring back to Figure 4, the output circuit 101 is also connected to the first node N1, the second node N2, and the first low-potential power supply terminal VGL1. Furthermore, the output circuit 101 is configured to control the switching between the first high-potential power supply terminal VGH1 and the output terminal OUT based on the potential of the first node N1, and to control the switching between the first low-potential power supply terminal VGL1 and the output terminal OUT based on the potential of the second node N2.

[0089] For example, when the potential of the first node N1 is low, the output circuit 101 can connect the first high-potential power supply terminal VGH1 to the output terminal OUT; when the potential of the first node N1 is high, the output circuit 101 can disconnect the first high-potential power supply terminal VGH1 from the output terminal OUT. When the potential of the second node N2 is low, the output circuit 101 can connect the first low-potential power supply terminal VGL1 to the output terminal OUT; when the potential of the second node N2 is high, the output circuit 101 can disconnect the first low-potential power supply terminal VGL1 from the output terminal OUT.

[0090] As shown in Figure 4, the first switching circuit 102 is also connected to the first node N1 and is configured to control the potential of the first node N1 according to the switching signal of the switching signal terminal CX. For example, the first switching circuit 102 can control the potential of the first node N1 to be high according to the switching signal, so that the output circuit 101 turns off the first high-potential power supply terminal VGH1 and the output terminal OUT, that is, turns off the potential output of the first high-potential power supply terminal VGH1.

[0091] As a first optional implementation of the first switching circuit 102, as shown in Figure 5, the first switching circuit 102 includes a first switching unit 1021 and a second switching unit 1022. The first switching unit 1021 is connected to the switching signal terminal CX, the second low-potential power supply terminal VGL2, and the third node N3, and is configured to output the potential of the second low-potential power supply terminal VGL2 to the third node N3 according to the switching signal provided by the switching signal terminal CX.

[0092] For example, when the switching signal provided by the switching signal terminal CX is at a low potential, the first switching unit 1021 can connect the second low-potential power supply terminal VGL2 to the third node N3, thereby making the potential of the third node N3 low. When the switching signal provided by the switching signal terminal CX is at a high potential, the first switching unit 1021 can disconnect the second low-potential power supply terminal VGL2 from the third node N3.

[0093] The second switching unit 1022 is connected to the first node N1, the third node N3, and the second high-potential power supply terminal VGH2. The second switching unit 1022 is configured to output the potential of the second high-potential power supply terminal VGH2 to the first node N1 based on the potential of the second low-potential power supply terminal VGL2 output to the third node N3 by the first switching unit 1021, so that the output circuit 101 controls the first high-potential power supply terminal VGH1 to disconnect from the output terminal OUT.

[0094] As mentioned earlier, when the switching signal provided by the switching signal terminal CX is at a low potential, the first switching unit 1021 can connect the second low-potential power supply terminal VGL2 to the third node N3, thereby making the potential of the third node N3 low. Correspondingly, the second switching unit 1022 can connect the second high-potential power supply terminal VGH2 to the first node N1 based on the low potential of the third node N3, thereby making the potential of the first node N1 the high potential output by the second high-potential power supply terminal VGH2. That is, it can keep the first node N1 at a high potential, thereby causing the output circuit 101 to control the first high-potential power supply terminal VGH1 to disconnect from the output terminal OUT.

[0095] Optionally, as shown in FIG6, in this first implementation, the first switching unit 1021 includes a first transistor T1, and the second switching unit 1022 includes a second transistor T2.

[0096] In this configuration, the gate of the first transistor T1 is connected to the switch signal terminal CX, its first electrode is connected to the second low-potential power supply terminal VGL2, and its second electrode is connected to the third node N3. When the switch signal provided by the switch signal terminal CX is high, the first transistor T1 is turned off, thereby turning off the second low-potential power supply terminal VGL2 and the third node N3. When the switch signal provided by the switch signal terminal CX is low, the first transistor T1 is turned on, thereby turning on the second low-potential power supply terminal VGL2 and the third node N3.

[0097] The gate of the second transistor T2 is connected to the third node N3, its first terminal is connected to the second high-potential power supply terminal VGH2, and its second terminal is connected to the first node N1. When the third node N3 is at a high potential, the second transistor T2 is turned off, thereby turning off the second high-potential power supply terminal VGH2 and the first node N1. When the third node N3 is at a low potential, the second transistor T2 is turned on, thereby turning on the second high-potential power supply terminal VGH2 and the first node N1.

[0098] It is understood that in the embodiments of this disclosure, one of the first and second terminals of the transistor is the source, and the other is the drain. For example, the first terminal can be the drain, and the second terminal can be the source. Alternatively, the first terminal can be the source, and the second terminal can be the drain.

[0099] As a second optional implementation of the first switching circuit 102, as shown in Figure 7, the first switching circuit 102 includes a first switching unit 1021 and a second switching unit 1022.

[0100] The first switch unit 1021 is connected to the switch signal terminal CX, the fourth node N4 and the first node N1 respectively, and is configured to control the on / off state of the fourth node N4 and the first node N1 according to the switch signal provided by the switch signal terminal CX.

[0101] For example, when the switching signal provided at the switching signal terminal CX is at a low potential, the first switching unit 1021 can turn on the fourth node N4 and the first node N1. When the switching signal provided at the switching signal terminal CX is at a high potential, the first switching unit 1021 can turn off the fourth node N4 and the first node N1.

[0102] The second switching unit 1022 is connected to the first node N1, the third node N3, and the second high-potential power supply terminal VGH2, respectively, and is configured to control the connection and disconnection between the second high-potential power supply terminal VGH2 and the first node N1 according to the potential of the third node N3.

[0103] For example, when the third node N3 is at a low potential, the second switching unit 1022 can connect the second high-potential power supply terminal VGH2 to the first node N1. When the third node N3 is at a high potential, the second switching unit 1022 can disconnect the second high-potential power supply terminal VGH2 from the first node N1.

[0104] In this second implementation, as shown in Figure 8, the first switching unit 1021 includes a third transistor T3, and the second switching unit 1022 includes a second transistor T2.

[0105] In this transistor, the gate of the third transistor T3 is connected to the switch signal terminal CX, the first terminal is connected to the fourth node N4, and the second terminal is connected to the first node N1. The third transistor T3 can be turned off when the switch signal provided by the switch signal terminal CX is high, and turned on when the switch signal provided by the switch signal terminal CX is low.

[0106] The gate of the second transistor T2 is connected to the third node N3, the first terminal is connected to the second high-potential power supply terminal VGH2, and the second terminal is connected to the first node N1. The second transistor T2 is turned off when the third node N3 is at a high potential and turned on when the third node N3 is at a low potential.

[0107] Optionally, continuing to refer to Figures 6 and 8, the output circuit 101 includes: a fourth transistor T4, a fifth transistor T5, and a first capacitor C1.

[0108] In this transistor, the gate of the fourth transistor T4 is connected to the first node N1, the first terminal is connected to the first high-potential power supply terminal VGH1, and the second terminal is connected to the output terminal OUT. The fourth transistor T4 can be turned on when the first node N1 is at a low potential, thereby outputting the potential of the first high-potential power supply terminal VGH1 to the output terminal OUT. The fourth transistor T4 can be turned off when the first node N1 is at a high potential, thereby turning off the potential output of the first high-potential power supply terminal VGH1.

[0109] The gate of the fifth transistor T5 is connected to the second node N2, its first terminal is connected to the first low-potential power supply terminal VGL1, and its second terminal is connected to the output terminal OUT. The fifth transistor T5 can be turned on when the second node N2 is at a low potential, thereby outputting the potential of the first low-potential power supply terminal VGL1 to the output terminal OUT. The fifth transistor T5 can be turned off when the second node N2 is at a high potential, thereby turning off the potential output of the first low-potential power supply terminal VGL1.

[0110] One end of the first capacitor C1 is connected to the first high-potential power supply terminal VGH1, and the other end is connected to the first node N1.

[0111] It is understandable that, based on the circuit structure of the output circuit 101 and the first switching circuit 102 shown in Figure 6, the first transistor T1 turns on when the switching signal is at a low potential, thereby controlling the third node N3 to be at a low potential. The second transistor T2 can then turn on under the control of this low potential. After the second transistor T2 turns on, it writes the high potential of the connected second high-potential power supply terminal VGH2 to the first node N1. The fourth transistor T4 turns off based on the high potential of the second high-potential power supply terminal VGH2 written to the first node N1, thereby shutting off the output of the first high-potential power supply terminal VGH1 to the output terminal OUT. Consequently, the output terminal OUT does not output the potential of the first high-potential power supply terminal VGH1.

[0112] Simultaneously, one end of the first capacitor C1 is connected to the first high-potential power supply terminal VGH1, and by discharging to the first node N1, the high potential of the first high-potential power supply terminal VGH1 is applied to the first node N1. This ensures that the potential of the first node N1 is maintained at a high potential.

[0113] Optionally, if the second transistor T2 is turned off based on the high potential power supply terminal written by the third node N3, then after the second transistor T2 is turned off, the high potential of the second high potential power supply terminal VGH2 cannot be written to the first node N1. Simultaneously, if the potential of the first node N1 is pulled low, the fourth transistor T4 is turned on based on the low potential of the low potential power supply terminal written by the first node N1, causing the potential of the first high potential power supply terminal VGH1 to be written to the output terminal OUT, i.e., the output terminal OUT outputs the potential of the first high potential power supply terminal VGH1 (i.e., an abnormally high potential).

[0114] Optionally, if the fifth transistor T5 is turned on based on the low potential of the low-potential power supply terminal written by the second node N2, then after the fifth transistor T5 is turned on, the potential of the first low-potential power supply terminal VGL1 is written to the output terminal OUT, and thus the output terminal OUT outputs the potential of the first low-potential power supply terminal VGL1. If the fifth transistor T5 is turned off based on the high potential of the high-potential power supply terminal written by the second node N2, then after the fifth transistor T5 is turned off, the potential of the first low-potential power supply terminal VGL1 cannot be written to the output terminal OUT, thus the output terminal OUT cannot output the potential of the first low-potential power supply terminal VGL1.

[0115] As can be seen, the output circuit 101 is connected to the first low-potential power supply terminal VGL1 and the first high-potential power supply terminal VGH1, and controls the output of the first low-potential power supply terminal VGL1 and the first high-potential power supply terminal VGH1 through the fourth transistor T4 and the fifth transistor T5, respectively.

[0116] Optionally, as shown in Figures 4 to 8, the shift register unit provided in this embodiment further includes an input circuit 103. The input circuit 103 is connected to a first clock signal terminal CK, an input signal terminal STV, and a second node N2, and is configured to control the on / off state of the input signal terminal STV and the second node N2 according to the potential of the first clock signal terminal CK.

[0117] The input signal terminal STV is also called the turn-on signal terminal. Furthermore, when the potential of the first clock signal terminal CK is low, the input circuit 103 can turn on the input signal terminal STV and the second node N2. When the potential of the first clock signal terminal CK is high, the input circuit 103 can turn off the input signal terminal STV and the second node N2.

[0118] Optionally, as shown in Figures 6 and 8, the input circuit 103 includes a sixth transistor T6. The gate of the sixth transistor T6 is connected to the first clock signal terminal CK, the first terminal is connected to the input signal terminal STV, and the second terminal is connected to the second node N2.

[0119] When the potential of the first clock signal terminal CK is low, the sixth transistor T6 is turned on, thereby connecting the input signal terminal STV to the second node N2. When the potential of the first clock signal terminal CK is high, the sixth transistor T6 is turned off, thereby turning off the input signal terminal STV to the second node N2.

[0120] Optionally, continuing to refer to Figures 6 and 8, the input circuit 103 further includes: a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10.

[0121] In this configuration, the gate of the seventh transistor T7 is connected to the third low-potential power supply terminal VGL3, its first terminal is connected to the third node N3, and its second terminal is connected to the second node N2. Furthermore, the second terminal of the sixth transistor T6 is connected to the second node N2 via the seventh transistor T7. This seventh transistor T7 can remain in a conducting state under the control of the low potential provided by the third low-potential power supply terminal VGL3. As can be seen from Solid State 6 and Figure 8, the second terminal of the sixth transistor T6 is connected to the third node N3 and then connected to the second node N2 via the normally-on seventh transistor T7.

[0122] The eighth transistor T8 has its gate connected to the first clock signal terminal CK, its first terminal connected to the input signal terminal STV, and its second terminal connected to the first terminal of the ninth transistor T9. When the potential of the first clock signal terminal CK is low, the eighth transistor T8 is turned on; when the potential of the first clock signal terminal CK is high, the eighth transistor T8 is turned off.

[0123] The ninth transistor T9 has its gate connected to the fourth low-potential power supply terminal VGL4, and its terminal connected to the fifth node N5. This ninth transistor T9 can remain in a conducting state under the control of the low potential provided by the fourth low-potential power supply terminal VGL4. The terminal of the eighth transistor T8 can then be connected to the fifth node N5 through the normally-on ninth transistor T9.

[0124] The tenth transistor, T10, has its gate and first terminal connected to the fifth node N5, and its second terminal connected to the second node N2. When the fifth node N5 is at a low potential, the tenth transistor T10 is turned on, thereby pulling the potential of the second node N2 low. When the fifth node N5 is at a high potential, the tenth transistor T10 is turned off.

[0125] It is understandable that the gate drive circuit of a display device includes multiple cascaded shift register units. Shift register unit 1 shown in Figure 6 is any one of these multiple cascaded shift register units, and is not the first shift register unit. For shift register unit 1, when powered on according to the timing diagram shown in Figure 9, at time t1, the potential of the input signal terminal STV changes from no signal (i.e., floating state) to a low level (also called low potential). However, since the shift register units are cascaded, the potential of the input signal terminal STV needs to be sequentially passed from the first shift register unit to the last shift register unit. Therefore, at the instant the input signal terminal STV is powered on and connected to the first shift register, only the first shift register unit can obtain a low-level input signal at this moment; other shift register units cannot receive a low-level input signal at time t1. Furthermore, the low-level input signal requires one frame to be transmitted to the last shift register unit. Therefore, at time t1, for shift register unit 1 that is not the first, the input signal terminal STV can be considered to be in a no-signal state, i.e., a floating state. Meanwhile, the high or low level of the clock signal can be simultaneously connected to each shift register unit.

[0126] As can be seen from Figures 6 and 8, even if the sixth transistor T6 is turned on by the low-potential first clock signal terminal CK during this frame, the input signal terminal STV does not have a low-potential input signal written to the third node N3 during the transmission of this frame.

[0127] According to the timing diagram shown in Figure 9, the switch signal terminal CX is at a low potential at power-on time t1, and remains at a low potential from time t1-t2 and time t3. Therefore, for the shift register unit shown in Figure 6, the first transistor T1 in the first switch circuit 102 can remain on during time t1-t3, writing the potential of the second low-potential power supply terminal VGL2 to the third node N3, and then writing it to the gate of the second transistor T2 through the third node N3. Based on this, the second transistor T2 can remain on during time t1-t3, continuously writing the potential of the second high-potential power supply terminal VGH2 to the first node N1. Thus, the potential of the output terminal OUT connected to the output circuit 101 can be controlled.

[0128] Specifically, the potential of the second high-potential power supply terminal VGH2 written by the first node N1 can keep the fourth transistor T4 in the output circuit 101 off during the time t1-t3, thereby turning off the output of the first high-potential power supply terminal VGH1, so that the output terminal OUT does not output an abnormally high potential during the time t1-t3, that is, it does not output the potential of the first high-potential power supply terminal VGH1.

[0129] Optionally, since the third node N3 maintains the potential of the second low-potential power supply terminal VGL2 during the time interval t1-t3, the input circuit 103 can also write the potential of the second low-potential power supply terminal VGL2 at the third node N3 to the second node N2. This enables the fifth transistor T5 to turn on, allowing the potential of the first low-potential power supply terminal VGL1 connected to the first electrode of the fifth transistor T5 to be output to the output terminal OUT.

[0130] It can be seen that when the first transistor T1 in the first switching circuit 102 is turned on by the switching signal provided by the switching signal terminal CX, it can use the second low-potential power supply terminal VGL2 to control the output circuit 101 to output a low potential and turn off the high-potential output.

[0131] Optionally, according to the timing diagram shown in Figure 9, from time t1 to t3, the potential of the third low-potential power supply VGL3 remains low. Based on this, the seventh transistor T7 remains on during time t1 to t3, thereby continuously writing the potential of the second low-potential power supply VGL2 written by the third node N3 to the second node N2, and then writing it to the gate of the fifth transistor T5 in the output circuit 101 through the second node N2. Correspondingly, during time t1 to t3, the fifth transistor T5 can remain on and continuously write the potential of the first low-potential power supply terminal VGL1 connected to the first terminal of the fifth transistor T5 to the output terminal OUT. That is, the output terminal OUT continuously outputs the potential of the first low-potential power supply terminal VGL1, thus obtaining the timing diagram shown in Figure 9, where the output terminal OUT remains low during time t1 to t3.

[0132] Understandably, according to the timing diagram shown in Figure 9, the fourth low-potential power supply terminal VGL4 remains at a low potential during times t1-t3, the first clock signal terminal CK remains at a high potential during times t1-t3, and the first clock signal terminal CK begins to alternate between high and low potentials at time t3. Based on this, the ninth transistor T9 remains on during times t1-t3; while the eighth transistor T8 is on when the first clock signal terminal CK is at a low potential and off when the first clock signal terminal CK is at a high potential.

[0133] During times t1-t2, the sixth transistor T6 and the eighth transistor T8 in the input circuit 103 remain off. Starting at time t3, they alternate between high and low potentials, following the first clock signal CK. Therefore, during times t1-t2, because the sixth transistor T6 and the eighth transistor T8 are off, the potential at node N5, after passing through the ninth transistor T9, cannot pass through the sixth transistor T6 and the eighth transistor T8, and thus cannot be written to node N3. Starting at time t3, the ninth transistor T9 remains on. When the sixth transistor T6 and the eighth transistor T8 are on, the potential at node N5 can pass through the ninth transistor T9, and then through the on-screen sixth transistor T6 and the eighth transistor T8 to be written to node N3.

[0134] It can be seen that by setting the eighth transistor T8 and the ninth transistor T9, the potential of the third node N3 can be controlled by the first clock signal terminal CK.

[0135] Optionally, as shown in Figures 7, 8 and 10, the shift register unit provided in the embodiments of this disclosure further includes a second switching circuit 104 and a third switching circuit 105.

[0136] The second switching circuit 104 is connected to the first clock signal terminal CK, the second clock signal terminal CB, the third node N3, the fifth node N5 and the sixth node N6 respectively. It is configured to control the potential of the sixth node N6 according to the potential of the first clock signal terminal CK and the potential of the third node N3, and to control the potential of the fifth node N5 according to the potential of the sixth node N6.

[0137] For example, when the first clock signal terminal CK is at a low potential, the second switching circuit 104 can pull down the potential of the sixth node N6 to the low potential of the low-potential power supply terminal. When the third node N3 is at a low potential, the second switching circuit 104 can write the potential of the first clock signal terminal CK to the sixth node N6. When the sixth node N6 is at a low potential, the second switching circuit 104 can control the potential of the fifth node N5 to be at a high potential.

[0138] The third switching circuit 105 is connected to the sixth node N6, the second clock signal terminal CB, and the first node N1, respectively, and is configured to control the potential of the first node N1 according to the potential of the sixth node N6 and the potential of the second clock signal terminal CB.

[0139] For example, when the sixth node N6 is at a low potential and the second clock signal terminal CB is at a low potential, the second switching circuit 104 can write the potential of the second clock signal terminal CB into the first node N1.

[0140] Optionally, as shown in Figures 8 and 11, the second switching circuit 104 includes:

[0141] The eleventh transistor T11 has its gate connected to the first clock signal terminal CK, its first terminal connected to the fifth low-potential power supply terminal VGL5, and its second terminal connected to the sixth node N6. The eleventh transistor T11 is turned on when the first clock signal terminal CK is at a low potential, writing the potential of the fifth low-potential power supply terminal VGL5 to the sixth node N6; the eleventh transistor T11 is turned off when the first clock signal terminal CK is at a high potential.

[0142] The twelfth transistor T12 has its gate connected to the third node N3, its first terminal connected to the first clock signal terminal CK, and its second terminal connected to the sixth node N6. The twelfth transistor T12 is turned on when the third node N3 is at a low potential, writing the potential of the first clock signal terminal CK to the sixth node N6; the twelfth transistor T12 is turned off when the third node N3 is at a high potential.

[0143] The thirteenth transistor T13 has its gate connected to the fifth node N5, its first terminal connected to the second clock signal terminal CB, and its second terminal connected to the seventh node N7. The thirteenth transistor T13 is turned on when the fifth node N5 is at a low potential, writing the potential of the second clock signal terminal CB to the seventh node N7; the thirteenth transistor T13 is turned off when the fifth node N5 is at a high potential.

[0144] The fourteenth transistor T14 has its gate connected to the sixth node N6, its first terminal connected to the third high-potential power supply terminal VGH3, and its second terminal connected to the seventh node N7. The fourteenth transistor T14 is turned on when the sixth node N6 is at a low potential, writing the potential of the third high-potential power supply terminal VGH3 to the seventh node N7; the fourteenth transistor T14 is turned off when the sixth node N6 is at a high potential.

[0145] The second capacitor C2 is connected between the fifth node N5 and the seventh node N7.

[0146] Optionally, as shown in Figures 8 and 11, the third switching circuit 105 includes:

[0147] The fifteenth transistor T15 has its gate connected to the sixth low-potential power supply terminal VGL6, its first terminal connected to the sixth node N6, and its second terminal connected to the eighth node N8. The fifteenth transistor T15 can remain on under the control of the low potential provided by the sixth low-potential power supply terminal VGL6, and will turn on the sixth node N6 and the eighth node N8.

[0148] The sixteenth transistor T16 has its gate connected to the eighth node N8, its first terminal connected to the second clock signal terminal CB, and its second terminal connected to the fourth node N4. The sixteenth transistor T16 is turned on when the eighth node N8 is at a low potential, writing the potential of the second clock signal terminal CB to the fourth node N4; the sixteenth transistor T16 is turned off when the eighth node N8 is at a high potential.

[0149] The seventeenth transistor T17 has its gate connected to the second clock signal terminal CB, its first terminal connected to the fourth node N4, and its second terminal connected to the first node N1. It can be understood that, in the implementation shown in Figure 8, the first terminal of the seventeenth transistor T17 is connected to the fourth node N4 through the third transistor T3. This seventeenth transistor T17 can conduct when the second clock signal terminal CB is at a low potential, thus connecting the fourth node N4 and the first node N1; the seventeenth transistor T17 is turned off when the second clock signal terminal CB is at a high potential.

[0150] The third capacitor C3 is connected between the eighth node N8 and the fourth node N4.

[0151] In this embodiment of the disclosure, according to the timing diagram shown in FIG9, the third high-potential power supply terminal VGH3 remains at a high potential from time t1 to t3. If the second switching circuit 103 writes a high potential to the third high-potential power supply terminal VGH3 to the fifth node N5, then the tenth transistor T10 is turned off. According to the timing diagram shown in FIG9, the third high-potential power supply terminal VGH3 remains at a high potential from time t1 to t3; therefore, the tenth transistor T10 remains turned off during time t1 to t3.

[0152] Optionally, as mentioned above, starting from time t3, when the first clock signal terminal CK is at a low potential, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are all turned on. The potential of the third high-potential power supply terminal VGH3 written at the fifth node N5 will be written to the third node N3 through the turned-on sixth transistor T6, eighth transistor T8, and ninth transistor T9. When the first clock signal terminal CK is at a high potential, the sixth transistor T4 and the eighth transistor T8 are turned off, and the potential of the third high-potential power supply terminal VGH3 written at the fifth node N5 cannot be written to the third node N3.

[0153] Based on the above analysis, when the input circuit 104 contains not only the tenth transistor T10 but also the seventh transistor T7, and the seventh transistor T7 remains on during times t1-t3 due to the low-potential third low-potential power supply terminal VGL3, then when the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are all on, the potential of the third high-potential power supply terminal VGH3, written from the fifth node N5 to the third node N3, can be written to the second node N2 through the on-state seventh transistor T7. This applies a high potential to the gate of the fifth transistor T5, causing the fifth transistor T5 to turn off. Consequently, the potential of the first low-potential power supply terminal VGL1 connected to the first electrode of the fifth transistor T5 cannot be transmitted to the output terminal OUT.

[0154] It can be seen that by setting the tenth transistor T10, when the fifth node N5 is at a high potential, the second node N2 is not written through the tenth transistor T10, thereby realizing the reset of the third node N3 and the second node N2 by using the sixth transistor T6 and the eighth transistor T8.

[0155] Optionally, according to the timing diagram shown in Figure 9, the first transistor T1 and the seventh transistor T7 remain on during times t1-t3. When the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are all on, the potential of the third high-potential power supply terminal VGH3 at the fifth node N5 is written to the third node N3 through T9, T8, and T6. Simultaneously, the low potential of the second low-potential power supply terminal VGL2 connected to the first electrode of the first transistor T1 is continuously written to the third node N3. Therefore, the potential of the third high-potential power supply terminal VGH3 at the third node N3 can be continuously pulled down to the potential of the second low-potential power supply terminal VGL2. Thus, a low potential can be applied to the gate of the fifth transistor T5, keeping the fifth transistor T5 on, thereby allowing the potential of the first potential power supply terminal VGL1 connected to the first electrode of the fifth transistor T5 to be transferred to the output terminal OUT.

[0156] As can be seen, based on the configured first transistor T1, seventh transistor T7, and tenth transistor T10, the potential of the second low-potential power supply terminal VGL2 output by the first transistor T1 causes the output of the first high-potential power supply terminal VGH1 in the output circuit 101 to be controlled to turn off. Furthermore, the second low-potential power supply terminal VGL2 output by the seventh transistor T7 causes the fifth transistor T5 to turn on, and the potential of the first high-potential power supply terminal VGL1 is output, thereby controlling the output circuit 101 to prevent abnormally high-potential output.

[0157] In this embodiment of the present disclosure, in the timing diagram shown in FIG9, at times t1-t2, both the first clock signal terminal CK and the second clock signal terminal CB are at high potentials, the low-potential power supply terminal VGL is at a low potential, and the high-potential power supply terminal VGH is at a high potential. Starting from time t3, both the first clock signal terminal CK and the second clock signal terminal CB begin to alternate between high and low potentials, and the high and low potentials of the first clock signal terminal CK and the second clock signal terminal CB are opposite. Accordingly, in the second switching circuit 104 and the third switching circuit 105 shown in FIG11, at times t1-t2, the transistors that remain off include: the eleventh transistor T11, the thirteenth transistor T13, the fourteenth transistor T14, the sixteenth transistor T16, and the seventeenth transistor T17, and the transistors that remain on include: the fifteenth transistor T15 and the twelfth transistor T12.

[0158] Understandably, during time t1-t2, the seventh node N7 is written with a high potential and applied to the second capacitor C2. This pulls the potential of the fifth node N5 high through the second capacitor C2, turning off the tenth transistor T10. Since the third node N3 is at a low potential, the twelfth transistor T12 is turned on, and the high potential of the first clock signal terminal CK is written to the sixth node, thus turning off the fourteenth transistor T14 and the sixteenth transistor T16. Simultaneously, the second node N2 is pulled low to a low potential due to the second low-potential power supply terminal VGL2 output by the seventh transistor T7, thereby turning on the fifth transistor T5 and outputting the potential of the first low-potential power supply terminal VGL1 to the output terminal OUT.

[0159] Optionally, at time t1-t2, since the seventeenth transistor T17 is turned off, the high potential at the first node N1 will not be released to the fourth node N4 through the seventeenth transistor T17.

[0160] Optionally, starting from time t3, when the first clock signal terminal CK is high, the second clock signal terminal CB is low, and the seventeenth transistor T17 turns on. This allows the high potential at the first node N1 to be output to the sixteenth transistor T16 through the seventeenth transistor T17 and the fourth node N4. The sixteenth transistor T16 is kept on by the third capacitor C3. Since the second clock signal terminal CB is low at this time, the sixteenth transistor T16 releases the high potential at the fourth node N4. When the second transistor T2 turns off, the high potential at the first node N1 is gradually pulled down to a low potential, thereby turning on the fourth transistor T4, so that the potential of the first high-potential power supply terminal VGH1 is output from the output terminal OUT.

[0161] In the timing diagram shown in Figure 9, since the first transistor T1 remains on throughout the time intervals t1-t3, VGL2 at the second low-potential power supply terminal can be continuously written to the gate of the second transistor T2. In other words, the second transistor T2 remains on, preventing the potential of the first node N1 from being pulled low by the sixteenth transistor T16 and the seventeenth transistor T17, and keeping it at a high potential. This, in turn, keeps the fourth transistor T4 off, preventing the output terminal OUT from outputting a high potential.

[0162] As can be seen, by configuring the first transistor T1, when the second clock signal terminal CB is at a low potential, and the high potential of the first node N1 is released through the sixteenth transistor T16 and the seventeenth transistor T17, the first transistor T1 can continuously write the potential of the second low-potential power supply terminal VGL2 to the gate of the second transistor T2. This allows the second transistor T2 to remain in the conducting state, thereby enabling the second high-potential power supply terminal VGH2 to maintain the high potential of the first node N1, and consequently causing the output circuit 101 to turn off the output of the potential of the first high-potential power supply terminal VGH1.

[0163] In this embodiment, when the second capacitor C2 pulls the potential of the fifth node N5 high, during the t1-t2 phase, since both the sixth transistor T6 and the eighth transistor T8 are turned off, the high potential written to the fifth node N5 cannot be written to the third node N3 and the second node N2. Therefore, the third node N3 and the second node N2 can be kept at low potentials. Furthermore, the fifth transistor T5 can be turned on, allowing the output terminal OUT to output the potential of the first low-potential power supply terminal VGL1 without outputting a high potential, thus realizing the timing diagram shown in Figure 9.

[0164] In this embodiment of the present disclosure, as described above, in the timing diagram shown in FIG9, at times t1-t2, both the first clock signal terminal CK and the second clock signal terminal CB are at high potentials, the low-potential power supply terminal VGL is at a low potential, and the high-potential power supply terminal VGH is at a high potential. Starting from time t3, both the first clock signal terminal CK and the second clock signal terminal CB begin to alternate between high and low potentials, and the high and low potentials of the first clock signal terminal CK and the second clock signal terminal CB are opposite. Accordingly, in the second switching circuit 104 and the third switching circuit 105 shown in FIG8, at times t1-t2, the transistors that remain off include: the eleventh transistor T11, the thirteenth transistor T13, the fourteenth transistor T14, the sixteenth transistor T16, and the seventeenth transistor T17, and the transistors that remain on include: the fifteenth transistor T15 and the twelfth transistor T12.

[0165] Understandably, during time t1-t2, the seventh node N7 is written with a high potential and applied to the second capacitor C2. This pulls the potential of the fifth node N5 high through the second capacitor C2, turning off the tenth transistor T10. During the t1-t2 phase, since both the sixth transistor T6 and the eighth transistor T8 are off, the high potential of the fifth node N5 cannot be written to the third node N3 and the second node N2. This keeps the third node N3 and the second node N2 at low power supply levels, thus turning on the second transistor T2 and the fifth transistor T5. The turning on of the second transistor T2 applies the potential of the second high-potential power supply terminal VGH2 to the gate of the fourth transistor T4, thereby turning off the output from the first high-potential power supply terminal VGH1 to the output terminal OUT. Simultaneously, since the seventeenth transistor T17 is turned off during t1-t2, the high potential at the first node N1 will not be released to the fourth node N4 through the seventeenth transistor T17 and the first switching circuit 102 (e.g., the third transistor T3), thus ensuring that the first node N1 is at a high potential during t1-t2.

[0166] Optionally, turning on the fifth transistor T5 causes the first low-potential power supply terminal VGL1 to be applied to the output terminal OUT, thereby maintaining the output terminal OUT at a low potential during the time interval t1-t2.

[0167] Optionally, starting from time t3, when the first clock signal terminal CK is at a high potential, the second clock signal terminal CB is at a low potential, and the sixteenth transistor T16 and the seventeenth transistor T17 are turned on, so that the high potential at the first node N1 is output to the first switching unit 1021 in the first switching circuit 102 through the seventeenth transistor T17.

[0168] Optionally, the first switching unit 1021 in the first switching circuit 102 connects the seventeenth transistor T17 and the fourth node N4. The high potential at the first node N1 is transferred to the fourth node N4. The sixteenth transistor T16 is kept on by the third capacitor C3. Since the second clock signal terminal CB is at a low potential at this time, the sixteenth transistor T16 can release the high potential at the fourth node N4. When the second transistor T2 is off and the first switching unit 1021 connects the fourth node N4 and the seventeenth transistor T17, the high potential of the first node N1 will be gradually pulled down to a low potential, thereby turning on the fourth transistor T4, so that the potential of the first high potential power supply terminal VGH1 is output from the output terminal OUT.

[0169] Optionally, if the second transistor T2 is turned off and the first switching unit 1021 disconnects the connection between the fourth node N4 and the seventeenth transistor T17, the high potential of the first node N1 will not be released and will remain at a high potential. This keeps the fourth transistor T4 off, so that the output terminal OUT does not output a high potential.

[0170] For example, when the switch signal terminal CX is at a high potential, the third transistor T3 is turned off, and when the switch signal terminal CX is at a low potential, the third transistor T3 is turned on.

[0171] Specifically, when the third transistor T3 is turned on, the seventeenth transistor T17 inputs the high potential at the first node N1 to the third transistor T3, and through the third transistor T3, outputs the high potential to the fourth node N4. When the second clock signal terminal CB is at a low potential, the high potential at the first node N1 is gradually released to a low potential, thereby turning on the fourth transistor T4, so that the potential of the first high potential power supply terminal VGH1 is output from the output terminal OUT.

[0172] Optionally, when the third transistor T3 is turned off, the high potential at the first node N1 connected to the third transistor T3 cannot be released through the third transistor T3, so that the high potential of the first node N1 will not be released and will remain at a high potential. Therefore, the fourth transistor T4 can be kept off, so that the output terminal OUT does not output the potential of the first high-potential power supply terminal VGH1.

[0173] As can be seen, by setting the third transistor T3, when the third node N3 is written with a high potential, causing the second transistor T2 to turn off and preventing the continuous writing of a high potential to the first node N1, the third transistor T3 can be turned off through the switching signal terminal CX. This ensures that the high potential of the first node N1 is not released through the third transistor T3, thus maintaining the high potential of the first node N1 and preventing the output circuit 102 from outputting the high potential of the first high-potential power supply terminal VGH1.

[0174] Optionally, the transistors included in the shift register unit provided in the embodiments of this disclosure are all P-type transistors.

[0175] It is understood that in this embodiment, the potentials of the various high-potential power supply terminals (such as VGH1, VGH2, and VGH3) can be different high potentials or the same high potential; that is, the various high-potential power supply terminals can be the same power supply terminal. In this embodiment, for ease of description, the high-potential power supply terminals connected to different components are distinguished. Similarly, the potentials of the various low-potential power supply terminals (such as VGL1, VGL2, VGL3, VGL4, VGL5, and VGL6) can be different low potentials or the same low potential; that is, the various low-potential power supply terminals can be the same power supply terminal. In this embodiment, for ease of description, the low-potential power supply terminals connected to different components are distinguished.

[0176] It should be noted that, as mentioned earlier, a high potential appearing in the first frame upon power-on will abnormally illuminate pixels that should not be lit. Therefore, the high potential output by shift register unit 1 in the first frame is an abnormally high potential. Then, after the first frame, the input signal of the input signal terminal STV can be transmitted to the last shift register unit 1. At this time, each pixel can be lit normally, so shift register unit 1 can output a high potential normally, thereby normally illuminating the pixels of the pixel driving circuit. Specifically, the normal high potential output of shift register unit 1 can be achieved by controlling the potential of the switch signal terminal CX.

[0177] For ease of description, the above apparatus is described in terms of its functions, divided into various modules. Of course, in implementing the embodiments of this disclosure, the functions of each module can be implemented in one or more software and / or hardware.

[0178] Based on the same inventive concept, and corresponding to the circuits of any of the above embodiments, embodiments of this disclosure also provide a control method for a shift register unit.

[0179] Referring to Figure 12, a circuit control method according to an embodiment of this disclosure is applied to the shift register unit 1 of the aforementioned embodiment, and specifically includes the following steps:

[0180] Step S1201: Control the potential of the switch signal provided by the switch signal terminal so that the first switch circuit controls the output circuit to turn off the potential output of the first high potential power supply terminal according to the switch signal.

[0181] Optionally, S1201 includes: when the display device is powered on, controlling the switch signal provided at the switch signal terminal to have a low potential. For example, for the shift register unit shown in FIG11, the switch signal potential can be controlled to be low when powered on. This enables the first transistor T1 and the second transistor T2 to be turned on, so that the second high-potential power supply terminal VGH2 can maintain a high potential at the first node N1, thereby causing the fourth transistor T4 in the output circuit 101 to turn off the output of the first high-potential power supply terminal VGH1.

[0182] For the shift register unit shown in Figure 8, S1201 includes: when the display device is powered on, the potential of the switch signal provided at the control switch signal terminal is high. This allows the third transistor T3 to be turned off, preventing the high potential of the first node N1 from being released.

[0183] Referring to FIG13, a circuit control method according to another embodiment of the present disclosure is applied to the shift register unit 1 of the foregoing embodiment, and specifically includes the following steps:

[0184] Step S1301: Connect the output circuit to the first high-potential power supply terminal.

[0185] Step S1302: Connect the first switching circuit to the output circuit and connect the switching signal terminal. Use the switching signal of the switching signal terminal to control the output circuit to turn off the potential output of the first high potential power supply terminal.

[0186] As can be seen, in the control method of the shift register unit of the present disclosure, the first switching circuit keeps it on or off based on the received switching signal, thereby controlling the output circuit to turn off the output of the first high-potential power supply terminal, preventing the potential of the first high-potential power supply terminal from being output to the output terminal, thereby preventing the pixel driving circuit from being abnormally lit due to the high potential.

[0187] It should be noted that the methods of the embodiments of this disclosure can be executed by a single device, such as a computer or server. The methods of this embodiment can also be applied to distributed scenarios, where multiple devices cooperate to complete the process. In such a distributed scenario, one of these devices may execute only one or more steps of the methods of the embodiments of this disclosure, and the multiple devices will interact with each other to complete the method described.

[0188] It should be noted that the above description describes some embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0189] The methods described above are applied to implement the corresponding shift register units in any of the foregoing embodiments and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0190] Based on the same inventive concept, corresponding to the shift register unit of any of the above embodiments, this disclosure also provides a gate driving circuit, also referred to as a driving substrate. Furthermore, as shown in FIG14, this gate driving circuit includes at least two cascaded shift register units 1 as described in any of the above embodiments. The gate driving circuit is an array substrate gate driver (GOA) circuit.

[0191] Based on the same inventive concept, corresponding to the gate driving circuit of the above embodiments, this disclosure also provides a display device, as shown in FIG15. The display device includes the gate driving circuit 10 provided in the above embodiments and a plurality of pixels 20.

[0192] The gate driving circuit 10 is connected to the plurality of pixels 20 and is used to transmit gate driving signals to the plurality of pixels 20 to drive the plurality of pixels 20 to emit light.

[0193] Optionally, the structure of each of the plurality of pixels 20 can be referred to in FIG1, and each pixel 20 includes a pixel circuit (also called a pixel driving circuit) and a light-emitting unit. The transistor (also called a driving transistor, such as transistor Tx in FIG1) used to receive the gate driving signal in the pixel circuit is an N-type transistor.

[0194] Optionally, the pixel circuit in pixel 20 is a low-temperature polycrystalline oxide (LTPO) pixel circuit. The LTPO pixel circuit includes low-temperature poly-silicon (LTPS) transistors and metal-oxide (Oxide) transistors.

[0195] Alternatively, the light-emitting unit in the pixel 20 can be an LED or an OLED.

[0196] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure (including the claims) is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of the different aspects of the embodiments of this disclosure as described above, which are not provided in detail for the sake of brevity.

[0197] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this disclosure, the well-known power / ground connections to the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this disclosure, and this also takes into account the fact that the details of implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this disclosure will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this disclosure, it will be apparent to those skilled in the art that the embodiments of this disclosure may be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0198] Although this disclosure has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0199] The embodiments disclosed herein are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A shift register unit, comprising: An output circuit, connected to a first high-potential power supply terminal and an output terminal, is configured to output the potential of the first high-potential power supply terminal to the output terminal; A first switching circuit, connected to the output circuit and connected to a switching signal terminal, is configured to control the output circuit to turn off the potential output of the first high-potential power supply terminal according to the switching signal provided by the switching signal terminal.

2. The shift register unit according to claim 1, wherein, The output circuit is also connected to the first node, the second node and the first low-potential power supply terminal respectively, and is configured to control the connection and disconnection between the first high-potential power supply terminal and the output terminal according to the potential of the first node, and to control the connection and disconnection between the first low-potential power supply terminal and the output terminal according to the potential of the second node. The first switching circuit is also connected to the first node and is configured to control the potential of the first node according to the switching signal.

3. The shift register unit according to claim 2, wherein, The first switching circuit includes a first switching unit and a second switching unit; The first switching unit is connected to the switching signal terminal, the second low-potential power supply terminal, and the third node respectively, and is configured to output the potential of the second low-potential power supply terminal to the third node according to the switching signal; The second switching unit is connected to the first node, the third node, and the second high-potential power supply terminal, respectively, and is configured to output the potential of the second high-potential power supply terminal to the first node according to the potential of the second low-potential power supply terminal output by the first switching unit to the third node, so that the output circuit controls the first high-potential power supply terminal to disconnect from the output terminal.

4. The shift register unit according to claim 3, wherein, The first switching unit includes a first transistor, and the second switching unit includes a second transistor; Wherein, the gate of the first transistor is connected to the switching signal terminal, the first electrode is connected to the second low-potential power supply terminal, and the second electrode is connected to the third node; The gate of the second transistor is connected to the third node, the first terminal is connected to the second high-potential power supply terminal, and the second terminal is connected to the first node.

5. The shift register unit according to claim 2, wherein, The first switching circuit includes a first switching unit and a second switching unit; The first switching unit is connected to the switch signal terminal, the fourth node and the first node respectively, and is configured to control the connection and disconnection between the fourth node and the first node according to the switch signal; The second switching unit is connected to the first node, the third node, and the second high-potential power supply terminal, respectively, and is configured to control the connection and disconnection between the second high-potential power supply terminal and the first node according to the potential of the third node.

6. The shift register unit according to claim 5, wherein, The first switching unit includes a third transistor, and the second switching unit includes a second transistor; The gate of the third transistor is connected to the switch signal terminal, the first terminal is connected to the fourth node, and the second terminal is connected to the first node. The gate of the second transistor is connected to the third node, the first terminal is connected to the second high-potential power supply terminal, and the second terminal is connected to the first node.

7. The shift register unit according to any one of claims 1 to 6, characterized in that, The output circuit includes: a fourth transistor, a fifth transistor, and a first capacitor; The gate of the fourth transistor is connected to the first node, the first terminal is connected to the first high-potential power supply terminal, and the second terminal is connected to the output terminal. The gate of the fifth transistor is connected to the second node, the first terminal is connected to the first low-potential power supply terminal, and the second terminal is connected to the output terminal. One end of the first capacitor is connected to the first high-potential power supply terminal, and the other end is connected to the first node.

8. The shift register unit according to any one of claims 1 to 7, wherein, Also includes: An input circuit, connected to a first clock signal terminal, an input signal terminal, and a second node, is configured to control the connection and disconnection between the input signal terminal and the second node based on the potential of the first clock signal terminal.

9. The shift register unit according to claim 8, wherein, The input circuit includes a sixth transistor; The gate of the sixth transistor is connected to the first clock signal terminal, the first terminal is connected to the input signal terminal, and the second terminal is connected to the second node.

10. The shift register unit according to claim 9, wherein, The input circuit also includes: a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; The seventh transistor has its gate connected to a third low-potential power supply terminal, its first terminal connected to a third node, and its second terminal connected to the second node. The second terminal of the sixth transistor is connected to the second node through the seventh transistor. The eighth transistor has its gate connected to the first clock signal terminal, its first terminal connected to the input signal terminal, and its second terminal connected to the first terminal of the ninth transistor. The ninth transistor has its gate connected to the fourth low-potential power supply terminal and its second terminal connected to the fifth node. The tenth transistor has its gate and first electrode connected to the fifth node, and its second electrode connected to the second node.

11. The shift register unit according to any one of claims 1 to 10, wherein, It also includes a second switching circuit and a third switching circuit; The second switching circuit is connected to the first clock signal terminal, the second clock signal terminal, the third node, the fifth node, and the sixth node, respectively, and is configured to control the potential of the sixth node according to the potential of the first clock signal terminal and the potential of the third node, and to control the potential of the fifth node according to the potential of the sixth node. The third switching circuit, which is connected to the sixth node, the second clock signal terminal, and the first node respectively, is configured to control the potential of the first node based on the potential of the sixth node and the potential of the second clock signal terminal.

12. The shift register unit according to claim 11, wherein, The second switching circuit includes: The eleventh transistor has its gate connected to the first clock signal terminal, its first terminal connected to the fifth low-potential power supply terminal, and its second terminal connected to the sixth node. The twelfth transistor has its gate connected to the third node, its first terminal connected to the first clock signal terminal, and its second terminal connected to the sixth node; The thirteenth transistor has its gate connected to the fifth node, its first terminal connected to the second clock signal terminal, and its second terminal connected to the seventh node. The fourteenth transistor has its gate connected to the sixth node, its first terminal connected to the third high-potential power supply terminal, and its second terminal connected to the seventh node. The second capacitor is connected between the fifth node and the seventh node.

13. The shift register unit according to claim 11 or 12, wherein, The third switching circuit includes: The fifteenth transistor has its gate connected to the sixth low-potential power supply terminal, its first terminal connected to the sixth node, and its second terminal connected to the eighth node. The sixteenth transistor has its gate connected to the eighth node, its first terminal connected to the second clock signal terminal, and its second terminal connected to the fourth node. The seventeenth transistor has its gate connected to the second clock signal terminal, its first terminal connected to the fourth node, and its second terminal connected to the first node. The third capacitor is connected between the eighth node and the fourth node.

14. The shift register unit according to any one of claims 1 to 13, wherein, The transistors included in the shift register unit are all P-type transistors.

15. A control method for a shift register unit, wherein, The shift register unit includes an output circuit and a first switching circuit. The output circuit is connected to a first high-potential power supply terminal and an output terminal. The first switching circuit is connected to the output circuit and a switching signal terminal. The method includes: The potential of the switch signal provided by the switch signal terminal is controlled so that the first switch circuit controls the output circuit to turn off the potential output of the first high potential power supply terminal according to the switch signal.

16. The method according to claim 15, wherein, The potential of the switch signal provided by the control switch signal terminal includes: When the display device is powered on, the potential of the switch signal provided by the control switch signal terminal is low.

17. A gate driving circuit, wherein, The gate drive circuit includes a plurality of cascaded shift register units as described in any one of claims 1-15.

18. A display device, wherein, It includes multiple pixels and the gate driving circuit as described in claim 17; The gate driving circuit is connected to the plurality of pixels and is used to transmit gate driving signals to the plurality of pixels to drive the plurality of pixels to emit light.

19. The display device according to claim 18, wherein, Each of the plurality of pixels includes a pixel circuit and a light-emitting unit, wherein the transistor in the pixel circuit for receiving the gate drive signal is an N-type transistor.

20. The display device according to claim 18 or 19, wherein, The pixel circuit in the pixel is a low-temperature polycrystalline silicon oxide semiconductor (LTPO) pixel circuit.

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