Display panel, display device, and manufacturing method

Abstract

A display panel, a display device, and a manufacturing method. The display panel comprises a hole area (NA) and a display area (AA); the display area (AA) comprises a pixel light-emitting area (Pix) located on at least one side of the hole area (NA); a display module comprises a substrate (10), a plurality of wiring layers (20) insulated from each other, a pixel defining layer (30), an encapsulation layer (40), and a shielding layer (50) which are sequentially stacked, wherein first through holes (31) are formed in the pixel defining layer (30) in the hole area (NA), and orthographic projections of the first through holes (31) on the substrate (10) are first hole projections; a combined projection of orthographic projections of the plurality of wiring layers (20) located in the display area (AA) on the substrate (10) surrounds the first hole projections; the plurality of wiring layers (20) include a first wiring layer (21) and a second wiring layer (22); the first wiring layer (21) is closer to the substrate (10) than the second wiring layer (22); and in a first direction, the central position of the first wiring layer (21) close to the first through holes (31) is disconnected, both ends of the second wiring layer (22) are separately electrically connected to the disconnected first wiring layer (21), and a first distance between the first wiring layer (21) and the first hole projections is less than a second distance between the second wiring layer (22) and the first hole projections.

Description

Display panel, display device and manufacturing method

[0001] The present application claims priority to the Chinese patent application No. 202410692365.9, filed on May 30, 2024, and entitled "A display panel, a display device and a manufacturing method", the contents of which are to be understood as incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present application relate to, but are not limited to, the technical field of display, and in particular to a display panel, a display device and a manufacturing method. BACKGROUND

[0003] With the development of COE (color film on encapsulation, i.e. forming a color film directly on an encapsulation layer) technology, for display panels with sensing function, customers not only have the demand for the transmittance of the sensor hole, but also have the strong demand for the field of view (FOV) at the position of the sensor hole. For the increasingly complex display driving circuit, the design space left for the sensor hole is not large, therefore, under the influence of the increasingly narrow circuit trace design, how to effectively improve the field of view and ensure the transmittance of the sensor hole becomes a problem to be solved. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present application provide a display panel, a display device and a manufacturing method.

[0006] In a first aspect, the embodiments of the present application provide a display panel, the display panel comprising a hole area and a display area surrounding at least part of the hole area, the display area comprising a pixel light-emitting area located on at least one side of the hole area, wherein the display panel comprises a substrate, a plurality of mutually insulated trace layers, a pixel defining layer, an encapsulation layer and a shielding layer which are sequentially stacked,

[0007] The pixel defining layer is provided with a first through hole in the hole area, and the shielding layer is provided with a second through hole at a position corresponding to the first through hole in the hole area, and the first through hole is a first hole projection in the orthographic projection of the substrate;

[0008] The plurality of trace layers located in the display area surround the first hole projection in the combination projection of the orthographic projection of the substrate,

[0009] The plurality of trace layers comprise a first trace layer and a second trace layer which both extend along a first direction, and the first trace layer is closer to the substrate than the second trace layer,

[0010] In the first direction, the first trace layer is disconnected at a position close to the center of the first via, and the two ends of the second trace layer are electrically connected to the disconnected first trace layer,

[0011] The minimum distance between the projection boundary of the substrate orthographic projection and the projection boundary of the first hole projection in the second direction is a first distance, and the minimum distance between the projection boundary of the substrate orthographic projection and the projection boundary of the first hole projection in the second direction is a second distance. The first distance is less than the second distance.

[0012] In an optional embodiment, in the stacking direction, the first trace layer and the second trace layer are two non-adjacent conductive layers,

[0013] The display panel further comprises at least one third trace layer and a plurality of insulating layers between the first trace layer and the second trace layer, and the plurality of insulating layers are used to insulate the first trace layer, the at least one third trace layer and the second trace layer respectively,

[0014] The first trace layer and the second trace layer are electrically connected through a first connection hole penetrating the plurality of insulating layers.

[0015] In an optional embodiment, the first trace layer is arranged in the same layer as a first gate layer of the display panel, the third trace layer is arranged in the same layer as a second gate layer located on the side of the first gate layer away from the substrate, and the second trace layer is arranged in the same layer as a first source-drain electrode layer located on the side of the second gate layer away from the substrate.

[0016] In an optional embodiment, on both sides of the opposite two first boundaries of the first hole projection, the disconnected first trace layer and the second trace layer are arranged,

[0017] The center axis of the first hole projection extending in the first direction is a first symmetry axis, and the disconnected first trace layer and the second trace layer on one side of each first boundary are symmetrically projected on the orthographic projection of the substrate with the first symmetry axis as the axis of symmetry.

[0018] In an optional embodiment, the first hole projection comprises a first boundary extending in the first direction and a second boundary extending in the second direction, and the first boundary comprises at least a straight boundary extending in the first direction,

[0019] The distance between the projection boundary of the substrate orthographic projection and the straight boundary of the first boundary is a first distance, and the distance between the projection boundary of the substrate orthographic projection and the straight boundary of the first boundary is a first distance.

[0020] In an optional embodiment, the second trace layer comprises: a first end portion and a second end portion electrically connected to the first end portion and the second end portion of the first trace layer which are disconnected, respectively, and a first connecting portion between the first end portion and the second end portion,

[0021] wherein the first end portion forms an overlap with one disconnected edge of the first trace layer in the orthographic projection of the substrate, and the second end portion forms an overlap with another disconnected edge of the first trace layer in the orthographic projection of the substrate,

[0022] an extension length of the first connecting portion in the orthographic projection of the substrate in the first direction is greater than or equal to an extension length of the straight boundary of the first boundary.

[0023] In an optional embodiment, the plurality of trace layers further comprises a fourth trace layer and a fifth trace layer insulated from the fourth insulating layer, the fourth trace layer is closer to the substrate than the fifth trace layer,

[0024] the fifth trace layer comprises:

[0025] a third end portion electrically connected to the fourth trace layer through a second connecting hole, the third end portion covers the orthographic projection of the fourth trace layer in the orthographic projection of the substrate; and

[0026] a second connecting portion extending in the second direction,

[0027] a minimum distance between the third end portion and a second boundary of the first hole projection extending in the second direction is a third distance, a minimum distance between the second connecting portion and the second boundary of the first hole projection extending in the second direction is a fourth distance, and the third distance is less than the fourth distance.

[0028] In an optional embodiment, in the stacking direction, the fourth trace layer and the fifth trace layer are two adjacent conductive layers,

[0029] The display panel further comprises: an insulating layer between the fourth trace layer and the fifth trace layer, and the fourth trace layer and the fifth trace layer are electrically connected through a second connecting hole penetrating the insulating layer.

[0030] In an optional embodiment, on both sides of the opposite two second boundaries of the first hole projection, the fourth trace layer and the fifth trace layer are arranged,

[0031] with a central axis of the first hole projection extending in the second direction as a second symmetry axis, the orthographic projection of the fourth trace layer and the fifth trace layer on one side of each of the second boundaries is symmetrically projected with the second symmetry axis as the second symmetry axis.

[0032] In an optional embodiment, the second boundary comprises at least a straight boundary extending along the first direction,

[0033] The combined projection of the third end portion and the second connecting portion along the second direction has a length greater than the length of the straight boundary of the second boundary.

[0034] In an optional embodiment, the width of the first connecting portion along the second direction is less than the width of the first end portion along the second direction.

[0035] In an optional embodiment, the distance between the first trace layer, the fourth trace layer, the second trace layer and the substrate gradually increases along the stacking direction, the fourth trace layer and the third trace layer are arranged in the same layer, and the second trace layer and the fifth trace layer are arranged in the same layer.

[0036] In an optional embodiment, the distance between the first trace layer, the fourth trace layer, the at least one third trace layer, and the second trace layer gradually increases along the stacking direction, one of the at least one third trace layer close to the substrate is arranged in the same layer as the fourth trace layer, and one of the at least one third trace layer is arranged in the same layer as the fifth trace layer.

[0037] In an optional embodiment, the plurality of trace layers further comprises at least one sixth trace layer, the sixth trace layer is the trace layer in the plurality of trace layers farthest from the substrate along the stacking direction,

[0038] The first trace layer, the second trace layer, the fourth trace layer, the fifth trace layer, and the sixth trace layer constitute a display driving circuit.

[0039] Or

[0040] The first trace layer, the second trace layer, the third trace layer, the fourth trace layer, the fifth trace layer, and the sixth trace layer constitute a display driving circuit.

[0041] In an optional embodiment, the display driving circuit is an 8T1C display driving circuit.

[0042] In an optional embodiment, a central axis extending along the second direction is taken as a cross section of the first hole projection, and the minimum boundary distance L between the side wall close to the first hole projection of each trace layer and the first boundary of the first hole projection satisfies the following formula:

[0043] H_1 is an interlayer thickness between a surface of each routing layer close to the substrate and a surface of the shielding layer close to the substrate;

[0044] a is a cross-sectional hole diameter of the second via under the cross section;

[0045] d is a sidewall distance between a sidewall of the first via and a sidewall of the second via;

[0046] c is an interlayer thickness between a surface of the pixel defining layer away from the substrate and a surface of the shielding layer close to the substrate;

[0047] e is a thickness of the pixel defining layer.

[0048] In an optional embodiment, the display area includes a first display area and a second display area surrounding the first display area,

[0049] The first display area includes a pixel light-emitting area and a non-pixel light-emitting area located at a periphery of the pixel light-emitting area,

[0050] The pixel light-emitting area is provided with individual sub-pixels defined by a pixel defining layer,

[0051] The non-pixel light-emitting area is provided with at least one hole area, and the hole area is arranged in a gap between individual sub-pixels.

[0052] In a second aspect, the embodiments of the present application provide a display device, including the display panel as described above.

[0053] In an optional embodiment, the display device further includes a sensing member arranged at a position corresponding to the hole area, and located away from the plurality of routing layers on a side of the substrate of the display panel.

[0054] In a third aspect, the embodiments of the present application provide a manufacturing method of the display panel as described above, and the method includes:

[0055] forming a plurality of mutually insulated routing layers on the substrate corresponding to the display area in sequence;

[0056] forming a pixel defining layer on the routing layers of the display area and the insulating layer of the hole area covering the routing layers;

[0057] etching the pixel defining layer at the hole area to form a first via, and a projection of the first via on the substrate is a first hole projection;

[0058] forming a packaging layer and a shielding layer on the pixel defining layer in sequence;

[0059] etching the shielding layer at a position corresponding to the first via to form a second via;

[0060] The method further includes forming multiple mutually insulating wiring layers sequentially on the substrate corresponding to the display area, and further comprising:

[0061] A first trace layer extending in a first direction is formed on a substrate corresponding to the display area, wherein the first trace layer is interrupted near the center of the first via in the first direction;

[0062] A second trace layer is formed on the first trace layer and extends along a first direction, which is insulated from the first trace layer. The two ends of the second trace layer are electrically disconnected from the first trace layer. The minimum distance between the projection boundary of the first trace layer on the substrate and the projection boundary of the first hole in the second direction is a first distance. The minimum distance between the projection boundary of the second trace layer on the substrate and the projection boundary of the first hole in the second direction is a second distance. The first distance is less than the second distance.

[0063] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0064] Overview of the attached figures

[0065] Figure 1 shows the wiring design around the hole area in the display panel of the related technology;

[0066] Figure 2 shows a schematic diagram of the layer structure when each routing layer is in the same layer under the routing structure shown in Figure 1.

[0067] Figure 3 shows the wiring design of the display panel on both sides of the first through hole according to an embodiment of this application;

[0068] Figure 4 shows a schematic diagram of the layered structure at the cross-sectional location in Figure 3;

[0069] Figure 5 shows a schematic diagram of the field of view under the wiring design shown in Figures 3 and 4;

[0070] Figure 6 shows another wiring design for the display panel on both sides of the first through hole according to an embodiment of this application;

[0071] Figure 7 shows a schematic diagram of the layered structure at the cross-sectional location in Figure 6;

[0072] Figure 8 shows a schematic diagram of the field of view under the wiring design shown in Figures 6 and 7;

[0073] Figure 9 illustrates the wiring design around the hole area in a display panel of another related technology;

[0074] Figure 10 illustrates another display panel wiring design on both sides of the first through hole according to an embodiment of this application;

[0075] Figure 11 shows a schematic diagram of the layered structure at the cross-sectional location in Figure 10;

[0076] Figure 12 illustrates the wiring design of the combined embodiment shown in Figures 3 and 10 of this application;

[0077] Figure 13 shows a schematic diagram of the layered structure at the cross-sectional location in Figure 11;

[0078] Figure 14 illustrates the wiring design of the combined embodiment shown in Figures 6 and 10 of this application;

[0079] Figure 15 shows a schematic diagram of the layered structure at the cross-sectional location in Figure 14;

[0080] Figure 16 shows a schematic diagram of the boundary distance between each routing layer and the sidewall of the first via;

[0081] Figure 17 shows a schematic diagram of the location of the hole region in one embodiment of this application;

[0082] Figure 18 shows a schematic diagram of the positions of multiple sub-pixels in the aperture area and pixel light-emitting area of ​​the embodiment of this application in Figure 17.

[0083] Detailed Explanation

[0084] To more clearly illustrate this application, the following description, in conjunction with embodiments and accompanying drawings, further clarifies the application. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of this application.

[0085] Figure 1 shows the wiring design of the display area near the hole area of ​​the display panel in the related art. Figure 2 shows a schematic diagram of the layer structure with the vertical axis shown in Figure 1 as the cross section. As shown in Figure 1, each wiring layer 20 is routed around the hole area NA. The metal wiring space of each wiring layer 20 around the hole area is further compressed. At this time, the field of view (FOV) of the sensor hole is mainly affected by the opening of the uppermost shielding layer 50 of the display panel and the spacing of the lowermost wiring layer 20 of the display panel. In view of this, the present application proposes a display panel, a display panel and a manufacturing method to solve the above problems.

[0086] This application provides a display panel, as shown in Figures 3 to 16. The display panel includes an aperture region NA and a display region AA surrounding at least a portion of the aperture region NA. The display region AA includes a pixel light-emitting region Pix located on at least one side of the aperture region NA. The display panel includes a substrate 10, a plurality of mutually insulated wiring layers 20, a pixel defining layer 30, an encapsulation layer 40, and a shielding layer 50, which are sequentially stacked.

[0087] The pixel defining layer 30 forms a first through hole 31 in the hole region NA, and the shielding layer 50 forms a second through hole 51 in the hole region NA at the position corresponding to the first through hole 31. The orthographic projection of the first through hole 31 onto the substrate 10 is the first hole projection.

[0088] The combined projection of the orthographic projection of the plurality of wiring layers 20 located in the display area AA onto the substrate 10 surrounds the projection of the first aperture.

[0089] The plurality of wiring layers 20 include a first wiring layer 21 and a second wiring layer 22, both extending along a first direction, wherein the first wiring layer 21 is closer to the substrate 10 than the second wiring layer 22.

[0090] In the first direction, the first trace layer 21 is disconnected near the center of the first via 31, and the two ends of the second trace layer 22 are electrically connected to the disconnected first trace layer 21.

[0091] The minimum distance between the projection boundary of the first wiring layer 21 on the substrate 10 and the projection boundary of the first hole in the second direction is the first distance D1. The minimum distance between the projection boundary of the second wiring layer 22 on the substrate 10 and the projection boundary of the first hole in the second direction is the second distance D2. The first distance D1 is less than the second distance D2.

[0092] In this embodiment, the traces extending along the first direction on the upper and lower sides of the first through hole 31 are designed to cross-connect, and the distance between the traces extending along the first direction and the first through hole 31 is calculated. Near the center of the first through hole 31, the second distance D2 between the second trace layer 22 located above the first through hole 31 in the layer structure is set to be larger than the first distance D1 between the first trace layer 21 and the first through hole 31, so as to achieve the effect of increasing the field of view.

[0093] As shown in Figure 1, the first hole projection in this embodiment is a square projection with rounded corners. In another example, the first hole projection may also be a square projection without rounded corners. For example, the first hole projection may also be a circular projection. That is, the shape of the first hole projection in this embodiment is designed according to the actual application.

[0094] In an optional embodiment, the first aperture projection includes a first boundary extending along a first direction and a second boundary extending along a second direction. The first boundary includes at least a straight line boundary extending along the first direction, and the second boundary includes at least a straight line boundary extending along the second direction. That is, the first aperture projection in this embodiment is a square projection with rounded corners as shown in FIG1. ​​This design can increase the aperture ratio of the first aperture projection, thereby improving the display effect of the display panel.

[0095] In this embodiment, the projection of the first hole shown in Figure 1 is used as an example. The minimum distance between the projection boundary of the first wiring layer on the substrate and the straight line boundary of the first boundary is the first distance, and the minimum distance between the projection boundary of the second wiring layer on the substrate and the straight line boundary of the first boundary is the second distance.

[0096] When the first hole projection is a circular projection, the first distance is the minimum distance between the projection boundary of the first wiring layer on the substrate and a certain arc-shaped position in the circular projection, and the second distance is the minimum distance between the projection boundaries of the second wiring layer on the substrate at that arc-shaped position. The wiring layout of the display panel described in the embodiments of this application will now be described using different examples.

[0097] In an optional embodiment, as shown in Figures 3 to 5, the first trace layer 21 and the second trace layer 22 are two non-adjacent conductive layers in the stacking direction.

[0098] The display panel further includes at least one third wiring layer 23 and a plurality of insulating layers located between the first wiring layer 21 and the second wiring layer 22, wherein the plurality of insulating layers are used to insulate the first wiring layer 21, the at least one third wiring layer 23 and the second wiring layer 22 respectively.

[0099] The first wiring layer 21 and the second wiring layer 22 are electrically connected through a first connection hole 201 that penetrates the plurality of insulating layers.

[0100] In other words, the routing layers serving as the first routing layer 21 and the second routing layer 22 in this embodiment of the application may have different positional relationships. This setting improves the application range under different driving circuits. The first routing layer 21 and the second routing layer 22 are electrically connected through the first connection hole 201, which can ensure the signal transmission effect under the original circuit structure.

[0101] In an optional embodiment, as shown in Figures 3 to 5, Figure 4 is a schematic diagram of the layer structure at the BB position of section 3 in Figure 3, and the cross-sectional view in Figure 5 is a combined cross-sectional view of all the layer structures appearing at the BB and CC positions of section 3 from the same perspective. That is, the schematic diagram of the layer structure shown in Figure 5 cannot be obtained using a single cross-sectional line. For example, the second sixth routing layer 262, the first sixth routing layer 261 (not shown in Figure 3), and the third routing layer 23, represented by the dashed lines in Figure 5, can be seen at the CC position of section 3 in Figure 3, while the first routing layer 21 and the second routing layer 22 in Figure 5 can be seen at the BB position of section 3 in Figure 3. Therefore, Figure 5 is only an exemplary illustration used to show the positions of multiple routing layers in the stacking direction.

[0102] As shown in Figures 3 to 5, if there is one third wiring layer 23, then the plurality of third wiring layers 23 in the stacking direction are sequentially the first wiring layer 21, the third wiring layer 23, and the second wiring layer 22. In an optional embodiment, the plurality of wiring layers 20 further includes at least one sixth wiring layer 26, which is the wiring layer with the largest distance from the substrate 10 in the stacking direction among the plurality of wiring layers 20. For example, as shown in Figures 3 and 4, the number of sixth wiring layers 26 is two.

[0103] In one embodiment, the first wiring layer 21 is disposed on the same layer as the first gate layer of the display panel, the third wiring layer 23 is disposed on the same layer as the second gate layer located on the side of the first gate layer away from the substrate 10, and the second wiring layer 22 is disposed on the same layer as the first source / drain electrode layer located on the side of the second gate layer away from the substrate 10. That is, when forming the layer structure of the thin-film driving transistor of the driving circuit, each wiring layer 20 is formed around the hole region NA using the same process, thereby improving the process manufacturing efficiency.

[0104] In an exemplary embodiment, as shown in FIG4, a first gate insulating layer 61 with a thickness of p is disposed on the substrate 10, a first wiring layer 21 with a thickness of o is disposed on the first gate insulating layer 61, a second gate insulating layer 62 with a thickness of n is disposed on the first wiring layer 21, a third wiring layer 23 with a thickness of m is disposed on the second gate insulating layer 62, an interlayer dielectric layer 63 with a thickness of l is disposed on the third wiring layer 23, a second wiring layer 22 with a thickness of k is disposed on the interlayer dielectric layer 63, and a first planarization layer 64 with a thickness of j is disposed on the second wiring layer 22.

[0105] In an optional embodiment, the field of view (FOV) at the central axis (section BB) extending along the second direction from the projection of the first aperture is taken as the section, and the field of view (FOV) at the section satisfies the following formula:

[0106] Wherein, H1 is the interlayer thickness between the surface of the second wiring layer 22 near the substrate 10 and the surface of the shielding layer 50 near the substrate 10; a is the cross-sectional diameter of the second via 51 in the cross-section; and d is the sidewall distance between one side wall of the first via 31 and one side wall of the second via 51.

[0107] In an exemplary embodiment, as shown in Figures 3 and 4, between the surface of the second wiring layer 22 near the substrate 10 and the surface of the shielding layer 50 near the substrate 10, a first planarization layer 64 of thickness j, a first sixth wiring layer 261 of thickness i, a second planarization layer 65 of thickness h covering the first sixth wiring layer 261, a second sixth wiring layer 262 of thickness g, a third planarization layer 66 of thickness f covering the second sixth wiring layer 262, a pixel defining layer of thickness e located on the third planarization layer 66, and an encapsulation layer of thickness c covering the pixel defining layer.

[0108] Based on the above membrane structure, with the central axis extending along the second direction from the projection of the first hole as the cross section (the center position of the cross section BB), the field of view angle under the cross section is:

[0109] For example, under the structures shown in Figures 1 and 2, the improved perspective of the embodiments of this application can be derived from the cross-sectional views:

[0110] In another example, under the membrane structure shown in Figures 1 and 2, the viewing angle under the cross-section can be obtained from the cross-sectional view as follows:

[0111] In other words, the field of view of the embodiments shown in Figures 3 and 4 of this application is improved by 1.36° on one side and 2.72° on both sides compared with the field of view of the related technologies in Figures 1 and 2, thus achieving the purpose of improving the field of view.

[0112] Considering that the display driving circuit has multiple routing layers, in another optional embodiment, the number of the third routing layers 23 is two, as shown in Figures 6 to 8.

[0113] Figure 7 is a schematic diagram of the layer structure at the DD position of section 6 in Figure 6. The cross-sectional view in Figure 8 is a combined cross-sectional view of all the layer structures at the DD and EE positions of section 6 in Figure 6 from the same perspective. That is, the schematic diagram of the layer structure shown in Figure 8 cannot be obtained using a single cross-sectional line. For example, the sixth routing layer 26 and the first and third routing layers 231, represented by the dashed lines in Figure 8, can be seen at the EE position of section 6 in Figure 6, while the first routing layer 21 and the second routing layer 22 in Figure 8 can be seen at the DD position of section 6 in Figure 6. Therefore, Figure 8 is only an exemplary illustration used to show the positions of multiple routing layers in the stacking direction.

[0114] As shown in Figures 6 to 8, the third routing layer 23 includes a first third routing layer 231 and a second third routing layer 232. Therefore, the routing layer 20 structure in the stacking direction is sequentially a first routing layer 21, a first third routing layer 231, a second third routing layer 232, and a second routing layer 22. The first third routing layer 231 and the second third routing layer 232 (not shown in Figure 6) are used to transmit data signals.

[0115] In one embodiment, as shown in Figures 6 to 8, the first wiring layer 21 is disposed on the same layer as the first gate layer of the display panel, the first third wiring layer 231 is disposed on the same layer as the second gate layer located on the side of the first gate layer away from the substrate 10, the second third wiring layer 232 is disposed on the same layer as the first source / drain electrode layer located on the side of the second gate layer away from the substrate 10, and the second wiring layer 22 is disposed on the same layer as the second source / drain electrode layer located on the side of the first source / drain electrode layer away from the substrate 10. That is, when forming the layer structure of the thin-film driving transistor of the driving circuit, each wiring layer 20 is formed around the hole region NA using the same process, thereby improving the process manufacturing efficiency.

[0116] In an exemplary embodiment, as shown in Figures 6 to 8, between the surface of the second wiring layer 22 near the substrate 10 and the surface of the shielding layer 50 near the substrate 10, a second planarization layer 65 of thickness h covering the first sixth wiring layer 26, a sixth wiring layer 26 of thickness g, a third planarization layer 66 of thickness f covering the sixth wiring layer 26, a pixel defining layer 30 of thickness e located on the third planarization layer 66, and an encapsulation layer 40 of thickness c covering the pixel defining layer 30 are sequentially disposed on the third planarization layer 22 of thickness i.

[0117] Based on the above membrane structure, with the central axis (center of section DD) extending along the second direction from the projection of the first hole as the cross section, the field of view angle under the cross section is:

[0118] In other words, the field of view of the embodiments shown in Figures 6 to 8 of this application is improved by 4.85° on one side and 9.7° on both sides compared with the related technologies in Figures 1 and 2. Based on the embodiments shown in Figures 2 to 5, the field of view is further improved.

[0119] In an optional embodiment, as shown in Figures 3 and 6, the disconnected first wiring layer 21 and second wiring layer 22 are provided on both sides of the two opposite first boundaries 311 of the first aperture projection. That is to say, the cross-line design of the first wiring layer 21 and the second wiring layer 22 in this embodiment can not only be applied to one side of the first aperture projection, such as the side above or below the first aperture projection, but also to both sides of the first aperture projection. For example, the first wiring layer 21 and the second wiring layer 22 with the cross-line design are provided above and below the first aperture projection, thereby improving the field of view on both sides. For example, the field of view on both sides shown in Figure 3 will be improved by 2.72°, and the field of view on both sides shown in Figure 6 will be improved by 9.7°.

[0120] In an optional embodiment, as shown in Figures 3 and 6, with the central axis extending along the first direction of the first hole projection as the first axis of symmetry, the orthographic projections of the disconnected first wiring layer 21 and second wiring layer 22 on the substrate 10 located on one side of each first boundary 311 are symmetrical about the first axis of symmetry.

[0121] That is, the first wiring layer 21 and the second wiring layer 22 of the crossover design located on the upper side of the first boundary 311 in this embodiment of the application are symmetrically designed with the first wiring layer 21 and the second wiring layer 22 of the crossover design located on the lower side of the first boundary 311. The first through hole 31 is located in the middle of the horizontal crossover design on both sides, ensuring the consistency of the bilateral viewing angle on both sides, thereby reducing the complexity of the process.

[0122] In an optional embodiment, the first boundary 311 includes at least a straight boundary extending along the first direction, for example as shown in Figures 3 and 6, where the shape of the first hole projection is approximately rectangular, with an arc-shaped structure at each right-angle position of the rectangle and a straight structure at the non-arc-shaped structure positions.

[0123] Based on the shape and structure of the first hole projection, the embodiments of this application further design the structure of the second wiring layer 22 closer to the center position.

[0124] In an optional embodiment, as shown in Figures 3 and 6, the second wiring layer 22 includes: a first end 221 and a second end 222 of the first wiring layer 21 that are electrically disconnected, and a first connection portion 223 located between the first end 221 and the second end 222.

[0125] Wherein, the orthographic projection of the first end 221 on the substrate 10 overlaps with the orthographic projection of a broken edge of the first wiring layer 21 on the substrate 10, and the orthographic projection of the second end 222 on the substrate 10 overlaps with the orthographic projection of another broken edge of the first wiring layer 21 on the substrate 10.

[0126] That is, in this embodiment, the first end 221 and the second end 222 are electrically connected to the first routing layer 21, and the first connection hole 201 falls within the overlapping projection of the orthographic projection of the first end 221 and the first routing layer 21, and falls within the overlapping projection of the orthographic projection of the second end 222 and the first routing layer 21, to ensure the electrical conductivity of the first routing layer 21 and the second routing layer 22 when they are connected across layers through vias.

[0127] In this embodiment, the extension length of the first connecting portion 223 along the first direction of the orthographic projection of the substrate 10 is greater than or equal to the extension length of the straight boundary of the first boundary 311. That is, the length of the second wiring layer 22 in the first direction is greater than or equal to the extension length of the straight boundary of the first boundary 311. With this setting, the distance between the second wiring layer 22 and the first boundary 311 is guaranteed to be equal. For example, the first end 221 and the second end 222 are respectively set at the position corresponding to the arc-shaped structure of the first hole projection, and the first connecting portion 223 is set at the position of the straight boundary of the first hole projection, thereby ensuring the consistency of the field of view within the extension range of the second wiring layer 22.

[0128] In an optional embodiment, in the second direction, the width of the first connecting portion 223 in the second direction is smaller than the width of the first end portion 221 in the second direction. In other words, the width of the first connecting portion 223 in the second direction is smaller than the width of the first wiring layer 21 in the second direction. This embodiment achieves the design that the second distance D2 between the first connecting portion 223 and the first wiring layer 21 is greater than the first distance D1 between the first wiring layer 21 and the first hole projection, thereby improving the field of view.

[0129] The above embodiments describe the design of the wiring bridging and wiring structure on the upper and lower sides of the first hole projection to improve the field of view on both sides. Figure 9 shows the structural design of the display driving circuit on both sides of the first through hole 31. As shown in Figure 9, wiring layers are also provided on the left and right sides of the first through hole 31 to form the display driving circuit. Therefore, when the wiring space is limited, the distance between the wiring layers on the left and right sides of the first through hole 31 and the first through hole 31 is also small, that is, the field of view on the left and right sides of the first through hole 31 is also limited. The embodiments of this application propose a design for wiring bridging and wiring structure on the left and right sides of the first hole projection, which can achieve the purpose of improving the field of view on the left and right sides.

[0130] In an optional embodiment, as shown in Figures 10 and 11, the plurality of wiring layers 20 further includes a fourth wiring layer 24 and a fifth wiring layer 25 insulated from the fourth wiring layer 24, wherein the fourth wiring layer 24 is closer to the substrate 10 than the fifth wiring layer 25.

[0131] The fifth wiring layer 25 includes:

[0132] The third end 251, electrically connected to the fourth wiring layer 24 via the second connection hole 202, has its orthographic projection on the substrate 10 covering the orthographic projection of the fourth wiring layer 24 on the substrate 10; and

[0133] The second connecting portion 252 extending along the second direction has a third distance D3 between its third end 251 and the second boundary 312 extending along the second direction from the projection of the first hole, and a fourth distance D4 between the second connecting portion 252 and the second boundary 312 extending along the second direction from the projection of the first hole. The third distance D3 is less than the fourth distance D4.

[0134] In this embodiment, the traces extending along the second direction on both sides of the first through hole 31 are designed to cross over each other, and the distance between the traces extending along the second direction and the first through hole 31 is calculated. In the layer structure, the fourth distance D4 between the second connecting part 252 and the second boundary 312 extending along the second direction of the projection of the first hole is set to be larger than the third distance D3 between the third end 251 and the second boundary 312 extending along the second direction of the projection of the first hole, so as to achieve the effect of increasing the field of view.

[0135] In an optional embodiment, as shown in FIG11, FIG11 illustrates a schematic diagram of the layer structure at the location FF in section 10. As shown in FIG11, in the stacking direction, the fourth wiring layer 24 and the fifth wiring layer 25 are two adjacent conductive layers.

[0136] The display panel further includes an insulating layer located between the fourth wiring layer 24 and the fifth wiring layer 25, wherein the fourth wiring layer 24 and the fifth wiring layer 25 are electrically connected through a second connection hole 202 penetrating the insulating layer.

[0137] Since the routing circuit in the second direction is relatively complex, this embodiment sets the fourth routing layer 24 and the fifth routing layer 25 as two adjacent routing layers to avoid making significant changes to the display driving circuit and reduce the difficulty of manufacturing process.

[0138] In an optional embodiment, the fourth routing layer 24 and the fifth routing layer 25 are provided on both sides of the two opposite second boundaries 312 of the first hole projection.

[0139] With the central axis extending along the second direction of the first hole projection as the second axis of symmetry, the orthographic projections of the fourth wiring layer 24 and the fifth wiring layer 25 located on one side of each second boundary 312 onto the substrate 10 are symmetrical projections with the second axis of symmetry as the second axis of symmetry.

[0140] In an optional embodiment, as shown in Figures 3 and 6, a fourth wiring layer 24 and a fifth wiring layer 25 electrically connected to the fourth wiring layer 24 are provided on both sides of the two opposite second boundaries 312 of the first aperture projection. That is to say, the cross-line design of the fourth wiring layer 24 and the fifth wiring layer 25 in this embodiment can not only be applied to one side of the first aperture projection, such as the left or right side of the first aperture projection, but also to both sides of the first aperture projection, such as the left and right sides of the first aperture projection, where the fourth wiring layer 24 and the fifth wiring layer 25 with the cross-line design are provided, thereby improving the field of view on both sides.

[0141] That is, in this embodiment of the application, the fourth wiring layer 24 and the fifth wiring layer 25 of the cross-line design on the left side of the second boundary 312 on the left side and the fourth wiring layer 24 and the fifth wiring layer 25 of the cross-line design on the right side of the second boundary 312 on the right side are symmetrically designed. The first through hole 31 is located at the center of the vertical cross-line design on both sides, ensuring the consistency of the bilateral viewing angle on both sides, thereby reducing the complexity of the process.

[0142] In an optional embodiment, the second boundary 312 includes at least a straight boundary extending along the second direction, for example as shown in Figures 3 and 6, where the shape of the first hole projection is approximately rectangular, with an arc-shaped structure at each right-angle position of the rectangle and a straight structure at the non-arc-shaped structure positions.

[0143] Based on the shape and structure of the first hole projection, this application embodiment further designs the structure of the fifth wiring layer 25. In an optional embodiment, the combined projection of the third end 251 and the second connection portion 252 onto the substrate 10 extends along the second direction at a length greater than the extension length of the straight boundary of the second boundary 312, thereby ensuring the consistency of the field of view within the extension range of the second wiring layer 22.

[0144] It is worth noting that the field-of-view structure design for the left and right sides of the display panel shown in Figures 10 and 11 of this application can also be applied to the field-of-view structure design for the top and bottom sides of the display panel in Figures 3 and 6. Considering that the wiring is more complex under the two combined schemes, this application describes the layer design of multiple wiring layers 20 under the two embodiments.

[0145] When the display panel adopts the wiring design shown in Figures 3 and 10, a layer structure schematic diagram as shown in Figures 12 and 13 is formed. In an optional embodiment, as shown in Figures 12 and 13, in the stacking direction, the distance between the first wiring layer 21, the fourth wiring layer 24 and the second wiring layer 22 and the substrate 10 gradually increases. The fourth wiring layer 24 and the third wiring layer 23 are disposed in the same layer, and the second wiring layer 22 and the fifth wiring layer 25 are disposed in the same layer.

[0146] In one embodiment, the first wiring layer 21 is disposed on the same layer as the first gate layer of the display panel, the third wiring layer 23 is disposed on the same layer as the second gate layer located on the side of the first gate layer away from the substrate 10, the fourth wiring layer 24 is disposed on the same layer as the third wiring layer 23, that is, the fourth wiring layer 24 is also disposed on the same layer as the second gate layer located on the side of the first gate layer away from the substrate 10, the second wiring layer 22 is disposed on the same layer as the first source / drain electrode layer located on the side of the second gate layer away from the substrate 10, and the fifth wiring layer 25 is disposed on the same layer as the first source / drain electrode layer located on the side of the second gate layer away from the substrate 10. That is, when forming the layer structure of the thin-film driving transistor of the driving circuit, each wiring layer 20 is formed around the via region NA using the same process, thereby improving the process manufacturing efficiency.

[0147] In an optional embodiment, as shown in Figures 12 and 13, the plurality of wiring layers 20 further includes at least one sixth wiring layer 26, which is the wiring layer among the plurality of wiring layers 20 that has the largest distance from the substrate 10 in the stacking direction.

[0148] In an exemplary embodiment, as shown in Figures 12 and 13, there are two sixth routing layers 26, including a first sixth routing layer 261 located on the second routing layer 22 (or the fifth routing layer 25 on the same layer as the second routing layer 22), and a second sixth routing layer 262 located above the first sixth routing layer 261.

[0149] In this embodiment, the first sixth wiring layer 261 extends along the second direction in the orthographic projection of the substrate 10. The end of the first sixth wiring layer 261 in the second direction is closer to the first boundary located below than the third end 251. In the extension direction of the second direction, the orthographic projection of the first sixth wiring layer 261 extends to the orthographic projection of the first wiring layer 21 located below.

[0150] In this embodiment, the second sixth wiring layer 262 extends along the second direction in the orthogonal projection of the substrate 10, and overlaps with the projections of the first wiring layer 21 located above the first via 51 and the first wiring layer 21 located below the first via 51.

[0151] The wiring layer also includes a data wiring layer 28 disposed on the same layer as the second wiring layer 22, which is used to transmit data signals. The orthogonal projection of the data wiring layer 28 on the substrate overlaps with the orthogonal projection of the first wiring layer 20.

[0152] In this embodiment, the first routing layer 21, the second routing layer 22, the data routing layer 28, a third routing layer 23, a fourth routing layer 24, a fifth routing layer 25, and a plurality of sixth routing layers 26 constitute a display driving circuit. For example, the display driving circuit is an 8T1C display driving circuit.

[0153] For example, the 8T1C display driving circuit is a circuit composed of 8 thin-film driving transistors and 1 capacitor unit, wherein the data routing layer 28 is used to transmit data signals, and the first routing layer 21 and the second routing layer 22, which are horizontally routed and connected, transmit a first initial signal.

[0154] The fourth routing layer 24 and the fifth routing layer 25, which are vertically routed and connected, transmit the second initial signal.

[0155] The first layer, sixth layer 261 of the vertical routing transmits the power supply voltage (VDD) signal; the second layer, sixth layer 262 of the vertical routing transmits the common voltage (VSS) signal. Thus, while ensuring the maximum viewing angle, it is applied to the 8T1C display driver circuit, so that the display panel has better display effect and lower power consumption.

[0156] In an optional embodiment, when the display panel adopts the wiring design shown in Figures 6 and 10, a structural schematic diagram as shown in Figures 14 and 15 is formed. In the stacking direction, the distance between the first wiring layer 21, the fourth wiring layer 24, the at least one third wiring layer 23, and the second wiring layer 22 and the substrate 10 gradually increases. The at least one third wiring layer 23 is disposed in the same layer as the first third wiring layer 231 and the fourth wiring layer 24, and the at least one third wiring layer 23 is disposed in the same layer as the second third wiring layer 232 and the fifth wiring layer 25, which is away from the substrate 10.

[0157] In an exemplary embodiment, the first wiring layer 21 is disposed on the same layer as the first gate layer of the display panel, the first third wiring layer 231 is disposed on the same layer as the second gate layer located on the side of the first gate layer away from the substrate 10, the fourth wiring layer 24 is disposed on the same layer as the first third wiring layer 231, that is, the fourth wiring layer 24 is disposed on the same layer as the second gate layer, the second third wiring layer 232 is disposed on the same layer as the first source / drain electrode layer located on the side of the second gate layer away from the substrate 10, one of the at least three third wiring layers 23 away from the substrate 10 is disposed on the same layer as the fifth wiring layer 25, that is, the fifth wiring layer 25 is disposed on the same layer as the first source / drain electrode layer, and the second wiring layer 22 is disposed on the same layer as the second source / drain electrode layer located on the side of the first source / drain electrode layer away from the substrate 10. In other words, when forming the layer structure of the thin-film driving transistor of the driving circuit, each wiring layer 20 is formed around the via region NA using the same process, thereby improving the process fabrication efficiency.

[0158] In an optional embodiment, the plurality of wiring layers 20 further includes a sixth wiring layer 26, which is the wiring layer among the plurality of wiring layers 20 that has the largest distance from the substrate 10 in the stacking direction. In this embodiment, the orthographic projection of the sixth wiring layer 26 onto the substrate 10 extends along a second direction and overlaps with the projections of both the first wiring layer 21 located above the first via 51 and the first wiring layer 21 located below the first via 51.

[0159] As shown in Figure 15, the plurality of wiring layers 20 also include a seventh wiring layer 27 disposed on the same layer as the second wiring layer 22. The orthographic projection of the seventh wiring layer 27 onto the substrate 10 extends along the second direction. In this embodiment, the end of the seventh wiring layer 27 in the second direction is closer to the lower first boundary than the third end 251. In the extension direction of the second direction, the orthographic projection of the seventh wiring layer 27 extends to the orthographic projection of the lower first wiring layer 21.

[0160] In an optional embodiment, the wiring layer further includes a data transmission wiring layer 28 disposed on the same layer as the second third wiring layer 232 (fifth wiring layer 25), and the data transmission wiring layer 28 partially overlaps with the orthographic projection of the first wiring layer 21 onto the substrate.

[0161] In this embodiment, the first routing layer 21, the second routing layer 22, multiple third routing layers 23, the fourth routing layer 24, the fifth routing layer 25, the sixth routing layer 26, the seventh routing layer 27, and the data transmission routing layer 28 constitute a display driving circuit. For example, the display driving circuit is an 8T1C display driving circuit.

[0162] For example, the 8T1C display driving circuit is a circuit consisting of 8 thin-film driving transistors and 1 capacitor unit;

[0163] Data transmission trace layer 28 is used to transmit data signals;

[0164] The first routing layer 21 and the second routing layer 22, which are horizontally routed and connected, transmit the first initial signal;

[0165] The fourth routing layer 24 and the fifth routing layer 25, which are vertically routed and connected, transmit the second initial signal;

[0166] The seventh routing layer of the vertical routing transmits the power supply voltage (VDD) signal;

[0167] The sixth routing layer 26 of the vertical routing transmits the common voltage (VSS) signal, which is applied to the 8T1C display driver circuit while ensuring the maximum viewing angle, so that the display panel has better display effect and lower power consumption.

[0168] Based on the embodiments of Figures 12 and 13, and the embodiments of Figures 14 and 15, the wiring structure of this application can be applied to display panels of various embodiments. While ensuring that the size of the second through-hole 51 remains unchanged, it can be applied to circuit designs with complex structures, achieving an improved field of view within a limited wiring space. It has broad application prospects and will not be elaborated further here. To ensure manufacturing precision, in an optional embodiment, the minimum boundary distance L between each wiring layer 20 and the sidewall of the first through-hole 31 facing each wiring layer 20 satisfies the following formula:

[0169] Wherein, H1 is the interlayer thickness between the surface of each wiring layer 20 near the substrate 10 and the surface of the shielding layer 50 near the substrate 10;

[0170] a is the diameter of the second through hole 51, and a is usually less than 10 μm; b is the diameter of the first through hole 31, and b is usually less than 12 μm.

[0171] d is the distance between one side wall of the first through hole 31 and one side wall of the second through hole 51, and d is usually 1 μm;

[0172] c is the interlayer thickness between the surface of the pixel defining layer 30 away from the substrate 10 and the surface of the shielding layer 50 close to the substrate 10;

[0173] e is the thickness of the pixel defining layer 30.

[0174] In an exemplary embodiment, taking the wiring arrangement of the display panel shown in Figures 12 and 13 as an example, Figure 16 shows a schematic diagram of all the wiring layers 20 in the same layer structure. The layer structure in Figure 16 takes the axes of the horizontal and vertical symmetry axes of the first through hole 21 as cross-sections, and the film layers in the two cross-sections are reflected in the same layer structure schematic diagram 16 to illustrate the distance design relationship between each wiring layer 20 and the first through hole 31. That is to say, the layer structure shown in Figure 16 is only an exemplary illustration. This layer structure is an integral layer structure that integrates the vertical axis cross-section and the horizontal axis cross-section. In other words, the minimum boundary distance L in this embodiment refers to the minimum boundary distance between each wiring layer 20 and the sidewall corresponding to the first boundary 311 or the second boundary 312 of the first through hole 31.

[0175] It is worth noting that, in the embodiments of this application, the thickness of the insulating film layer refers to the distance between the surface of the insulating film layer away from the substrate and the surface of the wiring layer covered by the insulating film layer that is in contact with the substrate. In an exemplary embodiment, the thicknesses of the multiple film layers are as follows:

[0176] The thickness of the first gate insulating layer 61 disposed on the substrate 10 is p, typically 0.13 μm.

[0177] The thickness of the first wiring layer 21 disposed on the first gate insulating layer 61 is 0, typically 0.3 μm.

[0178] The thickness of the second gate insulating layer 62 disposed on the first wiring layer 21 is n, that is, the thickness between the surface of the second gate insulating layer 62 away from the substrate and the surface of the first wiring layer 21 away from the substrate is n, which is typically 0.13 μm.

[0179] A third wiring layer 23 with a thickness of m, typically 0.3 μm, is disposed on the second gate insulating layer 62.

[0180] The thickness of the interlayer dielectric layer 63 disposed on the third wiring layer 23 is l, that is, the thickness between the surface of the third wiring layer 23 away from the substrate and the surface of the third wiring layer 23 away from the substrate is l, which is typically 0.13 μm.

[0181] The thickness of the second wiring layer 22 disposed on the interlayer dielectric layer 63 is k, typically 0.6 μm.

[0182] The thickness of the first planarization layer 64 disposed on the second wiring layer 22 is j, that is, the thickness between the surface of the first planarization layer 64 away from the substrate and the surface of the second wiring layer 22 away from the substrate is j, which is usually 1.5um.

[0183] The thickness of the first sixth wiring layer 261 set on the first flattening layer 64 is i, which is typically 0.6 μm;

[0184] The thickness of the second planarization layer 65 disposed on the first sixth wiring layer 261 is h, that is, the thickness between the surface of the second planarization layer 65 away from the substrate and the surface of the first sixth wiring layer 261 away from the substrate is h, which is usually 1.5um.

[0185] The thickness of the second sixth wiring layer 262 set on the second flattening layer 65 is g, typically 0.6um;

[0186] The thickness of the third planarization layer 66 disposed on the sixth wiring layer 262 of the second layer is f, that is, the thickness between the surface of the third planarization layer 66 away from the substrate and the surface of the sixth wiring layer 262 away from the substrate is f, which is usually 1.5um;

[0187] e is the thickness of the pixel boundary layer 30, which is usually 1.5um;

[0188] c is the thickness of the encapsulation layer 40, that is, the thickness between the surface of the encapsulation layer 40 away from the substrate and the surface of the pixel defining layer 30 away from the substrate. Typically, c is 10 μm.

[0189] By the Pythagorean theorem, we have: Tanα = (a + d) / (c + e)

[0190] =r / (f+g)

[0191] =s / (f+g+h+i)

[0192] =t / (f+g+h+i+j+k)

[0193] =u / (f+g+h+i+j+k+l+m)

[0194] =v / (f+g+h+i+j+k+l+m+n+o);

[0195] The vertical plane containing the bottom edge of the first sidewall of the first through hole 31 of the pixel defining layer 30 near the substrate 10 is the first included angle side. The line connecting the first bottom edge of the first sidewall of the first through hole 31 of the pixel defining layer 30 near the substrate 10 and the top edge of the second sidewall of the second through hole 51 away from the first bottom edge is the second included angle side. The included angle formed by the first included angle side and the second included angle side is α.

[0196] When it is required that all routing layers 20 below the first via 31 do not affect the viewing angle of the first via 31, different routing layers 20 have different interlayer thicknesses H1, according to... Based on the above definition of Tanα, the minimum boundary distances of the sidewalls of the first via 31 facing each routing layer 20 are as follows:

[0197] The minimum boundary distance Lr between the second and sixth routing layers 262, which is the topmost layer on the multiple routing layers 20, and the second boundary 312 of the first via 31 is:

[0198] The minimum boundary distance L between the first and sixth routing layers 261 located on multiple routing layers 20 s1 for:

[0199] For example, when the fifth routing layer 25 and the first sixth routing layer 261 are disposed on the same layer, the minimum boundary distance L between the fifth routing layer 25 and the second boundary 312 of the first via 31 is... s1 for:

[0200] The minimum boundary distance Lt between the second routing layer 22, located in the plurality of routing layers 20, and the first boundary 311 of the first via 31 is:

[0201] The minimum boundary distance L between the third routing layer 23 (one of the multiple routing layers 20) and the first via 31, and the second boundary 312. u1 for:

[0202] For example, when the fourth routing layer 24 and the third routing layer 23 are disposed on the same layer, the minimum boundary distance L between the fourth routing layer 24 and the second boundary 312 of the first via 31 is... u2 for:

[0203] The minimum boundary distance Lv of the first routing layer 21, which is connected to the second routing layer 22 among multiple routing layers 20, is:

[0204] Based on the minimum boundary distance design between each wiring layer 20 and the first via 31, it can be seen that from the direction of the substrate 10 from the encapsulation layer 40, the minimum boundary distance between each wiring layer 20 and the sidewall corresponding to the first boundary 311 or the second boundary 312 of the first via 31 gradually decreases, thereby ensuring that the field of view is not affected by each wiring layer 20 and ensuring the optimal display effect.

[0205] In an optional embodiment, as shown in Figures 17 and 18, the display area AA includes a first display area AA01 and a second display area AA02 surrounding the first display area AA01.

[0206] The second display area AA02 includes a pixel light-emitting area Pix.

[0207] The first display area AA01 includes the pixel light-emitting area Pix and the non-pixel light-emitting area NPix located around the pixel light-emitting area Pix.

[0208] The pixel light-emitting area Pix is ​​provided with a plurality of sub-pixels (R / G / B) defined by a pixel delimiting layer, and the non-pixel light-emitting area NPix is ​​provided with at least one aperture area NA, which is disposed in the gap between the plurality of sub-pixels.

[0209] This embodiment describes the location of the aperture area. As shown in Figure 17, the aperture area described in this embodiment can be set not only at the top of the display panel, but also in the first display area AA01 located in the center of the display panel, which is surrounded by the second display area AA02. This expands the application scenarios of the display panel that uses the aperture area NA for light sensing detection, such as camera acquisition, fingerprint recognition, and brightness adjustment.

[0210] In this embodiment, the difference between the first display area AA01 and the second display area AA02 lies in whether or not an aperture area NA is provided. That is, the second display area AA02 is provided with a non-pixel light-emitting area NPix for setting the aperture area NA, as shown in Figure 18. The aperture area NA is set in the gap between multiple sub-pixels. At the location of the aperture area NA, the pixel defining layer is not only used to define multiple sub-pixels (R / G / B), but also to open a first through hole in multiple gaps between multiple sub-pixels (R / G / B). The shielding layer at each location of the first through hole opens a second through hole to improve light transmittance. The structure of each wiring layer is described with reference to the above embodiment. The boundary distance of each wiring layer at the location of the first through hole is designed based on each first through hole, which will not be repeated here.

[0211] Another embodiment of this application provides a display device, which includes the display panel of the above embodiments of this application. The display device of this application can be any product or component that requires a liquid crystal display panel, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or vehicle display device, and the embodiments of this application are not limited thereto.

[0212] In an optional embodiment, as shown in FIG16, the display device further includes a sensor 70 disposed at a location corresponding to the hole area, located on the side of the substrate 10 of the display panel away from the plurality of wiring layers 20. The sensor is configured to emit and receive sensing signals to perform sensing. In this embodiment, the sensing signal is emitted from the first through hole 31, and the received sensing signal includes the collected sensing information, such as image information obtained by capturing a face. The sensing signal is then processed in the processor to realize the sensing function of the display panel.

[0213] Another embodiment of this application provides a method for manufacturing the above-mentioned display panel, the method comprising:

[0214] Multiple mutually insulating wiring layers 20 are sequentially formed on the substrate 10 corresponding to the display area AA;

[0215] A pixel defining layer 30 is formed on the wiring layer 20 of the display area AA and on the insulating layer covering the wiring layer 20 of the hole area NA;

[0216] The pixel defining layer 30 located in the aperture region NA is etched to form a first via 31, and the orthogonal projection of the first via 31 onto the substrate 10 is the first aperture projection.

[0217] An encapsulation layer 40 and a masking layer 50 are sequentially formed on the pixel defining layer 30;

[0218] The shielding layer 50 is etched at the position corresponding to the first through hole 31 to form a second through hole 51;

[0219] Among them, a plurality of mutually insulating wiring layers 20 are sequentially formed on the substrate 10 corresponding to the display area AA, further including:

[0220] A first trace layer 21 extending in a first direction is formed on the substrate 10 corresponding to the display area AA. In the first direction, the first trace layer 21 is broken near the center of the first via 31.

[0221] A second wiring layer 22 is formed on the first wiring layer 21 and extends along a first direction while being insulated from the first wiring layer 21. The two ends of the second wiring layer 22 are electrically connected to the disconnected first wiring layer 21. The distance between the projection boundary of the first wiring layer on the substrate and the projection boundary at any position of the first hole projection is a first distance. The minimum distance between the projection boundary of the first wiring layer on the substrate and the projection boundary of the first hole projection in a second direction is a first distance. The minimum distance between the projection boundary of the second wiring layer on the substrate and the projection boundary of the first hole projection in a second direction is a second distance. The first distance is less than the second distance.

[0222] The manufacturing method of this application embodiment does not add complicated process steps. The manufacturing process of multiple wiring layers 20 can refer to the manufacturing process of related technologies. In the process of manufacturing wiring layers 20, the distance between the first wiring layer 21 and the second wiring layer 22 and the first through hole 31 is designed. On the basis of ensuring the optimal size design of the first through hole 31 and the second through hole 51, the purpose of increasing the field of view is achieved.

[0223] It is worth noting that exemplary embodiments of the display panel manufacturing method in this application can be found in the display panels of the foregoing embodiments, and will not be repeated here.

[0224] In the description of this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0225] Obviously, the above embodiments of this application are merely examples for clearly illustrating this application, and are not intended to limit the implementation of this application. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. Any obvious variations or modifications derived from the technical solutions of this application are still within the protection scope of this application.

Claims

1. A display panel, the display panel including an aperture region and a display area at least surrounding a portion of the aperture region, the display area including a pixel light-emitting area located on at least one side of the aperture region, wherein, The display panel includes a substrate, multiple mutually insulated wiring layers, a pixel defining layer, an encapsulation layer, and a shielding layer stacked sequentially. Wherein, the pixel defining layer forms a first through hole in the hole area, and the shielding layer forms a second through hole in the hole area at a position corresponding to the first through hole, and the orthographic projection of the first through hole onto the substrate is the first hole projection; The combined projection of the orthographic projection of the multiple wiring layers located in the display area onto the substrate surrounds the projection of the first aperture. The plurality of wiring layers include a first wiring layer and a second wiring layer, both extending along a first direction, wherein the first wiring layer is closer to the substrate than the second wiring layer. In a first direction, the first trace layer is disconnected near the center of the first via, and the two ends of the second trace layer are electrically connected to the disconnected first trace layer. The minimum distance between the projection boundary of the first wiring layer on the substrate and the projection boundary of the first hole in the second direction is the first distance, and the minimum distance between the projection boundary of the second wiring layer on the substrate and the projection boundary of the first hole in the second direction is the second distance, wherein the first distance is less than the second distance.

2. The display panel according to claim 1, wherein, In the stacking direction, the first trace layer and the second trace layer are two non-adjacent conductive layers. The display panel further includes: at least one third wiring layer and a plurality of insulating layers located between the first wiring layer and the second wiring layer, wherein the plurality of insulating layers are used to insulate the first wiring layer, the at least one third wiring layer, and the second wiring layer, respectively. The first wiring layer and the second wiring layer are electrically connected through a first connection hole that penetrates the plurality of insulating layers.

3. The display panel according to claim 2, wherein, The first wiring layer is disposed on the same layer as the first gate layer of the display panel, the third wiring layer is disposed on the same layer as the second gate layer located on the side of the first gate layer away from the substrate, and the second wiring layer is disposed on the same layer as the first source / drain electrode layer located on the side of the second gate layer away from the substrate.

4. The display panel according to claim 1, wherein, On both sides of the two opposite first boundaries of the first hole projection, the disconnected first trace layer and second trace layer are provided. With the central axis extending along the first direction as the first axis of symmetry, the orthographic projections of the disconnected first and second trace layers on the substrate located on each side of the first boundary are symmetrical about the first axis of symmetry.

5. The display panel according to claim 1, wherein, The first aperture projection includes a first boundary extending along a first direction and a second boundary extending along a second direction, wherein the first boundary includes at least a straight boundary extending along the first direction. The minimum distance between the projection boundary of the first wiring layer on the substrate and the straight boundary of the first boundary is the first distance, and the minimum distance between the projection boundary of the second wiring layer on the substrate and the straight boundary of the first boundary is the first distance.

6. The display panel according to claim 5, wherein, The second routing layer includes: a first end and a second end of the first routing layer that are electrically disconnected, and a first connection portion located between the first end and the second end. Wherein, the orthographic projection of the first end on the substrate overlaps with the orthographic projection of a break edge of the first wiring layer on the substrate, and the orthographic projection of the second end on the substrate overlaps with the orthographic projection of another break edge of the first wiring layer on the substrate. The extension length of the first connection portion along the first direction in the orthographic projection of the substrate is greater than or equal to the extension length of the straight boundary of the first boundary.

7. The display panel according to claim 6, wherein, The width of the first connecting portion in the second direction is smaller than the width of the first end portion in the second direction.

8. The display panel according to any one of claims 2 to 7, wherein, The plurality of wiring layers further includes a fourth wiring layer and a fifth wiring layer that is insulated from the fourth wiring layer, wherein the fourth wiring layer is closer to the substrate than the fifth wiring layer. The fifth routing layer includes: A third end electrically connected to the fourth wiring layer via a second connection hole, wherein the orthographic projection of the third end onto the substrate overlaps the orthographic projection of the fourth wiring layer onto the substrate; and The second connecting portion extending along the second direction, The minimum distance between the third end and the second boundary extending along the second direction of the projection of the first hole is the third distance, and the minimum distance between the second connecting part and the second boundary extending along the second direction of the projection of the first hole is the fourth distance. The third distance is less than the fourth distance.

9. The display panel according to claim 8, wherein, In the stacking direction, the fourth wiring layer and the fifth wiring layer are two adjacent conductive layers. The display panel further includes an insulating layer located between the fourth wiring layer and the fifth wiring layer, wherein the fourth wiring layer and the fifth wiring layer are electrically connected through a second connection hole penetrating the insulating layer.

10. The display panel according to claim 8, wherein, On both sides of the two opposite second boundaries of the first hole projection, the fourth routing layer and the fifth routing layer are respectively provided. With the central axis extending along the second direction from the projection of the first hole as the second axis of symmetry, the orthographic projections of the fourth and fifth wiring layers located on each side of the second boundary onto the substrate are symmetrical projections with the second axis of symmetry as the second axis of symmetry.

11. The display panel according to claim 8, wherein, The second boundary includes at least a straight boundary extending along the first direction. The combined projection of the third end and the second connection portion onto the substrate extends along the second direction at a length greater than the extension length of the straight boundary of the second boundary.

12. The display panel according to claim 8, wherein, In the stacking direction, the distance between the first wiring layer, the fourth wiring layer and the second wiring layer and the substrate gradually increases. The fourth wiring layer and the third wiring layer are disposed in the same layer, and the second wiring layer and the fifth wiring layer are disposed in the same layer.

13. The display panel according to claim 8, wherein, In the stacking direction, the distance between the first wiring layer, the fourth wiring layer, the at least one third wiring layer, and the second wiring layer and the substrate gradually increases. Among the at least one third wiring layer, the third wiring layer closest to the substrate is disposed in the same layer as the fourth wiring layer, and one of the at least one third wiring layers is disposed in the same layer as the fifth wiring layer.

14. The display panel according to claim 8, wherein, The plurality of wiring layers further includes at least one sixth wiring layer, which is the wiring layer among the plurality of wiring layers that has the largest distance from the substrate in the stacking direction. The first routing layer, the second routing layer, the fourth routing layer, the fifth routing layer, and the sixth routing layer constitute a display driving circuit; or The first routing layer, the second routing layer, the third routing layer, the fourth routing layer, the fifth routing layer, and the sixth routing layer constitute a display driving circuit.

15. The display panel according to claim 14, wherein, The display driver circuit is an 8T1C display driver circuit.

16. The display panel according to claim 8, wherein, Taking the central axis extending along the second direction from the projection of the first hole as a cross section, the minimum boundary distance L between the sidewall of each routing layer near the projection of the first hole and the first boundary of the projection of the first hole satisfies the following formula: Wherein, H1 is the interlayer thickness between the surface of each wiring layer near the substrate and the surface of the shielding layer near the substrate; a is the diameter of the cross-section of the second through hole under the cross-section; d is the distance between one side wall of the first through hole and one side wall of the second through hole; c is the interlayer thickness between the surface of the pixel defining layer away from the substrate and the surface of the shielding layer close to the substrate; e is the thickness of the pixel-defining layer.

17. The display panel according to claim 1, wherein, The display area includes a first display area and a second display area surrounding the first display area. The first display area includes a pixel light-emitting area and a non-pixel light-emitting area located around the pixel light-emitting area. The pixel light-emitting area is provided with multiple sub-pixels defined by a pixel delimiting layer. The non-pixel light-emitting area is provided with at least one of the aperture areas, which are disposed in the gaps between multiple sub-pixels.

18. A display device, wherein, The display device includes the display panel according to any one of claims 1 to 17.

19. The display device of claim 18, further comprising a sensing element disposed at a location corresponding to the hole area, located on the side of the substrate of the display panel away from the plurality of wiring layers.

20. A method for manufacturing a display panel according to any one of claims 1 to 17, comprising: Multiple mutually insulating wiring layers are sequentially formed on the substrate corresponding to the display area; A pixel delimiting layer is formed on the wiring layer of the display area and on the insulating layer covering the wiring layer of the hole area; The pixel defining layer located in the hole region is etched to form a first via, and the orthographic projection of the first via on the substrate is the first hole projection; An encapsulation layer and a masking layer are sequentially formed on the pixel definition layer; The shielding layer is etched at the location corresponding to the first through-hole to form a second through-hole; The method further includes forming multiple mutually insulating wiring layers sequentially on the substrate corresponding to the display area, and further comprising: A first trace layer extending in a first direction is formed on a substrate corresponding to the display area, wherein the first trace layer is interrupted near the center of the first via in the first direction; A second trace layer is formed on the first trace layer and extends along a first direction, which is insulated from the first trace layer. The two ends of the second trace layer are electrically disconnected from the first trace layer. The minimum distance between the projection boundary of the first trace layer on the substrate and the projection boundary of the first hole in the second direction is a first distance. The minimum distance between the projection boundary of the second trace layer on the substrate and the projection boundary of the first hole in the second direction is a second distance. The first distance is less than the second distance.

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