Display panel and display apparatus

Abstract

A display panel and a display apparatus, which relate to the technical field of display. The display panel comprises a substrate, a plurality of sub-pixels, a gate driving circuit, and at least two power supply signal lines, wherein the at least two power supply signal lines connected in parallel are arranged in a non-display area, and the orthographic projection of at least one of the at least two power supply signal lines on the substrate overlaps with the orthographic projection of the gate driving circuit on the substrate, such that the total width or total cross-sectional area of the power supply signal lines can be increased, and it is not necessary to arrange a wider signal line on the side of the gate driving circuit that is away from a display area. Therefore, while ensuring a narrow bezel, the resistance of the power supply signal lines can be reduced by means of parallel connection, such that voltage drops of the power supply signal lines can be reduced, thereby improving the brightness uniformity of the display panel and reducing power consumption.

Description

Display panel and display device

[0001] The present application claims priority to the Chinese patent application No. 202410692113.6, filed on May 30, 2024, and entitled "Display panel and display device", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0003] The lighting of an organic light-emitting diode (OLED) panel is controlled by a cathode power signal (ELVSS), an anode power signal (ELVDD) and a data signal, wherein the voltage difference between ELVSS and ELVDD determines the lighting brightness of the OLED panel. SUMMARY

[0004] The present application provides a display panel and a display device, and the technical solutions are as follows:

[0005] In one aspect, a display panel is provided, which has a display area and a non-display area located at the periphery of the display area; the display panel comprises a substrate, a plurality of sub-pixels, a gate drive circuit and at least two power signal lines.

[0006] The plurality of sub-pixels are located on one side of the substrate and distributed in the display area.

[0007] The gate drive circuit is located on one side of the substrate and located in the non-display area; the gate drive circuit is electrically connected to at least part of the sub-pixels.

[0008] The at least two power signal lines are in parallel and distributed in the non-display area; the at least two power signal lines are electrically connected to at least part of the plurality of sub-pixels.

[0009] At least one of the at least two power signal lines on the substrate intersects with the projection of the gate drive circuit on the substrate.

[0010] Optionally, the at least two power signal lines comprise a first power signal line and a second power signal line, in a direction parallel to the substrate, the first power signal line is closer to the display area than the second power signal line; the projection of the first power signal line on the substrate intersects with the projection of the gate drive circuit on the substrate.

[0011] Optionally, the display panel further comprises a plurality of first conductive traces distributed in the non-display area.

[0012] One end of the plurality of first conductive traces is electrically connected with the first power signal line, and the other end of the plurality of first conductive traces is electrically connected with the second power signal line.

[0013] Optionally, the at least two power signal lines comprise a first power signal line and a third power signal line.

[0014] In a direction parallel to the substrate, the third power signal line is closer to the display area relative to the first power signal line, and a projection of the first power signal line on the substrate overlaps a projection of the gate driving circuit on the substrate.

[0015] Optionally, the display panel further comprises a plurality of second conductive traces distributed in the non-display area.

[0016] One end of the plurality of second conductive traces is electrically connected with the first power signal line, and the other end of the plurality of second conductive traces is electrically connected with the third power signal line.

[0017] Optionally, the at least two power signal lines comprise a first power signal line, a second power signal line, and a third power signal line.

[0018] In a direction parallel to the substrate, the second power signal line is farther away from the display area relative to the first power signal line, and the third power signal line is closer to the display area relative to the first power signal line; a projection of the first power signal line on the substrate overlaps a projection of the gate driving circuit on the substrate.

[0019] Optionally, the non-display area comprises two first sub-areas oppositely arranged in a first direction, and a second sub-area and a third sub-area oppositely arranged in a second direction; the non-display area further comprises a binding area, the binding area is located on a side of the third sub-area away from the display area in the second direction; the first direction intersects the second direction.

[0020] The second power signal line and the third power signal line are distributed at least in the two first sub-areas and the second sub-area; and the first power signal line is distributed at least in the two first sub-areas.

[0021] Optionally, the display panel further comprises a plurality of third conductive traces distributed in the second sub-area.

[0022] One end of the plurality of third conductive traces is electrically connected with the second power signal line, and the other end of the plurality of third conductive traces is electrically connected with the third power signal line.

[0023] Optionally, the first power signal line, the second power signal line and the third power signal line are all further distributed in the third subregion; the display panel further comprises: a first connecting segment and / or a second connecting segment distributed in the third subregion;

[0024] The extension direction of the first connecting segment is parallel to the first direction, and in the second direction, the first connecting segment is connected with the first power signal line and the second power signal line respectively on both sides of the first connecting segment.

[0025] The extension direction of the second connecting segment is parallel to the first direction, and in the second direction, the second connecting segment is connected with the first power signal line and the third power signal line respectively on both sides of the second connecting segment.

[0026] Optionally, the display panel further comprises: a plurality of fourth conductive traces and a plurality of fifth conductive traces distributed in the display region;

[0027] The fourth conductive traces extend along the first direction, and both ends of the fourth conductive traces are connected with the part of the third power signal line distributed in the two first subregions respectively;

[0028] The fifth conductive traces extend along the second direction, and both ends of the fifth conductive traces are connected with the part of the third power signal line distributed in the second subregion and the third subregion respectively.

[0029] Optionally, the fourth conductive traces and the fifth conductive traces are arranged in different layers; or, the fourth conductive traces and the fifth conductive traces are arranged in the same layer and are made of the same material.

[0030] Optionally, the display panel further comprises: a plurality of data signal lines and a plurality of fan-out leads distributed in the display region; the plurality of subpixels are arranged as a plurality of columns in the first direction; one data signal line is electrically connected with one column of subpixels, and at least part of the plurality of data signal lines are electrically connected with the plurality of fan-out leads correspondingly.

[0031] The projection of the fan-out lead on the substrate does not overlap with the projection of the fourth conductive trace on the substrate, and does not overlap with the projection of the fifth conductive trace on the substrate.

[0032] Optionally, the fan-out lead comprises: a first lead segment and a second lead segment connected with each other; the first lead segment extends along the first direction, and the second lead segment extends along the second direction.

[0033] The first lead segment and the fourth conductive trace are arranged in the same layer and are made of the same material, and the second lead segment and the fifth conductive trace are arranged in the same layer and are made of the same material.

[0034] Optionally, the display area is rectangular and has four corner regions.

[0035] The part of the third power signal line towards the corner region has a stepped structure, and the stepped structure is distributed around the corner region.

[0036] Optionally, the display panel further comprises a first conductive part in the non-display area; in a direction perpendicular to the substrate, the first conductive part is located on a side of the at least two power signal lines away from the substrate.

[0037] The at least two power signal lines comprise a first power signal line, a projection of the first power signal line on the substrate intersects with a projection of the gate driving circuit on the substrate; and the first conductive part is overlapped with the first power signal line.

[0038] Optionally, the sub-pixel comprises a pixel driving circuit and a light emitting device, the pixel driving circuit is located on a side of the substrate, and the light emitting device is located on a side of the pixel driving circuit away from the substrate and is electrically connected with the pixel driving circuit.

[0039] The first conductive part is arranged in the same layer as an anode of the light emitting device and is made of the same material.

[0040] Optionally, the at least two power signal lines further comprise a second power signal line, in a direction parallel to the substrate, the first power signal line is closer to the display area than the second power signal line; and the first conductive part is further overlapped with the second power signal line.

[0041] Optionally, the second power signal line comprises a first sub-power line and a second sub-power line arranged in a direction perpendicular to the substrate, the first sub-power line is closer to the substrate than the second sub-power line, and the first sub-power line is overlapped with the second sub-power line.

[0042] The second sub-power line is arranged in the same layer as the first power signal line and is made of the same material.

[0043] Optionally, the sub-pixel comprises a pixel driving circuit and a light emitting device, the pixel driving circuit is located on a side of the substrate, and the light emitting device is located on a side of the pixel driving circuit away from the substrate and is electrically connected with the pixel driving circuit.

[0044] The at least two power signal lines are electrically connected to cathodes of the respective light emitting devices.

[0045] In another aspect, a display device is provided, comprising: a display panel as any of the above described display panels, and a flexible circuit board, which is bonded to the non-display area and electrically connected to the at least two power signal lines. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0047] FIG. 1 is a structural schematic diagram of a display panel;

[0048] FIG. 2 is another structural schematic diagram of a display panel;

[0049] FIG. 3 is a schematic diagram of the film layer of the display panel shown in FIG. 1 at A-A';

[0050] FIG. 4 is a structural schematic diagram of a display panel provided by an embodiment of the present application;

[0051] FIG. 5 is another structural schematic diagram of a display panel provided by an embodiment of the present application;

[0052] FIG. 6 is a schematic diagram of the film layer of the display panel shown in FIG. 4 at B-B';

[0053] FIG. 7 is a partitioning schematic diagram of a non-display area of a display panel provided by an embodiment of the present application;

[0054] FIG. 8 is a structural schematic diagram of another display panel provided by an embodiment of the present application;

[0055] FIG. 9 is another structural schematic diagram of another display panel provided by an embodiment of the present application;

[0056] FIG. 10 is a structural schematic diagram of yet another display panel provided by an embodiment of the present application;

[0057] FIG. 11 is another structural schematic diagram of yet another display panel provided by an embodiment of the present application;

[0058] FIG. 12 is a structural schematic diagram of a display panel provided by another embodiment of the present application;

[0059] FIG. 13 is another structural schematic diagram of a display panel provided by another embodiment of the present application;

[0060] FIG. 14 is a structural schematic diagram of a display panel according to another embodiment of the present application;

[0061] FIG. 15 is a partial enlarged schematic diagram of the area A in FIG. 13;

[0062] FIG. 16 is a structural schematic diagram of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0063] In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0064] In the related art, the ELVSS signal line of the display panel is generally set to be long, and there is a problem of voltage drop in the product lighting process, so that the voltage applied by the light emitting device deviates from the preset voltage, and the voltage deviation between multiple light emitting devices is different, the lighting brightness of the OLED panel is reduced, thereby leading to poor brightness uniformity of the OLED panel.

[0065] In order to reduce the voltage drop of the ELVSS signal line, the line width of the ELVSS signal line is generally increased outside the display area of the display panel to reduce the impedance of the ELVSS signal line, thereby reducing the voltage drop of the ELVSS signal line with the increase of the length. However, with the current design of full screen, the requirement for the frame width of the OLED product is becoming narrower and narrower, therefore, the upper limit of the line width of the ELVSS signal line is limited by the demand of narrow frame, and the brightness uniformity of the OLED panel will be poor with the design of narrow frame of the product.

[0066] Please refer to FIGS. 1-3, FIG. 1 is a structural schematic diagram of a display panel, FIG. 2 is another structural schematic diagram of a display panel, and FIG. 3 is a schematic diagram of the film layer of the display panel shown in FIG. 1 at A-A'. As shown in FIG. 1, the display panel 00 has a display area 00a and a non-display area 00b located at the periphery of the display area 00a, and the part of the display panel 00 in the non-display area 00b can include a cathode power signal line 01 (ELVSS signal line).

[0067] For ease of description, FIG. 2 does not show signal lines other than the cathode power signal line 01 and the bonding structure 03. In the related art, the display panel 00 has a cathode power signal line 01 arranged in a ring shape in the non-display area 00b. As shown in FIGS. 1 and 3, the display panel 00 can further include a first conductive part 02 and a bonding structure 03, such as a bonding hole or a bonding groove, for bonding the first conductive part 02 to the cathode power signal line 01. The first conductive part 02 can be electrically connected to the cathode of the light emitting device in the display area 00a through the second conductive part 04. The cathode power signal line 01 is farther away from the display area 00a than the gate driving circuit 05. The distance between the cathode power signal line 01 and the edge of the substrate 00c is limited by the narrow frame of the display panel, and a preset threshold value is provided. The distance between the cathode power signal line 01 and the edge of the substrate 00c cannot be less than the threshold value. The distance between the cathode power signal line 01 and the edge of the substrate 00c is generally 100 μm to 200 μm.

[0068] As shown in FIG. 3, the display panel 00 can further include a plurality of layers of insulating layers 06 and a plurality of layers of conductive layers arranged alternately. The plurality of layers of insulating layers 06 can include an organic planarization layer, a pixel definition layer, and the like. The plurality of layers of conductive layers can be patterned to obtain the cathode power signal line 01, the first conductive part 02, and the second conductive part 04. The first conductive part 02 can be in the same layer of conductive layer as the anode of the light emitting device, and the second conductive part 04 can be in the same layer of conductive layer as the cathode of the light emitting device. It should be noted that the above is only an example for illustrating the film layer structure of the display panel 00 in the non-display area 00b, and is not intended to limit the specific structure of the display panel 00 described in the present application.

[0069] To reduce the voltage drop of the ELVSS signal line, the line width of the ELVSS signal line is generally increased outside the display area of the display panel to reduce the resistance of the ELVSS signal line, thereby improving the brightness uniformity of the display panel and reducing power consumption. However, the wider ELVSS signal line outside the display area occupies a larger frame of the display panel. As the size and display brightness of the display panel further increase, a sufficient ELVSS signal line width is required to bear the required large current. The narrow frame and low power consumption, high brightness uniformity become the contradictory points of the ELVSS signal line width.

[0070] At present, the cathode power supply signal line 01 arranged outside the gate drive circuit 05 can be a double-layer structure, and the cathode power supply signal line 01 can include a first sub-power line 01a and a second sub-power line 01b arranged in a third direction Z. In this way, the width of the cathode power supply signal line 01 in the first direction X can be reduced. However, even if the double-layer wiring is used, the above-mentioned voltage drop problem cannot be effectively improved. The third direction Z is a direction perpendicular to the substrate 00c, the first direction X is a direction parallel to the substrate 00c, and the second direction Y intersects the first direction X, for example, is perpendicular.

[0071] In addition, the ELVDD signal line also has a voltage drop, which is smaller than that of the ELVSS signal line, but also affects the panel brightness uniformity of the display panel.

[0072] To overcome the above technical problems, the display panel and display device provided by the embodiments of the present application can reduce the voltage drop of the power supply signal line and improve the brightness uniformity of the display panel and reduce power consumption by arranging at least two parallel power supply signal lines in the non-display area.

[0073] The display panel provided by the embodiments of the present application is described below with reference to FIGS. 4-7. FIG. 4 is a structural schematic diagram of a display panel provided by the embodiments of the present application, FIG. 5 is another structural schematic diagram of a display panel provided by the embodiments of the present application, FIG. 6 is a film layer schematic diagram of the display panel shown in FIG. 4 at B-B', and FIG. 7 is a partition schematic diagram of a non-display area of a display panel provided by the embodiments of the present application. The display panel 000 has a display area 000a and a non-display area 000b located at the periphery of the display area 000a. The display panel 000 can include a substrate 000c, a plurality of sub-pixels, a gate drive circuit 005, and at least two power supply signal lines 001.

[0074] The plurality of sub-pixels are located on one side of the substrate 000c and distributed in the display area 000a.

[0075] The gate drive circuit 005 is located on one side of the substrate 000c and located in the non-display area 000b. The gate drive circuit 005 is electrically connected to at least part of the sub-pixels.

[0076] The at least two power supply signal lines 001 are in parallel and distributed in the non-display area 000b. The at least two power supply signal lines 001 are electrically connected to at least part of the plurality of sub-pixels.

[0077] At least one of the at least two power supply signal lines 001 in the substrate 000c is in the orthographic projection of the gate drive circuit 005 on the substrate 000c.

[0078] In some possible implementation manners, the number of power signal lines 001 can be multiple, such as three, four, five, or the like. As shown in FIGS. 4-6, the at least two power signal lines 001 can include a first power signal line 001a, and at least one of a second power signal line 001b and a third power signal line 001c.

[0079] For example, as shown in FIG. 7, the display panel 000 provided in the embodiments of the present application can include, in the non-display area 000b, two first sub-areas 100a arranged opposite to each other in a first direction X, and a second sub-area 100b and a third sub-area 100c arranged opposite to each other in a second direction Y. The non-display area 000b can further include a binding area 101c located on a side of the third sub-area 100c away from the display area 000a in the second direction Y. The first direction X intersects the second direction Y, for example, the first direction X is perpendicular to the second direction Y. The display panel 000 is connected to a circuit board such as a flexible circuit board 201 that can supply power through the binding area 101c, and the at least two power signal lines 001 are connected to an external power supply circuit in the third sub-area 100c. For ease of description, the signal lines other than the power signal lines 001 and the bonding structure 003 in FIG. 4 are not shown in FIG. 5. The at least two power signal lines 001 are distributed in the non-display area 000b, and are at least connected in parallel in the third sub-area 100c.

[0080] As shown in FIG. 6, the display panel 000 can further include a plurality of layers of insulating layers 006 and a plurality of layers of conductive layers arranged alternately. The plurality of layers of insulating layers 006 can include an organic planarization layer, a pixel definition layer, and the like. After the plurality of layers of conductive layers are subjected to a patterning process, the power signal lines 001, the first conductive portions 002, and the second conductive portions 004 can be obtained. The first conductive portions 002 can be located in the same layer of conductive layer as the anode of the light-emitting device, and the second conductive portions 004 can be located in the same layer of conductive layer as the cathode of the light-emitting device. It should be noted that the above is only an example for illustration, and is not intended to limit the specific structure of the display panel 000 described in the present application.

[0081] It can be seen that, compared with the display panel 00 shown in FIGS. 1-3, the width of the cathode power signal line 01 in the first direction X is limited by the product demand for narrow frames, and the line width cannot be increased. In the embodiments of the present application, as shown in FIG. 6, the first power signal line 001a can be arranged above the gate driving circuit 005; or the first power signal line 001a is arranged above the gate driving circuit 005, and the third power signal line 001c is arranged on a side of the gate driving circuit 005 facing the display area 000a. In this way, the overall resistance of the power signal line 001 can be reduced.

[0082] It should be noted that in FIG. 6, the positional relationship between the gate drive circuit 005 and the at least two power signal lines 001 is schematically shown in a simple structure. In fact, part of the circuit in the gate drive circuit 005 can also be distributed in the same conductive layer as the first power signal line 001a, but the orthographic projection of the first power signal line 001a on the substrate 000c at least partially overlaps the orthographic projection of the gate drive circuit 005.

[0083] The display panel provided by the embodiment of the present application is characterized in that the orthographic projection of at least one of the at least two power signal lines on the substrate overlaps the orthographic projection of the gate drive circuit on the substrate, that is, in the third direction, the at least one power signal line is located on the side of the gate drive circuit away from the substrate. In this way, the total width or total cross-sectional area of the power signal line can be increased, and a power signal line with a large width does not need to be arranged on the side of the gate drive circuit away from the display area. Therefore, the resistance of the power signal line can be reduced in a parallel manner under the condition of ensuring a narrow frame, thereby reducing the voltage drop of the power signal line and improving the brightness uniformity of the display panel and reducing power consumption.

[0084] For example, in the display panel 000 provided by the embodiment of the present application, the distance between all the power signal lines 001 and the edge of the substrate 000c is not less than a preset threshold. The preset threshold is set according to the distance between the ELVSS wire of the display panel and the edge of the substrate of the display panel, for example, is not less than 100 μm-200 μm. That is, the embodiment of the present application increases the parallelly connected power signal lines 001 between the outer edge of the display area 000a and the preset threshold, thereby reducing the voltage drop of the power signal line 001 and realizing the narrow frame requirement of the display panel 000.

[0085] It should be noted that the embodiment of the present application does not limit the power signal line 001 to be necessarily a cathode power signal line, but can also be an anode power signal line.

[0086] In a possible implementation, referring to FIG. 8 and FIG. 9, FIG. 8 is a structural schematic diagram of another display panel provided by the embodiment of the present application, and FIG. 9 is another structural schematic diagram of another display panel provided by the embodiment of the present application. The at least two power signal lines 001 can include a first power signal line 001a and a second power signal line 001b. In the direction parallel to the substrate 000c, the first power signal line 001a is closer to the display area 000a than the second power signal line 001b. The orthographic projection of the first power signal line 001a on the substrate 000c overlaps the orthographic projection of the gate drive circuit 005 on the substrate 000c.

[0087] As shown in FIG. 7, the first power signal line 001a can be connected to the first conductive part 002 through the first connecting structure 003a, and the second power signal line 001b can be connected to the first conductive part 002 through the second connecting structure 003b. That is, compared with the display panel 000 shown in FIGS. 4-5, the display panel 000 shown in FIGS. 8-9 does not include the third power signal line 001c located on the side of the gate driving circuit 005 facing the display area 000a. The connection between the first power signal line 001a and the first conductive part 002 is achieved through the first connecting structure 003a, so that the connecting structure does not need to be additionally arranged on the outer side of the gate driving circuit 005, and the width of the frame is not increased, thereby meeting the requirement of narrow frame.

[0088] For ease of description, the signal lines and the connecting structures 003 other than the power signal lines 001 shown in FIG. 8 are not shown in FIG. 9. In the embodiment, the second power signal line 001b is farther away from the display area 000a than the gate driving circuit 005, and the first power signal line 001a is closer to the display area 000a than the second power signal line 001b. In this way, the resistance of the power signal line 001 can be reduced by connecting the first power signal line 001a and the second power signal line 001b in parallel, thereby effectively reducing the voltage drop and ensuring the uniformity of light emission of the display panel 000.

[0089] For example, the distance between the first power signal line 001a and the edge of the substrate 000c is greater than 100 μm-200 μm, and the distance between the second power signal line 001b and the edge of the substrate 000c is equal to 100 μm-200 μm. By connecting the first power signal line 001a in parallel with the second power signal line 001b between the outer edge of the display area 000a and the second power signal line 001b, the resistance can be reduced, thereby reducing the voltage drop of the power signal line 001, improving the brightness uniformity of the display panel 000, and reducing power consumption.

[0090] In a possible implementation, referring to FIG. 9, the display panel 000 can further include a plurality of first conductive traces 007 distributed in the non-display area 000b. One end of the plurality of first conductive traces 007 is electrically connected to the first power signal line 001a, and the other end of the plurality of first conductive traces 007 is electrically connected to the second power signal line 001b.

[0091] As shown in FIG. 9, between the first power signal line 001a and the second power signal line 001b, the parallel area or parallel point of the first power signal line 001a and the second power signal line 001b can be increased by arranging a plurality of first conductive traces 007, so as to further improve the integrity of the power signal in the non-display area 000b of the display panel 000, thereby further reducing the voltage drop problem of the power signal line 001.

[0092] In a possible implementation, referring to FIGS. 10-11, FIG. 10 is a structural schematic diagram of another display panel provided by an embodiment of the present application, and FIG. 11 is another structural schematic diagram of another display panel provided by an embodiment of the present application. The at least two power signal lines 001 can include a first power signal line 001a and a third power signal line 001c.

[0093] In a direction parallel to the substrate 000c, the third power signal line 001c is closer to the display area 000a than the first power signal line 001a, and the orthogonal projection of the first power signal line 001a on the substrate 000c overlaps with the orthogonal projection of the gate driving circuit 005 on the substrate 000c.

[0094] That is, compared with the display panel 000 shown in FIGS. 4-5, in FIGS. 10-11, the display panel 000 does not include the second power signal line 001b located on the side of the gate driving circuit 005 away from the display area 000a.

[0095] For ease of description, the signal lines and the lapping structure 003 other than the power signal line 001 in FIG. 10 are not shown in FIG. 11. In the embodiment of the present application, the third power signal line 001c is closer to the display area 000a than the gate driving circuit 005, and the first power signal line 001a is closer to the display area 000a than the second power signal line 001b. In this way, by parallel connection of the first power signal line 001a and the third power signal line 001c, compared with a single second power signal line 001b, the resistance of the power signal line 001 can be reduced, the voltage drop problem can be effectively reduced, and the uniformity of light emission of the display panel 000 can be ensured. In the embodiment of the present application, the second power signal line 001b is not arranged, so that the distance between the gate driving circuit 005 and the edge of the non-display area 000b can be set to be narrower, thereby further narrowing the frame of the display panel 000.

[0096] For example, the distance between the first power signal line 001a and the edge of the substrate 000c is greater than 100 μm to 200 μm, the distance between the third power signal line 001c and the edge of the substrate 000c is greater than the distance between the first power signal line 001a and the edge of the substrate 000c, compared with the display panel 000 shown in FIG. 4, the second power signal line 001b is cancelled, and the third power signal line 001c connected in parallel is added between the first power signal line 001a of the display panel 000 and the outer edge of the display area 000a, thereby further saving the frame, and the voltage drop of the power signal line 001 can be reduced, the brightness uniformity of the display panel 000 is improved, and the power consumption is reduced.

[0097] In a possible implementation, referring to FIGS. 10 to 11, the display panel 000 can further include a plurality of second conductive traces 008 distributed in the non-display area 000b; one end of the plurality of second conductive traces 008 is electrically connected to the first power signal line 001a, and the other end of the plurality of second conductive traces 008 is electrically connected to the third power signal line 001c.

[0098] As shown in FIG. 11, between the first power signal line 001a and the third power signal line 001c, the parallel area or parallel point of the first power signal line 001a and the third power signal line 001c can be increased by arranging the plurality of second conductive traces 008, thereby further improving the integrity of the power signal in the non-display area 000b of the display panel 000, and the voltage drop problem of the power signal line 001 can be further reduced.

[0099] In a possible implementation, referring to FIGS. 4 to 6 and FIGS. 12 to 13, FIG. 12 is a structural schematic diagram of a display panel provided by another embodiment of the present application; and FIG. 13 is another structural schematic diagram of a display panel provided by another embodiment of the present application. The at least two power signal lines 001 can include a first power signal line 001a, a second power signal line 001b, and a third power signal line 001c.

[0100] In a direction parallel to the substrate 000c, the second power signal line 001b is farther away from the display area 000a than the first power signal line 001a, and the third power signal line 001c is closer to the display area 000a than the first power signal line 001a; and the orthogonal projection of the first power signal line 001a on the substrate 000c intersects with the orthogonal projection of the gate driving circuit 005 on the substrate 000c.

[0101] Exemplarily, when the number of power signal lines 001 is 3, the position of the first power signal line 001a is arranged as described above, the second power signal line 001b is farther away from the display area 000a than the first power signal line 001a, and the third power signal line 001c is closer to the display area 000a than the first power signal line 001a. That is, the first power signal line 001a is respectively provided with the third power signal line 001c and the second power signal line 001b on the inner side and the outer side of the first power signal line 001a. Under the premise of maintaining the existing process, by arranging three parallelly connected power signal lines 001 in the non-display area 000b, the resistance is further reduced, and thus the voltage drop of the power signal line 001 can be further reduced, and the brightness uniformity of the display panel 000 and the power consumption can be improved.

[0102] The layout mode of the power signal line 001 in the display panel 000 provided by the embodiment of the present application can reduce the resistance and power consumption of the power signal line 001 and improve the brightness uniformity of the display panel 000 while reducing the frame occupation by using the partitioned wiring without changing the existing process and without increasing the punching process.

[0103] For ease of description, the signal lines other than the power signal line 001 and the lapping structure 003 in FIG. 12 are not shown in FIG. 13.

[0104] Exemplarily, the non-display area 000b can include two first partitions 100a arranged opposite to each other in the first direction X, and a second partition 100b and a third partition 100c arranged opposite to each other in the second direction Y. The non-display area 000b can further include a binding area 101c located on the side of the third partition 100c away from the display area 000a in the second direction Y. The first direction X intersects the second direction Y.

[0105] The second power signal line 001b and the third power signal line 001c are distributed in at least two first partitions 100a and a second partition 100b, and the first power signal line 001a is distributed in at least two first partitions 100a. As shown in FIG. 7 and FIG. 13, the first power signal line 001a is distributed in two first partitions 100a and a third partition 100c, and the second power signal line 001b and the third power signal line 001c are distributed in at least two first partitions 100a, a second partition 100b and a third partition 100c.

[0106] In a possible implementation, the display panel 000 can further include the plurality of first conductive traces 007, the plurality of second conductive traces 008, and a plurality of third conductive traces 009 distributed in the second subregion 100b; one end of the plurality of third conductive traces 009 is electrically connected to the second power signal line 001b, and the other end of the plurality of third conductive traces 009 is electrically connected to the third power signal line 001c.

[0107] As shown in FIG. 13, between the second power signal line 001b and the third power signal line 001c, the parallel area or parallel point of the second power signal line 001b and the third power signal line 001c can be increased by arranging the plurality of third conductive traces 009, so as to further reduce the voltage drop problem of the power signal line 001.

[0108] In a possible implementation, referring to FIG. 12 and FIG. 13, the first power signal line 001a, the second power signal line 001b, and the third power signal line 001c are all distributed in the third subregion 100c; the display panel 000 can further include a first connecting segment 012 and / or a second connecting segment 013 distributed in the third subregion 100c.

[0109] The first connecting segment 012 extends in the first direction X, and in the second direction Y, the first power signal line 001a and the second power signal line 001b are connected on the two sides of the first connecting segment 012.

[0110] The second connecting segment 013 extends in the first direction X, and in the second direction Y, the first power signal line 001a and the third power signal line 001c are connected on the two sides of the second connecting segment 013.

[0111] Through the first connecting segment 012 and / or the second connecting segment 013, the parallel area of the first power signal line 001a, the second power signal line 001b, and the third power signal line 001c in the third subregion 100c can be increased, so as to reduce the voltage drop problem of the power signal line 001.

[0112] In a possible implementation, referring to FIG. 10 and FIG. 12 to FIG. 13, the display panel 000 can further include a plurality of fourth conductive traces 010 and a plurality of fifth conductive traces 011 distributed in the display area 000a.

[0113] The fourth conductive trace 010 extends along the first direction X, and two ends of the fourth conductive trace 010 are connected with portions of the third power signal line 001c distributed in the two first sub-areas 100a, respectively. The fifth conductive trace 011 extends along the second direction Y, and two ends of the fifth conductive trace 011 are connected with portions of the third power signal line 001c distributed in the second sub-area 100b and the third sub-area 100c, respectively.

[0114] Alternatively, referring to FIGS. 8 and 9, the fourth conductive trace 010 extends along the first direction X, and two ends of the fourth conductive trace 010 are connected with portions of the first power signal line 001a distributed in the two first sub-areas 100a, respectively. The fifth conductive trace 011 extends along the second direction Y, and two ends of the fifth conductive trace 011 are connected with portions of the first power signal line 001a distributed in at least one of the second sub-area 100b and the third sub-area 100c, respectively.

[0115] The fourth conductive trace 010 and the fifth conductive trace 011 are arranged in different layers, or the fourth conductive trace 010 and the fifth conductive trace 011 are arranged in the same layer and are made of the same material.

[0116] The fourth conductive trace 010 and the fifth conductive trace 011 form a mesh structure, and the mesh structure capable of transmitting the power signal is arranged in the display area 000a, so that the parallel connection effect between the power signal lines 001 is further improved, and the voltage drop of the power signal line 001 is further reduced.

[0117] For example, as shown in FIGS. 8 to 13, a plurality of fourth conductive traces 010 are connected in parallel with the first power signal line 001a or the third power signal line 001c, and a plurality of fifth conductive traces 011 are connected in parallel with the first power signal line 001a or the third power signal line 001c. The current is shared by the plurality of fourth conductive traces 010 and the plurality of fifth conductive traces 011, so that the resistance of the power signal line 001 is further reduced, the voltage drop of the power signal line 001 is greatly reduced, the brightness uniformity of the display panel 000 is improved, and the power consumption is reduced. The plurality of fifth conductive traces 011 are arranged in the display area 000a, and do not occupy the non-display area 000b of the display panel 000, which is beneficial to the narrow frame design requirement of the display panel 000.

[0118] Exemplarily, the sub-pixel can include: a pixel driving circuit and a light emitting device, the pixel driving circuit is located on one side of the substrate 000c, and the light emitting device is located on the side of the pixel driving circuit away from the substrate 000c and is electrically connected with the pixel driving circuit. Wherein, the plurality of sub-pixels are arranged in a plurality of rows and a plurality of columns in the display area 000a along the first direction X and the second direction Y, so that one sub-pixel can be distributed in one grid of the mesh structure formed by the fourth conductive trace 010 and the fifth conductive trace 011, and the mesh structure can be located on the side of the light emitting device facing the substrate 000c, and is arranged in the same layer as one or two conductive parts in the pixel driving circuit, for example, is arranged in the same layer as the source / drain of the transistor in the pixel driving circuit. Further, one fourth conductive trace 010 can be distributed between two rows of sub-pixels, and one fifth conductive trace 011 can be distributed between two columns of sub-pixels, so as not to affect the arrangement of the pixel driving circuit of the sub-pixel and the light emission of the light emitting device.

[0119] In addition, in the case that the display panel 000 includes the fourth conductive trace 010 and the fifth conductive trace 011, as shown in FIGS. 8 to 13, between any two of the first power signal line 001a, the second power signal line 001b and the third power signal line 001c, the first conductive trace 007, the second conductive trace 008 and the third conductive trace 009 in the above embodiments can be selectively arranged, and the specific arrangement can be referred to the related description of the above embodiments. The main purpose is to improve the parallel effect between at least two power signal lines 001 by more conductive traces, and reduce the resistance of the power signal line 001.

[0120] In a possible implementation, please refer to FIG. 14, which is a structural schematic diagram of a display panel provided by another embodiment of the present application. The display panel 000 can further include: a plurality of data signal lines and a plurality of fan-out leads 014 distributed in the display area 000a; a plurality of sub-pixels arranged in a plurality of columns in the first direction X; one data signal line is electrically connected with one column of sub-pixels, and at least part of the plurality of data signal lines are electrically connected with the plurality of fan-out leads 014 correspondingly.

[0121] Wherein, the fan-out lead 014 is not overlapped with the fourth conductive trace 010 and the fifth conductive trace 011 in the orthographic projection of the substrate 000c.

[0122] In the embodiments of the present application, for the display panel 000 in which the fan-out lead 014 is arranged in the display area 000a, in the case where the fourth conductive trace 010 and the fifth conductive trace 011 are arranged in the display area 000a, the fan-out lead 014 can be arranged separately from the fourth conductive trace 010 and the fifth conductive trace 011, so that the fan-out lead 014 does not form a visible mura problem in the display area 000a.

[0123] It should be noted that in FIG. 14, in order to show the fan-out lead 014, the fourth conductive trace 010 and the fifth conductive trace 011 are distinguished by different sizes, but this is not a limitation on the specific size or distribution shape of the fan-out lead 014. That is, the pitch of the plurality of fan-out leads 014 in the first direction X or the second direction Y can be the same as or different from the pitch of the fourth conductive trace 010 or the fifth conductive trace 011.

[0124] For example, the fan-out lead 014 can include a first lead segment 014a and a second lead segment 014b connected to each other, the first lead segment 014a extends in the first direction X, and the second lead segment 014b extends in the second direction Y.

[0125] The first lead segment 014a and the fourth conductive trace 010 are arranged in the same layer and are made of the same material, and the second lead segment 014b and the fifth conductive trace 011 are arranged in the same layer and are made of the same material.

[0126] As shown in FIG. 6, the display panel 000 can include four conductive layers arranged in layers, which can be referred to as a first conductive layer (SD1), a second conductive layer (SD2), an anode conductive layer, and a cathode conductive layer, wherein the first conductive layer is closer to the substrate 000c. After the patterning process, each conductive layer forms structures such as the gate driving circuit 005, the pixel driving circuit, the cathode and anode of the light emitting device, etc. The fourth conductive trace 010 can be located in the first conductive layer, and the fifth conductive trace 011 can be located in the second conductive layer. The first power signal line 001a and the third power signal line 001c can be located in the second conductive layer, and the second power signal line 001b can be partially located in the first conductive layer and partially located in the second conductive layer. The anode of the light emitting device can be located in the anode conductive layer, and the cathode can be located in the cathode conductive layer. It should be noted that the above is only an example of a display panel 000 that can be implemented, and does not exclude the case where five or six conductive layers can be included, in which case the arrangement of each signal line and trace can be set according to the specific product.

[0127] In a possible implementation, please refer to FIG. 13 and FIG. 15, FIG. 15 is a partial enlarged view of the A area in FIG. 13, the display area 000a is rectangular and has four corner areas.

[0128] The portion of the third power signal line 001c facing the corner region has a stepped structure 0011, which is distributed around the corner region.

[0129] As shown in Figures 4 to 6 and Figures 10 to 14, when at least two power signal lines 001 include the aforementioned third power signal line 001c, the third power signal line 001c is distributed around the display area 000a. Furthermore, when the display area 000a has rounded corners, corresponding to the stepped arrangement of sub-pixels in the corner region of the display area 000a, the third power signal line 001c is provided with a corresponding matching stepped structure 0011, distributed around the corner region. This allows for the use of the area outside the display area 000a to arrange a larger area of ​​the third power signal line 001c. In this way, the voltage drop problem of the power signal line 001 can be further reduced.

[0130] In one possible implementation, referring to Figures 4 to 14, the display panel 000 may further include: a first conductive portion 002 located within the non-display area 000b; in a direction perpendicular to the substrate 000c, the first conductive portion 002 is located on the side of at least two power signal lines 001 facing away from the substrate 000c.

[0131] Among them, at least two power signal lines 001 may include a first power signal line 001a, the orthographic projection of the first power signal line 001a on the substrate 000c overlaps with the orthographic projection of the gate drive circuit 005 on the substrate 000c; the first conductive part 002 is connected to the first power signal line 001a.

[0132] In this embodiment, a power signal is transmitted via the first power signal line 001a, which is connected to the first conductive part 002. The connection structure 003 between the first power signal line 001a and the first conductive part 002 is the first connection structure 003a.

[0133] For example, a sub-pixel may include a pixel driving circuit and a light-emitting device, wherein the pixel driving circuit is located on one side of the substrate 000c, and the light-emitting device is located on the side of the pixel driving circuit opposite to the substrate 000c and is electrically connected to the pixel driving circuit.

[0134] The first conductive part 002 is disposed in the same layer as the anode of the light-emitting device and is made of the same material.

[0135] In other words, by patterning the anode conductive layer, a first conductive part 002 can be formed in the non-display area 000b, which can then be used for signal line splicing.

[0136] In a possible implementation, referring to FIGS. 4 to 9 and FIGS. 12 to 14, the at least two power signal lines 001 can further include a second power signal line 001b, the first power signal line 001a is closer to the display area 000a than the second power signal line 001b in a direction parallel to the substrate 000c; and the first conductive part 002 further overlaps the second power signal line 001b.

[0137] In the embodiment of the present application, the second power signal line 001b is overlapped with the first conductive part 002, so that the power signal can be transmitted through the second power signal line 001b. The overlapping structure 003 between the second power signal line 001b and the first conductive part 002 is a second overlapping structure 003b.

[0138] For example, as shown in FIG. 6, in the embodiment of the present application, the second power signal line 001b can include a first sub-power line and a second sub-power line which are stacked in a direction perpendicular to the substrate 000c, the first sub-power line is closer to the substrate 000c than the second sub-power line, and the first sub-power line overlaps the second sub-power line.

[0139] The second sub-power line is arranged in the same layer as the first power signal line 001a and is made of the same material.

[0140] In a possible implementation, referring to FIGS. 4 to 14, the sub-pixel can include a pixel driving circuit and a light emitting device, the pixel driving circuit is located on one side of the substrate 000c, the light emitting device is located on a side of the pixel driving circuit away from the substrate 000c and is electrically connected to the pixel driving circuit; and the at least two power signal lines 001 are electrically connected to cathodes of the respective light emitting devices.

[0141] That is, the power signal line 001 provided by the embodiment of the present application can be used to transmit the cathode power signal, so as to overcome the problem of voltage drop caused by long transmission distance of the cathode power signal line 01.

[0142] For example, the distance between the first power signal line 001a and the outer edge of the substrate 000c can be 400 μm to 600 μm. The distance between the third power signal line 001c and the outer edge of the substrate 000c can be 600 μm to 1000 μm. The distance between the second power signal line 001b and the outer edge of the substrate 000c can be 100 μm to 200 μm.

[0143] For example, the distance between the first power signal line 001a and the outer edge of the substrate 000c is 400-600 μm, for example, 400 μm, 420 μm, 450 μm, 500 μm, 530 μm, 550 μm, 580 μm, 600 μm, or a range formed by any of the above values. The distance between the third power signal line 001c and the outer edge of the substrate 000c can be 600-1000 μm, for example, 600 μm, 650 μm, 700 μm, 750 μm, 800 μm, 850 μm, 900 μm, 950 μm, 1000 μm, or a range formed by any of the above values. The third power signal line 001c and the first power signal line 001a are sequentially arranged from inside to outside. The position layout of the first power signal line 001a and the third power signal line 001c provided in the embodiments of the present application can achieve the narrow frame design requirement of the display panel 000, and can reduce the resistance of the power signal line 001, thereby reducing the voltage drop of the power signal line 001, improving the brightness uniformity of the display panel 000, and reducing power consumption. The distance between the second power signal line 001b and the outer edge of the substrate 000c can be 100-200 μm, for example, 100 μm, 130 μm, 150 μm, 170 μm, 200 μm, or a range formed by any of the above values. The second power signal line 001b and the first power signal line 001a are sequentially arranged from outside to inside. The position layout of the first power signal line 001a and the second power signal line 001b provided in the embodiments of the present application can reduce the resistance of the power signal line 001, thereby reducing the voltage drop of the power signal line 001, improving the brightness uniformity of the display panel 000, and reducing power consumption.

[0144] Compared with the ELVSS wiring scheme of the display panel 00 shown in FIGS. 1-3, the voltage drop of the display panel 000 provided in any of the embodiments of the present application can be reduced by 0.5-1.5 V, and the LRU (Long Range Uniformity) can be improved by 1-5%.

[0145] In summary, the display panel provided by the embodiments of the present application has at least two power supply signal lines in parallel in the non-display area, at least one of the at least two power supply signal lines has a projection on the substrate that overlaps with a projection of the gate drive circuit on the substrate, that is, in the third direction, the at least one power supply signal line is located on the side of the gate drive circuit away from the substrate. In this way, the total width or total cross-sectional area of the power supply signal line can be increased, and a signal line with a large width does not need to be arranged on the side of the gate drive circuit away from the display area. Therefore, the resistance of the power supply signal line can be reduced in a parallel manner under the condition of ensuring a narrow frame, thereby reducing the voltage drop of the power supply signal line, improving the brightness uniformity of the display panel, and reducing power consumption.

[0146] The embodiments of the present application also provide a display device. Referring to FIG. 16, FIG. 16 is a structural schematic diagram of a display device provided by the embodiments of the present application. The display device 200 can include a display panel 000 and a flexible circuit board 201. The display panel 000 is the display panel 000 described in any of the above embodiments. The flexible circuit board 201 is bound to the non-display area 000b and is electrically connected to the at least two power supply signal lines 001.

[0147] In the embodiments of the present application, the display panel 000 is a display substrate for realizing a display image (i.e., a picture) function. The display device 200 can include a display or a product containing a display. The display can be a flat panel display (FPD), a micro display, etc. If divided according to whether a user can see the back of the display, the display can be a transparent display or an opaque display. If divided according to whether the display can be bent or rolled, the display can be a flexible display or a normal display (which can be referred to as a rigid display). The display device 200 can be a display screen in a display device such as a mobile phone, a tablet computer, a notebook computer, a display, a smart television, etc. The display device 200 can also have the technical effects of the display panel 000 described above, which will not be described again here.

[0148] In some other embodiments of the present application, the display device 200 can be a lighting device, in which case the display device 200 is used as a light source to realize a lighting function. For example, the display device 200 can be a backlight module in a liquid crystal display device, a lamp for internal or external lighting, or various signal lights, etc.

[0149] It is to be understood that the figures illustrate the concept, and that for clarity's sake the size of layers and regions can have been exaggerated. It is to be further understood that, when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer, or intervening layers can also be present. Furthermore, it can be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or layer, or one or more intervening layers or elements can also be present. In addition, it can be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer or element between the two layers or elements, or one or more intervening layers or elements can also be present. Similar reference characters do not indicate similar elements throughout the several views.

[0150] In this application, the terms "first" and "second" are used only for descriptive purposes and are not to be taken literally or to imply relative importance. The term "plurality" means two or more, unless expressly specified otherwise.

[0151] The embodiments of methods, hardware, and / or software described herein can be modified or combined in various ways. The above description is that of certain examples of implementations of the application. However, the scope of the application is not limited to the specific described embodiments, but rather only by the claims.

Claims

1. A display panel, characterized by, The display panel has a display area and a non-display area located at the periphery of the display area; the display panel comprises a substrate, a plurality of sub-pixels, a gate drive circuit and at least two power signal lines; The plurality of sub-pixels are located on one side of the substrate and distributed in the display area; The gate drive circuit is located on one side of the substrate and located in the non-display area; the gate drive circuit is electrically connected with at least part of the sub-pixels; The at least two power signal lines are in parallel and distributed in the non-display area; the at least two power signal lines are electrically connected with at least part of the plurality of sub-pixels; The orthogonal projection of at least one of the at least two power signal lines on the substrate and the orthogonal projection of the gate drive circuit on the substrate overlap.

2. The display panel according to claim 1, characterized in that, The at least two power signal lines comprise a first power signal line and a second power signal line; in the direction parallel to the substrate, the first power signal line is closer to the display area than the second power signal line; the orthogonal projection of the first power signal line on the substrate and the orthogonal projection of the gate drive circuit on the substrate overlap.

3. The display panel of claim 2, wherein, The display panel further comprises a plurality of first conductive tracks distributed in the non-display area; One end of the plurality of first conductive tracks is electrically connected with the first power signal line, and the other end of the plurality of first conductive tracks is electrically connected with the second power signal line.

4. The display panel of claim 1, wherein, The at least two power signal lines comprise a first power signal line and a third power signal line; In the direction parallel to the substrate, the third power signal line is closer to the display area than the first power signal line; the orthogonal projection of the first power signal line on the substrate and the orthogonal projection of the gate drive circuit on the substrate overlap.

5. The display panel of claim 4, wherein, The display panel further comprises a plurality of second conductive tracks distributed in the non-display area; One end of the plurality of second conductive tracks is electrically connected with the first power signal line, and the other end of the plurality of second conductive tracks is electrically connected with the third power signal line.

6. The display panel of any of claims 1 to 5, wherein, The at least two power signal lines comprise a first power signal line, a second power signal line and a third power signal line; In the direction parallel to the substrate, the second power signal line is farther away from the display area than the first power signal line, and the third power signal line is closer to the display area than the first power signal line; the orthogonal projection of the first power signal line on the substrate and the orthogonal projection of the gate drive circuit on the substrate overlap.

7. The display panel of claim 6, wherein, The non-display area comprises two first sub-areas oppositely arranged in a first direction, and a second sub-area and a third sub-area oppositely arranged in a second direction; the non-display area further comprises a binding area located on the side of the third sub-area away from the display area in the second direction; the first direction intersects with the second direction; The second power signal line and the third power signal line are distributed at least in the two first sub-areas and the second sub-area; the first power signal line is distributed at least in the two first sub-areas.

8. The display panel of claim 7, wherein, The display panel further comprises a plurality of third conductive tracks distributed in the second sub-region. One end of the plurality of third conductive tracks is electrically connected with the second power signal line, and the other end of the plurality of third conductive tracks is electrically connected with the third power signal line.

9. The display panel of claim 7, wherein, The first power signal line, the second power signal line and the third power signal line are further distributed in the third sub-region; the display panel further comprises a first connecting segment and / or a second connecting segment distributed in the third sub-region. The first connecting segment extends in a direction parallel to the first direction, and the first connecting segment is connected with the first power signal line and the second power signal line on two sides thereof in the second direction. The second connecting segment extends in a direction parallel to the first direction, and the second connecting segment is connected with the first power signal line and the third power signal line on two sides thereof in the second direction.

10. The display panel of any of claims 7-9, wherein, The display panel further comprises a plurality of fourth conductive tracks and a plurality of fifth conductive tracks distributed in the display region. The fourth conductive tracks extend in the first direction, and two ends of the fourth conductive tracks are connected with portions of the third power signal line distributed in the two first sub-regions. The fifth conductive tracks extend in the second direction, and two ends of the fifth conductive tracks are connected with portions of the third power signal line distributed in the second sub-region and the third sub-region.

11. The display panel of claim 10, wherein, The fourth conductive tracks and the fifth conductive tracks are arranged in different layers, or the fourth conductive tracks and the fifth conductive tracks are arranged in the same layer and are made of the same material.

12. The display panel according to claim 10, characterized in that, The display panel further comprises a plurality of data signal lines and a plurality of fan-out leads distributed in the display region; the plurality of sub-pixels are arranged in a plurality of columns in the first direction; one data signal line is electrically connected with one column of sub-pixels, and at least part of the plurality of data signal lines are electrically connected with the plurality of fan-out leads in correspondence. The fan-out lead does not overlap with the fourth conductive track and the fifth conductive track in the orthographic projection of the substrate.

13. The display panel of claim 12, wherein, The fan-out lead comprises a first lead segment and a second lead segment connected with each other; the first lead segment extends in the first direction, and the second lead segment extends in the second direction. The first lead segment and the fourth conductive track are arranged in the same layer and are made of the same material, and the second lead segment and the fifth conductive track are arranged in the same layer and are made of the same material.

14. The display panel of any one of claims 4-13, wherein, The display region is rectangular and has four corner regions. The portion of the third power signal line towards the corner region has a stepped structure, and the stepped structure is distributed around the corner region.

15. The display panel of any one of claims 1-14, wherein, The display panel further comprises a first conductive part located in the non-display region; in a direction perpendicular to the substrate, the first conductive part is located on a side of the at least two power signal lines away from the substrate. The at least two power signal lines include a first power signal line, a projection of the first power signal line on the substrate overlaps with a projection of the gate drive circuit on the substrate.

16. The display panel of claim 15, wherein, The sub-pixel includes a pixel drive circuit and a light emitting device, the pixel drive circuit is located on one side of the substrate, and the light emitting device is located on a side of the pixel drive circuit away from the substrate and is electrically connected with the pixel drive circuit. The first conductive part is arranged in the same layer as the anode of the light emitting device and is made of the same material.

17. The display panel of claim 15, wherein, The at least two power signal lines further include a second power signal line, in a direction parallel to the substrate, the first power signal line is closer to the display area than the second power signal line, and the first conductive part further overlaps with the second power signal line.

18. The display panel of any one of claims 2-3, 6-9, 17, wherein, The second power signal line includes a first sub-power line and a second sub-power line arranged in a direction perpendicular to the substrate, the first sub-power line is closer to the substrate than the second sub-power line, and the first sub-power line overlaps with the second sub-power line. The second sub-power line is arranged in the same layer as the first power signal line and is made of the same material.

19. The display panel of any one of claims 1-18, wherein, The sub-pixel includes a pixel drive circuit and a light emitting device, the pixel drive circuit is located on one side of the substrate, and the light emitting device is located on a side of the pixel drive circuit away from the substrate and is electrically connected with the pixel drive circuit. The at least two power signal lines are electrically connected with the cathodes of the light emitting devices.

20. A display device comprising: The display panel includes: The display panel is any one of the display panels in claims 1-19, and the flexible circuit board is bound to the non-display area and is electrically connected with the at least two power signal lines.

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