Semiconductor device

Abstract

Provided is a semiconductor device that includes: a gallium oxide crystal substrate; an electric field relaxation layer which is provided in contact with the inner surface of the gallium oxide crystal substrate; a silicon oxide film which is provided in contact with the outer surface of the gallium oxide crystal substrate and which is in contact with the electric field relaxation layer; a protective film which is provided in contact with the silicon oxide film; a metal film which is provided in contact with the outer surface of the gallium oxide crystal substrate and which is in contact with the silicon oxide film and the protective film; a solder film which is provided in contact with the metal film but which is not in contact with the gallium oxide crystal substrate; a metal plate which is provided in contact with the solder film but which is not in contact with the gallium oxide crystal substrate; and an electrode part which is provided in contact with the outer surface of the gallium oxide crystal substrate but which is provided in a manner of not being directly electrically connected to the solder film or the metal plate.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] Patent Document 1 discloses a "semiconductor device."

[0003] Patent Document 1 Patent No. 6573207

[0004] Gallium oxide (GaO) with a large energy band gap is a next-generation switching element that can achieve high voltage resistance, low loss, and high heat resistance. ２ O ３ Semiconductor devices using Schottky barrier diodes (SBDs) have been attracting attention and are expected to be applied to power semiconductor devices such as inverters. FIG. 1 of Patent Document 1 schematically shows a suitable example of a Schottky barrier diode (SBD).

[0005] In a first aspect of the present invention, there is provided a semiconductor device comprising: a gallium oxide crystal substrate; an electric field relaxation layer provided in contact with the inner surface of the gallium oxide crystal substrate; a silicon oxide film provided in contact with the outer surface of the gallium oxide crystal substrate and in contact with the electric field relaxation layer; a protective film provided in contact with the silicon oxide film; a metal film provided in contact with the outer surface of the gallium oxide crystal substrate and in contact with the silicon oxide film and the protective film; a solder film provided in contact with the metal film and not in contact with the gallium oxide crystal substrate; a metal plate provided in contact with the solder film and not in contact with the gallium oxide crystal substrate; and an electrode portion provided in contact with the outer surface of the gallium oxide crystal substrate so as not to be directly electrically connected to the solder film and the metal plate.

[0006] In a second aspect of the present invention, there is provided a semiconductor device comprising: a gallium oxide crystal substrate; an electric field relaxation layer provided in contact with an outer surface of the gallium oxide crystal substrate; a silicon oxide film provided in contact with the outer surface of the gallium oxide crystal substrate and in contact with the electric field relaxation layer; a protective film provided in contact with the silicon oxide film; a metal film provided in contact with the outer surface of the gallium oxide crystal substrate and in contact with the protective film; a solder film provided in contact with the metal film and not in contact with the gallium oxide crystal substrate; a metal plate provided in contact with the solder film and not in contact with the gallium oxide crystal substrate; and an electrode portion provided in contact with the outer surface of the gallium oxide crystal substrate so as not to be directly electrically connected to the solder film and the metal plate.

[0007] In a third aspect of the present invention, there is provided a semiconductor device comprising: a gallium oxide crystal substrate; a P-type oxide semiconductor layer provided in contact with an outer surface of the gallium oxide crystal substrate; an electric field buffer layer provided in contact with an inner surface of the gallium oxide crystal substrate and in contact with the P-type oxide semiconductor layer; a silicon oxide film provided in contact with the outer surface of the gallium oxide crystal substrate and in contact with the electric field buffer layer; a protective film provided in contact with the silicon oxide film; a metal film provided in contact with the outer surface of the gallium oxide crystal substrate and in contact with the P-type oxide semiconductor layer; a solder film provided in contact with the metal film but not in contact with the gallium oxide crystal substrate; a metal plate provided in contact with the solder film but not in contact with the gallium oxide crystal substrate; and an electrode portion provided in contact with the outer surface of the gallium oxide crystal substrate so as not to be directly electrically connected to the solder film and the metal plate.

[0008] In a fourth aspect of the present invention, there is provided a semiconductor device comprising: a gallium oxide crystal substrate; a P-type oxide semiconductor layer provided in contact with the outer surface of the gallium oxide crystal substrate; an electric field buffer layer provided in contact with the P-type oxide semiconductor layer in contact with the outer surface of the gallium oxide crystal substrate; a silicon oxide film provided in contact with the outer surface of the gallium oxide crystal substrate and in contact with the electric field buffer layer; a protective film provided in contact with the silicon oxide film; a metal film provided in contact with the outer surface of the gallium oxide crystal substrate and in contact with the P-type oxide semiconductor layer and the protective film; a solder film provided in contact with the metal film and not in contact with the gallium oxide crystal substrate; a metal plate provided in contact with the solder film and not in contact with the gallium oxide crystal substrate; and an electrode portion provided in contact with the outer surface of the gallium oxide crystal substrate and not directly electrically connected to the solder film and the metal plate. Note that the above summary of the invention does not comprehensively list all of the features of the present invention. Furthermore, any combination of these features can be an invention.

[0009] 1 shows an example of a semiconductor device 100 according to Example 1. 2 shows an enlarged view of a portion of the example of the semiconductor device 100 according to Example 1. 3 shows an example of a thermal circuit network according to Example 1. 4 shows an example of a semiconductor device 150 according to a conventional example. 5 shows an example of a thermal circuit network according to a conventional example. 6 shows an example diagram for explaining a contact angle according to Example 1. 7 shows an example of a semiconductor device 151 according to a pre-invention period. 8 shows an example of a semiconductor device 101 according to Example 2. 9 shows an example of a semiconductor device 102 according to Example 3. 10 shows an enlarged view of a portion of the example of the semiconductor device 102 according to Example 3. 11 shows an example of a semiconductor device 103 according to Example 4. 12 shows an enlarged view of a portion of the example of the semiconductor device 103 according to Example 4. 13 shows an example of a semiconductor device 104 according to Example 5. 14 shows an enlarged view of a portion of the example of the semiconductor device 104 according to Example 5.

[0010] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. Furthermore, the semiconductor device of the present invention is assumed to be large enough to be visible to the naked eye. Therefore, the electron waves that play an important role in the semiconductor device are sufficiently spread within the semiconductor device. Electrons are reflected by the inner side of the semiconductor body, i.e., the inner surface of the semiconductor body. The electron waves also spread to the outer side of the semiconductor body, i.e., the outer surface of the semiconductor body. Furthermore, it is assumed that structure functions and thermal circuits related to heat capacity and thermal resistance can be assumed. Note that the drawings used in the following description are schematic, and the dimensional relationships and ratios of elements in the drawings do not necessarily correspond to actual ones. Furthermore, the dimensional relationships and ratios of elements in multiple drawings do not necessarily correspond to actual ones.

[0011] FIG. 1 shows an example of the configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 2 shows an enlarged view of the portion surrounded by the dashed line in FIG. 1. Note that the dimensional relationships and ratios of the elements do not necessarily match exactly. The semiconductor device 100 shown in FIG. 1 has an electrode portion 301 and a metal plate 700 for electrical connection to the outside. The semiconductor device 100 includes a gallium oxide crystal substrate 200, an electric field relaxation layer 210 provided in contact with the inner surface 200b of the gallium oxide crystal substrate 200, a silicon oxide film 600 provided in contact with the outer surface 200a of the gallium oxide crystal substrate 200 and in contact with the electric field relaxation layer 210, a protective film 800 provided in contact with the silicon oxide film 600, and a silicon oxide film 600 provided in contact with the outer surface 200a of the gallium oxide crystal substrate 200. 00 and protective film 800, a solder film 500 provided in contact with the metal film 401 but not in contact with the gallium oxide crystal substrate 200, a metal plate 700 provided in contact with the solder film 500 but not in contact with the gallium oxide crystal substrate 200, and an electrode portion 301 provided in contact with the outer surface 200a of the gallium oxide crystal substrate 200 so as not to be directly electrically connected to the solder film 500 and the metal plate 700.

[0012] The semiconductor device 100 corresponds to the semiconductor device in the first embodiment described in the Summary of the Invention section. The gallium oxide crystal substrate 200 corresponds to the gallium oxide crystal substrate in the first embodiment described in the Summary of the Invention section. The inner surface 200b of the gallium oxide crystal substrate corresponds to the inner surface of the gallium oxide crystal substrate in the first embodiment described in the Summary of the Invention section. The N-type gallium oxide crystal substrate 200 corresponds to the N ＋ Gallium oxide crystal substrate 270 and N － The inner surface 200b of the gallium oxide crystal substrate 260 is partially N. － Gallium oxide crystal substrate 260 or N ＋ It is also the inner surface of the gallium oxide crystal substrate 270. The electric field relaxation layer 210 corresponds to the electric field relaxation layer provided in contact with the inner surface of the gallium oxide crystal substrate in the first embodiment described in the Summary of the Invention section. The outer surface 200a of the gallium oxide crystal substrate corresponds to the outer surface of the gallium oxide crystal substrate in the first embodiment described in the Summary of the Invention section. The N-type gallium oxide crystal substrate 200 is N ＋ Gallium oxide crystal substrate 270 and N － The gallium oxide crystal substrate 260 is made up of a gallium oxide crystal substrate. Therefore, the outer surface 200a of the gallium oxide crystal substrate is partially made of N. － Gallium oxide crystal substrate 260 or N ＋It is also the outer surface of the gallium oxide crystal substrate 270. The silicon oxide film 600 corresponds to the silicon oxide film provided in contact with the outer surface of the gallium oxide crystal substrate in the first embodiment described in the Summary of the Invention and in contact with the electric field relaxation layer. The protective film 800 corresponds to the protective film provided in contact with the silicon oxide film in the first embodiment described in the Summary of the Invention. The metal film 401 corresponds to the metal film provided in contact with the outer surface of the gallium oxide crystal substrate in the first embodiment described in the Summary of the Invention and in contact with the silicon oxide film and the protective film. The solder film 500 corresponds to the solder film provided in contact with the metal film in the first embodiment described in the Summary of the Invention and not in contact with the gallium oxide crystal substrate. The metal plate 700 corresponds to the metal plate provided in contact with the solder film in the first embodiment described in the Summary of the Invention and not in contact with the gallium oxide crystal substrate. The electrode portion 301 corresponds to the electrode portion in the first embodiment described in the Summary of the Invention, which is provided in contact with the outer surface of the gallium oxide crystal substrate and is not directly electrically connected to the solder film and the metal plate.

[0013] The electrode portion 301 is provided in contact with the outer surface 200a of the N-type gallium oxide crystal substrate 200. The gallium oxide crystal substrate 200 is made of N-type gallium oxide crystals having different electrical conductivities. － Gallium oxide crystal substrate 260 and N ＋ The gallium oxide crystal substrate 270 is made of two layers, and has low electrical conductivity. － The electric field relaxation layer 210 is provided on the gallium oxide crystal substrate 260. The N-type gallium oxide crystal substrate 200 is ＋ Gallium oxide crystal substrate 270 and N － Since the electrode portion 301 is made of a gallium oxide crystal substrate 260, ＋It can also be viewed as being provided in contact with the outer surface of the gallium oxide crystal substrate 270. The crystal structure of the N-type gallium oxide crystal substrate 200 is described as β-type, but other crystal structures may be used. The electrode portion 301 is not directly electrically connected to the solder film 500. The electrode portion 301 is not directly electrically connected to the solder film 500, meaning that the electrode portion 301 and the solder film 500 are not in physical contact with each other, and even when a DC voltage is applied between them, no DC current flows through an intervening material. Similarly, the electrode portion 301 is not directly electrically connected to the metal plate 700. The electrode portion 301 and the metal plate 700 are not in physical contact with each other, and even when a DC voltage is applied between them, no DC current flows through an intervening material. The metal plate 700 is provided in contact with the solder film 500 and is not in contact with the gallium oxide crystal substrate 200. The solder film 500 is provided in contact with the metal film 401, but not in contact with the gallium oxide crystal substrate 200. The metal film 401 is provided in contact with the outer surface 200a of the gallium oxide crystal substrate 200. The N-type gallium oxide crystal substrate 200 is ＋ Gallium oxide crystal substrate 270 and N － Since the metal film 401 is made of gallium oxide crystal substrate 260, ＋ It can also be seen as being provided in contact with the outer surface of the gallium oxide crystal substrate 260. The metal film 401 is in contact with the silicon oxide film 600. The metal film 401 is in contact with the protective film 800. An electric field relaxation layer 210 is provided on the inner surface 200b of the gallium oxide crystal substrate 200 so as to be in contact with the silicon oxide film 600. The silicon oxide film 600 is provided in contact with the outer surface 200a of the gallium oxide crystal substrate 200 so as to be in contact with the electric field relaxation layer 210. The protective film 800 is provided in contact with the silicon oxide film 600.

[0014] The electrode portion may be a layer made of any one of titanium element, nickel element, silver element, and gold element, or a layer having any one of titanium element, nickel element, silver element, and gold element, or a combination of these layers.

[0015] The electrode portion 301 is connected to the N-type gallium oxide crystal substrate 200 through a process that allows chemical bonding. In Example 1, a sputtering method is used as such a process. Depending on the process conditions of this sputtering method and the process conditions of the post-treatment, a Schottky barrier may be formed between the electrode portion 301 and the N-type gallium oxide crystal substrate 200, or an ohmic connection may be formed. In Example 1 of the present invention, a process that forms an ohmic connection between the electrode portion 301 and the N-type gallium oxide crystal substrate 200 is used. Titanium metal is also used as the sputtering material. As an example, the thickness of the electrode portion 301 is several hundred nanometers.

[0016] The N-type gallium oxide crystal substrate 200 is manufactured by processing an N-type β-type gallium oxide crystal substrate having a wafer shape that is approximately circular when viewed from the direction in which the electrode portion 301 or electrode plate 700 is formed. The thickness of the substrate is approximately 0.6 mm. Several representative methods are known for manufacturing N-type gallium oxide crystal substrates. Detailed descriptions of these manufacturing methods will be omitted here. As an example, the dopant concentration of the substrate of the gallium oxide crystal substrate is 1×10 １６ cm －３ From 1 x 10 １９ cm －３ It is possible to control the concentration within the range of 100 ppm, and it is also possible to provide layers with multiple concentrations.

[0017] The metal plate may consist of only copper or may contain copper elements.

[0018] The metal plate 700 is made by processing a copper plate having a predetermined thickness, for example by cutting it. The copper plate may be solid or plated. Copper plates have high thermal conductivity and excellent heat dissipation properties, but it is difficult to achieve a chemical bond with the gallium oxide crystal substrate 200. For this reason, the metal plate 700 is ultimately electrically connected to the gallium oxide crystal substrate 200 via the solder film 500. As an example, the thickness of the metal plate 700 is 0.5 mm to several mm.

[0019] The solder film may be made of elemental lead and elemental tin.

[0020] The solder film may contain other elements in addition to lead and tin.

[0021] The solder film 500 is formed through a process of providing a solder material having a predetermined thickness between the metal plate 700 and the metal film 401, a process of melting the solder material, and a process of cooling the solder material. The solder material may be made of lead and tin, or may be lead-free. In Example 1 of the present invention, a solder material made of lead and tin is used. As an example, the thickness of the solder film 500 is approximately 30 μm to 100 μm.

[0022] The metal film may be a layer made of any of nickel, aluminum, gold, titanium, platinum, molybdenum, and cobalt, or a layer having any of nickel, aluminum, gold, titanium, platinum, molybdenum, and cobalt, or a combination of these layers.

[0023] The metal film 401 is connected to the N-type gallium oxide crystal substrate 200 through a process that allows it to be chemically bonded. In Example 1, a sputtering method is used as such a process. Depending on the process conditions of this sputtering method and the process conditions of the post-treatment, a Schottky barrier may be formed between the metal film 401 and the N-type gallium oxide crystal substrate 200, or an ohmic connection may be formed. In Example 1 of the present invention, a process that forms a Schottky barrier between the metal film 401 and the N-type gallium oxide crystal substrate 200 is used. Nickel metal is also used as the sputtering material. As an example, the thickness of the electrode portion 401 is several hundred nanometers. In another example, the metal film 401 may be formed by electron beam evaporation. This is because, when sputtering is used, plasma damage is inflicted on the gallium oxide substrate 200, whereas when electron beam evaporation is used, damage to the gallium oxide crystal substrate 200 can be prevented.

[0024] The silicon oxide film 600 is provided through a process that allows it to be chemically bonded to the gallium oxide crystal substrate 200. As such a process, a CVD (Chemical Vapor Deposition) method is used in Example 1. As an example, the thickness of the silicon oxide film 600 is several tens of nanometers.

[0025] The protective film may have a contact angle with the solder film of 90° or more and less than 180° when the solder film melts during the manufacturing process of the semiconductor device.

[0026] The protective film may be made of a silicon nitride film.

[0027] The protective film 800 is provided through a process that allows it to be chemically bonded to the silicon oxide film 600. In Example 1, a CVD (Chemical Vapor Deposition) method is used as such a process. The protective film 800 is desirably provided so that the solder layer 500 does not creep up and come into contact with the gallium oxide crystal substrate 200 during the manufacturing process of the semiconductor device 100. In Example 1, a silicon nitride film is selected as the protective film. As an example, the thickness of the protective film 800 is several tens of nanometers.

[0028] The electric field relaxation layer is made of a NiO-based material, a CuO-based material, or a Cu ２ The oxide may be an O-based material or an SnO-based material, or an oxide formed from a combination thereof.

[0029] The electric field relaxation layer may have a high resistance layer in which any one of nitrogen atoms, iron atoms, beryllium atoms, zinc atoms, phosphorus atoms, oxygen atoms, argon atoms, and magnesium atoms is present in the gallium oxide crystal substrate and functions as a P-type dopant.

[0030] The electric field relaxation layer 210 is formed by forming a recess in the N-type gallium oxide crystal substrate 200 and refilling it with a P-type oxide. Specifically, a groove is formed in the N-type gallium oxide crystal substrate using the same principle as the groove formation process used in the manufacturing process of a semiconductor device using a silicon wafer. The groove is then filled with a P-type oxide using the same principle as the groove filling process used in the manufacturing process of a semiconductor device using silicon.

[0031] That is, the grooves provided in the N-type gallium oxide crystal substrate 200 are filled with P-type oxide by sputtering or CVD. The P-type oxide is nickel oxide (NiO), copper oxide (CuO, Cu ２ The gallium oxide layer 210 may be either gallium arsenide (GaAs), gallium arsenide (GaAs), or tin oxide (SnO), or a combination thereof. In the above process, the heat treatment is performed as appropriately as possible so that the various introduced atoms form appropriate chemical bonds with adjacent atoms and are present inside the gallium oxide crystal substrate with P-type electrical properties. Needless to say, the conditions are not one and depend on the manufacturing equipment used. As an example, the depth direction of the electric field buffer layer 210 is several tens of nanometers. As an example, the lateral direction of the electric field buffer layer 210 is several tens to several hundreds of nanometers.

[0032] Furthermore, by forming a recess in the N-type gallium oxide crystal substrate 200 and filling the recess with a P-type oxide different from the N-type gallium oxide crystal substrate 200, a change occurs in the electronic state. The electronic state at and near the interface between the gallium oxide crystal substrate 200 and the electric field relaxation layer 210 is different from the inside of the gallium oxide crystal 200 excluding the interface between the gallium oxide crystal substrate 200 and the electric field relaxation layer 210 and the vicinity thereof. This may affect the operation of the semiconductor device 100.

[0033] Furthermore, residual stress at or near the interface and stress distribution when the semiconductor device 100 generates heat may differ compared to when the electric field relaxation layer 210 is not provided.

[0034] Incidentally, the electric field buffer layer 210 can also be provided on the N-type gallium oxide crystal substrate 200 by a process different from the process used in Example 1. Specifically, ionized nitrogen atoms N are implanted into the N-type gallium oxide crystal substrate 200 in the region where the electric field buffer layer 210 is to be provided, using a principle similar to that of the ion implantation process used in the manufacturing process of semiconductor devices using silicon wafers. The implanted nitrogen atoms behave like P-type dopants in the N-type gallium oxide crystal substrate 200 through a so-called activation process. As a result, the ion-implanted region becomes a high-resistance layer due to a compensation effect, forming the electric field buffer layer 210.

[0035] In addition, instead of nitrogen atoms N, iron atoms Fe, beryllium atoms Be, zinc atoms Zn, phosphorus atoms P, oxygen atoms O, argon atoms Ar, or magnesium atoms Mg can also be used. When the electric field buffer layer 210 is provided by ion implantation as described above, it is considered difficult to completely eliminate damage to the gallium oxide crystal substrate, such as the generation of crystal defects caused by ion implantation. Therefore, the electronic state at and near the interface between the gallium oxide crystal substrate 200 and the electric field buffer layer 210 differs from that inside the gallium oxide crystal and may affect the operation of the semiconductor device 100. Furthermore, the residual stress at or near the interface and the stress distribution when the semiconductor device 100 generates heat may be different compared to when the electric field buffer layer 210 is not provided.

[0036] Next, we will explain the operation of the semiconductor device 100. Through the steps described above, a Schottky barrier is formed between the electrode portion 401 and the N-type gallium oxide crystal substrate 200, and an ohmic connection is formed between the electrode portion 301 and the N-type gallium oxide crystal substrate 200, so that the semiconductor device 100 operates as a so-called Schottky barrier diode.

[0037] When the semiconductor device 100 is operating, a certain current always flows through the semiconductor device 100, and a certain potential difference is generated across the semiconductor device 100, causing the semiconductor device 100 to generate heat. Therefore, for example, determining the path through which the generated heat should be dissipated is an important issue. This issue is common to the semiconductor devices 101, 102, 103, and 104 according to the embodiment, as well as the conventional semiconductor device 150 and the semiconductor device 151 according to the pre-invention period. Furthermore, the issues imposed on the semiconductor device are further exacerbated depending on the operating state expected depending on the intended use.

[0038] In particular, when the semiconductor device 100 is used in a power device and operates as a switching element, current flows intermittently and periodically, which makes it easy for the semiconductor device 100 to expand and contract intermittently and periodically due to heat generation and heat dissipation, making it easy for defects to occur at specific locations in the semiconductor device 100. The periodic expansion and contraction is a kind of resonance state, and mechanical energy is continuously concentrated, so that defects can occur in the semiconductor device 100 even with less heat than expected. It goes without saying that the locations that can cause defects vary depending on the operating state of the semiconductor device 100, but they also naturally depend on the structure of the semiconductor device 100.

[0039] Under certain conditions, the heat generation and heat dissipation conditions within the semiconductor device 100 differ between when a surge voltage or surge current occurs in the semiconductor device 100 and when a current flows intermittently and periodically. Therefore, the temporal and spatial changes in temperature within the semiconductor device 100 may differ, leading to different failure modes for the semiconductor device 100. Furthermore, when a surge voltage or surge current occurs in the semiconductor device 100, the response of electrons, which are important for the operation of the semiconductor device 100, may differ depending on the temporal change in voltage or current, which may further complicate the failure modes. When a current flows intermittently and periodically in the semiconductor device 100, failure analysis using structure functions and thermal networks related to heat capacity and thermal resistance is often easier than when a surge voltage or surge current occurs in the semiconductor device 100. It can be considered that the failure models for a semiconductor device differ between when a surge voltage or surge current occurs in the semiconductor device and when a current flows intermittently and periodically in the semiconductor device. The present invention was created from this perspective, particularly focusing on the electrode configuration.

[0040] In a Schottky barrier diode, a potential difference occurs due to the Schottky barrier, so the anode electrode side where the Schottky barrier exists is more likely to generate heat than the cathode electrode side where an ohmic connection exists. Here, when comparing the anode electrode side and the cathode electrode side from the perspective of the heat generation path, the presence of the metal plate 700 makes the thickness of the anode side several times to several tens of times greater than that of the cathode electrode side. Therefore, the heat capacity of the anode side is larger than that of the cathode electrode side. Furthermore, when comparing the anode electrode side and the cathode electrode side from the perspective of implementation, the presence of the metal plate 700 makes it easier to connect the anode electrode side to a structure intended for heat dissipation, such as a heat sink. Therefore, it is easier to substantially reduce the thermal resistance of the anode electrode side compared to the cathode electrode side. That is, in Example 1, the side of the gallium oxide crystal substrate 200 where the metal film 401 exists is more likely to generate heat, and the generated heat easily flows to the metal plate 700 via the metal film 401 and the solder film 500. Therefore, compared to the conventional semiconductor device 150 shown in FIG. 4, it is easier to suppress one or both of the temperature rise and the temperature change rate of the semiconductor device 100.

[0041] As a result, even if current flows intermittently and periodically when the semiconductor device 100 operates as a switching element in a power device, it becomes easier to suppress one or both of the temperature rise and the temperature change rate of the semiconductor device, thereby improving the stability of element operation and ultimately the reliability of the semiconductor device 100. These effects are common to other embodiments of the present invention in which a metal plate is provided on the anode side.

[0042] 4 shows a semiconductor device 150 in which the positions of the anode and cathode electrodes are reversed, although the internal structure of the gallium oxide crystal substrate 200 is the same as that of the semiconductor device 100. In the semiconductor device 150, the metal plate 700 is provided on the cathode electrode side, so even if the semiconductor device 150 performs exactly the same electrical operation, roughly speaking, the semiconductor device 150 is less likely to dissipate generated heat than the semiconductor device 100.

[0043] The thermal circuit network of the semiconductor device 100 of FIG. 1 is shown in FIG. 3. Similarly, the thermal circuit network of the semiconductor device 150 of FIG. 4 is shown in FIG. 5. Even if the same heat generation occurs, the distribution of heat capacity and thermal resistance is different, so the internal temperature distribution and temporal change may differ between the semiconductor device 100 and the semiconductor device 150. In conventional semiconductor devices, as shown in the semiconductor device 150 of FIG. 4, a metal plate is provided on the cathode electrode side. This is because, in the case of power semiconductors, the structure of the anode side in particular is often devised from the perspective of ease of designing the manufacturing process and improving manufacturing yield. On the other hand, gallium oxide crystals are physically fragile and easily broken, a characteristic not found in other semiconductor materials, and therefore handling them is difficult both experimentally and in the manufacturing process.

[0044] 1 and the semiconductor device 150 of FIG. 4 differ at least in that the semiconductor device 100 of FIG. 1 has a protective film 800. This protective film 800 plays an important role. If the semiconductor device 100 does not have the protective film 800, as shown in FIG. 7, the solder film 500 may creep up the silicon oxide film 600 and reach the gallium oxide crystal substrate 200, potentially causing defects in the semiconductor device 151. Due to this behavior of the solder film 500, a need to prevent such defects arose as an example of a new problem before the present invention was arrived at. The smaller the contact angle θ between the solder film 500 and the silicon oxide film 600 when the solder film 500 melts, the more easily the solder film creeps up the silicon oxide film, so the function and properties of the protective film 800 become important.

[0045] The protective film may have a contact angle with the solder film of 90° or more and less than 180° when the solder film melts during the manufacturing process of the semiconductor device.

[0046] This is because if the contact angle with the solder layer is likely to be 90° or more and less than 180° during the manufacturing process of the semiconductor device, the solder layer can be prevented from creeping up to the gallium oxide crystal substrate, causing defects in the semiconductor device.

[0047] The protective film may be made of a silicon nitride film.

[0048] This is because the contact angle with the solder layer is likely to be 90° or more and less than 180° during the manufacturing process of the semiconductor device, which can prevent the solder layer from creeping up to the gallium oxide crystal substrate and causing defects in the semiconductor device.

[0049] The contact angle θ can be calculated by capturing an image of the front of the solder layer with a camera and then processing it with software. Calculation methods include the contact angle sessile drop method (ellipse fitting method, tangent method, circle method, θ / 2 method, Young-Laplace method), dynamic advancing / receding angle (expansion / contraction method), and surface free energy (OWRK method). The Young-Laplace method and θ / 2 method are generally used.

[0050] When measuring the contact angle of solder with a silicon nitride film, the solder layer is formed by forming a silicon oxide film and a silicon nitride film in that order on the surface of a flat gallium oxide crystal substrate, and then forming a solder layer on the silicon nitride film, and then photographing the molten solder with a camera. The solder is melted under the same temperature conditions as in the manufacturing process. In Figure 6, Liquid is the solder that makes up the solder layer, Solid is the silicon nitride film, and γ is the interfacial tension. The interfacial tension γ corresponds to liquid / gas, solid / liquid, and solid / gas, and is expressed as γ ｌｖ , γ ｓｌ , γ ｓｖ and satisfies Young's formula.

[0051] In this regard, in Example 1, a protective film 800 made of a silicon nitride film is newly provided, thereby improving the situation so that the solder film 500 does not creep up the silicon oxide film 600 and reach the gallium oxide crystal substrate 200. A silicon nitride film is an excellent protective film 800 that performs this function. The silicon nitride film is formed using a CVD method. Since the silicon nitride film is electrically an insulating film, there is no problem even if it comes into contact with the gallium oxide crystal substrate 200. Figure 7 schematically shows an example of a semiconductor device 151 according to the pre-invention period, in which the solder film 500 creeps up the silicon oxide film 600 and reaches the gallium oxide crystal substrate 200 when the protective film 800 made of a silicon nitride film is not present.

[0052] The metal plate may consist of only copper or may contain copper elements.

[0053] Copper has a very high thermal conductivity, which makes it easy to suppress temperature rise in the semiconductor device, thereby improving the stability of element operation and, ultimately, the reliability of the semiconductor device.

[0054] The metal film may be a layer made of any one of nickel, aluminum, gold, titanium, platinum, molybdenum, and cobalt, or a layer made of any combination of nickel, aluminum, gold, titanium, platinum, molybdenum, and cobalt, or a combination of these layers.

[0055] A layer made of nickel element is likely to form an excellent Schottky barrier between itself and the gallium oxide crystal substrate, and is therefore advantageous for the production of Schottky barrier diodes.

[0056] The solder film may be composed of elemental lead and elemental tin.

[0057] This is because the use of such a solder film makes it possible to improve the stability and reliability of a semiconductor device that operates as a switching element in a power device.

[0058] The electrode portion may be a layer made of any one of titanium element, nickel element, silver element, and gold element, or a layer having any one of titanium element, nickel element, silver element, and gold element, or a combination of these layers.

[0059] This is because such a layer is likely to form an excellent ohmic contact with the gallium oxide crystal substrate, making it advantageous as a component of the cathode electrode of a Schottky barrier diode.

[0060] 8 shows an example of the configuration of a semiconductor device 101 according to a second embodiment of the present invention. The second embodiment differs from the first embodiment in that the anode and cathode electrodes have a multilayer structure composed of multiple layers. Specifically, the anode electrode is composed of Ni layers 410 and 430 composed of nickel and an Al layer 420 composed of aluminum. The cathode electrode is composed of a Ti layer 310 composed of titanium, a Ni layer 320 composed of nickel, and an Ag layer 330 composed of silver.

[0061] For example, there is a need to further improve the stability and reliability of the semiconductor device, and the reason for using a multilayer structure for the electrodes is to further reduce malfunctions caused by heat generation in the semiconductor device 101 compared to when using a single-layer electrode, thereby improving the stability and reliability of the semiconductor device 101.

[0062] As mentioned above, the locations that can cause defects naturally depend on the structure of the semiconductor device.

[0063] Therefore, the total number of electrodes, the thickness of each layer, the order of lamination thereof, etc. are determined by carefully considering the physical properties of the constituent elements, etc. From another perspective, since there is a greater degree of freedom in design, Example 2 has an added advantage over Example 1 in that it becomes easier to further improve the stability and reliability of element operation in accordance with the expected operation of the semiconductor device 101.

[0064] It goes without saying that the Ni layer 410 made of nickel and the Ti layer 310 made of titanium, which come into direct contact with the gallium oxide crystal substrate, are selected from the viewpoint of electrical properties in addition to the mechanical properties described above. Furthermore, although not used in Example 2, a layer made of gold, titanium, platinum, molybdenum, or cobalt can be used as the layer constituting the anode electrode. A layer made of gold can also be used as the layer constituting the cathode electrode.

[0065] The gallium oxide crystal substrate may be a gallium oxide crystal substrate having N-type electrical conductivity and made up of multiple layers with different electrical conductivities, with an electric field relaxation layer being provided on the layer with the lowest electrical conductivity among the multiple layers.

[0066] As an example, this configuration makes it possible to minimize layers with low electrical conductivity, making it easier to suppress heat generation in the gallium oxide crystal substrate 200. If the same current flows uniformly, layers with low electrical conductivity are more likely to generate heat than layers with high conductivity. If heat generation can be suppressed throughout the semiconductor device, it becomes easier to obtain the additional effect of further improving the stability and reliability of the semiconductor device. As an example, it becomes easier to minimize the thickness of the gallium oxide crystal substrate, which leads to a reduction in the cost of the expensive gallium oxide crystal substrate, and it becomes easier to obtain the additional effect of making it easier to reduce the overall manufacturing cost of the semiconductor device.

[0067] The gallium oxide crystal substrate 200 is made of N － Gallium oxide crystal substrate 260 and N ＋ It consists of two layers of gallium oxide crystal substrate 270. － An electric field relaxation layer 210 is provided on a gallium oxide crystal substrate 260 .

[0068] As an example, N doped with silicon atoms － Gallium oxide crystal substrate 260 and N ＋ The approximate values ​​of the activated donor concentrations in the gallium oxide crystal substrate 270 are 2×10 １６ cm －３ and 1 x 10 １９ cm －３ It is. － The thickness of the gallium oxide crystal substrate 260 is approximately 10 μm. ＋ The thickness of the gallium oxide crystal substrate 270 is approximately 600 μm.

[0069] As an example, the area of ​​the electrode portion 301 formed on the chip of the N-type gallium oxide crystal substrate 200 cut out by dicing from the wafer state is 4×4 mm ２ is.

[0070] Examples 1, 3, 4 and 5 of the present invention and the conventional example have the same outline of each component, and the thickness and impurity concentration of each crystal substrate, as well as the area of ​​the electrode portion, are also approximately the same.

[0071] In addition, since the gallium oxide crystal substrate is made up of multiple layers with different electrical conductivities, the distribution and temporal change of the internal temperature of the semiconductor device may change, and it is fully expected that it will become necessary to change the type and thickness of the materials constituting the electrodes, the order of lamination of those materials, etc. Therefore, designing the electrodes may become more difficult.

[0072] FIG. 9 shows an example of the configuration of a semiconductor device 102 according to a third embodiment of the present invention. FIG. 10 shows an enlarged view of the area surrounded by the dashed line in FIG. 9. Note that the dimensional relationships and ratios of the elements do not necessarily match exactly. The semiconductor device 102 shown in FIG. 9 has an electrode portion 301 and a metal plate 700 for electrical connection to the outside. The semiconductor device 102 comprises a gallium oxide crystal substrate 200, an electric field relaxation layer 220 provided in contact with the outer surface 200 a of the gallium oxide crystal substrate 200, a silicon oxide film 600 provided in contact with the outer surface 200 a of the gallium oxide crystal substrate 200 and in contact with the electric field relaxation layer 220, a protective film 600 provided in contact with the silicon oxide film 600, a metal film 401 provided in contact with the outer surface 200 a of the gallium oxide crystal substrate 200 and in contact with the protective film 600, a solder film 500 provided in contact with the metal film 401 but not in contact with the gallium oxide crystal substrate 200, a metal plate 700 provided in contact with the solder film 500 but not in contact with the gallium oxide crystal substrate 200, and an electrode portion 301 provided in contact with the outer surface 200 a of the gallium oxide crystal substrate 200 so as not to be directly electrically connected to the solder film 500 and the metal plate 700.

[0073] The semiconductor device 102 corresponds to the semiconductor device in the second embodiment described in the Summary of the Invention section. The gallium oxide crystal substrate 200 corresponds to the gallium oxide crystal substrate in the second embodiment described in the Summary of the Invention section. The electric field relaxation layer 220 corresponds to the electric field relaxation layer provided in contact with the outer surface of the gallium oxide crystal substrate in the second embodiment described in the Summary of the Invention section. The outer surface 200a of the gallium oxide crystal substrate corresponds to the outer surface of the gallium oxide crystal substrate in the second embodiment described in the Summary of the Invention section. The N-type gallium oxide crystal substrate 200 is an N-type gallium oxide crystal substrate. ＋ Gallium oxide crystal substrate 270 and N － The gallium oxide crystal substrate 260 is made up of a gallium oxide crystal substrate. Therefore, the outer surface 200a of the gallium oxide crystal substrate is partially made of N. － Gallium oxide crystal substrate 260 or N ＋ It is also the outer surface of the gallium oxide crystal substrate 270. The silicon oxide film 600 corresponds to the silicon oxide film provided in contact with the outer surface of the gallium oxide crystal substrate in the second embodiment described in the Summary of the Invention and in contact with the electric field relaxation layer. The protective film 800 corresponds to the protective film provided in contact with the silicon oxide film 600 in the second embodiment described in the Summary of the Invention. The metal film 401 corresponds to the metal film provided in contact with the outer surface of the gallium oxide crystal substrate in the second embodiment described in the Summary of the Invention and in contact with the protective film. The solder film 500 corresponds to the solder film provided in contact with the metal film in the second embodiment described in the Summary of the Invention and not in contact with the gallium oxide crystal substrate. The metal plate 700 corresponds to the metal plate provided in contact with the solder film in the second embodiment described in the Summary of the Invention and not in contact with the gallium oxide crystal substrate. The electrode portion 301 corresponds to the electrode portion in the second embodiment described in the Summary of the Invention, which is provided in contact with the outer surface of the gallium oxide crystal substrate and is not directly electrically connected to the solder film and the metal plate.

[0074] Example 3 differs from Examples 1 and 2 in that the electric field buffer layer 220 is provided in contact with the outer surface 200a of the gallium oxide crystal substrate 200, rather than the inner surface 200b of the gallium oxide crystal substrate 200. In Examples 1 and 2, the manufacturing process for providing the electric field buffer layer includes a step of providing a recess in the gallium oxide crystal substrate. Unexpected floating debris and impurities tend to accumulate in the recess, making cleaning the recess before refilling it with P-type oxide problematic. This problem is particularly likely to become apparent when the opening area of ​​the recess is small. When the electric field buffer layer is provided in contact with the outer surface of the gallium oxide crystal substrate, such problems are unlikely to occur. Furthermore, as in Example 1, a protective film 800 is provided that prevents the solder layer 500 from creeping up, thereby suppressing semiconductor device defects as in Example 1. Therefore, the semiconductor device 102 can more easily improve the stability of element operation and thus the reliability of the semiconductor device 100, as described in Example 1.

[0075] On the other hand, when the electric field relaxation layer is provided in contact with the outer surface of the gallium oxide crystal substrate as in Example 3, it may be necessary to devise not only the shape, arrangement, and impurity concentration of the electric field relaxation layer but also the shape of the electrode layer from the viewpoint of JTE (Junction Termination Extension) or field plates, etc., so that the function of electric field relaxation can be fully exerted. Therefore, in the case of Example 3, the device design and process design of the electric field relaxation layer become complicated, and there is a good possibility that the so-called design requires time and cost. In some cases, the heat capacity and thermal resistance of the electrode layer, protective film, or electric field relaxation layer may change significantly, and the design may become even more complicated from the viewpoint of thermal design.

[0076] FIG. 11 shows an example of the configuration of a semiconductor device 103 according to a fourth embodiment of the present invention. FIG. 12 shows an enlarged view of the portion surrounded by the dashed line in FIG. 11 . Note that the dimensional relationships and ratios of the elements do not necessarily match exactly. The semiconductor device 103 shown in FIG. 11 has an electrode portion 301 and a metal plate 700 for electrical connection to the outside. The semiconductor device 103 includes a gallium oxide crystal substrate 200, a P-type oxide semiconductor layer 900 provided in contact with the outer surface 200 a of the gallium oxide crystal substrate 200, an electric field relaxation layer 210 provided in contact with the inner surface 200 b of the gallium oxide crystal substrate 200 and in contact with the P-type oxide semiconductor layer 900, a silicon oxide film 600 provided in contact with the outer surface 200 a of the gallium oxide crystal substrate 200 and in contact with the electric field relaxation layer 210, a protective film 800 provided in contact with the silicon oxide film 600, and a gallium oxide film 700. a metal film 401 provided in contact with the outer surface 200a of the gallium oxide crystal substrate 200 and in contact with the P-type oxide semiconductor layer 900; a solder film 500 provided in contact with the metal film 401 and not in contact with the gallium oxide crystal substrate 200; a metal plate 700 provided in contact with the solder film 500 and not in contact with the gallium oxide crystal substrate 200; and an electrode portion 301 provided in contact with the outer surface 200a of the gallium oxide crystal substrate 200 so as not to be directly electrically connected to the solder film 500 and the metal plate 700.

[0077] The semiconductor device 103 corresponds to the semiconductor device in the third embodiment described in the Summary of the Invention section. The gallium oxide crystal substrate 200 corresponds to the gallium oxide crystal substrate in the third embodiment described in the Summary of the Invention section. The inner surface 200b of the gallium oxide crystal substrate corresponds to the inner surface of the gallium oxide crystal substrate in the third embodiment described in the Summary of the Invention section. The N-type gallium oxide crystal substrate 200 corresponds to the N ＋ Gallium oxide crystal substrate 270 and N － The inner surface 200b of the gallium oxide crystal substrate 260 is partially N. － Gallium oxide crystal substrate 260 or N ＋It is also the inner surface of the gallium oxide crystal substrate 270. The electric field relaxation layer 210 corresponds to the electric field relaxation layer provided in contact with the inner surface of the gallium oxide crystal substrate in the third embodiment described in the Summary of the Invention, and in contact with the P-type oxide semiconductor layer. The outer surface 200a of the gallium oxide crystal substrate corresponds to the outer surface of the gallium oxide crystal substrate in the third embodiment described in the Summary of the Invention. The N-type gallium oxide crystal substrate 200 is ＋ Gallium oxide crystal substrate 270 and N － The gallium oxide crystal substrate 260 is made up of a gallium oxide crystal substrate. Therefore, the outer surface 200a of the gallium oxide crystal substrate is partially made of N. － Gallium oxide crystal substrate 260 or N ＋ It also forms the outer surface of the gallium oxide crystal substrate 270. The silicon oxide film 600 corresponds to the silicon oxide film provided in contact with the outer surface of the gallium oxide crystal substrate in the third embodiment described in the Summary of the Invention and in contact with the electric field relaxation layer. The protective film 800 corresponds to the protective film provided in contact with the silicon oxide film in the third embodiment described in the Summary of the Invention. The metal film 401 corresponds to the metal film provided in contact with the outer surface of the gallium oxide crystal substrate in the third embodiment described in the Summary of the Invention and in contact with the P-type oxide semiconductor layer. The solder film 500 corresponds to the solder film provided in contact with the metal film but not in contact with the gallium oxide crystal substrate in the third embodiment described in the Summary of the Invention. The electrode portion 301 corresponds to the electrode portion provided in contact with the outer surface of the gallium oxide crystal substrate in the third embodiment described in the Summary of the Invention and in such a way that it is not directly electrically connected to the solder film and the metal plate.

[0078] Example 4 differs from Example 1, 2, or 3 in that a P-type oxide semiconductor layer 900, which is not present in Example 1, 2, or 3, is additionally provided in contact with the outer surface 200a of the gallium oxide crystal substrate 200. This P-type oxide semiconductor layer 900 is provided so as to be in ohmic contact with the gallium oxide crystal substrate 200. Therefore, the semiconductor device 100 of Example 1, the semiconductor device 101 of Example 2, and the semiconductor device 102 of Example 3 operate as so-called Schottky barrier diodes as described above, whereas the semiconductor device 103 of Example 4 operates as a so-called PN diode. As in Example 1, 2, or 3, the protective film 800 that prevents the solder layer 500 from creeping up is provided, making it easier to suppress manufacturing defects in the semiconductor device as in Example 1, 2, or 3. Because an electric field is likely to concentrate at and near the interface between the outer edge of the P-type oxide semiconductor layer 900 and the gallium oxide crystal substrate, an electric field relaxation layer 210 may be provided. This can make it easier to improve the reliability of the semiconductor device 104.

[0079] The P-type oxide semiconductor portion is made of NiO-based material, CuO-based material, Cu ２ The oxide may be an O-based material or an SnO-based material, or an oxide formed from a combination thereof.

[0080] Using the same principle as in the process used in the manufacturing process of a semiconductor device using ordinary silicon, a P-type oxide semiconductor 900 is provided in contact with the outer surface 200a of the gallium oxide crystal substrate 200. That is, the P-type oxide semiconductor 900 is provided in contact with the outer surface 200a of the N-type gallium oxide crystal substrate 200 by sputtering or CVD, and heat treatment is performed so that an ohmic connection is formed between the P-type oxide semiconductor layer 900 and the gallium oxide crystal substrate 200. The dopant concentration of the P-type oxide semiconductor layer 900 is designed to be sufficiently high. The activated acceptor concentration is set to 10 １９ / cm ２ It may be more than this.

[0081] FIG. 13 shows an example of the configuration of a semiconductor device 104 according to a fifth embodiment of the present invention. FIG. 14 shows an enlarged view of the portion surrounded by the dashed line in FIG. 13 . Note that the dimensional relationships and ratios of the elements do not necessarily match exactly. The semiconductor device 104 shown in FIG. 13 has an electrode portion 301 and a metal plate 700 for electrical connection to the outside. The semiconductor device 104 includes a gallium oxide crystal substrate 200, a P-type oxide semiconductor layer 900 provided in contact with the outer surface 200 a of the gallium oxide crystal substrate 200, an electric field relaxation layer 220 provided in contact with the outer surface 200 a of the gallium oxide crystal substrate 200 and in contact with the P-type oxide semiconductor layer 900, a silicon oxide film 600 provided in contact with the outer surface 200 a of the gallium oxide crystal substrate 200 and in contact with the electric field relaxation layer 220, a protective film 800 provided in contact with the silicon oxide film 600, and a gallium oxide film 700. The semiconductor device comprises a metal film 401 that is provided in contact with the outer surface 200a of the crystal substrate 200 and is in contact with the P-type oxide semiconductor layer 900 and the protective film 800, a solder film 500 that is provided in contact with the metal film 401 and is not in contact with the gallium oxide crystal substrate 200, a metal plate 700 that is provided in contact with the solder film 500 and is not in contact with the gallium oxide crystal substrate 200, and an electrode portion 301 that is provided in contact with the outer surface of the gallium oxide crystal substrate 200 and is not directly electrically connected to the solder film 500 and the metal plate 700.

[0082] The semiconductor device 104 corresponds to the semiconductor device in the fourth embodiment described in the Summary of the Invention section. The gallium oxide crystal substrate 200 corresponds to the gallium oxide crystal substrate in the fourth embodiment described in the Summary of the Invention section. The outer surface 200a of the gallium oxide crystal substrate 200 corresponds to the outer surface of the gallium oxide crystal substrate in the fourth embodiment described in the Summary of the Invention section. The N-type gallium oxide crystal substrate 200 corresponds to the N-type gallium oxide crystal substrate. ＋ Gallium oxide crystal substrate 270 and N － The gallium oxide crystal substrate 260 is made up of a gallium oxide crystal substrate. Therefore, the outer surface 200a of the gallium oxide crystal substrate is partially made of N. － Gallium oxide crystal substrate 260 or N ＋It is also the outer surface of the gallium oxide crystal substrate 270. The P-type oxide semiconductor layer 900 corresponds to the P-type oxide semiconductor layer provided in contact with the outer surface of the gallium oxide crystal substrate in the fourth embodiment described in the Summary of the Invention. The electric field relaxation layer 220 corresponds to the electric field relaxation layer provided in contact with the outer surface of the gallium oxide crystal substrate in the fourth embodiment described in the Summary of the Invention and in contact with the P-type oxide semiconductor layer. The silicon oxide film 600 corresponds to the silicon oxide film provided in contact with the outer surface of the gallium oxide crystal substrate in the fourth embodiment described in the Summary of the Invention and in contact with the electric field relaxation layer. The protective film 800 corresponds to the protective film provided in contact with the silicon oxide film in the fourth embodiment described in the Summary of the Invention. The metal film 401 corresponds to the metal film provided in contact with the outer surface of the gallium oxide crystal substrate in the fourth embodiment described in the Summary of the Invention and in contact with the P-type oxide semiconductor layer and the protective film. The solder film 500 corresponds to the solder film provided in contact with the metal film but not in contact with the gallium oxide crystal substrate in the fourth embodiment described in the Summary of the Invention. The metal plate 700 corresponds to the metal plate provided in contact with the solder film but not in contact with the gallium oxide crystal substrate in the fourth embodiment described in the Summary of the Invention. The electrode portion 301 corresponds to the electrode portion provided in contact with the outer surface of the gallium oxide crystal substrate in the fourth embodiment described in the Summary of the Invention, but not in direct electrical connection with the solder film and the metal plate.

[0083] Example 5 differs from Examples 1, 2, and 3 in that a P-type oxide semiconductor layer 900, which is not present in Examples 1, 2, and 3, is additionally provided in contact with the outer surface 200a of the gallium oxide crystal substrate 200. Example 5 differs from Example 4 in that an electric field relaxation layer 220 is provided in contact with the outer surface 200a of the gallium oxide crystal substrate 200. This additional P-type oxide semiconductor layer 900 is provided to enable the semiconductor device 104 to function as a PN diode. Therefore, the P-type oxide semiconductor layer 900 has a high dopant concentration, similar to Example 4. In addition, the process is designed, including material selection, so that the metal film 401 and the P-type oxide semiconductor layer 900 are ohmic-connected. As with Examples 1, 2, and 3, the anode electrode side is more likely to generate heat when the semiconductor device 104 is operating. As in Example 1, 2, or 3, there is a protective film 800 that prevents the solder layer 500 from creeping up, which makes it easier to suppress defects in the manufacturing of the semiconductor device, as in Example 1, 2, or 3. As in Example 4, it can be easier to improve the stability of the element operation as a PN diode, and therefore the reliability of the semiconductor device 104.

[0084] Since the electric field relaxation layer 220 is provided in contact with the outer surface 200a of the gallium oxide crystal substrate 200, as in Example 3, it may be necessary to devise not only the shape, arrangement, and impurity concentration of the electric field relaxation layer but also the shape of the electrode layer from the viewpoint of JTE (Junction Termination Extension) or field plates, etc., so that the function of electric field relaxation can be fully exerted. Therefore, in the case of Example 5, the device design and process design of the electric field relaxation layer may become complicated, and so-called design may require time and cost. In some cases, the heat capacity and thermal resistance of the electrode layer, protective film, or electric field relaxation layer may change significantly, and the design may become even more complicated from the viewpoint of thermal design.

[0085] (Supplementary Note 1) A semiconductor device comprising: a gallium oxide crystal substrate; an electric field relaxation layer provided in contact with an inner surface of the gallium oxide crystal substrate; a silicon oxide film provided in contact with an outer surface of the gallium oxide crystal substrate and in contact with the electric field relaxation layer; a protective film provided in contact with the silicon oxide film; a metal film provided in contact with the outer surface of the gallium oxide crystal substrate and in contact with the silicon oxide film and the protective film; a solder film provided in contact with the metal film and not in contact with the gallium oxide crystal substrate; a metal plate provided in contact with the solder film and not in contact with the gallium oxide crystal substrate; and an electrode portion provided in contact with the outer surface of the gallium oxide crystal substrate so as not to be directly electrically connected to the solder film and the metal plate.

[0086] (Supplementary Note 2) A semiconductor device comprising: a gallium oxide crystal substrate; an electric field relaxation layer provided in contact with an outer surface of the gallium oxide crystal substrate; a silicon oxide film provided in contact with the outer surface of the gallium oxide crystal substrate and in contact with the electric field relaxation layer; a protective film provided in contact with the silicon oxide film; a metal film provided in contact with the outer surface of the gallium oxide crystal substrate and in contact with the protective film; a solder film provided in contact with the metal film but not in contact with the gallium oxide crystal substrate; a metal plate provided in contact with the solder film but not in contact with the gallium oxide crystal substrate; and an electrode portion provided in contact with the outer surface of the gallium oxide crystal substrate so as not to be directly electrically connected to the solder film and the metal plate.

[0087] a metal film provided in contact with the outer surface of the gallium oxide crystal substrate and in contact with the P-type oxide semiconductor layer; a solder film provided in contact with the metal film but not in contact with the gallium oxide crystal substrate; a metal plate provided in contact with the solder film but not in contact with the gallium oxide crystal substrate; and an electrode portion provided in contact with the outer surface of the gallium oxide crystal substrate so as not to be directly electrically connected to the solder film and the metal plate.

[0088] a metal film provided in contact with the outer surface of the gallium oxide crystal substrate and in contact with the P-type oxide semiconductor layer and the protective film; a solder film provided in contact with the metal film and not in contact with the gallium oxide crystal substrate; a metal plate provided in contact with the solder film and not in contact with the gallium oxide crystal substrate; and an electrode portion provided in contact with the outer surface of the gallium oxide crystal substrate so as not to be directly electrically connected to the solder film and the metal plate.

[0089] (Supplementary Note 5) The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the electrode portion is a layer made of any one of titanium element, nickel element, silver element, and gold element, or a layer having any one of titanium element, nickel element, silver element, and gold element, or a combination of these layers.

[0090] (Supplementary Note 6) The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the metal plate is made of copper element only or contains copper element.

[0091] (Supplementary Note 7) The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the solder film is made of elemental lead and elemental tin.

[0092] (Supplementary Note 8) The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the metal film is a layer made of any one of nickel, aluminum, gold, titanium, platinum, molybdenum, and cobalt, or a layer having any one of nickel, aluminum, gold, titanium, platinum, molybdenum, and cobalt, or a combination of these layers.

[0093] (Supplementary Note 9) The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the protective film has a contact angle with the solder film of 90° or more and less than 180° when the solder film melts in a manufacturing process of the semiconductor device.

[0094] (Supplementary Note 10) The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the protective film is made of a silicon nitride film.

[0095] (Note 11) The electric field relaxation layer is made of a NiO-based material, a CuO-based material, or a Cu ２ 5. The semiconductor device according to claim 1, further comprising an oxide made of an O-based material, an SnO-based material, or a combination thereof.

[0096] (Supplementary Note 12) The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the electric field relaxation layer has a high resistance layer in which any one of nitrogen atoms, iron atoms, beryllium atoms, zinc atoms, phosphorus atoms, oxygen atoms, argon atoms, and magnesium atoms is present in the gallium oxide crystal substrate and functions as a P-type dopant.

[0097] (Supplementary Note 13) The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the gallium oxide crystal substrate is a gallium oxide crystal substrate having N-type electrical conductivity and is composed of a plurality of layers with different electrical conductivities, and the electric field relaxation layer is provided in the layer with the smallest electrical conductivity among the plurality of layers.

[0098] (Appendix 14) The P-type oxide semiconductor layer is made of a NiO-based material, a CuO-based material, a Cu ２ 5. The semiconductor device according to claim 3, further comprising an oxide made of an O-based material or an SnO-based material, or a combination thereof.

[0099] As described above, the present invention has been described using Examples 1 to 5, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the content of the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0100] It should be noted that the order of the devices, steps, or device operations shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that they can be performed in any order as long as the results of a previous process are not used in a later process. The use of "first," "next," etc. in the claims, specifications, and device operations does not necessarily mean that they must be performed in that order.

[0101] 100...semiconductor device, 101...semiconductor device, 102...semiconductor device, 103...semiconductor device, 104...semiconductor device, 150...semiconductor device, 151...semiconductor device, 200...gallium oxide crystal substrate, 200a...outer surface of gallium oxide crystal substrate, 200b...inner surface of gallium oxide crystal substrate, 210...electric field relaxation layer, 220...electric field relaxation layer, 260...N － Gallium oxide crystal substrate, 270...N ＋ Gallium oxide crystal substrate, 300... electrode portion, 301... electrode portion, 310... Ti layer, 320... Ni layer, 330... Ag layer, 401... metal film, 410... Ni layer, 420... Al layer, 430... Ni layer, 500... solder film, 600... silicon oxide film, 700... metal plate, 800... protective film, 900... P-type oxide semiconductor layer

Claims

1. A semiconductor device comprising: a gallium oxide crystal substrate; an electric field relaxation layer provided in contact with the inner surface of the gallium oxide crystal substrate; a silicon oxide film provided in contact with the outer surface of the gallium oxide crystal substrate and in contact with the electric field relaxation layer; a protective film provided in contact with the silicon oxide film; a metal film provided in contact with the outer surface of the gallium oxide crystal substrate and in contact with the silicon oxide film and the protective film; a solder film provided in contact with the metal film and not in contact with the gallium oxide crystal substrate; a metal plate provided in contact with the solder film and not in contact with the gallium oxide crystal substrate; and an electrode portion provided in contact with the outer surface of the gallium oxide crystal substrate so as not to be directly electrically connected to the solder film and the metal plate.

2. A semiconductor device comprising: a gallium oxide crystal substrate; an electric field relaxation layer provided in contact with an outer surface of the gallium oxide crystal substrate; a silicon oxide film provided in contact with the outer surface of the gallium oxide crystal substrate and in contact with the electric field relaxation layer; a protective film provided in contact with the silicon oxide film; a metal film provided in contact with the outer surface of the gallium oxide crystal substrate and in contact with the protective film; a solder film provided in contact with the metal film but not in contact with the gallium oxide crystal substrate; a metal plate provided in contact with the solder film but not in contact with the gallium oxide crystal substrate; and an electrode portion provided in contact with the outer surface of the gallium oxide crystal substrate so as not to be directly electrically connected to the solder film and the metal plate.

3. A semiconductor device comprising: a gallium oxide crystal substrate; a P-type oxide semiconductor layer provided in contact with the outer surface of the gallium oxide crystal substrate; an electric field buffer layer provided in contact with the inner surface of the gallium oxide crystal substrate and in contact with the P-type oxide semiconductor layer; a silicon oxide film provided in contact with the outer surface of the gallium oxide crystal substrate and in contact with the electric field buffer layer; a protective film provided in contact with the silicon oxide film; a metal film provided in contact with the outer surface of the gallium oxide crystal substrate and in contact with the P-type oxide semiconductor layer; a solder film provided in contact with the metal film but not in contact with the gallium oxide crystal substrate; a metal plate provided in contact with the solder film but not in contact with the gallium oxide crystal substrate; and an electrode portion provided in contact with the outer surface of the gallium oxide crystal substrate so as not to be directly electrically connected to the solder film and the metal plate.

4. A semiconductor device comprising: a gallium oxide crystal substrate; a P-type oxide semiconductor layer provided in contact with an outer surface of the gallium oxide crystal substrate; an electric field buffer layer provided in contact with the outer surface of the gallium oxide crystal substrate and in contact with the P-type oxide semiconductor layer; a silicon oxide film provided in contact with the outer surface of the gallium oxide crystal substrate and in contact with the electric field buffer layer; a protective film provided in contact with the silicon oxide film; a metal film provided in contact with the outer surface of the gallium oxide crystal substrate and in contact with the P-type oxide semiconductor layer and the protective film; a solder film provided in contact with the metal film and not in contact with the gallium oxide crystal substrate; a metal plate provided in contact with the solder film and not in contact with the gallium oxide crystal substrate; and an electrode portion provided in contact with the outer surface of the gallium oxide crystal substrate so as not to be directly electrically connected to the solder film and the metal plate.

5. A semiconductor device according to any one of claims 1 to 4, wherein the electrode portion is made of a layer consisting of any one of titanium element, nickel element, silver element, and gold element, or a layer containing any one of titanium element, nickel element, silver element, and gold element, or a combination of these layers.

6. The semiconductor device according to any one of claims 1 to 4, wherein the metal plate is made of copper element only or contains copper element.

7. The semiconductor device according to any one of claims 1 to 4, wherein the solder film is made of lead and tin elements.

8. A semiconductor device according to any one of claims 1 to 4, wherein the metal film is a layer made of any of nickel, aluminum, gold, titanium, platinum, molybdenum, and cobalt, or a layer having any of nickel, aluminum, gold, titanium, platinum, molybdenum, and cobalt, or a combination of these layers.

9. A semiconductor device according to any one of claims 1 to 4, wherein the protective film has a contact angle with the solder film of 90° or more and less than 180° when the solder film melts during the manufacturing process of the semiconductor device.

10. The semiconductor device according to any one of claims 1 to 4, wherein the protective film is made of a silicon nitride film.

11. The electric field relaxation layer is made of a NiO-based material, a CuO-based material, or a Cu ２ The semiconductor device according to claim 1 , further comprising an oxide made of either an O-based material or an SnO-based material, or a combination thereof.

12. A semiconductor device according to any one of claims 1 to 4, wherein the electric field relaxation layer has a high resistance layer in which any one of nitrogen atoms, iron atoms, beryllium atoms, zinc atoms, phosphorus atoms, oxygen atoms, argon atoms, and magnesium atoms is present in the gallium oxide crystal substrate and functions as a P-type dopant.

13. A semiconductor device according to any one of claims 1 to 4, wherein the gallium oxide crystal substrate is a gallium oxide crystal substrate having N-type electrical conductivity and is composed of multiple layers with different electrical conductivities, and the electric field relaxation layer is provided in the layer of the multiple layers with the lowest electrical conductivity.

14. The P-type oxide semiconductor layer is made of a NiO-based material, a CuO-based material, or a Cu ２ 5. The semiconductor device according to claim 3, further comprising an oxide made of either an O-based material or an SnO-based material, or a combination thereof.

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