Semiconductor stack using semiconductor device template, and manufacturing method therefor

Abstract

The present invention relates to a manufacturing method for a semiconductor stack using a semiconductor device template, comprising: a preparation step of preparing a first substrate and a second substrate; a bonding step of bonding the first substrate and the second substrate through a bonding layer; a molding step of molding the second substrate into an ultra-thin type of a predetermined thickness so as to manufacture a template; and a forming step of forming a semiconductor light-emitting structure on the second substrate of the template.　According to the present invention, a semiconductor light-emitting device or a die (epitaxy die or chip die) having a thickness of less than 50 µm can be manufactured.

Description

Semiconductor laminate using a template for semiconductor devices and its manufacturing method

[0001] The present invention relates to a semiconductor laminate using a template for a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor laminate using a template for a semiconductor device including an ultra-thin sapphire substrate, which can drastically reduce thickness and facilitate reduction of chip die size, thereby improving light output, and a method for manufacturing the same.

[0002] In general, micro LED (including mini LED) displays can be divided into micro LED displays using the PM (Passive Matrix) driving method and micro LED displays using the AM (Active Matrix) driving method.

[0003] Here, a typical PM (Passive Matrix) driven micro LED display has a sorted thick BGR (Blue, Green, Red) chip (both LED anodes and cathodes are completed) with a sapphire support substrate as the final substrate, and is transferred through a chip die-level process, and generally horizontal chips or flip chips can be used.

[0004] Additionally, micro LED displays with an AM (Active Matrix) drive method typically do not have a sapphire support substrate at the end, so they have thin, unsorted BGR chips (both LED anodes and cathodes are completed) that are transferred through a wafer-level process, and generally horizontal chips, flip chips, or vertical chips can all be used.

[0005] These conventional PM (passive matrix) driving method and AM (active matrix) driving method micro LED displays have the following common issues.

[0006] First, when considering vertical chip application to reduce chip die size, unlike flip chips where defects can be confirmed immediately after bonding, vertical chips have the problem of defects being confirmed after top wiring after bonding.

[0007] In addition, in terms of the bonding process, an increase in bonding process precision is required due to the reduction of the chip die, and an improvement in bonding strength is required due to the reduction of the bonding area.

[0008] In addition, in terms of the tiling process that combines multiple unit displays like tiles, there is an issue with a distinct border when the display is OFF or on a black screen, and this is more noticeable in the PM driving method than in the AM driving method. Although many parts have been improved, there is still a problem with visible borders in monochrome screens and still screens, and there is a problem with the process being difficult due to glass breakage when tiling based on a TFT Glass panel. Furthermore, there are various issues, such as it is expected to be difficult to apply to products less than 100 inches depending on the tolerance relationship between the pixel pitch and the tiling border.

[0009] Meanwhile, as smaller and smaller dies (epitaxial dies or chips) are required for manufacturing mini or micro level semiconductor light emitting devices, thinner and thinner sapphire molding process technology is needed.

[0010] That is, in order to achieve chip die size reduction from the aspect ratio perspective, it is essential to reduce the thickness of the final growth substrate (or support substrate) sapphire. However, the current thickness of the growth substrate (or support substrate) sapphire is limited to about 80 ㎛ to 70 ㎛, and when the thickness is reduced to 50 ㎛ or less, the issue of sapphire substrate breakage occurs.

[0011] For this reason, there are attempts to form the initial growth substrate sapphire thinly from the beginning and then grow the group III nitride semiconductor, but there is a problem that the die or wafer is deformed and damaged during the forming or transfer process due to thermo-mechanical induced stress caused by the difference in lattice constant (LC) and coefficient of thermal expansion (CTE) between the sapphire growth substrate and the group III nitride semiconductor.

[0012] The purpose of the present invention is to solve the above-described conventional problems, and relates to a semiconductor laminate using a semiconductor element template including an ultra-thin type sapphire substrate, which can drastically reduce the thickness and facilitate reduction of the chip die size, thereby improving the light output, and a method for manufacturing the same.

[0013] The above object is achieved by a method for manufacturing a semiconductor laminate using a template for a semiconductor device, which comprises a preparation step of preparing a first substrate and a second substrate according to the present invention; a bonding step of bonding the first substrate and the second substrate through a bonding layer; a forming step of manufacturing a template by forming the second substrate into an ultra-thin shape with a preset thickness; and a forming step of forming a semiconductor light-emitting structure on the second substrate of the template.

[0014] In addition, the above forming step can form a positive ohmic contact electrode on one surface of the semiconductor light-emitting portion after growing the semiconductor light-emitting portion on the second substrate.

[0015] In addition, the forming step may etch one side of the positive ohmic contact electrode and the semiconductor light-emitting portion, and then form a negative ohmic contact electrode on one side of the etched semiconductor light-emitting portion.

[0016] In addition, the above forming step can form a positive ohmic contact electrode on one surface of a semiconductor light-emitting part, and then bond the other surface of the semiconductor light-emitting part to the second substrate through a bonding layer.

[0017] In addition, the forming step may form a positive ohmic contact electrode on one surface of the semiconductor light-emitting portion, form a negative ohmic contact electrode and a protective layer on the other surface of the semiconductor light-emitting portion, and then bond the protective layer to the second substrate through a bonding layer.

[0018] In addition, the forming step can expose the cathode ohmic contact electrode to the outside by etching one side of the anode ohmic contact electrode and the semiconductor light-emitting portion.

[0019] In addition, the above forming step can form a positive ohmic contact electrode on one surface of a semiconductor light emitting portion, and then bond the positive ohmic contact electrode to the second substrate through a bonding layer.

[0020] In addition, the above forming step can form a cathode ohmic contact electrode on the other surface of the semiconductor light emitting portion.

[0021] In addition, the forming step can etch one side of the negative ohmic contact electrode and the semiconductor light-emitting portion to expose the positive ohmic contact electrode to the outside.

[0022] Additionally, the first substrate and the second substrate may be sapphire substrates.

[0023] Additionally, the thickness of the second substrate formed in the forming step may be less than 50 μm.

[0024] In addition, a separation layer is formed on the upper surface of the first substrate, and the bonding step can bond the separation layer and the second substrate through the bonding layer.

[0025] The above object is achieved by a semiconductor laminate using a template for a semiconductor device, according to the present invention, comprising: a first substrate; a separation layer formed on the first substrate; a bonding layer formed on the separation layer; a second substrate formed on the bonding layer and formed into an ultra-thin shape with a preset thickness; and a semiconductor light-emitting structure formed on the second substrate.

[0026] In addition, the semiconductor light-emitting structure may include a semiconductor light-emitting portion grown on the second substrate, and a positive ohmic contact electrode formed on the semiconductor light-emitting portion.

[0027] In addition, the positive ohmic contact electrode and the semiconductor light-emitting portion may have one side etched, and a negative ohmic contact electrode may be formed on one side of the etched semiconductor light-emitting portion.

[0028] In addition, the semiconductor light-emitting structure may include a bonding layer formed on the second substrate, a semiconductor light-emitting portion formed on the bonding layer, and a positive ohmic contact electrode formed on the semiconductor light-emitting portion.

[0029] In addition, the semiconductor light-emitting structure may include a bonding layer formed on the second substrate, a protective layer formed on the bonding layer, a cathode ohmic contact electrode formed on the protective layer, a semiconductor light-emitting portion formed on the cathode ohmic contact electrode, and an anode ohmic contact electrode formed on the semiconductor light-emitting portion.

[0030] In addition, the positive ohmic contact electrode and the semiconductor light emitting portion may have one side etched so that the negative ohmic contact electrode is exposed to the outside.

[0031] In addition, the semiconductor light-emitting structure may include a protective layer formed on the second substrate, an anode ohmic contact electrode formed on the protective layer, and a semiconductor light-emitting portion formed on the anode ohmic contact electrode.

[0032] In addition, the semiconductor light-emitting structure may further include a cathode ohmic contact electrode formed on the semiconductor light-emitting portion.

[0033] In addition, the cathode ohmic contact electrode and the semiconductor light emitting portion may have one side etched so that the anode ohmic contact electrode is exposed to the outside.

[0034] Additionally, the first substrate and the second substrate may be sapphire substrates.

[0035] Additionally, the thickness of the second substrate may be less than 50 μm.

[0036] According to the present invention, there is an effect that enables the manufacture of a semiconductor light emitting element or die (epitaxial die or chip die) having a thickness of less than 50㎛.

[0037] In addition, according to the present invention, the advantages of the mini LED manufacturing process, namely, easy defect classification and low process cost and equipment investment cost since existing general-purpose transfer equipment can be used as is, and the advantages of the micro LED manufacturing process, namely, the advantage of improved light output due to the ease of drastic thickness reduction and reduction in chip die size, can be simultaneously satisfied.

[0038] In addition, according to the present invention, unlike a conventional chip die in which both electrodes, i.e., an anode and a cathode, are exposed to the outside, the epitaxy die of the present invention has a structure in which only one electrode is exposed to the outside, so that electrical sorting through an EL (electro luminescence, electric field application) measurement method is not performed, but optical sorting can be performed through a high-speed PL (photo luminescence, light energy application) measurement method, so that defective (NG) can be easily determined primarily using only optical characteristics (wavelength, half-maximum width, intensity, etc.).

[0039] In addition, the epitaxy die of the present invention has the advantage of not requiring a high-temperature heat treatment process after transfer since the process of forming a p-ohmic contact electrode or an n-ohmic contact electrode, which requires a high-temperature heat treatment of 300°C or higher, is completed in the epitaxy die manufacturing stage.

[0040] Meanwhile, the effects of the present invention are not limited to the effects mentioned above, and various effects may be included within a range obvious to those skilled in the art from the contents described below.

[0041] Figure 1 is a flowchart of a method for manufacturing a semiconductor laminate using a semiconductor element template according to the first embodiment of the present invention.

[0042] FIG. 2 illustrates a process of manufacturing a semiconductor element template in a method for manufacturing a semiconductor laminate using a semiconductor element template according to the first embodiment of the present invention.

[0043] FIG. 3 illustrates a process of manufacturing a semiconductor laminate using a semiconductor element template according to the first embodiment of the present invention.

[0044] FIG. 4 is a flowchart of a method for manufacturing a semiconductor laminate using a semiconductor element template according to a second embodiment of the present invention.

[0045] Figures 5 to 7 illustrate a process of manufacturing a semiconductor laminate using a semiconductor element template according to a second embodiment of the present invention.

[0046] FIG. 8 illustrates another laminated structure having an etch-stop layer of a method for manufacturing a semiconductor laminate using a template for a semiconductor element according to the first or second embodiment of the present invention.

[0047] FIG. 9 illustrates a method for manufacturing a semiconductor laminate using a semiconductor element template according to the first or second embodiment of the present invention, in which a semiconductor light-emitting portion is divided into a plurality of regions through an etch-stop layer.

[0048] Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. When designating components in each drawing, it should be noted that, where possible, identical components are given the same reference numerals, even if they appear in different drawings.

[0049] In addition, when describing an embodiment of the present invention, if a detailed description of a related known configuration or function is judged to hinder understanding of the embodiment of the present invention, the detailed description is omitted.

[0050] Additionally, when describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only intended to distinguish the components from other components, and the nature, order, or sequence of the components are not limited by the terms.

[0051]

[0052] The present invention relates to an epitaxy die and chip die for a semiconductor light-emitting device for emitting blue, green, or red light, which is a semiconductor laminate having a thickness of less than 50 μm, which was previously impossible, by using a template for a semiconductor device including an ultra-thin type sapphire substrate. In the present invention, a semi-finished light source die having the following characteristics and a size smaller than a mini LED that can be sorted is defined as the epitaxy die of the present invention.

[0053] First, unlike conventional chip dies in which both electrodes, i.e., the anode and the cathode, are exposed to the outside, the epitaxy die of the present invention has a structure in which the electrodes are not exposed or only one electrode is exposed to the outside. Accordingly, although the epitaxy die of the present invention is not electrically sorted through an EL (electro luminescence, electric field application) measurement method, it can be optically sorted through a high-speed PL (photo luminescence, light energy application) measurement method, so that defective (NG) can be quickly and easily determined primarily using only optical characteristics (wavelength, half maximum width, intensity, etc.).

[0054] Second, the epitaxy die of the present invention has the process of forming a positive ohmic contact electrode (p-ohmic contact electrode) or a negative ohmic contact electrode (n-ohmic contact electrode), which requires a high-temperature heat treatment of 300°C or higher, completed during the epitaxy die manufacturing stage. Accordingly, the epitaxy die of the present invention has the advantage of not requiring a high-temperature heat treatment process after transfer to the final substrate.

[0055] Third, the epitaxy die of the present invention is attached to a relatively thick sapphire first substrate (11a) (support substrate), which is removed after transfer. Accordingly, it has the advantage of being able to be positioned collectively or individually (selectively) through conventional chip die transfer processes such as pick-and-place and replace.

[0056] That is, the epitaxy die of the present invention and the chip die manufactured therefrom can simultaneously satisfy the advantages of the mini LED manufacturing process, namely, easy defect classification and low process cost and equipment investment cost since existing general-purpose transfer equipment can be used as is, and the advantages of the micro LED manufacturing process, namely, the removal of the final support substrate allows for a dramatic thickness reduction and easy reduction in chip die size, thereby improving light output.

[0057]

[0058] From now on, with reference to the attached drawings, a method (S100) for manufacturing a semiconductor laminate using a semiconductor element template according to the first embodiment of the present invention will be described in detail.

[0059] FIG. 1 is a flowchart of a method for manufacturing a semiconductor laminate using a template for a semiconductor device according to a first embodiment of the present invention, FIG. 2 illustrates a process for manufacturing a semiconductor device template in a method for manufacturing a semiconductor laminate using a template for a semiconductor device according to a first embodiment of the present invention, and FIG. 3 illustrates a process for manufacturing a semiconductor laminate in a method for manufacturing a semiconductor laminate using a template for a semiconductor device according to a first embodiment of the present invention.

[0060] As illustrated in FIGS. 1 to 3, a method (S100) for manufacturing a semiconductor laminate using a semiconductor element template according to the first embodiment of the present invention includes a preparation step (S110), a bonding step (S120), a molding step (S130), and a forming step (S140) for directly growing a semiconductor light-emitting portion (110) on a semiconductor element template.

[0061] The preparation step (S110) is a step of preparing the first substrate (11a) and the second substrate (11b).

[0062] Here, the first substrate (11a) and the second substrate (11b) are provided as sapphire substrates. Such sapphire substrates are optically transparent and have high temperature resistance, which theoretically allow 100% transmission of a laser beam (single wavelength light) without absorption in a laser lift off (LLO) process, and can be provided as α-phase Al2O3 sapphire (including ScAlMgO4), etc. In addition, it is preferable that the second substrate (11b) placed on the top of the template have a protrusion shape that is regularly or irregularly patterned in various dimensions (size and shape) in the microscale or nanoscale in order to minimize crystal defects within the group III nitride semiconductor epitaxial thin film grown thereon.

[0063] In addition, the first substrate (11a) serves as a carrier sapphire substrate and does not require a relatively high quality compared to the second substrate (11b), but requires that both sides be polished to be optically transparent.

[0064] And the second substrate (11b) serves as a growth sapphire substrate in this embodiment, and is formed into an ultra-thin type in a subsequent step to function as a seed layer. This second substrate (11b) must be positioned so that the surface on which a group III nitride semiconductor such as GaN is grown becomes the upper surface, and it is required that both sides be polished to a high quality level to be optically transparent.

[0065] The bonding step (S120) is a step of bonding the first substrate (11a) and the second substrate (11b) through the bonding layer (12).

[0066] In more detail, the bonding layer (12) can be formed on the upper surface of the first substrate (11a) or the lower surface of the second substrate (11b), and then the first substrate (11a) and the second substrate (11b) can be bonded together. Preferably, the bonding layer (12) is formed on the upper surface of the first substrate (11a) and the lower surface of the second substrate (11b), respectively, and then the first substrate (11a) and the second substrate (11b) can be bonded together by applying pressure at a temperature of less than 300°C.

[0067] It is preferable that this bonding layer (12) be formed of a material that does not melt or decompose before and after the growth temperature of the semiconductor light-emitting portion (110), which is a group III nitride semiconductor layer, and at the same time does not cause issues such as contamination during the growth process. Specifically, the material forming the bonding layer (12) is a dielectric material that does not change in physical properties in the MOCVD chamber (at a temperature of 1000°C or higher and in a reducing atmosphere) in which a group III nitride semiconductor is grown. For example, SiO 2( 0.8ppm), SiN x( 3.8ppm), SiCN (3.8-4.8ppm), AlN (4.6ppm), AlO 3(6.8ppm), and further, FOx (flowable oxides) such as SOG (Spin On Glass, liquid SiO2) and HSQ (hydrogen silsesquioxane) can be included to improve surface roughness.

[0068] Meanwhile, a separation layer (13) is formed on the upper surface of the first substrate (11a), so that the second substrate (11b) can be bonded to the separation layer (13) through the bonding layer (12). However, it goes without saying that the separation layer (13) can be omitted if the separation of the first substrate (11a) is possible through the bonding layer (12).

[0069] Here, the separation layer (13) is a layer that is separated by sacrifice when the first substrate (11a) is separated using the laser lift-off (LLO) technique. It is preferable that this separation layer (13) is formed of a material that does not melt or decompose before and after the growth temperature of the semiconductor light-emitting portion (110), which is a group III nitride semiconductor layer, and at the same time does not cause issues such as contamination during the growth process. In this case, the separation layer (13) is composed of a material that allows for sacrificial separation by a thermo-chemical decomposition reaction, and for example, in the case of a sapphire growth substrate (G), it may be composed of a group III nitride semiconductor material such as GaN, InGaN, AlGaN, or InAlN.

[0070] Meanwhile, when the chemical lift-off (CLO) technique is used to separate the substrate, the separation layer (13) may be composed of a material including CrN, TiN, etc. that can be wet-etched.

[0071] The forming step (S130) is a step of manufacturing a template by forming the second substrate (11b) into an ultra-thin shape with a preset thickness so that the second substrate (11b) functions as a semiconductor seed layer.

[0072] At this time, it is preferable that the thickness of the molded sapphire second substrate (11b) be molded to have a thickness of less than 50 μm so as to enable the manufacture of a small die (epitaxial die or chip) having a thickness of less than 50 μm, which was previously impossible.

[0073] Here, the second substrate (11b) can be formed by a polishing process of a sapphire substrate, which will be described later. At this time, the final thickness (F) formed can be calculated as follows using the thickness (A) of the first substrate (11a), the thickness (B) of the second substrate (11b), the total thickness (C) of the template bonded prior to polishing forming, and the target thickness (D) of the second substrate (11b).

[0074] ⅰ) Thickness (B) of the second substrate (11b) - Target thickness (D) of the second substrate (11b) = Thickness (E) of the second substrate (11b) to be removed by polishing

[0075] ⅱ) Total thickness of the bonded template prior to polishing molding (C) - thickness of the second substrate (11b) to be removed by polishing (E) = final thickness of the second substrate (11b) after polishing (F)

[0076] In addition, the specific process is as follows, but is not limited thereto, and is not limited as long as it is for forming the second substrate (11b) to the final thickness (F). First, the second substrate (11b) sapphire is subjected to a lapping process for mechanically polishing at a high speed, and then a mechanical polishing process is performed so that the second substrate (11b) has an accurate ultra-thin final thickness (F). Thereafter, as the final forming step, a chemical mechanical polishing (CMP) process is performed so that the surface of the second substrate (11b) has a surface roughness of 0.5 nm or less to enable epitaxial growth of a group III nitride semiconductor, thereby completing the forming process.

[0077] In addition, if necessary, in order to improve the quality of the group III nitride semiconductor epitaxial thin film and maximize the light extraction efficiency after the CMP process, it is also desirable to have a protrusion shape patterned regularly or irregularly in various dimensions (size and shape) in the microscale or nanoscale on the upper surface of the sapphire of the second substrate (11b).

[0078] As smaller and smaller dies (epitaxial dies or chips) are required for manufacturing mini or micro level semiconductor light emitting devices, thinner and thinner sapphire process technology is needed.

[0079] At this time, when the thickness of the sapphire substrate was formed thinly from the beginning and then the group III nitride semiconductor was grown or bonded, a problem occurred in which the die or wafer was deformed and damaged during the forming or transfer process due to thermo-mechanical induced stress caused by the difference in lattice constant (LC) and coefficient of thermal expansion (CTE) between the sapphire substrate and the group III nitride semiconductor.

[0080] Accordingly, the present invention uses an ultra-thin sapphire substrate (second substrate (11b)) as a seed layer, and bonds a relatively thick carrier sapphire substrate (first substrate (11a)) therebelow, thereby solving the problem of wafer damage due to thermo-mechanical induced stress caused by the difference in lattice constant (LC) and coefficient of thermal expansion (CTE) between the thin sapphire substrate and the group III nitride semiconductor. After completing the structure of the semiconductor light-emitting element on such a template, by removing the thick first substrate (11a) in the final transfer process, it is possible to manufacture a small die (epitaxial die or chip) having a thickness of less than 50 μm.

[0081] The forming step (S140) is a step of forming a semiconductor light-emitting structure on the second substrate (11b) of the template. However, the present invention is not limited thereto, and the template of the present invention can also be applied to switching or wireless amplifier power semiconductor devices such as HEMT, AlN-based communication filters, etc.

[0082] Specifically, as illustrated in FIG. 3, the forming step (S140) can form an epitaxy die structure by growing a semiconductor light-emitting portion (110) on a second substrate (11b) and then forming a positive ohmic contact electrode (120) on one surface of the semiconductor light-emitting portion (110).

[0083] Here, the semiconductor light emitting part (110) generates light, and in the case of emitting ultraviolet light, blue light, green light, red light, etc., binary, ternary, and quaternary compounds such as InN, InGaN, GaN, AlGaN, AlN, AlGaInN, which are group III (Al, Ga, In) nitride semiconductors, can be arranged in an appropriate position and order on the second substrate (11b) and epitaxy grown.

[0084] In particular, a high-quality group III nitride semiconductor such as InGaN having a high indium (In) composition to emit blue or green light should be preferentially formed on top of a group III nitride semiconductor composed of GaN, AlGaN, AlN, or AlGaInN, but is not limited thereto.

[0085] The semiconductor light-emitting portion (110) includes, more specifically, a p-type semiconductor region (111), an active region (113) (multi quantum wells, MQWs), and an n-type semiconductor region (112). The semiconductor light-emitting portion (110) may have a structure in which the n-type semiconductor region (112), the active region (113), and the p-type semiconductor region (111) are sequentially epitaxially grown on a second substrate (11b), and may ultimately have a thickness of about 5.0 to 8.0 ㎛ overall, typically including several multi-layers of group III nitrides, but is not limited thereto.

[0086] Each of the p-type semiconductor region (111), the active region (113), and the n-type semiconductor region (112) may be formed as a single layer or multiple layers, and although not shown, prior to epitaxially growing the semiconductor light-emitting portion (110) on the sapphire second substrate (11b), necessary layers such as a buffer region may be added to improve the quality of the epitaxially grown semiconductor light-emitting portion (110). For example, the buffer region may be formed to have a thickness of typically about 4.0 μm, including a compliant layer composed of a nucleation layer and an undoped semiconductor region to relieve stress and improve thin film quality.

[0087] The n-type semiconductor region (112) has n-type conductivity and is formed on the second substrate (11b). This n-type semiconductor region (112) may have a thickness of 2.0 to 3.5 μm.

[0088] The active region (113) generates light by utilizing the recombination of electrons and holes, and is formed on the n-type semiconductor region (112). This active region (113) may have a thickness of several tens of nm in multiple layers.

[0089] The p-type semiconductor region (111) has p-type conductivity and is formed on the active region (113). This p-type semiconductor region (111) may have a thickness of several tens of nm to several μm in multiple layers, and the upper surface has a polarity of a group 3 element (such as Ga).

[0090] That is, the active region (113) is interposed between the p-type semiconductor region (111) and the n-type semiconductor region (112), and when the holes in the p-type semiconductor region (111), which is the p-type semiconductor region (111), and the electrons in the n-type semiconductor region (112), which is the n-type semiconductor region (112), recombine in the active region (113), light is generated.

[0091] The present invention can form an epitaxy die structure by forming an anode ohmic contact electrode (120) on one surface of the semiconductor light-emitting portion (110) described above, and can form a chip die structure or a semiconductor light-emitting element structure by performing a fab process such as etching, electrode formation, and passivation layer formation on the provided epitaxy die.

[0092] That is, in the formation step (S140), in the above-described epitaxy structure, after mesa-etching one side of the anode ohmic contact electrode (120) and the semiconductor light-emitting portion (110), a cathode ohmic contact electrode (130) is formed on one side of the etched semiconductor light-emitting portion (110), i.e., the n-type semiconductor region (112), thereby forming a chip die structure in which both the anode and the cathode are exposed to the outside.

[0093] Here, the anode ohmic contact electrode (120) plays a role in spreading (horizontal direction) the current injection (vertical direction) formed on the p-type semiconductor (GaN, AlGaN, InGaN) region, and must undergo an annealing process at 400°C or higher. This anode ohmic contact electrode (120) may be selected from the group consisting of ITO, ZnO, IZO, NiO, Pd(O), Pt(O), Ir(O), Au as a highly transparent material, Ag, AgCu, Rh, Al, alloy, DBR (TiO2 / SiO2) as a highly reflective material, or may be composed of a multilayer material having high transparency / high reflectivity, but is not limited thereto.

[0094] Additionally, the cathode ohmic contact electrode (130) (and electrode pad) may be selected from the group consisting of Ti, Cr, Al, V, Re, Ni, Pt, Au, TiN, VN, CrN, ITO, IZO and / or ZnO, but is not limited thereto.

[0095] A semiconductor laminate using a semiconductor element template according to this includes a separation layer (13) formed on a first substrate (11a), a bonding layer (12) formed on the separation layer (13), a second substrate (11b) formed on the bonding layer (12) but formed into an ultra-thin shape with a preset thickness, and a semiconductor light-emitting structure formed on the second substrate (11b), and the semiconductor light-emitting structure may have an epitaxial die structure including a semiconductor light-emitting portion (110) grown on the second substrate (11b) and an anode ohmic contact electrode (120) formed on the semiconductor light-emitting portion (110), and further, one side of the anode ohmic contact electrode (120) and the semiconductor light-emitting portion (110) is etched, and a cathode ohmic contact electrode (130) is formed on one side of the etched semiconductor light-emitting portion (110), i.e., an n-type semiconductor region (112), so that the anode and the cathode are connected. They may all have an externally exposed chip die (horizontal chip or flip chip) structure.

[0096]

[0097] From now on, with reference to the attached drawings, a method (S200) for manufacturing a semiconductor laminate using a semiconductor element template according to the second embodiment of the present invention will be described in detail.

[0098] FIG. 4 is a flowchart of a method for manufacturing a semiconductor laminate using a template for a semiconductor device according to a second embodiment of the present invention, and FIGS. 5 to 7 illustrate a process for manufacturing a semiconductor laminate using a template for a semiconductor device according to a second embodiment of the present invention.

[0099] As illustrated in FIGS. 4 to 7, a method (S200) for manufacturing a semiconductor laminate using a semiconductor element template according to a second embodiment of the present invention includes a preparation step (S210), a bonding step (S220), a molding step (S230), and a forming step (S240) for bonding a semiconductor light-emitting part (110) onto a semiconductor element template.

[0100] The preparation step (S210) is a step of preparing the first substrate (11a) and the second substrate (11b).

[0101] Here, the first substrate (11a) and the second substrate (11b) are prepared as sapphire substrates. These sapphire substrates are optically transparent and have high temperature resistance, through which a laser beam (single wavelength light) can theoretically be 100% transmitted without absorption in a laser lift off (LLO) process, and can be prepared as α-phase Al2O3 sapphire (including ScAlMgO4).

[0102] In addition, the first substrate (11a) serves as a carrier sapphire substrate, and the first substrate (11a) and the second substrate (11b) are required to be optically transparent by being polished on both sides.

[0103] The bonding step (S220) is a step of bonding the first substrate (11a) and the second substrate (11b) through the bonding layer (12).

[0104] In more detail, the bonding layer (12) can be formed on the upper surface of the first substrate (11a) or the lower surface of the second substrate (11b), and then the first substrate (11a) and the second substrate (11b) can be bonded together. Preferably, the bonding layer (12) is formed on the upper surface of the first substrate (11a) and the lower surface of the second substrate (11b), respectively, and then the first substrate (11a) and the second substrate (11b) can be bonded together by applying pressure. In the present embodiment, the bonding layer (12) can be made of a metal having a strong bonding force, such as Sn, In, Au, Ag, Cu, or Pd, or an alloy such as Au-Sn, Ni-Sn, Ag-In, Cu-Sn, or Pd-In, or a dielectric, etc.

[0105] Meanwhile, a separation layer (13) is formed on the upper surface of the first substrate (11a), so that the second substrate (11b) can be bonded to the separation layer (13) through the bonding layer (12). However, it goes without saying that the separation layer (13) can be omitted if the separation of the first substrate (11a) is possible through the bonding layer (12).

[0106] Here, the separation layer (13) is a layer that is separated by sacrifice when the first substrate (11a) is separated using the laser lift-off (LLO) technique, and the separation layer (13) is composed of a material that can be separated by sacrifice by a thermal-chemical decomposition reaction, for example, PZT, ITO, ZnO, IZO, ZITO, In2O3, SnO2, SiN. x , GaNO, GaO x , InGaO, InGaNO, etc.

[0107] The forming step (S230) is a step of manufacturing a template by forming the second substrate (11b) into an ultra-thin shape with a preset thickness.

[0108] The following contents of the forming step (S230) are the same as the method for manufacturing a semiconductor laminate using a semiconductor element template according to the first embodiment of the present invention described above (S100), so a duplicate description is omitted.

[0109] The forming step (S240) is a step of forming a semiconductor light-emitting structure on the second substrate (11b) of the template. However, the present invention is not limited thereto, and the template of the present invention can also be applied to switching or wireless amplifier power semiconductor devices such as HEMT, AlN-based communication filters, etc.

[0110] At this time, the forming step (S240) forms a positive ohmic contact electrode (120) on one surface of the semiconductor light-emitting portion (110), and then bonds the other surface of the semiconductor light-emitting portion (110) to the second substrate (11b) through the bonding layer (B) to form an epitaxial die structure.

[0111] Specifically, as illustrated in FIG. 5, in the present embodiment, a semiconductor light-emitting portion (110) may be grown through a separate growth substrate (G), and then a positive ohmic contact electrode (120) may be formed on one surface of the semiconductor light-emitting portion (110). Thereafter, a temporary substrate (T) may be bonded on the positive ohmic contact electrode (120), and the sapphire growth substrate (G) may be removed through laser lift-off to expose the other surface of the semiconductor light-emitting portion (110) to the outside, and then the other surface of the semiconductor light-emitting portion (110) may be bonded to a second substrate (11b) through a bonding layer (B), and the temporary substrate (T) may be removed. Meanwhile, in the case of a red light-emitting element, the GaAs growth substrate (G) can be removed through chemical lift-off, and a protective layer (P) can be inserted when bonding the anode ohmic contact electrode (120) and the temporary substrate (T), and of course, a sacrificial layer can be inserted for removing the temporary substrate (T).

[0112] In addition, the Ga droplet residue on the other surface of the light-emitting portion exposed to the outside (the surface of the n-type semiconductor region (112)) can be removed, or a patterning or CMP process can be performed, and the bonding layer (B) can be made of a transparent material such as SiO2 or SiN. x , AlN, Al2O3, and further, FOx (flowable oxides) such as SOG (Spin On Glass, liquid SiO2), HSQ (hydrogen silsesquioxane) can be included to improve surface roughness.

[0113] A semiconductor laminate using a semiconductor element template according to this includes a separation layer (13) formed on a first substrate (11a), a bonding layer (12) formed on the separation layer (13), a second substrate (11b) formed on the bonding layer (12) but formed into an ultra-thin shape with a preset thickness, and a semiconductor light-emitting structure formed on the second substrate (11b), and the semiconductor light-emitting structure may have an epitaxial die structure including a bonding layer (B) formed on the second substrate (11b), a semiconductor light-emitting portion (110) bonded on the bonding layer (B), and an anode ohmic contact electrode (120) formed on the semiconductor light-emitting portion (110). Furthermore, one side of the positive ohmic contact electrode (120) and the semiconductor light-emitting portion (110) is etched, and a negative ohmic contact electrode (130) is formed on one side of the etched semiconductor light-emitting portion (110), i.e., on the n-type semiconductor region (112), so that a chip die structure in which both the positive and negative electrodes are exposed to the outside can be provided.

[0114] In addition, the forming step (S140) may form an anode ohmic contact electrode (120) on one surface of the semiconductor light-emitting portion (110), form a cathode ohmic contact electrode (130) and a protective layer (P) on the other surface of the semiconductor light-emitting portion (110), and then bond the protective layer (P) to the second substrate (11b) through the bonding layer (B) to form an epitaxial die structure.

[0115] Specifically, as illustrated in FIG. 6, in the present embodiment, a semiconductor light-emitting portion (110) may be grown through a separate growth substrate (G), and then a positive ohmic contact electrode (120) may be formed on one surface of the semiconductor light-emitting portion (110). Thereafter, a temporary substrate (T) is bonded on the positive ohmic contact electrode (120), and the growth substrate (G) is removed through laser lift-off to expose the other surface of the semiconductor light-emitting portion (110) to the outside, and then a negative ohmic contact electrode (130) and a protective layer (P) (SiO2, SiN) are formed on the other surface of the semiconductor light-emitting portion (110). x ) can be formed. Thereafter, the protective layer (P) can be bonded to the second substrate (11b) through the bonding layer (B), and the temporary substrate (T) can be removed. Meanwhile, it goes without saying that the protective layer (P) can be inserted even when bonding the positive ohmic contact electrode (120) and the temporary substrate (T).

[0116] Furthermore, when one side of the positive ohmic contact electrode (120) and the semiconductor light-emitting portion (110) is etched to expose the negative ohmic contact electrode (130) to the outside, a chip die structure in which both the positive and negative electrodes are exposed to the outside can be formed.

[0117] A semiconductor laminate using a semiconductor element template according to this includes a separation layer (13) formed on a first substrate (11a), a bonding layer (12) formed on the separation layer (13), a second substrate (11b) formed on the bonding layer (12) but formed into an ultra-thin shape with a preset thickness, and a semiconductor light-emitting structure formed on the second substrate (11b), and the semiconductor light-emitting structure may have an epitaxial die structure including a protective layer (P) formed on the second substrate (11b), a cathode ohmic contact electrode (130) formed on the protective layer (P), a semiconductor light-emitting part (110) formed on the cathode ohmic contact electrode (130), and an anode ohmic contact electrode (120) formed on the semiconductor light-emitting part (110), and one side of the anode ohmic contact electrode (120) and the semiconductor light-emitting part (110) is etched to form a cathode. By exposing the ohmic contact electrode (130) to the outside, it is possible to have a chip die structure in which both the anode and cathode are exposed to the outside.

[0118] In addition, the forming step (S140) may form a positive ohmic contact electrode (120) on one surface of the semiconductor light-emitting portion (110), and then bond the positive ohmic contact electrode (120) to the second substrate (11b) through the bonding layer (B), and after bonding, form a negative ohmic contact electrode (130) on the other surface of the semiconductor light-emitting portion (110) to form an epitaxial die structure.

[0119] Specifically, as illustrated in FIG. 7, in the present embodiment, a semiconductor light-emitting portion (110) may be grown through a separate growth substrate (G), and then a positive ohmic contact electrode (120) may be formed on one surface of the semiconductor light-emitting portion (110). Thereafter, a protective layer (P) may be formed on the positive ohmic contact electrode (120), and then the protective layer (P) may be bonded to a second substrate (11b) through a bonding layer (B), and the growth substrate (G) may be removed through laser lift-off to expose the other surface of the semiconductor light-emitting portion (110) to the outside. Furthermore, a negative ohmic contact electrode (130) may be formed on the other surface of the semiconductor light-emitting portion (110), and when the negative ohmic contact electrode (130) and one side of the semiconductor light-emitting portion (110) are etched to expose the positive ohmic contact electrode (120) to the outside, a chip die structure in which both the positive and negative electrodes are exposed to the outside may be formed.

[0120] A semiconductor laminate using a semiconductor element template according to this includes a separation layer (13) formed on a first substrate (11a), a bonding layer (12) formed on the separation layer (13), a second substrate (11b) formed on the bonding layer (12) but formed into an ultra-thin shape with a preset thickness, and a semiconductor light-emitting structure formed on the second substrate (11b), and the semiconductor light-emitting structure may include a protective layer (P) formed on the second substrate (11b), a positive ohmic contact electrode (120) formed on the protective layer (P), and a semiconductor light-emitting part (110) formed on the positive ohmic contact electrode (120). Furthermore, the semiconductor laminate may have an epitaxial die structure in which a cathode ohmic contact electrode (130) is formed on a semiconductor light-emitting portion (110), and one side of the cathode ohmic contact electrode (130) and the semiconductor light-emitting portion (110) is etched to expose the anode ohmic contact electrode (120) to the outside, thereby having a chip die structure in which both the anode and the cathode are exposed to the outside.

[0121]

[0122] FIG. 8 illustrates another laminated structure having an etch-stop layer in a method for manufacturing a semiconductor laminate using a template for a semiconductor element according to the first or second embodiment of the present invention, and FIG. 9 illustrates a semiconductor light-emitting portion being divided into a plurality of regions through an etch-stop layer in a method for manufacturing a semiconductor laminate using a template for a semiconductor element according to the first or second embodiment of the present invention.

[0123] Meanwhile, as illustrated in FIGS. 8 and 9, a semiconductor laminate using a template for a semiconductor element of the present invention may include a first substrate (11a), a separation layer (13), a bonding layer (12), and an ultra-thinly formed second substrate (11b), in which a semiconductor light-emitting portion (110) is formed on a template, and then a bonding pad layer (BP) for die bonding may be formed on the semiconductor light-emitting portion (110). At this time, an etching stop layer (E) may be provided between the semiconductor light-emitting portion (110) and the bonding pad layer (BP) to prevent the bonding pad layer (BP) from being etched (FIG. 8 illustrates a state in which the template is arranged on the upper side and the bonding pad layer (BP) is arranged on the lower side, and the bonding pad layer (BP) is visible through the transparent template and the semiconductor light-emitting portion (110).

[0124] That is, when dividing the semiconductor light-emitting portion in the present invention into multiple regions (for example, dividing into three chip dies), if the semiconductor light-emitting portion (110) is etched to the extent that it is completely isolated from each other (Full Isolation), a part of the bonding pad layer (BP) having a metal component at the division boundary may be etched together and then redeposited, which may cause a defect in the device.

[0125] Accordingly, the semiconductor laminate of the present invention has a window or window frame shape and is provided with an etch-stop layer (E) arranged on a split boundary surface, thereby preventing the bonding pad layer (BP) from being etched on the split boundary surface. This etch-stop layer (E) is made of SiO2, SiN x , can be formed from dielectric materials, etc.

[0126] In addition, the bonding pad layer (BP) for die bonding may be composed of multiple layers, each for a different function, and specifically, may be composed of a die bonding layer that is directly bonded to a die, a substrate, etc., a material diffusion barrier layer formed on the die bonding layer and used to prevent material diffusion, a reflective layer formed on the material diffusion barrier layer and made of a highly reflective material such as a metal alloy, and an ohmic contact layer formed on the reflective layer and made in ohmic contact with a semiconductor light-emitting portion (110).

[0127]

[0128] Although all components constituting the embodiments of the present invention have been described as being combined or operating in combination as one, the present invention is not necessarily limited to such embodiments. That is, within the scope of the present invention, all of the components may be selectively combined and operated in one or more combinations.

[0129] Furthermore, terms such as "include," "comprise," or "have" described above, unless specifically stated otherwise, imply that the corresponding component may be present, and therefore should be interpreted to include other components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as terms defined in dictionaries, should be interpreted to be consistent with the contextual meaning of the relevant technology, and shall not be interpreted in an ideal or overly formal sense, unless explicitly defined in the present invention.

[0130] The above description is merely an example of the technical idea of ​​the present invention, and those skilled in the art will appreciate that various modifications and variations can be made without departing from the essential characteristics of the present invention.

[0131] Accordingly, the embodiments disclosed in the present invention are intended to illustrate, rather than limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical concepts within the scope equivalent thereto should be construed as being included within the scope of the present invention.

Claims

1. Preparatory step of preparing the first substrate and the second substrate; A bonding step of bonding the first substrate and the second substrate through a bonding layer; A molding step for manufacturing a template by molding the second substrate into an ultra-thin shape with a preset thickness; and A method for manufacturing a semiconductor laminate using a template for a semiconductor device, comprising a forming step of forming a semiconductor light-emitting structure on the second substrate of the template.

2. In claim 1, The above formation stage is, A method for manufacturing a semiconductor laminate using a template for a semiconductor element, which comprises growing a semiconductor light-emitting portion on the second substrate and then forming a positive ohmic contact electrode on one surface of the semiconductor light-emitting portion.

3. In claim 2, The above formation stage is, A method for manufacturing a semiconductor laminate using a template for a semiconductor element, wherein one side of the positive ohmic contact electrode and the semiconductor light-emitting portion is etched, and then a negative ohmic contact electrode is formed on one side of the etched semiconductor light-emitting portion.

4. In claim 1, The above formation stage is, A method for manufacturing a semiconductor laminate using a template for a semiconductor element, wherein a positive ohmic contact electrode is formed on one surface of a semiconductor light-emitting portion, and then the other surface of the semiconductor light-emitting portion is bonded to the second substrate through a bonding layer.

5. In claim 1, The above formation stage is, A method for manufacturing a semiconductor laminate using a template for a semiconductor element, wherein a positive ohmic contact electrode is formed on one surface of a semiconductor light-emitting portion, a negative ohmic contact electrode and a protective layer are formed on the other surface of the semiconductor light-emitting portion, and then the protective layer is bonded to the second substrate through a bonding layer.

6. In claim 5, The above formation stage is, A method for manufacturing a semiconductor laminate using a template for a semiconductor element, wherein one side of the positive ohmic contact electrode and the semiconductor light-emitting portion is etched to expose the negative ohmic contact electrode to the outside.

7. In claim 1, The above formation stage is, A method for manufacturing a semiconductor laminate using a template for a semiconductor element, wherein a positive ohmic contact electrode is formed on one surface of a semiconductor light-emitting portion, and then the positive ohmic contact electrode is bonded to the second substrate through a bonding layer.

8. In claim 7, The above formation stage is, A method for manufacturing a semiconductor laminate using a semiconductor element template, which forms a cathode ohmic contact electrode on the other surface of the semiconductor light-emitting portion.

9. In claim 8, The above formation stage is, A method for manufacturing a semiconductor laminate using a template for a semiconductor element, wherein one side of the cathode ohmic contact electrode and the semiconductor light-emitting portion is etched to expose the anode ohmic contact electrode to the outside.

10. In claim 1, The above first substrate and the above second substrate, A method for manufacturing a semiconductor laminate using a sapphire substrate as a template for a semiconductor device.

11. In claim 10, The thickness of the second substrate formed in the above forming step is: A method for manufacturing a semiconductor laminate using a semiconductor element template having a diameter of less than 50㎛.

12. In claim 1, On the upper surface of the first substrate, A separation layer is formed, The above bonding step is, A method for manufacturing a semiconductor laminate using a semiconductor element template, wherein the separation layer and the second substrate are bonded through the bonding layer.

13. First substrate; A separation layer formed on the first substrate; A bonding layer formed on the above separation layer; A second substrate formed on the above bonding layer and formed into an ultra-thin shape with a preset thickness; and A semiconductor laminate using a template for a semiconductor element, comprising a semiconductor light-emitting structure formed on the second substrate.

14. In claim 13, The above semiconductor light emitting structure is, A semiconductor laminate using a template for a semiconductor element, comprising a semiconductor light-emitting portion grown on the second substrate and a positive ohmic contact electrode formed on the semiconductor light-emitting portion.

15. In claim 14, The above-mentioned positive ohmic contact electrode and the above-mentioned semiconductor light-emitting part, One side is etched, On one side of the etched semiconductor light-emitting portion, A semiconductor laminate using a template for a semiconductor device, in which a negative ohmic contact electrode is formed.

16. In claim 13, The above semiconductor light emitting structure is, A semiconductor laminate using a template for a semiconductor element, comprising a bonding layer formed on the second substrate, a semiconductor light-emitting portion formed on the bonding layer, and a positive ohmic contact electrode formed on the semiconductor light-emitting portion.

17. In claim 13, The above semiconductor light emitting structure is, A semiconductor laminate using a template for a semiconductor element, comprising a bonding layer formed on the second substrate, a protective layer formed on the bonding layer, a cathode ohmic contact electrode formed on the protective layer, a semiconductor light-emitting portion formed on the cathode ohmic contact electrode, and a positive ohmic contact electrode formed on the semiconductor light-emitting portion.

18. In claim 17, The above-mentioned positive ohmic contact electrode and the above-mentioned semiconductor light-emitting part, A semiconductor laminate using a template for a semiconductor device, one side of which is etched so that the cathode ohmic contact electrode is exposed to the outside.

19. In claim 13, The above semiconductor light emitting structure is, A semiconductor laminate using a template for a semiconductor element, comprising a protective layer formed on the second substrate, a positive ohmic contact electrode formed on the protective layer, and a semiconductor light-emitting portion formed on the positive ohmic contact electrode.

20. In claim 19, The above semiconductor light emitting structure is, A semiconductor laminate using a template for a semiconductor element, further comprising a cathode ohmic contact electrode formed on the semiconductor light emitting portion.

21. In claim 20, The above cathode ohmic contact electrode and the semiconductor light emitting part, A semiconductor laminate using a template for a semiconductor device, one side of which is etched to expose the anode ohmic contact electrode to the outside.

22. In claim 13, The above first substrate and the above second substrate, A semiconductor laminate using a sapphire substrate as a template for semiconductor devices.

23. In claim 22, The thickness of the above second substrate is A semiconductor laminate using a template for a semiconductor device having a thickness of less than 50㎛.

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