Display device and electronic device comprising same

Abstract

A display device according to an embodiment may comprise: a first sub-pixel and a second sub-pixel arranged in a first direction and constituting a first sub-pixel unit; a third sub-pixel and a fourth sub-pixel arranged in the first direction and constituting a second sub-pixel unit positioned adjacent to the first sub-pixel unit; a pixel circuit provided in each of the first to fourth sub-pixels; a vertical bridge line extending in a second direction and disposed in each of the first and second sub-pixel units; a data line extending in the second direction and disposed to be spaced apart from the vertical bridge line; a horizontal bridge line extending along the first direction; and a dummy electrode positioned at a boundary part between the first sub-pixel unit and the second sub-pixel unit and electrically connected to the horizontal bridge line. The dummy electrode may be electrically connected to at least one of the first and second sub-pixel units.

Description

Display device and electronic device including same

[0001] The present invention relates to a display device and an electronic device including the same.

[0002] As interest in information displays has grown recently, research and development on display devices are continuously being conducted.

[0003] The present invention can provide a display device capable of improving space efficiency and an electronic device including the same.

[0004] A display device according to one embodiment may include: first sub-pixels and second sub-pixels arranged along a first direction and constituting a first sub-pixel unit; third sub-pixels and fourth sub-pixels arranged along the first direction and constituting a second sub-pixel unit adjacent to the first sub-pixel unit; pixel circuits of each of the first to fourth sub-pixels; a vertical bridge line extending in a second direction and disposed in each of the first and second sub-pixel units; a data line extending in the second direction and spaced apart from the vertical bridge line; a horizontal bridge line extending along the first direction; and a dummy electrode positioned at a boundary portion between the first sub-pixel unit and the second sub-pixel unit and electrically connected to the horizontal bridge line. The dummy electrode may be electrically connected to at least one of the first and second sub-pixel units.

[0005] In one embodiment, when viewed on a plane, the vertical bridge line may be positioned closer to the edge of each of the first and second sub-pixel units than the data line.

[0006] In one embodiment, the vertical bridge line may include a first vertical bridge line, a second vertical bridge line, a third vertical bridge line, and a fourth vertical bridge line arranged along the first direction. The first vertical bridge line may overlap the pixel circuit of the first sub-pixel, the second vertical bridge line may overlap the pixel circuit of the second sub-pixel, the third vertical bridge line may overlap the pixel circuit of the third sub-pixel, and the fourth vertical bridge line may overlap the pixel circuit of the fourth sub-pixel. When viewed in a plan view, the dummy electrode may be disposed between the second vertical bridge line and the third vertical bridge line.

[0007] In one embodiment, the data line may include a first data line spaced apart from the first vertical bridge line, a second data line spaced apart from the second vertical bridge line, a third data line spaced apart from the third vertical bridge line, and a fourth data line spaced apart from the fourth vertical bridge line. When viewed in a plan view, the second vertical bridge line may be positioned closer to the dummy electrode than the second data line, and the third vertical bridge line may be positioned closer to the dummy electrode than the third data line.

[0008] In one embodiment, the display device may further include a first via layer including a first via hole disposed on the horizontal bridge line and exposing an area of ​​the horizontal bridge line; and a second via layer including a second via hole disposed on the dummy electrode and exposing an area of ​​the dummy electrode. The first to fourth vertical bridge lines may be disposed on the second via layer, and the dummy electrode may be disposed between the first via layer and the second via layer. The dummy electrode may be electrically connected to the horizontal bridge line through the first via hole.

[0009] In one embodiment, one end of the dummy electrode may be electrically connected to the horizontal bridge line through the first via hole, and the other end of the dummy electrode may be electrically connected to at least one of the second vertical bridge line and the third vertical bridge line through the second via hole.

[0010] In one embodiment, the display device may further include a first additional conductive pattern disposed between the first via layer and the second via layer of the second sub-pixel and under the second vertical bridge line, and electrically connected to the second vertical bridge line; and a second additional conductive pattern disposed between the first via layer and the second via layer of the third sub-pixel and under the third vertical bridge line, and electrically connected to the third vertical bridge line. The first and second additional conductive patterns may be disposed on the same layer as the dummy electrode. The dummy electrode may be formed integrally with at least one of the first and second additional conductive patterns.

[0011] In one embodiment, the display device may further include an additional conductive pattern disposed below at least one of the second and third vertical bridge lines between the first via layer and the second via layer. The additional conductive pattern may be disposed in the same layer as the dummy electrode and may be formed integrally with the dummy electrode.

[0012] In one embodiment, when viewed in a planar manner, the data line may be closer to an edge of each of the first and second sub-pixel units than the vertical bridge line.

[0013] According to one embodiment, a display device includes a substrate including a display area including a first area and a second area, and a non-display area surrounding at least one side of the display area; first and second sub-pixels arranged along a first direction in each of first and second pixel rows of the substrate and forming a first sub-pixel unit; third and fourth sub-pixels arranged along the first direction in each of the first and second pixel rows of the substrate and forming a second sub-pixel unit adjacent to the first sub-pixel unit; pixel circuits provided in each of the first to fourth sub-pixels; a vertical bridge line extending in a second direction and disposed in each of the first and second sub-pixel units; a data line extending in the second direction and spaced apart from the vertical bridge line; a first horizontal bridge line extending along the first direction in the first pixel row; a second horizontal bridge line extending along the first direction in the second pixel row; The first dummy electrode may be positioned at a boundary between the first sub-pixel unit and the second sub-pixel unit in the first pixel row and electrically connected to the first horizontal bridge line; and the second dummy electrode may be positioned at a boundary between the first sub-pixel unit and the second sub-pixel unit in the second pixel row and electrically connected to the second horizontal bridge line. When viewed in a plan view, the first dummy electrode and the second dummy electrode may be positioned in the same column.

[0014] In one embodiment, when viewed in a plan view, the vertical bridge line may be closer to an edge of each of the first and second sub-pixel units than the data line.

[0015] In one embodiment, the vertical bridge line may include a first vertical bridge line, a second vertical bridge line, a third vertical bridge line, and a fourth vertical bridge line arranged along the first direction in each of the first and second pixel rows. The first vertical bridge line may overlap the pixel circuit of the first sub-pixel, the second vertical bridge line may overlap the pixel circuit of the second sub-pixel, the third vertical bridge line may overlap the pixel circuit of the third sub-pixel, and the fourth vertical bridge line may overlap the pixel circuit of the fourth sub-pixel. When viewed in a plan view, each of the first and second dummy electrodes may be disposed between the second vertical bridge line and the third vertical bridge line.

[0016] In one embodiment, the data line may include a first data line spaced apart from the first vertical bridge line, a second data line spaced apart from the second vertical bridge line, a third data line spaced apart from the third vertical bridge line, and a fourth data line spaced apart from the fourth vertical bridge line. When viewed in a plan view, the second vertical bridge line may be positioned closer to the first and second dummy electrodes than the second data line, and the third bridge line may be positioned closer to the first and second dummy electrodes than the third data line.

[0017] In one embodiment, the first dummy electrode may be electrically connected to at least one of the second and third vertical bridge lines, and the second dummy electrode may be electrically connected to the remaining of the second and third vertical bridge lines.

[0018] In one embodiment, the display device may further include a first additional conductive pattern overlapping a portion of the second vertical bridge line in the second sub-pixel of each of the first and second pixel rows; and a second additional conductive pattern overlapping a portion of the third vertical bridge line in the third sub-pixel of each of the first and second pixel rows. The first and second additional conductive patterns may be arranged in the same layer as the first and second dummy electrodes. The first dummy electrode may be formed integrally with the second additional conductive pattern, and the second dummy electrode may be formed integrally with the first additional conductive pattern.

[0019] In one embodiment, the display device may further include a first via layer disposed on the first and second horizontal bridge lines, the first via layer including an eleventh via hole exposing a portion of the first horizontal bridge line and a twelfth via hole exposing a portion of the second horizontal bridge line; and a second via layer disposed on the first and second additional conductive patterns, the second via layer including a twenty-first via hole exposing a portion of the first additional conductive pattern and a twenty-second via hole exposing a portion of the second additional conductive pattern. The first to fourth vertical bridge lines may be disposed on the second via layer, and the first and second dummy electrodes and the first and second additional conductive patterns may be disposed between the first via layer and the second via layer.

[0020] In one embodiment, the first dummy electrode may be electrically connected to the first horizontal bridge line through the eleventh via hole, and the second additional conductive pattern formed integrally with the first dummy electrode may be electrically connected to the third vertical bridge line through the twenty-second via hole. The second dummy electrode may be electrically connected to the second horizontal bridge line through the twelfth via hole, and the first additional conductive pattern formed integrally with the second dummy electrode may be electrically connected to the second vertical bridge line through the twenty-first via hole.

[0021] In one embodiment, the eleventh via hole and the twelfth via hole may be located at a boundary portion between the first sub-pixel unit and the second sub-pixel unit. When viewed in a plane, the eleventh via hole and the twelfth via hole may be located in the same row.

[0022] In one embodiment, the method may further include: a second additional conductive pattern positioned below the third vertical bridge line in the first pixel row and overlapping a portion of the third vertical bridge line; and a first additional conductive pattern positioned below the second vertical bridge line in the second pixel row and overlapping a portion of the second vertical bridge line. The first dummy electrode may be formed integrally with the second additional conductive pattern, and the second dummy electrode may be formed integrally with the first additional conductive pattern.

[0023] In one embodiment, when viewed on a plane, the data line may be arranged closer to the edge of each of the first and second sub-pixel units than the vertical bridge line.

[0024] An electronic device according to one embodiment may include a processor configured to provide input image data to a display device; and a display device configured to display an image based on the input image data. The display device may include first and second sub-pixels arranged in a first direction and constituting a first sub-pixel unit; third and fourth sub-pixels arranged in the first direction and constituting a second sub-pixel unit positioned adjacent to the first sub-pixel unit; pixel circuits provided in each of the first to fourth sub-pixels; a vertical bridge line extending in a second direction and disposed in each of the first and second sub-pixel units; a data line extending in the second direction and disposed spaced apart from the vertical bridge line; a horizontal bridge line extending along the first direction; and a dummy electrode positioned at a boundary portion between the first and second sub-pixel units and electrically connected to the horizontal bridge line. The dummy electrode may be electrically connected to at least one of the first and second sub-pixel units.

[0025] According to embodiments, an electrode pattern (or dummy electrode) electrically connected to a horizontal bridge line through a first via hole may be arranged at a boundary portion between a first sub-pixel unit and a second sub-pixel unit arranged in each pixel row in one area of ​​a display area.

[0026] According to embodiments, in each pixel row, an electrode pattern (or a first via hole) is arranged at a boundary portion between a first sub-pixel unit and a second sub-pixel unit, so that the electrode pattern (or the first via hole) can be concentratedly positioned in a specific region of the display area. Accordingly, design constraints according to the position of the electrode pattern (or the first via hole) for each pixel row in the display area are reduced, so that design optimization for horizontal bridge lines and vertical bridge lines in the display area is possible, thereby further securing the effective space of each sub-pixel.

[0027] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0028] Figure 1 is a schematic plan view showing a display device according to one embodiment.

[0029] Figure 2 is a schematic plan view showing a display device according to one embodiment.

[0030] Figure 3 is a schematic enlarged view showing the EA1 portion of Figure 2.

[0031] FIG. 4 is a drawing showing an example of a display area of ​​a display panel included in the display device of FIG. 2.

[0032] Fig. 5 is a circuit diagram showing an example of a sub-pixel included in the display area of ​​Fig. 1.

[0033] FIG. 6 is a schematic cross-sectional view showing one area of ​​a display device according to one embodiment.

[0034] FIG. 7 is a schematic plan view showing sub-pixels located in one area of ​​a display area of ​​a display device according to one embodiment.

[0035] FIG. 8 is a schematic plan view showing only the configurations included in the first, second, fifth, sixth, seventh, and eighth transistors and the first conductive layer in FIG. 7.

[0036] Fig. 9 is a schematic plan view showing only the components included in the second challenge layer in Fig. 7.

[0037] FIG. 10 is a schematic plan view showing only the third and fourth transistors and the configurations included in the third conductive layer in FIG. 7.

[0038] Fig. 11 is a schematic plan view showing only the components included in the fourth challenge layer in Fig. 7.

[0039] Fig. 12 is a schematic plan view showing only the components included in the fifth challenge layer in Fig. 7.

[0040] Fig. 13 is a schematic plan view showing only the components included in the 6th challenge layer in Fig. 7.

[0041] FIG. 14 is a schematic plan view showing only the components included in the fourth conductive layer, fifth conductive layer, and sixth conductive layer in FIG. 7.

[0042] Figure 15 is a schematic enlarged view showing the EA2 portion of Figure 14.

[0043] Figure 16 is a schematic cross-sectional view taken along lines Ⅰ to Ⅰ' of Figure 15.

[0044] FIG. 17 is a schematic plan view showing sub-pixels arranged in first and second pixel rows located in one area of ​​a display area of ​​a display device according to one embodiment.

[0045] FIG. 18 is a schematic drawing showing the positions of a first via hole and a second via hole in one area of ​​a display area of ​​a display device according to one embodiment.

[0046] FIG. 19 is a schematic plan view showing sub-pixels located in one area of ​​a display area of ​​a display device according to one embodiment.

[0047] Figures 20 and 21 are schematic enlarged views showing the EA3 portion of Figure 19.

[0048] FIG. 22 is a schematic plan view showing sub-pixels arranged in first and second pixel rows located in one area of ​​a display area of ​​a display device according to one embodiment.

[0049] FIG. 23 is a schematic drawing showing the positions of a first via hole and a second via hole in one area of ​​a display area of ​​a display device according to one embodiment.

[0050] FIG. 24 is a schematic plan view showing sub-pixels arranged in first and second pixel rows located in one area of ​​a display area of ​​a display device according to one embodiment.

[0051] Figure 25 is a schematic enlarged view showing the EA4 portion of Figure 24.

[0052] Figure 26 is a schematic cross-sectional view taken along lines Ⅱ to Ⅱ' of Figure 25.

[0053] FIG. 27 is a block diagram showing an electronic device according to one embodiment.

[0054] FIG. 28 is a schematic diagram showing an example of a smartphone that can be implemented using the electronic device of FIG. 27.

[0055] FIG. 29 is a schematic diagram showing an example of a tablet computer that can be implemented using the electronic device of FIG. 27.

[0056] The present invention is susceptible to various modifications and takes various forms. Specific embodiments are illustrated in the drawings and described in detail herein. However, this is not intended to limit the present invention to specific disclosed forms, but rather to encompass all modifications, equivalents, and alternatives falling within the technical scope of the present invention.

[0057] In describing each drawing, similar reference numerals are used to designate similar components. In the attached drawings, the dimensions of structures are shown exaggerated for clarity of the present invention. Terms such as first, second, etc. may be used to describe various components, but these components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the scope of the present invention, a first component could be referred to as a second component, and similarly, a second component could also be referred to as a first component.

[0058] In this application, terms such as "include" or "have" are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but should be understood to not preemptively exclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. In addition, when a part such as a layer, film, region, or plate is said to be "on" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. In addition, in this specification, when a part such as a layer, film, region, or plate is said to be formed on another part, the direction in which it is formed is not limited to the upper direction, but also includes the case where it is formed in the side or lower direction. Conversely, when a part such as a layer, film, region, or plate is said to be "under" another part, this includes not only the case where it is "directly below" the other part, but also the case where there is another part in between.

[0059] Hereinafter, with reference to the attached drawings, preferred embodiments of the present invention and other details necessary for those skilled in the art to easily understand the content of the present invention will be described in detail. In the following description, singular expressions also include plural expressions, unless the context clearly indicates that only the singular is included.

[0060] The terms "about" or "approximately" as used herein include the stated value and mean an acceptable range of variation, as determined by a person skilled in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (e.g., limitations of the measurement system). For example, "about" could mean within one or more standard deviations, or within about ±30%, ±20%, ±10%, or ±5% of the stated value.

[0061] In the description, the term "and / or" is used to include all combinations of "and" and "or" for the purposes of its meaning and interpretation. For example, "A and / or B" can be understood to mean "A, B, or A and B." The terms "and" and "or" can be used in either a conjunctive or disjunctive sense and can be understood as equivalent to "and / or." In the description, the expression "at least one" is used to include the meaning "at least one selected from the group" for the purposes of its meaning and interpretation. For example, "at least one of A and B" can be understood to mean "A, B, or A and B."

[0062] Those skilled in the art will understand, when considering the entire disclosure, that suitable features included in each of the various embodiments of the disclosure may be partially or fully combined or interlocked with one another, and may be interlocked and operated in various technically suitable ways. Furthermore, unless otherwise specified or implied, each embodiment may be implemented independently of the other or together in a mutually suitable manner.

[0063] FIG. 1 is a schematic plan view showing a display device (DD) according to one embodiment.

[0064] In Fig. 1, for convenience, the structure of a display device (DD), for example, a display panel (DP) provided in the display device (DD), is briefly illustrated with a display area (DA) where an image is displayed as the center.

[0065] Referring to FIG. 1, a display device (DD) (or display panel (DP)) may include a substrate (SUB) and sub-pixels (SPX).

[0066] The display device (DD) may be provided in various shapes, and for example, may be provided in the shape of a rectangular plate having two pairs of sides that are parallel to each other, but is not limited thereto. If the display device (DD) is an electronic device having a display surface applied to at least one surface, such as a smart phone, a television, a tablet PC, a mobile phone, a video phone, an e-book reader, a desktop PC, a laptop PC, a netbook computer, a workstation, a server, a PDA, a portable multimedia player (PMP), an MP3 player, a medical device, a camera, and / or a wearable, the present embodiment may be applied.

[0067] The substrate (SUB) may be capable of transmitting light by including a transparent insulating material. The substrate (SUB) may be a rigid substrate or a flexible substrate.

[0068] The rigid substrate may be, for example, a glass substrate, a quartz substrate, a glass ceramic substrate, and / or a crystalline glass substrate.

[0069] The flexible substrate may be one of a film substrate including a polymer organic material and a plastic substrate. For example, the flexible substrate may include polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and / or cellulose acetate propionate.

[0070] One area of ​​the substrate (SUB) may be provided as a display area (DA) on which sub-pixels (SPX) are arranged, and the remaining area of ​​the substrate (SUB) may be provided as a non-display area (NDA). The non-display area (NDA) may be arranged around the display area (DA) along the edge or perimeter of the display area (DA).

[0071] In one embodiment, the display area (DA) may include a first area (DA1) and a second area (DA2). For example, the display area (DA) may include a second area (DA2) located in the center and first areas (DA1) positioned on both sides of the second area (DA2). The first area (DA1) may be an area positioned in an outer direction rather than in the center direction of the display panel (DP) with respect to the second area (DA2), but is not limited thereto.

[0072] Sub-pixels (SPX) can be arranged in each of the first area (DA1) and the second area (DA2).

[0073] Each of the sub-pixels (SPX) may include a light-emitting element comprising an emission layer. Depending on the embodiment, the light-emitting element may include, but is not limited to, an organic light-emitting diode (OLED) or an inorganic light-emitting diode having a size in the micro to nanoscale (or meter) range.

[0074] The display device (DD) can display an image in the first area (DA1) and the second area (DA2) by driving sub-pixels (SPX) in response to input image data.

[0075] According to an embodiment, the display area (DA) may include a detection area capable of detecting a user's fingerprint, etc. For example, the first area (DA1) and the second area (DA2) may be set as detection areas capable of detecting a user's fingerprint, etc. If the entire display area (DA) is set as a detection area, the non-display area (NDA) surrounding the display area (DA) may become a non-detection area.

[0076] The non-display area (NDA) may include a fan-out area (FTA) and a pad area (PDA).

[0077] The pad area (PDA) may be located closest to the edge of the non-display area (NDA).

[0078] A fan-out area (FTA) may be located adjacent to a display area (DA) in a non-display area (NDA). For example, the fan-out area (FTA) may be a region of the non-display area (NDA) located between a pad area (PDA) and the display area (DA). In some embodiments, the non-display area (NDA) may include an anti-static circuit area in which an anti-static circuit is located to prevent static electricity generation and is electrically connected to signal lines located in the display area (DA).

[0079] A wiring section (see “LP” in Fig. 2) can be located in the fan-out area (FTA), and a pad section (PDP) can be located in the pad area (PDA).

[0080] The display device (DD) may include a circuit board or circuit board (FPCB) connected to a display panel (DP) via a pad portion (PDP). The circuit board (FPCB) may be, but is not limited to, a flexible circuit board.

[0081] A circuit board (FPCB) can process various signals input from a printed circuit board (PCB) and output them to a display panel (DP). To this end, one end of the circuit board (FPCB) can be attached to the display panel (DP), and the other end facing the one end can be attached to the printed circuit board. The circuit board (FPCB) can be connected to each of the display panel (DP) and the printed circuit board by a conductive adhesive material (e.g., an anisotropic conductive film).

[0082] A driving unit (DIC) may be mounted on a circuit board (FPCB). The driving unit (DIC) may be, for example, an integrated circuit (IC). The driving unit (DIC) may include a panel driving unit, etc.

[0083] The panel driver may sequentially scan the sub-pixels (SPX) and supply data signals corresponding to the image data signals to the sub-pixels (SPX). In this case, the display panel (DP) may display an image corresponding to the image data. In some embodiments, the panel driver may supply driving signals for fingerprint detection to the sub-pixels (SPX).

[0084] FIG. 2 is a schematic plan view showing a display device (DD) according to one embodiment, and FIG. 3 is a schematic enlarged view showing a portion EA1 of FIG. 2.

[0085] In FIGS. 2 and 3, differences from the above-described embodiment will be explained in detail to avoid redundant explanation.

[0086] Referring to FIGS. 2 and 3, the display device (DD) (or display panel (DP)) may include a substrate (SUB), a wiring portion (LP), and a pad portion (PDP).

[0087] The pad part (PDP) is located in the pad area (PDA) of the non-display area (NDA) and can be electrically connected to the wiring part (LP).

[0088] The wiring unit (LP) is located in the fan-out area (FTA) of the non-display area (NDA), and is electrically connected to the sub-pixels (see "SPX" in FIG. 1) so that a predetermined signal applied from the driver unit (see "DIC" in FIG. 1) can be transmitted to the signal lines. The wiring unit (LP) may include fan-out lines that electrically connect the driver unit (DIC) and the sub-pixels (SPX) in the fan-out area (FTA).

[0089] In one embodiment, the wiring portion (LP) may be located in a central portion of a fan-out area (FTA) corresponding to a second area (DA2) of the display area (DA). The wiring portion (LP) may include a first wiring portion (LP1) and a second wiring portion (LP2). The first wiring portion (LP1) may be electrically connected to data lines (D5, D6, D7, ... Dk) located in the second area (DA2) of the display area (DA) through a first contact hole (CH1). The second wiring portion (LP2) may be electrically connected to data lines (D1, D2, D3, D4) located in the first area (DA1) of the display area (DA) through a second contact hole (CH2) and bridge lines (BRL) (e.g., BRL1, BRL2, BRL3, and BRL4).

[0090] A substrate (SUB) may include a display area (DA) and a non-display area (NDA). The display area (DA) may be divided into a first area (DA1) and a second area (DA2).

[0091] Signal lines to which various signals are applied may be arranged in the first area (DA1) and the second area (DA2). For example, data lines (D1 to Dk) to which data signals for controlling brightness in each sub-pixel (SPX) are applied may be arranged in the first area (DA1) and the second area (DA2). In addition to the data lines (D1 to Dk), various signal lines such as power lines and scan lines may be arranged in the first area (DA1) and the second area (DA2).

[0092] In the first area (DA1) and the second area (DA2), the sub-pixel (SPX) may be arranged or located in an area (e.g., a pixel area) defined by scan lines and data lines (e.g., D1 to Dk). The data lines (D1 to Dk) may extend along the second direction (DR2) in the display area (DA). In FIGS. 2 and 3 , the first to fourth data lines (D1 to D4) may be located in the first area (DA1, hereinafter referred to as “area 1-1”) adjacent to one side (e.g., the left side) of the second area (DA2). In addition, four data lines may be arranged in the first area (DA1, hereinafter referred to as “area 1-2”) adjacent to the other side (e.g., the right side) of the second area (DA2). For convenience of explanation, four data lines are illustrated as being arranged in the first area (DA1), but the present invention is not limited thereto.

[0093] Each of the fifth to kth data lines (D5 to Dk) located in the second area (DA2) may be electrically connected to the first wiring (LP1). For example, in the second area (DA2), each of the fifth data line (D5), the sixth data line (D6), and the seventh data line (D7) may be electrically connected to the corresponding first wiring (LP1) through the first contact hole (CH1).

[0094] The first to fourth data lines (D1 to D4) located in the first-first area (DA1) may be electrically connected to the bridge line (BRL). In addition, four data lines located in the first-second area (DA1) may also be electrically connected to the bridge line (BRL). The bridge line (BRL) may be arranged to pass through the display area (DA) bypassing a portion of the display area (DA) adjacent to the non-display area (NDA).

[0095] In the first-1 area (DA1), the first data line (D1) may be electrically connected to the first bridge line (BRL1), the second data line (D2) may be electrically connected to the second bridge line (BRL2), the third data line (D3) may be electrically connected to the third bridge line (BRL3), and the fourth data line (D4) may be electrically connected to the fourth bridge line (BRL4).

[0096] Each of the first to fourth bridge lines (BRL1 to BRL4) may extend from the second area (DA2) to the first-first area (DA1). For example, each of the first to fourth bridge lines (BRL1 to BRL4) may be routed from the central portion (or inner side) of the display area (DA) to the edge (or outer side) of the display area (DA). Each of the first to fourth bridge lines (BRL1 to BRL4) may be electrically connected to the first to fourth data lines (D1 to D4) through a via hole (VIH) and may be electrically connected to a corresponding second wiring (LP2) through a second contact hole (CH2).

[0097] In Fig. 3, the second bridge line (BRL2) may have one end electrically connected to the second wiring (LP2) through the second contact hole (CH2), and the other end electrically connected to the second data line (D2) through the via hole (VIH). The third bridge line (BRL3) may have one end electrically connected to the second wiring (LP2) through the second contact hole (CH2), and the other end electrically connected to the third data line (D3) through the via hole (VIH). The fourth bridge line (BRL4) may have one end electrically connected to the second wiring (LP2) through the second contact hole (CH2), and the other end electrically connected to the fourth data line (D4) through the via hole (VIH).

[0098] The second to fourth bridge lines (BRL2 to BRL4) may each have one end electrically connected to the second wiring (LP2) through the second contact hole (CH2) between the second display area (DA2) and the non-display area (NDA), and the other end electrically connected to the second to fourth data lines (D2 to D4) through the via hole (VIH) in the first-first area (DA1). That is, the second to fourth bridge lines (BRL2 to BRL4) may each receive an input signal (e.g., a data signal) from the second wiring (LP2) and transmit the same to the second to fourth data lines (D2 to D4), respectively. The second to fourth bridge lines (BRL2 to BRL4) may be arranged on the same layer as the second wiring (LP2) or may be arranged on a different layer.

[0099] The fifth to seventh data lines (D5 to D7) of FIG. 3 may be arranged in the same layer, or some may be arranged in different layers. For example, the fifth to seventh data lines (D5 to D7) may be arranged alternately in different layers.

[0100] As described above, by not directly connecting the data line to the wiring unit (LP) in a part of the display area (DA) (for example, the first area (DA1)), but by transmitting the input signal of the wiring unit (LP) to the data line through a bridge line (BRL) bypassing a part of the display area (DA), the area of ​​the non-display area (NDA) outside the display area (DA) can be effectively reduced.

[0101] FIG. 4 is a drawing showing an example of a display area of ​​a display panel included in the display device of FIG. 2.

[0102] Referring to FIGS. 2 and 4, sub-pixels can be arranged in a display area (DA) of a display panel (DP).

[0103] The display area (DA) may be divided into pixel rows (R1 to R4). The pixel rows (R1 to R4) may extend in a first direction (DR1) and be arranged along a second direction (DR2). Each of the pixel rows (R1 to R4) may include sub-pixels (SPX1 to SPX4). Each of the sub-pixels (SPX1 to SPX4) may include one of the pixel circuits (PXC11 to PXC44) and a light-emitting element (see "LD" in FIG. 5).

[0104] In one embodiment, each of the first to fourth pixel rows (R1 to R4) may have sub-pixels (SPX1 to SPX4) arranged in the order of a first sub-pixel (SPX1), a second sub-pixel (SPX2), a third sub-pixel (SPX3), and a fourth sub-pixel (SPX4) along the first direction (DR1).

[0105] A first sub-pixel (SPX1) and a second sub-pixel (SPX2) may constitute a first sub-pixel unit (SPU1), and a third sub-pixel (SPX3) and a fourth sub-pixel (SPX4) may constitute a second sub-pixel unit (SPU2). It may be understood that predetermined first and second sub-pixel units (SPU1, SPU2) adjacent to each other constitute one pixel unit (PU).

[0106] In a first pixel row (R1) (or a first horizontal line), pixel circuits (PXC11 to PXC14) corresponding to the sub-pixels (SPX1 to SPX4) of the first pixel row (R1) may be arranged along a first direction (DR1). In a second pixel row (R2) (or a second horizontal line), pixel circuits (PXC21 to PXC24) corresponding to the sub-pixels (SPX1 to SPX4) of the second pixel row (R2) may be arranged along the first direction (DR1). In a third pixel row (R3) (or a third horizontal line), pixel circuits (PXC31 to PXC34) corresponding to the sub-pixels (SPX1 to SPX4) of the third pixel row (R3) may be arranged along the first direction (DR1). In the fourth pixel row (R4) (or fourth horizontal line), pixel circuits (PXC41 to PXC44) corresponding to the sub-pixels (SPX1 to SPX4) of the fourth pixel row (R4) can be arranged along the first direction (DR1).

[0107] The first, second, third, and fourth sub-pixels (SPX1, SPX2, SPX3, SPX4) of each of the first to fourth pixel rows (R1 to R4) may be included in one pixel unit (PU).

[0108] Fig. 5 is a circuit diagram showing an example of a sub-pixel (SPX) included in the display area of ​​Fig. 1. For convenience of explanation, Fig. 5 illustrates a sub-pixel (SPX) located on the i-th horizontal line (or i-th pixel row) and connected to the j-th data line (Dj).

[0109] Referring to FIGS. 1 and 5, the sub-pixel (SPX) can be arranged on the i-th horizontal line.

[0110] A sub-pixel (SPX) may include a light-emitting element (LD) and a pixel circuit (PXC). In one embodiment, the pixel circuit (PXC) may include first, second, third, fourth, fifth, sixth, seventh, and eighth transistors (T1, T2, T3, T4, T5, T6, T7, and T8), a storage capacitor (Cst), and a boost capacitor (Cbst).

[0111] A first transistor (T1) (or driving transistor) may be electrically connected between a first power line (PL1) and a first electrode (or anode electrode) of a light-emitting element (LD). The first transistor (T1) may include a gate electrode electrically connected to a first node (N1). The first transistor (T1) may control an amount of current (or driving current) flowing from the first power line (PL1) to the electrode (EP) (or power line) via the light-emitting element (LD) based on a voltage of the first node (N1). A first power voltage (VDD) is supplied to the first power line (PL1), a second power voltage (VSS) is supplied to the electrode (EP), and the first power voltage (VDD) may be set to a voltage higher than the second power voltage (VSS).

[0112] The second transistor (T2) may be electrically connected between the j-th data line (Dj) and the second node (N2). The gate electrode of the second transistor (T2) may be connected to the 1i-th scan line (S1i) (or the first scan line). The second transistor (T2) may be turned on when the first scan signal (GW[i]) (e.g., the first scan signal at a low level) is supplied to the 1i-th scan line (S1i), thereby electrically connecting the j-th data line (Dj) and the second node (N2). When each of the first transistor (T1) and the third transistor (T3) is turned on, the second transistor (T2) may transmit the data signal of the j-th data line (Dj) to the second node (N2) in response to the first scan line (GW[i]).

[0113] The third transistor (T3) may be electrically connected between the first node (N1) and the third node (N3). The gate electrode of the third transistor (T3) may be electrically connected to the 4i scan line (S4i) (or the fourth scan line). The third transistor (T3) may be turned on when the fourth scan signal (GC[i]) is supplied to the 4i scan line (S4i). When the third transistor (T3) is turned on, the first transistor (T1) is connected between the second node (N2) and the third node (N3), and the gate electrode of the first transistor (T1) is connected to the first node (N1), so the first transistor (T1) may have a diode-connected form.

[0114] The fourth transistor (T4) may be electrically connected between the first node (N1) and the second power line (PL2). The gate electrode of the fourth transistor (T4) may be electrically connected to the secondi scan line (S2i) (or the second scan line). A first initialization power voltage (Vint1) may be provided to the second power line (PL2). The fourth transistor (T4) may be turned on by the second scan signal (GI[i]) supplied to the secondi scan line (S2i). When the fourth transistor (T4) is turned on, the first initialization power voltage (Vint1) may be supplied to the first node (N1) (i.e., the gate electrode of the first transistor (T1)).

[0115] The fifth transistor (T5) may be electrically connected between the first power line (PL1) and the second node (N2). A gate electrode of the fifth transistor (T5) may be electrically connected to the ith light emission control line (Ei). A sixth transistor (T6) may be electrically connected between the third node (N3) and the light emitting element (LD) (or the fourth node (N4)). A gate electrode of the sixth transistor (T6) may be electrically connected to the ith light emission control line (Ei). The fifth transistor (T5) and the sixth transistor (T6) may be turned off when a light emission control signal (EM[i]) (for example, a high-level light emission control signal (EM[i])) is supplied to the ith light emission control line (Ei), and may be turned on when a low-level light emission control signal (EM[i]) is supplied to the light emission control line (Ei).

[0116] The seventh transistor (T7) may be electrically connected between the first electrode (i.e., the fourth node (N4)) of the light emitting element (LD) and the third power line (PL3). The gate electrode of the seventh transistor (T7) may be electrically connected to the 3i scan line (S3i). The third power line (PL3) may be supplied with a second initialization power voltage (Vint2). Depending on the embodiment, the second initialization power voltage (Vint2) may be the same as or different from the first initialization power voltage (Vint1). The seventh transistor (T7) may be turned on by the third scan signal (GB[i]) supplied to the 3i scan line (S3i) to supply the second initialization power voltage (Vit2) to the first electrode (e.g., the fourth node (N4)) of the light emitting element (LD).

[0117] The eighth transistor (T8) may be electrically connected between the second node (N2) and the fourth power line (PL4). The gate electrode of the eighth transistor (T8) may be electrically connected to the third i scan line (S3i). A bias voltage (VOBS) may be supplied to the fourth power line (PL4). The eighth transistor (T8) may be turned on by the third scan signal (GB[i]) supplied to the third i scan line (S3i) to supply the bias voltage (VOBS) to the second node (N2).

[0118] A storage capacitor (Cst) may be connected or formed between the first power line (PL1) and the first node (N1).

[0119] A boost capacitor (Cbst) (or capacitor) may be connected or formed between the gate electrode of the second transistor (T2) and the gate electrode of the first transistor (T1) (e.g., the first node (N1)).

[0120] The light emitting element (LD) may include a first electrode (or anode electrode) and a second electrode (or cathode electrode). The first electrode may be connected to a fourth node (N4) and the second electrode may be connected to an electrode (EP). The second electrode of the light emitting element (LD) may be supplied with a second power voltage (VSS). The light emitting element (LD) may receive a driving current from the first transistor (T1) and emit light.

[0121] In an embodiment, the pixel circuit (PXC) may include a P-type transistor and an N-type transistor. The third transistor (T3) and the fourth transistor (T4) may be formed as oxide semiconductor transistors including an oxide semiconductor (or a second type semiconductor). For example, the third transistor (T3) and the fourth transistor (T4) may be N-type oxide semiconductor transistors and may include an oxide semiconductor layer as an active layer, but are not limited thereto.

[0122] The remaining transistors (e.g., the first, second, fifth, sixth, seventh, and eighth transistors (T1, T2, T5, T6, T7, and T8)) are formed as polysilicon transistors including silicon semiconductors (or first type semiconductors) and may include a polysilicon semiconductor layer as an active layer. For example, the active layer may be formed through a low-temperature polysilicon process (e.g., a low-temperature poly-silicon (LTPS) process).

[0123] Below, the stacked structure (or cross-sectional structure) of a sub-pixel (SPX) including a light-emitting element (LD) will be described with reference to FIG. 6.

[0124] FIG. 6 is a schematic cross-sectional view showing one area of ​​a display device (DD) according to one embodiment.

[0125] In FIG. 6, a cross-section of a portion corresponding to the third transistor (T3) among the first to eighth transistors (T1 to T8) illustrated in FIG. 5 and a cross-section of a portion corresponding to the sixth transistor (T6) are illustrated.

[0126] Referring to FIG. 6, the display device (DD) may include a sub-pixel (SPX) provided in one area of ​​the substrate (SUB).

[0127] A pixel circuit layer (PCL) of a sub-pixel (SPX) may be arranged on a substrate (SUB). At least one insulating layer may be arranged on the pixel circuit layer (PCL). The insulating layer may include a first insulating layer (INS1), a second insulating layer (INS2), a third insulating layer (INS3), a fourth insulating layer (INS4), a fifth insulating layer (INS5), a sixth insulating layer (INS6), a seventh insulating layer (INS7), an eighth insulating layer (INS8), and a ninth insulating layer (INS9) sequentially laminated on the substrate (SUB) along a third direction (DR3).

[0128] A first insulating layer (INS1) (or buffer layer) may be disposed on a substrate (SUB). The first insulating layer (INS1) may prevent diffusion of impurities into the third transistor (T3) and the sixth transistor (T6). The first insulating layer (INS1) may be an inorganic film including an inorganic material (or substance). The first insulating layer (INS1) may include silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and / or aluminum oxide (AlOx). The first insulating layer (INS1) may be provided as a single layer, but may also be provided as a multilayer of at least two layers or more. The first insulating layer (INS1) may be omitted depending on the material of the substrate (SUB), process conditions, etc.

[0129] The second insulating layer (INS2) (or first gate insulating layer) may be disposed on the first insulating layer (INS1). The second insulating layer (INS2) may include the same material as the first insulating layer (INS1) or may include a suitable (or selected) material from among the materials exemplified as constituent materials of the first insulating layer (INS1). For example, the second insulating layer (INS2) may be an inorganic film including an inorganic material.

[0130] The third insulating layer (INS3) (or second gate insulating layer) may be disposed on the second insulating layer (INS2). The third insulating layer (INS3) may include the same material as the first insulating layer (INS1) or may include one or more materials suitable (or selected) from among the materials exemplified as constituent materials of the first insulating layer (INS1).

[0131] The fourth insulating layer (INS4) (or the first interlayer insulating layer) may be disposed on the third insulating layer (INS3). The fourth insulating layer (INS4) may be an inorganic film including an inorganic material or an organic film including an organic material.

[0132] The fifth insulating layer (INS5) (or third gate insulating layer) may be disposed on the fourth insulating layer (INS4). The fifth insulating layer (INS5) may be an inorganic film including an inorganic material or an organic film including an organic material.

[0133] The sixth insulating layer (INS6) (or second interlayer insulating layer) may be disposed on the fifth insulating layer (INS5). The sixth insulating layer (INS6) may be an inorganic film including an inorganic material or an organic film including an organic material.

[0134] The seventh insulating layer (INS7) (or the first via layer) may be disposed on the sixth insulating layer (INS6). The seventh insulating layer (INS7) may be an inorganic film including an inorganic material or an organic film including an organic material. The inorganic film may include, for example, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), and / or aluminum oxide (AlOx). The organic film may include, for example, at least one of a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfides resin, and / or a benzocyclobutene resin. In one embodiment, the seventh insulating layer (INS7) may be an organic film.

[0135] The eighth insulating layer (INS8) (or the second via layer) may be disposed on the seventh insulating layer (INS7). The eighth insulating layer (INS8) may include the same material as the seventh insulating layer (INS7) or may include one or more materials suitable (or selected) from among the materials exemplified as constituent materials of the seventh insulating layer (INS7). For example, the eighth insulating layer (INS8) may be an organic film including an organic material.

[0136] The ninth insulating layer (INS9) (or third via layer) may be disposed on the eighth insulating layer (INS8). The ninth insulating layer (INS9) may include the same material as the seventh insulating layer (INS7) or may include one or more materials suitable (or selected) from among the materials exemplified as constituent materials of the seventh insulating layer (INS7). For example, the ninth insulating layer (INS9) may be an organic film including an organic material.

[0137] The pixel circuit layer (PCL) may include at least one conductive layer disposed between the above-described insulating layers. For example, the conductive layers may include a first conductive layer (CL1) disposed between a second insulating layer (INS2) and a third insulating layer (INS3), a second conductive layer (CL2) disposed between a third insulating layer (INS3) and a fourth insulating layer (INS4), a third conductive layer (CL3) disposed between a fifth insulating layer (INS5) and a sixth insulating layer (INS6), a fourth conductive layer (CL4) disposed between a sixth insulating layer (INS6) and a seventh insulating layer (INS7), a fifth conductive layer (CL5) disposed between a seventh insulating layer (INS7) and an eighth insulating layer (INS8), and a sixth conductive layer (CL6) disposed between an eighth insulating layer (INS8) and a ninth insulating layer (INS9). The insulating layers and conductive layers are not limited to the above-described embodiments, and depending on the embodiment, other insulating layers and other conductive layers may be disposed within the pixel circuit layer (PCL) in addition to the insulating layers and the conductive layers.

[0138] In one embodiment, a first semiconductor layer may be disposed between a first insulating layer (INS1) and a second insulating layer (INS2). The first semiconductor layer may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. The first semiconductor layer may include, but is not limited to, low-temperature polysilicon. The first semiconductor layer may include a first semiconductor region having high conductivity and a second semiconductor region having low conductivity. The first semiconductor region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second semiconductor region may be an undoped region or a region doped at a lower concentration than the first semiconductor region. The conductivity of the first semiconductor region may be greater than the conductivity of the second semiconductor region. The first semiconductor region may substantially function as an electrode or a signal wiring. The second semiconductor region may substantially correspond to an active pattern (or channel region) of the transistor. A portion of the first semiconductor layer may be an active pattern region of the transistor, another portion of the first semiconductor layer may be a source / drain region (or a source / drain electrode) of the transistor, and another portion of the first semiconductor layer may be a connection electrode or a connection signal wiring, but is not limited thereto.

[0139] In one embodiment, a second semiconductor layer may be disposed between the fourth insulating layer (INS4) and the fifth insulating layer (INS5). The second semiconductor layer may include an oxide semiconductor. The oxide semiconductor may include a plurality of regions that are distinguished depending on whether a metal oxide is reduced. A region in which the metal oxide is reduced (hereinafter referred to as a “reduced region”) may have greater conductivity than a region in which the metal oxide is not reduced (hereinafter referred to as a “non-reduced region”). The reduced region may be substantially utilized as a source / drain region or a signal wiring of the transistor. The non-reduced region may substantially correspond to an active pattern (or channel region) of the transistor. A portion of the second semiconductor layer may be an active pattern of the transistor, another portion may be a source / drain region (or a source / drain electrode) of the transistor, and another portion may be a signal transmission region, but is not limited thereto.

[0140] A third transistor (T3) and a sixth transistor (T6) may be arranged in the pixel circuit layer (PCL).

[0141] The sixth transistor (T6) may include a gate electrode (GE6, hereinafter referred to as “sixth gate electrode”), a first semiconductor pattern (SCP1), a first terminal (TE1), and a second terminal (TE2). The third transistor (T3) may include a gate electrode (GE3, hereinafter referred to as “third gate electrode”), a second semiconductor pattern (SCP2), a third terminal (TE3), and a fourth terminal (TE4).

[0142] A first semiconductor pattern (SCP1) may be disposed on a first insulating layer (INS1). The first semiconductor pattern (SCP1) may be composed of a first semiconductor layer. The first semiconductor pattern (SCP1) may include a channel region, a first contact region connected to one end of the channel region, and a second contact region connected to the other end of the channel region. A second insulating layer (INS2) may be disposed on the first semiconductor pattern (SCP1).

[0143] The sixth gate electrode (GE6) may be a first conductive layer (CL1) disposed on the second insulating layer (INS2). The first conductive layer (CL1) may be formed as a single layer or multiple layers made of molybdenum, copper, chromium, gold, silver, titanium, nickel, neodymium, indium, tin, and oxides or alloys thereof. For example, the first conductive layer (CL1) may be formed as a multiple layer in which titanium, copper, and / or indium main oxides are sequentially or repeatedly stacked, but is not limited thereto. The sixth gate electrode (GE6) may overlap a region of the first semiconductor pattern (SCP1) in the thickness direction of the substrate (SUB) (for example, the third direction (DR3)). A region of the first semiconductor pattern (SCP1) overlapping the sixth gate electrode (GE6) may be a channel region of the sixth transistor (T6). A third insulating layer (INS3) may be placed on the sixth gate electrode (GE6).

[0144] The first terminal (TE1) and the second terminal (TE2) may be disposed on the sixth insulating layer (INS6). The first terminal (TE1) and the second terminal (TE2) may be formed of a fourth conductive layer (CL4). The fourth conductive layer (CL4) may be formed as a single layer or multiple layers made of molybdenum, copper, aluminum, chromium, gold, silver, titanium, nickel, neodymium, indium, tin, and / or oxides and / or alloys thereof.

[0145] The first terminal (TE1) can be electrically connected to a second contact area of ​​the first semiconductor pattern (SCP1) through a first contact portion (CNT1) penetrating the second insulating layer (INS2), the third insulating layer (INS3), the fourth insulating layer (INS4), the fifth insulating layer (INS5), and the sixth insulating layer (INS6). The first terminal (TE1) can be electrically connected to an anode electrode (AE) of the light emitting element (LD). The second terminal (TE2) can be electrically connected to the first contact area of ​​the first semiconductor pattern (SCP1) through another first contact portion (CNT1) penetrating the second insulating layer (INS2), the third insulating layer (INS3), the fourth insulating layer (INS4), the fifth insulating layer (INS5), and the sixth insulating layer (INS6). The first terminal (TE1) and the second terminal (TE2) can be spaced apart from each other on the sixth insulating layer (INS6). A seventh insulating layer (INS7) may be placed on the first terminal (TE1) and the second terminal (TE2).

[0146] A second semiconductor pattern (SCP2) may be disposed on a fourth insulating layer (INS4). The second semiconductor pattern (SCP2) may be composed of a second semiconductor layer. The second semiconductor pattern (SCP2) may include a channel region, a first contact region connected to one end of the channel region, and a second contact region connected to the other end of the channel region. A fifth insulating layer (INS5) may be disposed on the second semiconductor pattern (SCP2).

[0147] The third gate electrode (GE3) may be disposed on the fifth insulating layer (INS5). The third gate electrode (GE3) may be composed of a third conductive layer (CL3). The third conductive layer (CL3) may include the same material as the first conductive layer (CL1) and / or the fourth conductive layer (CL4), or may include a suitable (or selected) material from among the materials exemplified as constituent materials of the first conductive layer (CL1) and / or the fourth conductive layer (CL4). The third gate electrode (GE3) may overlap a region of the second semiconductor pattern (SCP2). A region of the second semiconductor pattern (SCP2) overlapping the third gate electrode (GE3) may be a channel region of the third transistor (T3).

[0148] A sixth insulating layer (INS6) may be placed on the third gate electrode (GE3).

[0149] The third terminal (TE3) and the fourth terminal (TE4) may be arranged on the sixth insulating layer (INS6). The third terminal (TE3) and the fourth terminal (TE4) may be formed of the fourth conductive layer (CL4).

[0150] The third terminal (TE3) may be electrically connected to a first contact area of ​​the second semiconductor pattern (SCP2) through a second contact portion (CNT2) penetrating the fifth insulating layer (INS5) and the sixth insulating layer (INS6). The fourth terminal (TE4) may be electrically connected to a second contact area of ​​the second semiconductor pattern (SCP2) through another second contact portion (CNT2) penetrating the fifth insulating layer (INS5) and the sixth insulating layer (INS6). The third terminal (TE3) and the fourth terminal (TE4) may be spaced apart from each other on the sixth insulating layer (INS6). A seventh insulating layer (INS7) may be disposed on the third terminal (TE3) and the fourth terminal (TE4).

[0151] A storage capacitor (Cst) may be arranged in the pixel circuit layer (PCL). The storage capacitor (Cst) may include a lower electrode (LE) and an upper electrode (UE).

[0152] The lower electrode (LE) may be disposed on the second insulating layer (INS2). The lower electrode (LE) may be composed of a first conductive layer (CL1) and may be provided on the same layer as the sixth gate electrode (GE6), but is not limited thereto. A third insulating layer (INS3) may be disposed on the lower electrode (LE).

[0153] The upper electrode (UE) may be disposed on the third insulating layer (INS3). The upper electrode (UE) may be composed of, but is not limited to, a second conductive layer (CL2). The second conductive layer (CL2) may include the same material as the first conductive layer (CL1) and / or the fourth conductive layer (CL4), or may include one or more materials suitable (or selected) from among the materials exemplified as constituent materials of the first conductive layer (CL1) and / or the fourth conductive layer (CL4). The upper electrode (UE) may overlap the lower electrode (LE) in the third direction (DR3) with the third insulating layer (INS3) interposed therebetween to form a capacitance.

[0154] A connection pattern (CNP) and a bridge pattern (BRP) can be arranged on the pixel circuit layer (PCL).

[0155] A connection pattern (CNP) may be disposed on a seventh insulating layer (INS7). The connection pattern (CNP) may be composed of a fifth conductive layer (CL5). The fifth conductive layer (CL5) may include the same material as the first conductive layer (CL1) and / or the fourth conductive layer (CL4), or may include one or more materials suitable (or selected) from among the materials exemplified as constituent materials of the first conductive layer (CL1) and / or the fourth conductive layer (CL4). The connection pattern (CNP) may be electrically connected to a first terminal (TE1) of a sixth transistor (T6) through a first via hole (VIH1) penetrating the seventh insulating layer (INS7). An eighth insulating layer (INS8) may be disposed on the connection pattern (CNP).

[0156] The bridge pattern (BRP) may be disposed on the eighth insulating layer (INS8). The bridge pattern (BRP) may be composed of a sixth conductive layer (CL6). The sixth conductive layer (CL6) may include the same material as the first conductive layer (CL1) and / or the fourth conductive layer (CL4), or may include one or more materials suitable (or selected) from among the materials exemplified as constituent materials of the first conductive layer (CL1) and / or the fourth conductive layer (CL4). The bridge pattern (BRP) may be electrically connected to the connection pattern (CNP) through a second via hole (VIH2) penetrating the eighth insulating layer (INS8). A ninth insulating layer (INS9) may be disposed on the bridge pattern (BRP).

[0157] A display element layer (DPL) can be placed on the pixel circuit layer (PCL).

[0158] A light emitting element (LD) and a bank (BNK) may be arranged on a display element layer (DPL). The light emitting element (LD) may include an anode electrode (AE) (or pixel electrode), a light emitting layer (EML), and a cathode electrode (CE) (or common electrode). The light emitting element (LD) may be electrically connected to a sixth transistor (T6) through a bridge pattern (BRP) and a connection pattern (CNP). The light emitting layer (EML) may include a hole transport layer, an organic material layer (or a light generating layer), and an electron transport layer.

[0159] The anode electrode (AE) may be disposed on the ninth insulating layer (INS9). The anode electrode (AE) may be formed of a metal layer such as silver, magnesium, aluminum, platinum, palladium, gold, nickel, neodymium, iridium, chromium, and / or an alloy thereof, and / or indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc., but is not limited thereto. The anode electrode (AE) may be electrically connected to the bridge pattern (BRP) through a third via hole (VIH3) penetrating the ninth insulating layer (INS9).

[0160] The bank (BNK) may be arranged on the ninth insulating layer (INS9) in the non-emission area (NEA) of the sub-pixel (SPX). The bank (BNK) may be a pixel definition film that defines (or partitions) the emission area (EMA) of the sub-pixel (SPX). The bank (BNK) may be an organic film including an organic material (or substance). The organic material may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0161] In some embodiments, the bank (BNK) may include (or be included in) a light absorbing material, and may have a light absorbing agent applied thereto to absorb light introduced from the outside. For example, the bank (BNK) may include, but is not limited to, a carbon-based black pigment. The bank (BNK) may also include an opaque metal material having high light absorption, such as chromium, molybdenum, an alloy of molybdenum and titanium, tungsten, vanadium, niobium, tantalum, manganese, cobalt, and / or nickel. The bank (BNK) may include an opening exposing a region of the anode electrode (AE). The opening of the bank (BNK) may correspond to an emission region (EMA) of the sub-pixel (SPX).

[0162] An emission layer (EML) may be disposed on the anode electrode (AE). The emission layer (EML) may include an organic emission layer. Depending on the organic material included in the emission layer (EML), the emission layer (EML) may emit light of a color such as red light, green light, or blue light, but is not limited thereto.

[0163] A cathode electrode (CE) may be disposed on the light-emitting layer (EML). The cathode electrode (CE) may be a common electrode integrally formed in the display area (DA). A second power supply voltage (VSS) may be supplied to the cathode electrode (CE).

[0164] The cathode electrode (CE) may be formed of a metal layer such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, etc. and / or a transparent conductive layer such as ITO, IZO, ZnO, ITZO, etc. In an embodiment, the cathode electrode (CE) may be formed of multiple layers, such as a double layer or more, and for example, the cathode electrode (CE) may be formed of a triple layer of ITO / Ag / ITO.

[0165] A thin film encapsulation layer (TFE) can be formed on the cathode electrode (CE).

[0166] The thin film encapsulation layer (TFE) may be formed as a single layer, but may also be formed as a multilayer. The thin film encapsulation layer (TFE) may include a plurality of insulating layers covering the light emitting element (LD). Specifically, the thin film encapsulation layer (TFE) may include at least one inorganic film and / or at least one organic film. For example, the thin film encapsulation layer (TFE) may have a structure in which inorganic films and organic films are alternately laminated.

[0167] A color filter layer (CFL) may be disposed on a thin film encapsulation layer (TFE). The color filter layer (CFL) may include a light-shielding pattern and a color filter. The light-shielding pattern may be disposed in a non-emission area (NEA) surrounding an emission area (EMA) of a sub-pixel (SPX), and the color filter may be disposed in the emission area (EMA). The above-described color filter layer (CFL) may also be utilized as an anti-reflection layer that blocks external light reflection. A window (WD) may be disposed on the color filter layer (CFL).

[0168] The window (WD) can protect the exposed surface of the display device (DD). The window (WD) can protect the display device (DD) from external impact and provide an input surface and / or a display surface to the user. The window (WD) (or cover glass) can have a multilayer structure selected from a glass substrate, a plastic film, and / or a plastic substrate. This multilayer structure can be formed through a continuous process or an adhesive process using an adhesive layer. The window (WD) can be flexible in whole or in part.

[0169] FIG. 7 is a schematic plan view showing sub-pixels located in one area of ​​a display area (DA) of a display device according to one embodiment, FIG. 8 is a schematic plan view showing only the components included in the first, second, fifth, sixth, seventh, and eighth transistors (T1, T2, T5, T6, T7, and T8) and the first conductive layer (CL1) in FIG. 7, FIG. 9 is a schematic plan view showing only the components included in the second conductive layer (CL2) in FIG. 7, FIG. 10 is a schematic plan view showing only the components included in the third and fourth transistors (T3, T4) and the third conductive layer (CL3) in FIG. 7, FIG. 11 is a schematic plan view showing only the components included in the fourth conductive layer (CL4) in FIG. 7, FIG. 12 is a schematic plan view showing only the components included in the fifth conductive layer (CL5) in FIG. 7, and FIG. 13 is a schematic plan view showing only the components included in the 7 is a schematic plan view showing only the components included in the sixth conductive layer (CL6), FIG. 14 is a schematic plan view showing only the components included in the fourth conductive layer (CL4), the fifth conductive layer (CL5), and the sixth conductive layer (CL6) in FIG. 7, FIG. 15 is a schematic enlarged view showing part EA2 of FIG. 14, and FIG. 16 is a schematic cross-sectional view along lines Ⅰ to Ⅰ' of FIG. 15.

[0170] For convenience of explanation, in FIGS. 7 to 16, the 11th sub-pixel (SPX11), the 12th sub-pixel (SPX12), the 13th sub-pixel (SPX13), and the 14th sub-pixel (SPX14) arranged in the same pixel row (for example, the 1st pixel row) are illustrated.

[0171] Referring to FIGS. 1 to 16, in a display area (see “DA” in FIG. 2), an eleventh sub-pixel (SPX11) (or a first sub-pixel), a twelfth sub-pixel (SPX12) (or a second sub-pixel), a thirteenth sub-pixel (SPX13) (or a third sub-pixel), and a fourteenth sub-pixel (SPX14) (or a fourth sub-pixel) may be arranged along a first direction (DR1). In one embodiment, the eleventh sub-pixel (SPX11) and the fourteenth sub-pixel (SPX14) may be red sub-pixels that emit red light, the twelfth sub-pixel (SPX12) may be a green sub-pixel that emits green light, and the thirteenth sub-pixel (SPX13) may be a blue sub-pixel that emits blue light, but is not limited thereto.

[0172] In one embodiment, the eleventh sub-pixel (SPX11) and the twelfth sub-pixel (SPX12) may constitute a first sub-pixel unit (SPU1), and the thirteenth sub-pixel (SPX13) and the fourteenth sub-pixel (SPX14) may constitute a second sub-pixel unit (SPU2).

[0173] Each of the eleventh to fourteenth sub-pixels (SPX11 to SPX14) may include a pixel circuit (PXC). For example, the eleventh sub-pixel (SPX11) may include an eleventh pixel circuit (PXC11), the twelfth sub-pixel (SPX12) may include a twelfth pixel circuit (PXC12), the thirteenth sub-pixel (SPX13) may include a thirteenth pixel circuit (PXC13), and the fourteenth sub-pixel (SPX14) may include a fourteenth pixel circuit (PXC14).

[0174] The 11th to 14th sub-pixels (SPX11 to SPX14) may include a substrate (SUB), a pixel circuit layer (PCL), a display element layer (DPL), a thin film encapsulation layer (TFE), a color filter layer (CFL), and a window (WD).

[0175] The substrate (SUB) may be capable of transmitting light by including a transparent insulating material. The substrate (SUB) may be a rigid substrate or a flexible substrate.

[0176] The eleventh to fourteenth pixel circuits (PXC11 to PXC14) and signal wires can be arranged in the pixel circuit layer (PCL).

[0177] A light emitting element (see “LD” in FIG. 6) electrically connected to each of the 11th to 14th pixel circuits (PXC11 to PXC14) may be arranged in the display element layer (DPL).

[0178] The pixel circuit layer (PCL) may include a first insulating layer (INS1), a second insulating layer (INS2), a third insulating layer (INS3), a fourth insulating layer (INS4), a fifth insulating layer (INS5), a sixth insulating layer (INS6), a seventh insulating layer (INS7), an eighth insulating layer (INS8), and a ninth insulating layer (INS9) sequentially laminated along a third direction (DR3) from one surface of the substrate (SUB).

[0179] In addition, the pixel circuit layer (PCL) may have at least one conductive layer and at least one semiconductor layer arranged thereon. For example, the pixel circuit layer (PCL) may include a first semiconductor layer, a first conductive layer (CL1), a second conductive layer (CL2), a second semiconductor layer, a third conductive layer (CL3), a fourth conductive layer (CL4), a fifth conductive layer (CL5), and a sixth conductive layer (CL6) sequentially stacked along a third direction (DR3) from one surface of the substrate (SUB).

[0180] Signal lines may be arranged in the display area (DA) where the 11th to 14th sub-pixels (SPX11 to SPX14) are located. For example, the first to sixteenth lines (WL1 to WL16), the first to fourth data lines (D1 to D4), the first power line (PL1), and the first to fourth vertical bridge lines (BRL1_V to BRL4_V) may be arranged in the display area (DA).

[0181] The first wiring (WL1) may extend in the first direction (DR1) and may be composed of a first conductive layer (CL1). The first wiring (WL1) may be the 1i scan line (S1i) described with reference to FIG. 5. One area of ​​the first wiring (WL1) may be a gate electrode (hereinafter referred to as “second gate electrode”) of the second transistor (T2) of each of the 11th to 14th pixel circuits (PXC11 to PXC14).

[0182] The second wiring (WL2) may extend in the first direction (DR1) and be arranged to be spaced apart from the first wiring (WL1). The second wiring (WL2) may be composed of a first conductive layer (CL1). The second wiring (WL2) may be the ith light emission control line (Ei) described with reference to FIG. 5. One region of the second wiring (WL2) may be a gate electrode (hereinafter, referred to as a “fifth gate electrode”) of the fifth transistor (T5) of each of the eleventh to fourteenth pixel circuits (PXC11 to PXC14). In addition, another region of the second wiring (WL2) may be a gate electrode (hereinafter, referred to as a “sixth gate electrode”) of the sixth transistor (T6) of each of the eleventh to fourteenth pixel circuits (PXC11 to PXC14).

[0183] The third wiring (WL3) may extend in the first direction (DR1) and be arranged to be spaced apart from the first and second wirings (WL1, WL2). The third wiring (WL3) may be formed of a first conductive layer (CL1). In one embodiment, the third wiring (WL3) may be the 3i scan line (S3i) described with reference to FIG. 5. One region of the third wiring (WL3) may be a gate electrode (hereinafter, referred to as a “seventh gate electrode”) of the seventh transistor (T7) of each of the eleventh to fourteenth pixel circuits (PXC11 to PXC14). Another region of the third wiring (WL3) may be a gate electrode (hereinafter, referred to as a “eighth gate electrode”) of the eighth transistor (T8) of each of the eleventh to fourteenth pixel circuits (PXC11 to PXC14).

[0184] The fourth wiring (WL4) extends in the first direction (DR1) and may be composed of a second conductive layer (CL2). The fourth wiring (WL4) may be a dummy line overlapping the ninth wiring (WL9) composed of the third conductive layer (CL3), but is not limited thereto.

[0185] The fifth wiring (WL5) may extend in the first direction (DR1) and may be formed of a second conductive layer (CL2). The fifth wiring (WL5) may be arranged to be spaced apart from the fourth wiring (WL4). The fifth wiring (WL5) may be a dummy line overlapping the tenth wiring (WL10) formed of the third conductive layer (CL3), but is not limited thereto.

[0186] The sixth wiring (WL6) may extend in the first direction (DR1) and may be formed of a second conductive layer (CL2). The sixth wiring (WL6) may be arranged to be spaced apart from the fourth and fifth wirings (WL4, WL5). The sixth wiring (WL6) may be a dummy line overlapping the eleventh wiring (WL11) formed of the third conductive layer (CL3), but is not limited thereto.

[0187] The seventh wiring (WL7) may extend in the first direction (DR1) and may be formed of a third conductive layer (CL3). The seventh wiring (WL7) may be the third power line (PL3) described with reference to FIG. 5 in each of the eleventh and fourteenth sub-pixels (SPX11, SPX14). The seventh wiring (WL7) may be supplied with a second initialization power voltage (refer to “Vint2” in FIG. 5). The seventh wiring (WL7) may be electrically connected to the first semiconductor pattern (SCP1) of the seventh transistor (T7) of each of the eleventh and fourteenth pixel circuits (PXC11 and PXC14).

[0188] The eighth wiring (WL8) may extend in the first direction (DR1) and may be formed of a third conductive layer (CL3). In one embodiment, the eighth wiring (WL8) may be the third power line (PL3) described with reference to FIG. 5 in each of the 12th and 13th sub-pixels (SPX12, SPX13). The eighth wiring (WL8) may be supplied with the second initialization power voltage (Vint2). The eighth wiring (WL8) may be electrically connected to the first semiconductor pattern (SCP1) of the seventh transistor (T7) of each of the 12th and 13th pixel circuits (PXC12 and PXC13).

[0189] The ninth wiring (WL9) may extend in the first direction (DR1) and may be composed of a third conductive layer (CL3). The ninth wiring (WL9) may be the 4i scan line (S4i) described with reference to FIG. 5. One area of ​​the ninth wiring (WL9) may be a gate electrode (hereinafter referred to as “third gate electrode”) of the third transistor (T3) of each of the eleventh to fourteenth pixel circuits (PXC11 to PXC14).

[0190] The tenth wiring (WL10) may extend in the first direction (DR1) and may be formed of a third conductive layer (CL3). The tenth wiring (WL10) may be the secondi scan line (S2i) described with reference to FIG. 5. One area of ​​the tenth wiring (WL10) may be a gate electrode (hereinafter referred to as “fourth gate electrode”) of the fourth transistor (T4) of each of the eleventh to fourteenth pixel circuits (PXC11 to PXC14).

[0191] The eleventh wiring (WL11) extends in the first direction (DR1) and may be composed of a third conductive layer (CL3). The eleventh wiring (WL11) may be a dummy line overlapping with the fourteenth wiring (WL14) composed of the fourth conductive layer (CL4), but is not limited thereto.

[0192] The twelfth wiring (WL12) may extend in the first direction (DR1) and may be formed of a fourth conductive layer (CL4). The twelfth wiring (WL12) may be the fourth power line (PL4) described with reference to FIG. 5. The twelfth wiring (WL12) may be supplied with a bias voltage (refer to “VOBS” in FIG. 5). The twelfth wiring (WL12) may be electrically connected to the first semiconductor pattern (SCP1) of the eighth transistor (T8) of each of the eleventh to fourteenth pixel circuits (PXC11 to PXC14).

[0193] The 13th wiring (WL13) may extend in the first direction (DR1) and be arranged to be spaced apart from the 12th wiring (WL12). The 13th wiring (WL13) may be formed of a fourth conductive layer (CL4). The 13th wiring (WL13) may be a first horizontal bridge line (BRL1_H). The 13th wiring (WL13) may be electrically connected to a corresponding data line among the data lines located in the first area (see "DA1" of FIG. 2) of the display area (DA).

[0194] The fourteenth wiring (WL14) may extend in the first direction (DR1) and may be arranged to be spaced apart from the twelfth and thirteenth wirings (WL12, WL13). The fourteenth wiring (WL14) may be formed of a fourth conductive layer (CL4). The fourteenth wiring (WL14) may be the second power line (PL2) described with reference to FIG. 5. The fourteenth wiring (WL14) may be supplied with a first initialization power voltage (refer to “Vint1” in FIG. 5). The fourteenth wiring (WL14) may be electrically connected to a second semiconductor pattern (SCP2) of a fourth transistor (T4) of each of the eleventh to fourteenth pixel circuits (PXC11 to PXC14).

[0195] The fifteenth wiring (WL15) extends in the first direction (DR1) and may be arranged to be spaced apart from the twelfth to fourteenth wirings (WL12 to WL14). The fifteenth wiring (WL15) may be composed of a fourth conductive layer (CL4).

[0196] The sixteenth wiring (WL16) may extend in the second direction (DR2) and may be formed of a sixth conductive layer (CL6). The sixteenth wiring (WL16) may be arranged between two adjacent sub-pixels. For example, the sixteenth wiring (WL16) may be arranged between the eleventh sub-pixel (SPX11) and the twelfth sub-pixel (SPX12) and between the thirteenth sub-pixel (SPX13) and the fourteenth sub-pixel (SPX14), respectively. The sixteenth wiring (WL16) may be electrically connected to the fifth connection pattern (CNP5) of each of the eleventh to fourteenth sub-pixels (SPX11 to SPX14) through a second via hole (VIH2) penetrating the eighth insulating layer (INS8).

[0197] The fifth connection pattern (CNP5) may be formed of a fifth conductive layer (CL5). In the eleventh to fourteenth sub-pixels (SPX11 to SPX14), the fifth connection pattern (CNP5) may be electrically connected to the sixteenth wiring (WL16) through a corresponding second via hole (VIH2). In addition, the fifth connection pattern (CNP5) may be electrically connected to the fourteenth wiring (WL14) through a first via hole (VIH1) penetrating the seventh insulating layer (INS7).

[0198] In each of the 11th to 14th sub-pixels (SPX11 to SPX14), a first initialization power voltage (Vint1) may be applied to a 14th wiring (WL14) and a 16th wiring (WL16) that are electrically connected through a 5th connection pattern (CNP5). In one embodiment, the 14th wiring (WL14) may be a horizontal power line of the second power line (PL2), and the 16th wiring (WL16) may be a vertical power line of the second power line (PL2). Due to the 14th wiring (WL14) and the 16th wiring (WL16) being electrically connected to each other, the second power line (PL2) may have a mesh structure.

[0199] The first data line (D1) may extend in the second direction (DR2) and may be formed of a sixth conductive layer (CL6). The first data line (D1) may be arranged in the same layer as the sixteenth wiring (WL16) and may be arranged spaced apart from the sixteenth wiring (WL16). The first data line (D1) may be the j-th data line (Dj) described with reference to FIG. 5. The first data line (D1) may be electrically connected to the first semiconductor pattern (SCP1) of the second transistor (T2) of the eleventh pixel circuit (PXC11).

[0200] The second data line (D2) may extend in the second direction (DR2) and may be formed of a sixth conductive layer (CL6). The second data line (D2) may be arranged on the same layer as the first data line (D1) and may be arranged spaced apart from the first data line (D1). The second data line (D2) may be the j-th data line (Dj) described with reference to FIG. 5. The second data line (D2) may be electrically connected to the first semiconductor pattern (SCP1) of the second transistor (T2) of the twelfth pixel circuit (PXC12).

[0201] The third data line (D3) may extend in the second direction (DR2) and may be formed of a sixth conductive layer (CL6). The third data line (D3) may be arranged on the same layer as the first and second data lines (D1, D2), and may be arranged spaced apart from the first and second data lines (D1, D2). The third data line (D3) may be electrically connected to the first semiconductor pattern (SCP1) of the second transistor (T2) of the thirteenth pixel circuit (PXC13).

[0202] The fourth data line (D4) extends in the second direction (DR2) and may be formed of a sixth conductive layer (CL6). The fourth data line (D4) may be arranged in the same layer as the first to third data lines (D1 to D3) and may be arranged spaced apart from the first to third data lines (D1 to D3). The fourth data line (D4) may be electrically connected to the first semiconductor pattern (SCP1) of the second transistor (T2) of the fourteenth pixel circuit (PXC14).

[0203] The first vertical bridge line (BRL1_V) may extend in the second direction (DR2) and may be formed of a sixth conductive layer (CL6). The first vertical bridge line (BRL1_V) may be arranged on the same layer as the first to fourth data lines (D1 to D4) and may be arranged to be spaced apart from the first to fourth data lines (D1 to D4). The first vertical bridge line (BRL1_V) may overlap with a part of the configuration of the eleventh pixel circuit (PXC11). The first vertical bridge line (BRL1_V) may be located on one side (for example, the left side) of the first data line (D1) in the eleventh sub-pixel (SPX11) when viewed in a plan view. The first vertical bridge line (BRL1_V) may be located outside the first data line (D1) within the 11th sub-pixel (SPX11) when viewed from the boundary between two adjacent sub-pixels in the first direction (DR1), for example, the 11th sub-pixel (SPX11) and the 12th sub-pixel (SPX12).

[0204] The first vertical bridge line (BRL1_V) may be electrically connected to a corresponding one of the data lines located in the first area (DA1). The first vertical bridge line (BRL1_V) may be electrically connected to a fan-out line located in a fan-out area (see "FTA" in FIG. 2) of a non-display area (see "NDA" in FIG. 2) and the data line. In addition, the first vertical bridge line (BRL1_V) may be electrically connected to a third connection pattern (CNP3) of an eleventh sub-pixel (SPX11) through a second via hole (VIH2) penetrating the eighth insulating layer (INS8).

[0205] The second vertical bridge line (BRL2_V) may extend in the second direction (DR2) and may be arranged to be spaced apart from the first vertical bridge line (BRL1_V). The second vertical bridge line (BRL2_V) may be formed of a sixth conductive layer (CL6). The second vertical bridge line (BRL2_V) may overlap with a part of the configuration of the twelfth pixel circuit (PXC12). The second vertical bridge line (BRL2_V) may be located on one side (for example, the right side) of the second data line (D2) in the twelfth sub-pixel (SPX12) when viewed in a plan view. The second vertical bridge line (BRL2_V) may be located inside the 12th sub-pixel (SPX12) relative to the boundary between two adjacent sub-pixels in the first direction (DR1), for example, the 12th sub-pixel (SPX12) and the 13th sub-pixel (SPX13). In addition, the second vertical bridge line (BRL2_V) may be located outside the second data line (D2) within the 12th sub-pixel (SPX12) relative to the boundary between two adjacent sub-pixels in the opposite direction of the first direction (DR1), for example, the 12th sub-pixel (SPX12) and the 11th sub-pixel (SPX11).

[0206] The second vertical bridge line (BRL2_V) may be electrically connected to a corresponding one of the data lines located in the first area (DA1). The second vertical bridge line (BRL2_V) may be electrically connected to a fan-out line located in a fan-out area (FTA) and the data line. In addition, the second vertical bridge line (BRL2_V) may be electrically connected to a third connection pattern (CNP3) of a twelfth sub-pixel (SPX12) through a second via hole (VIH2) penetrating the eighth insulating layer (INS8).

[0207] The third vertical bridge line (BRL3_V) may extend in the second direction (DR2) and may be arranged to be spaced apart from the second vertical bridge line (BRL2_V). The third vertical bridge line (BRL3_V) may be formed of a sixth conductive layer (CL6). The third vertical bridge line (BRL3_V) may overlap with a part of the configuration of the 13th pixel circuit (PXC13). The third vertical bridge line (BRL3_V) may be located on one side (for example, the left side) of the third data line (D3) in the 13th sub-pixel (SPX13) when viewed in a plan view. The third vertical bridge line (BRL3_V) may be located outside the third data line (D3) when viewed based on a boundary between two adjacent sub-pixels in the first direction (DR1), for example, the 13th sub-pixel (SPX13) and the 14th sub-pixel (SPX14). Additionally, the third vertical bridge line (BRL3_V) may be located inside the third data line (D3) when viewed from the boundary between two adjacent sub-pixels in the opposite direction of the first direction (DR1), for example, the 13th sub-pixel (SPX13) and the 12th sub-pixel (SPX12).

[0208] The third vertical bridge line (BRL3_V) may be electrically connected to a corresponding one of the data lines located in the first region (DA1). The third vertical bridge line (BRL3_V) may electrically connect the data line to a fan-out line located in the fan-out region (FTA). In addition, the third vertical bridge line (BRL3_V) may be electrically connected to a third connection pattern (CNP3) of a thirteenth sub-pixel (SPX13) through a second via hole (VIH2) penetrating the eighth insulating layer (INS8).

[0209] The fourth vertical bridge line (BRL4_V) may extend in the second direction (DR2) and be arranged to be spaced apart from the third vertical bridge line (BRL3_V). The fourth vertical bridge line (BRL4_V) may be formed of the sixth conductive layer (CL6). The fourth vertical bridge line (BRL4_V) may be located on one side (for example, the right side) of the fourth data line (D4) in the fourteenth sub-pixel (SPX14) when viewed in a plan view. The fourth vertical bridge line (BRL4_V) may be located inside the fourth data line (D4) when viewed based on a boundary between two sub-pixels adjacent in the opposite direction of the first direction (DR1), for example, the fourteenth sub-pixel (SPX14) and the thirteenth sub-pixel (SPX13).

[0210] The fourth vertical bridge line (BRL4_V) may be electrically connected to a corresponding one of the data lines located in the first area (DA1). The fourth vertical bridge line (BRL4_V) may be electrically connected to a fan-out line located in a fan-out area (FTA) of a non-display area (NDA) and the data line. In addition, the fourth vertical bridge line (BRL4_V) may be electrically connected to a third connection pattern (CNP3) of a fourteenth sub-pixel (SPX14) through a second via hole (VIH2) penetrating the eighth insulating layer (INS8).

[0211] In each of the 11th to 14th sub-pixels (SPX11 to SPX14), the third connection pattern (CNP3) is formed of a fifth conductive layer (CL5) and can be electrically connected to a corresponding vertical bridge line through a corresponding second via hole (VIH2). For example, the third connection pattern (CNP3) of the 11th sub-pixel (SPX1) may be electrically connected to the first vertical bridge line (BRL1_V) through the corresponding second via hole (VIH2), the third connection pattern (CNP3) of the 12th sub-pixel (SPX12) may be electrically connected to the second vertical bridge line (BRL2_V) through the corresponding second via hole (VIH2), the third connection pattern (CNP3) of the 13th sub-pixel (SPX13) may be electrically connected to the third vertical bridge line (BRL3_V) through the corresponding second via hole (VIH2), and the third connection pattern (CNP3) of the 14th sub-pixel (SPX14) may be electrically connected to the fourth vertical bridge line (BRL4_V) through the corresponding second via hole (VIH2). The third connection pattern (CNP3) may be an island-shaped conductive pattern.

[0212] In one embodiment, the third connection pattern (CNP3) of the 13th sub-pixel (SPX13) may be electrically and / or physically connected to the dummy electrode (DME).

[0213] The dummy electrode (DME) is formed of a fifth conductive layer (CL5) and can be positioned at a boundary between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) (or a boundary between the twelfth sub-pixel (SPX12) and the thirteenth sub-pixel (SPX13)). The dummy electrode (DME) can be formed integrally with the third connection pattern (CNP3) of the thirteenth sub-pixel (SPX13). In this case, the dummy electrode (DME) can be regarded as a region of the third connection pattern (CNP3) of the thirteenth sub-pixel (SPX13). The dummy electrode (DME) can be electrically connected to the third vertical bridge line (BRL3_V) through the third connection pattern (CNP3) of the thirteenth sub-pixel (SPX13). Additionally, the dummy electrode (DME) can be electrically connected to the first horizontal bridge line (BRL1_H) through a first via hole (VIH1) penetrating the seventh insulating layer (INS7).

[0214] The above-described first data line (D1), second data line (D2), third data line (D3), fourth data line (D4), first vertical bridge line (BRL1_V), second vertical bridge line (BRL2_V), third vertical bridge line (BRL3_V), and fourth vertical bridge line (BRL4_V) may be formed through the same process, contain the same material, and be arranged on the same layer.

[0215] The first power line (PL1) may extend in the second direction (DR2) and may be formed of a fifth conductive layer (CL5). The first power line (PL1) may be the first power line (PL1) described with reference to FIG. 5. The first power line (PL1) may be supplied with a first power voltage (VDD). The 11th sub-pixel (SPX11) and the 12th sub-pixel (SPX12) may share one first power line (PL1), and the 13th sub-pixel (SPX13) and the 14th sub-pixel (SPX14) may share one first power line (PL1), but are not limited thereto.

[0216] In each of the 11th to 14th sub-pixels (SPX11 to SPX14), the first power line (PL1) can be electrically connected to the third conductive pattern (CP3) composed of the fourth conductive layer (CL4) through a corresponding first via hole (VIH1) penetrating the seventh insulating layer (INS7).

[0217] The third conductive pattern (CP3) is formed of a fourth conductive layer (CL4) and can be electrically connected to the first power line (PL1) through a corresponding first via hole (VIH1). In addition, the third conductive pattern (CP3) can be electrically connected to the first semiconductor pattern (SCP1) of the fifth transistor (T5) of each of the eleventh to fourteenth pixel circuits (PXC11 to PXC14) through a corresponding first contact portion (CNT1) penetrating the sixth insulating layer (INS6), the fifth insulating layer (INS5), the fourth insulating layer (INS4), the third insulating layer (INS3), and the second insulating layer (INS2). In one embodiment, the first power line (PL1) formed of the fifth conductive layer (CL5) can be electrically connected to the first semiconductor pattern (SCP1) of the fifth transistor (T5) formed of the first semiconductor layer through the third conductive pattern (CP3) formed of the fourth conductive layer (CL4). Additionally, the third conductive pattern (CP3) can be electrically connected to the upper electrode (UE) composed of the second conductive layer (CL2) through the corresponding first contact portion (CNT1) penetrating the sixth insulating layer (INS6), the fifth insulating layer (INS5), and the fourth insulating layer (INS4).

[0218] The eleventh pixel circuit (PXC11), the twelfth pixel circuit (PXC12), the thirteenth pixel circuit (PXC13), and the fourteenth pixel circuit (PXC14) may have substantially similar or identical structures. For example, the eleventh and twelfth pixel circuits (PXC11, PXC12) included in the first sub-pixel unit (SPU1) and the thirteenth and fourteenth pixel circuits (PXC13, PXC14) included in the second sub-pixel unit (SPU2) may be symmetrical to each other. In one embodiment, the eleventh pixel circuit (PXC11) and the twelfth pixel circuit (PXC12) may be mirror-symmetrical when viewed based on the boundary between the eleventh sub-pixel (SPX11) and the twelfth sub-pixel (SPX12), and the thirteenth pixel circuit (PXC13) and the fourteenth pixel circuit (PXC14) may be mirror-symmetrical when viewed based on the boundary between the thirteenth sub-pixel (SPX13) and the fourteenth sub-pixel (SPX14), but are not limited thereto.

[0219] In the following, for convenience, the description will focus on the 11th pixel circuit (PXC11), and any duplicate description will not be repeated.

[0220] The eleventh pixel circuit (PXC11) may include first, second, third, fourth, fifth, sixth, seventh, and eighth transistors (T1, T2, T3, T4, T5, T6, T7, T8) and a storage capacitor (Cst).

[0221] The first transistor (T1) may include a first active pattern (ACT1) and a first gate electrode (GE1).

[0222] The first active pattern (ACT1) may be a region of the first semiconductor pattern (SCP1) that overlaps the first gate electrode (GE1). The first semiconductor pattern (SCP1) may be a first semiconductor layer. The first active pattern (ACT1) may be a channel region of the first transistor (T1).

[0223] The channel region may be, for example, an intrinsic semiconductor pattern that is not doped with impurities. The remaining region of the semiconductor pattern excluding the channel region may be a doped semiconductor pattern.

[0224] A region of the first semiconductor pattern (SCP1) that does not overlap with the first gate electrode (GE1) and is connected to one side of the first active pattern (ACT1) (or channel region) (for example, the left side of the first active pattern (ACT1) in a plan view) may be a first contact region. A region of the first semiconductor pattern (SCP1) that does not overlap with the first gate electrode (GE1) and is connected to the other side of the first active pattern (ACT1) (for example, the right side of the first active pattern (ACT1) in a plan view) may be a second contact region. The first contact region and the second contact region may extend in opposite directions from the first active pattern (ACT1) (or channel region). The first contact region and the second contact region may face each other in a first direction (DR1) with the first active pattern (ACT1) therebetween.

[0225] The first contact area is connected to one side of the first active pattern (ACT1) and can be connected to the first semiconductor pattern (SCP1) of the second transistor (T2) and the first semiconductor pattern (SCP1) of the fifth transistor (T5). The second contact area is connected to the other side of the first active pattern (ACT1) and can be connected to the first semiconductor pattern (SCP1) of the sixth transistor (T6).

[0226] The first gate electrode (GE1) overlaps the first active pattern (ACT1) and may be formed of a first conductive layer (CL1). The first gate electrode (GE1) may be an island-shaped conductive pattern. The first gate electrode (GE1) may be electrically connected to the third transistor (T3) and the fourth transistor (T4) through the fifth conductive pattern (CP5).

[0227] The fifth conductive pattern (CP5) may be formed of a fourth conductive layer (CL4). One end of the fifth conductive pattern (CP5) may be electrically connected to the first gate electrode (GE1) through a corresponding first contact portion (CNT1) penetrating the sixth insulating layer (INS6), the fifth insulating layer (INS5), the fourth insulating layer (INS4), and the third insulating layer (INS3). The other end of the fifth conductive pattern (CP5) may be electrically connected to a region of the second semiconductor pattern (SCP2) shared by the third transistor (T3) and the fourth transistor (T4) through a second contact portion (CNT2) penetrating the sixth insulating layer (INS6) and the fifth insulating layer (INS5).

[0228] The second transistor (T2) may include a second active pattern (ACT2) and a second gate electrode.

[0229] The second active pattern (ACT2) may be a region of the first semiconductor pattern (SCP1) that overlaps the first wiring (WL1). The first semiconductor pattern (SCP1) may be formed of a first semiconductor layer. The second active pattern (ACT2) may be a channel region of the second transistor (T2).

[0230] An area of ​​the first semiconductor pattern (SCP1) that does not overlap with the first wiring (WL1) and is connected to one side of the second active pattern (ACT2) (for example, the lower side of the second active pattern (ACT2) in a plan view) may be a first contact area, and an area of ​​the first semiconductor pattern (SCP1) that does not overlap with the first wiring (WL1) and is connected to the other side of the second active pattern (ACT2) (for example, the upper side of the second active pattern (ACT2) in a plan view) may be a second contact area. The first contact area may be connected to one side of the second active pattern (ACT2) and may be electrically connected to the sixth conductive pattern (CP6). The second contact area may be connected to the other side of the second active pattern (ACT2) and may be connected to the first contact area of ​​the first transistor (T1).

[0231] The sixth conductive pattern (CP6) may be composed of a fourth conductive layer (CL4). The sixth conductive pattern (CP6) may be electrically connected to a first semiconductor pattern (SCP1) corresponding to a first contact area of ​​a second transistor (T2) through a first contact portion (CNT1) penetrating the sixth insulating layer (INS6), the fifth insulating layer (INS5), the fourth insulating layer (INS4), the third insulating layer (INS3), and the second insulating layer (INS2). In addition, the sixth conductive pattern (CP6) may be electrically connected to a second connection pattern (CNP2) through a first via hole (VIH1).

[0232] The second connection pattern (CNP2) is formed of a fifth conductive layer (CL5) and can be electrically connected to a sixth conductive pattern (CP6) through a first via hole (VIH1) penetrating a seventh insulating layer (INS7). In addition, the second connection pattern (CNP2) can be electrically connected to a first data line (D1) formed of a sixth conductive layer (CL6) through a second via hole (VIH2) penetrating an eighth insulating layer (INS8).

[0233] The first contact area of ​​the first semiconductor pattern (SCP1) of the second transistor (T2) can be electrically connected to the first data line (D1) through the sixth conductive pattern (CP6) and the second connection pattern (CNP2).

[0234] The second gate electrode may be an area of ​​the first wiring (WL1) that overlaps the second active pattern (ACT2).

[0235] The third transistor (T3) may include a third active pattern (ACT3) and a third gate electrode.

[0236] The third active pattern (ACT3) is a region of the second semiconductor pattern (SCP2) that overlaps the ninth wiring (WL9) and may constitute a channel region of the third transistor (T3). The second semiconductor pattern (SCP2) may be formed of a second semiconductor layer.

[0237] An area of ​​the second semiconductor pattern (SCP2) that does not overlap with the ninth wiring (WL9) and is connected to one side of the third active pattern (ACT3) (for example, the upper side of the third active pattern (ACT3) in a plan view) may be a first contact area, and an area of ​​the second semiconductor pattern (SCP2) that does not overlap with the ninth wiring (WL9) and is connected to the other side of the third active pattern (ACT3) (for example, the lower side of the third active pattern (ACT3) in a plan view) may be a second contact area. The first contact area may be connected to one side of the third active pattern (ACT3) and may be electrically connected to the first transistor (T1) and the sixth transistor (T6) via the seventh conductive pattern (CP7). The second contact area may be connected to the other side of the third active pattern (ACT3) and may be connected to the second semiconductor pattern (SCP2) of the fourth transistor (T4).

[0238] The seventh conductive pattern (CP7) may be formed of a fourth conductive layer (CL4). One end of the seventh conductive pattern (CP7) may be electrically connected to a first contact area of ​​a third transistor (T3) through a second contact portion (CNT2) penetrating the sixth insulating layer (INS6) and the fifth insulating layer (INS5). The other end of the seventh conductive pattern (CP7) may be electrically connected to a region of a first semiconductor pattern (SCP1) shared by the first transistor (T1) and the sixth transistor (T6) through a first contact portion (CNT1) penetrating the sixth insulating layer (INS6), the fifth insulating layer (INS5), the fourth insulating layer (INS4), the third insulating layer (INS3), and the second insulating layer (INS2).

[0239] The third gate electrode may be an area of ​​the ninth wiring (WL9) that overlaps the third active pattern (ACT3).

[0240] The fourth transistor (T4) may include a fourth active pattern (ACT4) and a fourth gate electrode.

[0241] The fourth active pattern (ACT4) is an area of ​​the second semiconductor pattern (SCP2) that overlaps the tenth wiring (WL10) and may constitute a channel area of ​​the fourth transistor (T4). The second semiconductor pattern (SCP2) may be formed of a second semiconductor layer.

[0242] An area of ​​the second semiconductor pattern (SCP2) that does not overlap with the tenth wiring (WL10) and is connected to one side of the fourth active pattern (ACT4) (for example, an upper side of the fourth active pattern (ACT4) in a plan view) may be a first contact area, and an area of ​​the second semiconductor pattern (SCP2) that does not overlap with the tenth wiring (WL10) and is connected to the other side of the fourth active pattern (ACT4) (for example, a lower side of the fourth active pattern (ACT4) in a plan view) may be a second contact area. The first contact area may be connected to one side of the fourth active pattern (ACT4) and may be connected to the second semiconductor pattern (SCP2) of the third transistor (T3). The second contact area may be connected to the other side of the fourth active pattern (ACT4) and may be electrically connected to a fourteenth wiring (WL14) formed of a fourth conductive layer (CL4) through a corresponding second contact portion (CNT2) penetrating the sixth insulating layer (INS6) and the fifth insulating layer (INS5).

[0243] The fourth gate electrode may be an area of ​​the tenth wiring (WL10) that overlaps the fourth active pattern (ACT4).

[0244] The fifth transistor (T5) may include a fifth active pattern (ACT5) and a fifth gate electrode.

[0245] The fifth active pattern (ACT5) is a region of the first semiconductor pattern (SCP1) that overlaps the second wiring (WL2) and may constitute a channel region of the fifth transistor (T5). The first semiconductor pattern (SCP1) may be formed of a first semiconductor layer.

[0246] An area of ​​the first semiconductor pattern (SCP1) that does not overlap with the second wiring (WL2) and is connected to one side of the fifth active pattern (ACT5) (for example, an upper side of the fifth active pattern (ACT5) in a plan view) may be a first contact area, and an area of ​​the first semiconductor pattern (SCP1) that does not overlap with the second wiring (WL2) and is connected to the other side of the fifth active pattern (ACT5) (for example, a lower side of the fifth active pattern (ACT5) in a plan view) may be a second contact area. The first contact area may be connected to one side of the fifth active pattern (ACT5) and may be electrically connected to the third conductive pattern (CP3) via a corresponding first contact portion (CNT1). The second contact area may be connected to the other side of the fifth active pattern (ACT5) and may be connected to the first semiconductor pattern (SCP1) of each of the first and second transistors (T1, T2).

[0247] The fifth gate electrode may be an area of ​​the second wiring (WL2) that overlaps the fifth active pattern (ACT5).

[0248] The sixth transistor (T6) may include a sixth active pattern (ACT6) and a sixth gate electrode.

[0249] The sixth active pattern (ACT6) is a region of the first semiconductor pattern (SCP1) that overlaps the second wiring (WL2), and may be a channel region of the sixth transistor (T6). The first semiconductor pattern (SCP1) may be composed of a first semiconductor layer.

[0250] An area of ​​the first semiconductor pattern (SCP1) that does not overlap with the second wiring (WL2) and is connected to one side of the sixth active pattern (ACT6) (for example, an upper side of the sixth active pattern (ACT6) in a plan view) may be a first contact area, and an area of ​​the first semiconductor pattern (SCP1) that does not overlap with the second wiring (WL2) and is connected to the other side of the sixth active pattern (ACT6) (for example, a lower side of the sixth active pattern (ACT6) in a plan view) may be a second contact area. The first contact area may be connected to one side of the sixth active pattern (ACT6) and the first semiconductor pattern (SCP1) of the seventh transistor (T7), respectively. The second contact area may be connected to the other side of the sixth active pattern (ACT6) and the first semiconductor pattern (SCP1) of the first transistor (T1), respectively. Additionally, the second contact area can be electrically connected to the fourth conductive pattern (CP4) through the corresponding first contact portion (CNT1).

[0251] The fourth conductive pattern (CP4) may be formed of a fourth conductive layer (CL4). The fourth conductive pattern (CP4) may be electrically connected to a second contact area of ​​the sixth transistor (T6) through a corresponding first contact portion (CNT1) penetrating the sixth insulating layer (INS6), the fifth insulating layer (INS5), the fourth insulating layer (INS4), the third insulating layer (INS3), and the second insulating layer (INS2). In addition, the fourth conductive pattern (CP4) may be electrically connected to a first connection pattern (CNP1) formed of the fifth conductive layer (CL5) through a corresponding first via hole (VIH1).

[0252] One end of the first connection pattern (CNP1) may be electrically connected to the fourth conductive pattern (CP4) through a corresponding first via hole (VIH1) penetrating the seventh insulating layer (INS7). The other end of the first connection pattern (CNP1) may be electrically connected to a bridge pattern (BRP) through a corresponding second via hole (VIH2) penetrating the eighth insulating layer (INS8). The bridge pattern (BRP) may be the bridge pattern (BRP) described with reference to FIG. 6. The bridge pattern (BRP) may be electrically connected to an anode electrode (refer to "AE" in FIG. 6) of an eleventh sub-pixel (SPX11) through a third via hole (refer to "VIH3" in FIG. 6) penetrating the ninth insulating layer (INS9).

[0253] The sixth gate electrode may be an area of ​​the second wiring (WL2) that overlaps the sixth active pattern (ACT6).

[0254] The seventh transistor (T7) may include a seventh active pattern (ACT7) and a seventh gate electrode.

[0255] The seventh active pattern (ACT7) may be a region of the first semiconductor pattern (SCP1) overlapping the third wiring (WL3). The first semiconductor pattern (SCP1) may be formed of a first semiconductor layer. The seventh active pattern (ACT7) may be a channel region of the seventh transistor (T7).

[0256] An area of ​​the first semiconductor pattern (SCP1) that does not overlap with the third wiring (WL3) and is connected to one side of the seventh active pattern (ACT7) (for example, the lower side of the seventh active pattern (ACT7) in a plan view) may be a first contact area, and an area of ​​the first semiconductor pattern (SCP1) that does not overlap with the third wiring (WL3) and is connected to the other side of the seventh active pattern (ACT7) (for example, the upper side of the seventh active pattern (ACT7) in a plan view) may be a second contact area. The first contact area may be connected to one side of the seventh active pattern (ACT7) and may be connected to the first semiconductor pattern (SCP1) of the sixth transistor (T6). The second contact area may be connected to the other side of the seventh active pattern (ACT7) and may be electrically connected to the first conductive pattern (CP1).

[0257] The first conductive pattern (CP1) may be formed of a fourth conductive layer (CL4). The first conductive pattern (CP1) may be electrically connected to the first semiconductor pattern (SCP1) of the seventh transistor (T7) through a corresponding first contact portion (CNT1) penetrating the sixth insulating layer (INS6), the fifth insulating layer (INS5), the fourth insulating layer (INS4), the third insulating layer (INS3), and the second insulating layer (INS2). In addition, the first conductive pattern (CP1) may be electrically connected to the eighth wiring (WL8) through a corresponding second contact portion (CNT2) penetrating the sixth insulating layer (INS6). Additionally, the first conductive pattern (CP1) may be electrically connected to the fourth connection pattern (CNP4).

[0258] The fourth connection pattern (CNP4) may be formed of a fifth conductive layer (CL5). The fourth connection pattern (CNP4) may be electrically connected to the first conductive pattern (CP1) through a corresponding first via hole (VIH1) penetrating the seventh insulating layer (INS7).

[0259] The seventh gate electrode may be an area of ​​the third wiring (WL3) overlapping the seventh active pattern (ACT7).

[0260] The eighth transistor (T8) may include an eighth active pattern (ACT8) and an eighth gate electrode.

[0261] The eighth active pattern (ACT8) may be a region of the first semiconductor pattern (SCP1) overlapping the third wiring (WL3). The first semiconductor pattern (SCP1) may be formed of a first semiconductor layer. The eighth active pattern (ACT8) may be a channel region of the eighth transistor (T8).

[0262] An area of ​​the first semiconductor pattern (SCP1) that does not overlap with the third wiring (WL3) and is connected to one side of the eighth active pattern (ACT8) (for example, an upper side of the eighth active pattern (ACT8) in a plan view) may be a first contact area, and an area of ​​the first semiconductor pattern (SCP1) that does not overlap with the third wiring (WL3) and is connected to the other side of the eighth active pattern (ACT8) (for example, a lower side of the eighth active pattern (ACT8) in a plan view) may be a second contact area. The first contact area may be connected to one side of the eighth active pattern (ACT8) and may be electrically connected to the twelfth wiring (WL12). The second contact area may be connected to the other side of the eighth active pattern (ACT8) and may be electrically connected to the second conductive pattern (CP2).

[0263] The 12th wiring (WL12) is composed of a fourth conductive layer (CL4) and can be electrically connected to a first contact area of ​​a first semiconductor pattern (SCP1) of an eighth transistor (T8) through a first contact portion (CNT1) penetrating the sixth insulating layer (INS6), the fifth insulating layer (INS5), the fourth insulating layer (INS4), the third insulating layer (INS3), and the second insulating layer (INS2).

[0264] The second conductive pattern (CP2) is formed of a fourth conductive layer (CL4) and can be electrically connected to a second contact area of ​​the first semiconductor pattern (SCP1) of the eighth transistor (T8) through a first contact portion (CNT1) penetrating the sixth insulating layer (INS6), the fifth insulating layer (INS5), the fourth insulating layer (INS4), the third insulating layer (INS3), and the second insulating layer (INS2). In addition, the second conductive pattern (CP2) can be electrically connected to the first semiconductor pattern (SCP1) of the fifth transistor (T5) through a first contact portion (CNT1) penetrating the sixth insulating layer (INS6), the fifth insulating layer (INS5), the fourth insulating layer (INS4), the third insulating layer (INS3), and the second insulating layer (INS2).

[0265] The eighth gate electrode may be an area of ​​the third wiring (WL3) that overlaps the eighth active pattern (ACT8).

[0266] The storage capacitor (Cst) may include a lower electrode (LE) and an upper electrode (UE).

[0267] The lower electrode (LE) may be formed integrally with the first gate electrode (GE1). The lower electrode (LE) may be composed of a first conductive layer (CL1).

[0268] The upper electrode (UE) may overlap the lower electrode (LE) and may be formed of a second conductive layer (CL2). The upper electrode (UE) may include an opening (OPN) from which a portion thereof is removed. A portion of the lower electrode (LE) overlapping the upper electrode (UE) may be exposed by the opening (OPN). The upper electrode (UE) may be electrically connected to a third conductive pattern (CP3).

[0269] According to the above-described embodiment, the first sub-pixel unit (SPU1) may include an eleventh sub-pixel (SPX11) and a twelfth sub-pixel (SPX12), and the second sub-pixel unit (SPU2) may include a thirteenth sub-pixel (SPX13) and a fourteenth sub-pixel (SPX14). In each of the first and second sub-pixel units (SPU1, SPU2), the vertical bridge line may be positioned adjacent to an edge of the corresponding sub-pixel unit. For example, in the first sub-pixel unit (SPU1), the first vertical bridge line (BRL1_V) may be positioned adjacent to the left edge of the first sub-pixel unit (SPU1), and the second vertical bridge line (BRL2_V) may be positioned adjacent to the right edge of the first sub-pixel unit (SPU1). In the second sub-pixel unit (SPU2), the third vertical bridge line (BRL3_V) may be positioned adjacent to the left edge of the second sub-pixel unit (SPU2) and adjacent to the right edge of the fourth vertical bridge line (BRL4_V).

[0270] According to the above-described embodiment, a dummy electrode (DME) may be positioned at a boundary portion between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) (or a boundary portion between the twelfth sub-pixel (SPX12) and the thirteenth sub-pixel (SPX13)). The dummy electrode (DME) may be positioned between a second vertical bridge line (BRL2_V) among the vertical bridge lines arranged adjacent to an edge of the first sub-pixel unit (SPU1) and a third vertical bridge line (BRL3_V) among the vertical bridge lines arranged adjacent to an edge of the second sub-pixel unit (SPU2).

[0271] The dummy electrode (DME) is formed of a fifth conductive layer (CL5) and is formed integrally with the third connection pattern (CNP3) (or the second additional conductive pattern (ACP2)) of the 13th sub-pixel (SPX13) so as to be electrically connected to the third vertical bridge line (BRL3_V). The dummy electrode (DME) can be electrically connected to the first horizontal bridge line (BRL1_H) through a first via hole (VIH1) at a boundary between the 12th sub-pixel (SPX12) and the 13th sub-pixel (SPX13). The first via hole (VIH1) can correspond to a position of the dummy electrode (DME). For example, when viewed in a plan view, the first via hole (VIH1) can overlap the dummy electrode (DME) at a boundary between the 12th sub-pixel (SPX12) and the 13th sub-pixel (SPX13). A first via hole (VIH1) overlapping with a dummy electrode (DME) may be positioned at a boundary portion between the 12th sub-pixel (SPX12) and the 13th sub-pixel (SPX13) (or a boundary portion between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2)).

[0272] According to the above-described embodiment, when viewed in a plan view, the second vertical bridge line (BRL2_V) and the third vertical bridge line (BRL3_V) may be spaced apart from each other with the dummy electrode (DME) therebetween. For example, when viewed in a plan view, the second vertical bridge line (BRL2_V) may be located on the left side of the dummy electrode (DME), and the third bridge line (BRL3_V) may be located on the right side of the dummy electrode (DME).

[0273] When viewed in a plan view, the second data line (D2) and the third data line (D3) may be spaced apart from each other with the dummy electrode (DME) therebetween. When viewed in a plan view, the second data line (D2) may be located on the left side of the dummy electrode (DME) and may be located outside the second vertical bridge line (BRL2_V) with respect to the dummy electrode (DME). That is, when viewed in a plan view, the second vertical bridge line (BRL2_V) may be located closer to the dummy electrode (DME) than the second data line (D2). When viewed in a plan view, the third data line (D3) may be located on the right side of the dummy electrode (DME) and may be located outside the third vertical bridge line (BRL3_V) with respect to the dummy electrode (DME). That is, when viewed on a plane, the third vertical bridge line (BRL3_V) may be positioned closer to the dummy electrode (DME) than the third data line (D3).

[0274] According to the above-described embodiment, the spacing (d1) between the second vertical bridge line (BRL2_V) and the third vertical bridge line (BRL3_V) may be smaller (or narrower) than the spacing (d2) between the second data line (D2) and the third data line (D3).

[0275] In the above-described embodiment, the dummy electrode (DME) is described as being formed integrally with the third connection pattern (CNP3) (or the second additional conductive pattern (ACP2)) of the 13th sub-pixel (SPX13) and electrically connected to the third vertical bridge line (BRL3_V), but is not limited thereto. According to an embodiment, the dummy electrode (DME) may be formed integrally with the third connection pattern (CNP3) (or the first additional conductive pattern (ACP1)) of the 12th sub-pixel (SPX12) and electrically connected to the second vertical bridge line (BRL2_V). In this case, the dummy electrode (DME) may electrically connect the first horizontal bridge line (BRL1_H) and the second vertical bridge line (BRL2_V).

[0276] FIG. 17 is a schematic plan view showing sub-pixels arranged in first and second pixel rows (R1, R2) located in one area of ​​a display area (DA) of a display device according to one embodiment.

[0277] For convenience of explanation, in Fig. 17, only the configurations included in the 4th conductive layer, the 5th conductive layer, and the 6th conductive layer in the sub-pixels arranged in the 1st and 2nd pixel rows (R1, R2) are shown.

[0278] In Fig. 17, in order to avoid redundant explanation, the differences from the above-described embodiment will be explained.

[0279] Referring to FIG. 17, in the first pixel row (R1), an eleventh sub-pixel (SPX11) (or a first sub-pixel), a twelfth sub-pixel (SPX12) (or a second sub-pixel), a thirteenth sub-pixel (SPX13) (or a third sub-pixel), and a fourteenth sub-pixel (SPX14) (or a fourth sub-pixel) may be arranged along a first direction (DR1). In the second pixel row (R2), a twenty-first sub-pixel (SPX21) (or a first sub-pixel), a twenty-second sub-pixel (SPX22) (or a second sub-pixel), a twenty-third sub-pixel (SPX23) (or a third sub-pixel), and a twenty-fourth sub-pixel (SPX24) (or a fourth sub-pixel) may be arranged along a first direction (DR1).

[0280] The eleventh sub-pixel (SPX11) may include an eleventh pixel circuit (PXC11), the twelfth sub-pixel (SPX12) may include a twelfth pixel circuit (PXC12), the thirteenth sub-pixel (SPX13) may include a thirteenth pixel circuit (PXC13), and the fourteenth sub-pixel (SPX14) may include a fourteenth pixel circuit (PXC14). The twenty-first sub-pixel (SPX21) may include a twenty-first pixel circuit (PXC21), the twenty-second sub-pixel (SPX22) may include a twenty-second pixel circuit (PXC22), the twenty-third sub-pixel (SPX23) may include a twenty-third pixel circuit (PXC23), and the twenty-fourth sub-pixel (SPX24) may include a twenty-fourth pixel circuit (PXC24). A first vertical bridge line (BRL1_V) may be commonly provided to an 11th sub-pixel (SPX11) and a 21st sub-pixel (SPX21) adjacent in the second direction (DR2). A second vertical bridge line (BRL2_V) may be commonly provided to a 12th sub-pixel (SPX12) and a 22nd sub-pixel (SPX22) adjacent in the second direction (DR2). A third vertical bridge line (BRL3_V) may be commonly provided to a 13th sub-pixel (SPX13) and a 23rd sub-pixel (SPX23) adjacent in the second direction (DR2). A fourth vertical bridge line (BRL4_V) may be commonly provided to a 14th sub-pixel (SPX14) and a 24th sub-pixel (SPX24) adjacent in the second direction (DR2). In each of the first and second pixel rows (R1, R2), each of the first to fourth vertical bridge lines (BRL1_V to BRL4_V) can be electrically connected to the third connection pattern (CNP3) through a corresponding second via hole (VIH2).

[0281] In the first pixel row (R1), the 11th sub-pixel (SPX11) and the 12th sub-pixel (SPX12) may constitute a first sub-pixel unit (see "SPU1" in FIG. 14), and the 13th sub-pixel (SPX13) and the 14th sub-pixel (SPX14) may constitute a second sub-pixel unit (see "SPU2" in FIG. 14). In the second pixel row (R2), the 21st sub-pixel (SPX21) and the 22nd sub-pixel (SPX22) may constitute a first sub-pixel unit (SPU1), and the 23rd sub-pixel (SPX23) and the 24th sub-pixel (SPX24) may constitute a second sub-pixel unit (SPU2).

[0282] In each of the first and second pixel rows (R1, R2), a dummy electrode (DME) may be positioned at a boundary between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) (or between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2)). For example, in the first pixel row (R1), the first dummy electrode (DME1) may be positioned at a boundary between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) (or a boundary between the twelfth sub-pixel (SPX12) and the thirteenth sub-pixel (SPX13)). In the second pixel row (R2), the second dummy electrode (DME2) may be positioned at a boundary between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) (or a boundary between the 22nd sub-pixel (SPX22) and the 23rd sub-pixel (SPX23)).

[0283] The first dummy electrode (DME1) and the second dummy electrode (DME2) may be formed of a fifth conductive layer (see "CL5" in FIG. 14). In one embodiment, each of the first and second dummy electrodes (DME1, DME2) may be electrically connected to a corresponding horizontal bridge line through one first via hole (VIH1) at a boundary between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2). For example, the first dummy electrode (DME1) may be electrically connected to the first horizontal bridge line (BRL1_H) (or the thirteenth wiring (WL13)) through one eleventh via hole (VIH11) at a boundary between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) of the first pixel row (R1) (or a boundary between the twelfth sub-pixel (SPX12) and the thirteenth sub-pixel (SPX13)). The second dummy electrode (DME2) can be electrically connected to the second horizontal bridge line (BRL2_H) (or the 13th wiring (WL13)) through one twelfth via hole (VIH12) at the boundary between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) of the second pixel row (R2) (or the boundary between the 22nd sub-pixel (SPX22) and the 23rd sub-pixel (SPX23)).

[0284] In one embodiment, the first dummy electrode (DME1) may be formed integrally with the third connection pattern (CNP3) (or the second additional conductive pattern (ACP2)) of the 13th sub-pixel (SPX13). The third connection pattern (CNP3) (or the second additional conductive pattern (ACP2)) may be electrically connected to the third vertical bridge line (BRL3_V) through the 22nd via hole (VIH22). As the first dummy electrode (DME1) is electrically connected to the first horizontal bridge line (BRL1_H) through the 11th via hole (VIH11), the first horizontal bridge line (BRL1_H) may be electrically connected to the third vertical bridge line (BRL3_V).

[0285] In one embodiment, the second dummy electrode (DME2) may be formed integrally with the third connection pattern (CNP3) (or the first additional conductive pattern (ACP1)) of the 22nd sub-pixel (SPX22). The third connection pattern (CNP3) (or the first additional conductive pattern (ACP1)) may be electrically connected to the second vertical bridge line (BRL2_V) through the 21st via hole (VIH21). As the second dummy electrode (DME2) is electrically connected to the second horizontal bridge line (BRL2_H) through the 12th via hole (VIH12), the second horizontal bridge line (BRL2_H) may be electrically connected to the second vertical bridge line (BRL2_V).

[0286] In the first pixel row (R1), the first horizontal bridge line (BRL1_H) may be electrically connected to the first dummy electrode (DME1) through the eleventh via hole (VIH11) and may be electrically connected to the third vertical bridge line (BRL3_V) through the first dummy electrode (DME1). In the second pixel row (R2), the second horizontal bridge line (BRL2_H) may be electrically connected to the second dummy electrode (DME2) through the twelfth via hole (VIH12) and may be electrically connected to the second vertical bridge line (BRL2_V) through the second dummy electrode (DME2).

[0287] A dummy electrode (DME) (for example, the first dummy electrode (DME1)) located at a boundary portion between a first sub-pixel unit (SPU1) and a second sub-pixel unit (SPU2) in an odd-numbered pixel row (for example, the first pixel row R1) of a display area (DA) can be electrically connected to a vertical bridge line arranged adjacent to the dummy electrode (DME) among sub-pixels included in one of the first and second sub-pixel units (SPU1, SPU2). A dummy electrode (DME) (for example, the second dummy electrode (DME2)) located at a boundary portion between a first sub-pixel unit (SPU1) and a second sub-pixel unit (SPU2) in an even-numbered pixel row of a display area (DA) can be electrically connected to a vertical bridge line arranged adjacent to the dummy electrode (DME) among sub-pixels included in the remaining sub-pixel units among the first and second sub-pixel units (SPU1, SPU2). Accordingly, the dummy electrode (DME) located in the odd-numbered pixel row (e.g., the first dummy electrode (DME1)) and the dummy electrode (DME) located in the even-numbered pixel row (e.g., the second dummy electrode (DME2)) can be electrically connected to different vertical bridge lines.

[0288] According to the above-described embodiment, the dummy electrodes (DME) and the first via holes (VIH1) electrically connecting the horizontal bridge line and the vertical bridge line in one area of ​​the display area (DA) may be positioned in the same column (or on the same line) in the second direction (DR2) when viewed on a plane. For example, the first dummy electrode (DME1) positioned in the first pixel row (R1) and the second dummy electrode (DME2) positioned in the second pixel row (R2) may be positioned in the same column (or on the same line) in the second direction (DR2), and the 11th via hole (VIH11) positioned in the first pixel row (R1) and the 12th via hole (VIH12) positioned in the second pixel row (R2) may be positioned in the same column (or on the same line) in the second direction (DR2). In this case, the first and second dummy electrodes (DME1, DME2) (or dummy electrodes (DME)) and the eleventh and twelfth via holes (VIH11, VIH12) (or the first via holes (VIH1)) may be positioned only in a specific area of ​​the display area (DA) (for example, a boundary between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) in each pixel row). That is, the dummy electrodes (DME) and the first via holes (VIH1) may be concentratedly positioned in a specific area (for example, a boundary between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) in each pixel row) in the display area (DA). In this case, design constraints on the positions of connecting members (e.g., dummy electrodes (DMEs) and first via holes (VIH1)) for electrically connecting vertical bridge lines and horizontal bridge lines for each pixel row in one area of ​​the display area (DA) can be reduced. Accordingly, design optimization for vertical bridge lines and horizontal bridge lines in the display area can be enabled, thereby securing effective space in each sub-pixel.

[0289] FIG. 18 is a schematic drawing showing the positions of a first via hole (VIH1) and a second via hole (VIH2) in one area of ​​a display area (DA) of a display device according to one embodiment.

[0290] In Fig. 18, for convenience of explanation, only some signal wirings in the sub-pixels arranged in each of the first to fourth pixel rows (R1 to R4) are illustrated.

[0291] In Fig. 18, in order to avoid redundant explanation, the differences from the above-described embodiment will be explained.

[0292] Referring to FIG. 18, the display area (DA) may be divided into pixel rows (R1 to R4). The pixel rows (R1 to R4) may extend in a first direction (DR1) and be arranged along a second direction (DR2). Each of the pixel rows (R1 to R4) may include first to eighth sub-pixels (SPX1 to SPX8). The first to eighth sub-pixels (SPX1 to SPX8) may include pixel circuits.

[0293] In one embodiment, the sub-pixels (SPX1 to SPX8) may be arranged along the first direction (DR1) in the following order: a first sub-pixel (SPX1), a second sub-pixel (SPX2), a third sub-pixel (SPX3), a fourth sub-pixel (SPX4), a fifth sub-pixel (SPX5), a sixth sub-pixel (SPX6), a seventh sub-pixel (SPX7), and an eighth sub-pixel (SPX8) in each of the first to fourth pixel rows (R1 to R4). The first sub-pixel (SPX1) and the second sub-pixel (SPX2) may constitute a first sub-pixel unit (see "SPU1" in FIG. 4), and the third sub-pixel (SPX3) and the fourth sub-pixel (SPX4) may constitute a second sub-pixel unit (see "SPU2" in FIG. 4). Additionally, the fifth sub-pixel (SPX5) and the sixth sub-pixel (SPX6) may constitute a first sub-pixel unit (SPU1), and the seventh sub-pixel (SPX7) and the eighth sub-pixel (SPX8) may constitute a second sub-pixel unit (SPU2).

[0294] In a first pixel row (R1), pixel circuits (PXC11 to PXC18) corresponding to the sub-pixels (SPX1 to SPX8) of the first pixel row (R1) may be arranged along a first direction (DR1). In a second pixel row (R2), pixel circuits (PXC21 to PXC28) corresponding to the sub-pixels (SPX1 to SPX8) of the second pixel row (R2) may be arranged along the first direction (DR1). In a third pixel row (R3), pixel circuits (PXC31 to PXC38) corresponding to the sub-pixels (SPX1 to SPX8) of the third pixel row (R3) may be arranged along the first direction (DR1). In the fourth pixel row (R4), pixel circuits (PXC41 to PXC48) corresponding to the sub-pixels (SPX1 to SPX8) of the fourth pixel row (R4) can be arranged in the first direction (DR1).

[0295] A first horizontal bridge line (BRL1_H) may be arranged in the first pixel row (R1), a second horizontal bridge line (BRL2_H) may be arranged in the second pixel row (R2), a third horizontal bridge line (BRL3_H) may be arranged in the third pixel row (R3), and a fourth horizontal bridge line (BRL4_H) may be arranged in the fourth pixel row (R4).

[0296] A first vertical bridge line (BRL1_V) and a first data line (D1) may be arranged in the first sub-pixels (SPX1) of the first to fourth pixel rows (R1 to R4). A second vertical bridge line (BRL2_V) and a second data line (D2) may be arranged in the second sub-pixels (SPX2) of the first to fourth pixel rows (R1 to R4). A third vertical bridge line (BRL3_V) and a third data line (D3) may be arranged in the third sub-pixels (SPX3) of the first to fourth pixel rows (R1 to R4). A fourth vertical bridge line (BRL4_V) and a fourth data line (D4) may be arranged in the fourth sub-pixel (SPX4) of the first to fourth pixel rows (R1 to R4). A fifth vertical bridge line (BRL5_V) and a fifth data line (D5) may be arranged in the fifth sub-pixels (SPX5) of the first to fourth pixel rows (R1 to R4). A sixth vertical bridge line (BRL6_V) and a sixth data line (D6) may be arranged in the sixth sub-pixels (SPX6) of the first to fourth pixel rows (R1 to R4). A seventh vertical bridge line (BRL7_V) and a seventh data line (D7) may be arranged in the seventh sub-pixels (SPX7) of the first to fourth pixel rows (R1 to R4). An eighth vertical bridge line (BRL8_V) and an eighth data line (D8) may be arranged in the eighth sub-pixel (SPX8) of the first to fourth pixel rows (R1 to R4).

[0297] In each of the first and second sub-pixel units (SPU1, SPU2), the vertical bridge line may be positioned adjacent to an edge of the corresponding sub-pixel unit. For example, in each of the first to fourth pixel rows (R1 to R4), the first vertical bridge line (BRL1_V) (or the fifth vertical bridge line (BRL5_V)) and the second vertical bridge line (BRL2_V) (or the sixth vertical bridge line (BRL6_V)) of the first sub-pixel unit (SPU1) may be positioned adjacent to an edge of the first sub-pixel unit (SPU1). Additionally, in each of the second sub-pixel units (SPU2) of the first to fourth pixel rows (R1 to R4), the third vertical bridge line (BRL3_V) (or the seventh vertical bridge line (BRL7_V)) and the fourth vertical bridge line (BRL4_V) (or the eighth vertical bridge line (BRL8_V)) may be positioned adjacent to the edge of the second sub-pixel unit (SPU2).

[0298] In one embodiment, a first via hole (VIH1) may be positioned at a boundary portion between a first sub-pixel unit (SPU1) and a second sub-pixel unit (SPU2) in each of the first to fourth pixel rows (R1 to R4). The first via hole (VIH1) may be formed by removing a portion of an insulating layer, for example, a seventh insulating layer (see "INS7" in FIG. 16), located between a horizontal bridge line and a dummy electrode arranged in each pixel row, and may be a connection point that electrically connects the horizontal bridge line and the dummy electrode.

[0299] Two second via holes (VIH2) may be arranged in a diagonal direction of the first via hole (VIH1) in each of the first to fourth pixel rows (R1 to R4). The two second via holes (VIH2) may be electrically connected to corresponding vertical bridge lines at the boundary between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2).

[0300] The first via holes (VIH1) located in the first pixel row (R1), the first via holes (VIH1) located in the second pixel row (R2), the first via holes (VIH1) located in the third pixel row (R3), and the first via holes (VIH1) arranged in the fourth pixel row (R4) may be located in the same column (or on the same line) in the second direction (DR2). Accordingly, the first via holes (VIH1) may be concentrated only in a specific area (for example, a boundary portion between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) of each of the first to fourth pixel rows (R1 to R4)) in the display area (DA). In this case, design constraints for electrical connection of the horizontal bridge line and the vertical bridge line in each pixel row may be reduced, and effective space may be secured for some sub-pixels included in each pixel row.

[0301] FIG. 19 is a schematic plan view showing sub-pixels located in one area of ​​a display area (DA) of a display device according to one embodiment, and FIGS. 20 and 21 are schematic enlarged views showing part EA3 of FIG. 19.

[0302] For convenience of explanation, in FIGS. 19 to 21, only the configurations included in the fourth conductive layer (CL4), the fifth conductive layer (CL5), and the sixth conductive layer (CL6) in the sub-pixels arranged in the same pixel row (e.g., the first pixel row) are illustrated.

[0303] In Figs. 19 to 21, in order to avoid redundant explanation, differences from the above-described embodiment will be explained.

[0304] Referring to FIGS. 19 to 21, an eleventh sub-pixel (SPX11) (or first sub-pixel), a twelfth sub-pixel (SPX12) (or second sub-pixel), a thirteenth sub-pixel (SPX13) (or third sub-pixel), and a fourteenth sub-pixel (SPX14) (or fourth sub-pixel) may be arranged along a first direction (DR1) in a display area (DA). The eleventh sub-pixel (SPX11) and the twelfth sub-pixel (SPX12) may constitute a first sub-pixel unit (SPU1), and the thirteenth sub-pixel (SPX13) and the fourteenth sub-pixel (SPX14) may constitute a second sub-pixel unit (SPU2).

[0305] A dummy electrode (DME) may be positioned at a boundary portion between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) (or a boundary portion between the 12th sub-pixel (SPX12) and the 13th sub-pixel (SPX13)). The dummy electrode (DME) may be formed of a fifth conductive layer (CL5) and may be electrically connected to a first horizontal bridge line (BRL1_H) (or a 13th wiring (WL13)) formed of a fourth conductive layer (CL4) through a first via hole (VIH1) penetrating a seventh insulating layer (see "INS7" of FIG. 16). The dummy electrode (DME) may be formed integrally with a third connection pattern (CNP3) (or an additional conductive pattern (ACP)) of the 13th sub-pixel (SPX13) of the second sub-pixel unit (SPU2). Accordingly, the dummy electrode (DME) can be electrically and physically connected to the third connection pattern (CNP3). The dummy electrode (DME) and the additional conductive pattern (ACP) (or the third connection pattern (CNP3) of the 13th sub-pixel (SPX13)) formed integrally can have various shapes at the boundary portion between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2), as illustrated in FIGS. 20 and 21.

[0306] When viewed on a plane, the second vertical bridge line (BRL2_V) disposed in the 12th sub-pixel (SPX12) and the third vertical bridge line (BRL3_V) disposed in the 13th sub-pixel (SPX13) may be disposed to be spaced apart from each other with a dummy electrode (DME) therebetween. According to an embodiment, the second vertical bridge line (BRL2_V) disposed in the 12th sub-pixel (SPX12) may have a shape substantially the same as or similar to the third vertical bridge line (BRL3_V) as illustrated in FIG. 20, but is not limited thereto. According to an embodiment, as illustrated in FIG. 21, the second vertical bridge line (BRL2_V) may have a different shape from the third vertical bridge line (BRL3_V).

[0307] The second and third vertical bridge lines (BRL2_V, BRL3_V) may be formed of a sixth conductive layer (CL6). The third vertical bridge line (BRL3_V) may be electrically connected to the third connection pattern (CNP3) of the thirteenth sub-pixel (SPX13) through a second via hole (VIH2) penetrating the eighth insulating layer (see "INS8" in FIG. 16).

[0308] A first horizontal bridge line (BRL1_H) may be electrically connected to a third vertical bridge line (BRL3_V) via a dummy electrode (DME) (or an additional conductive pattern (ACP)). The third vertical bridge line (BRL3_V) may be electrically connected to a corresponding fan-out line disposed in a fan-out area (see "FTA" in FIG. 2) to supply a predetermined signal transmitted from the fan-out line to the first horizontal bridge line (BRL1_H). The first horizontal bridge line (BRL1_H) may be electrically connected to a corresponding data line located in a first area (see "DA1" in FIG. 2) of a display area (DA) to supply the predetermined signal (for example, a data signal) to the data line.

[0309] In one embodiment, the 12th sub-pixel (SPX12) of the first sub-pixel unit (SPU1) may not be provided with the third connection pattern (CNP3) (or an additional conductive pattern). That is, the third connection pattern (CNP3) may be omitted in the 12th sub-pixel (SPX12). In this case, the second via hole (VIH2) for electrically connecting the second vertical bridge line (BRL2_V) disposed in the 12th sub-pixel (SPX12) and the third connection pattern (CNP3) may be omitted, thereby reducing design constraints on the position of the second via hole (VIH2). Accordingly, the effective space in the 12th sub-pixel (SPX12) may be further secured.

[0310] FIG. 22 is a schematic plan view showing sub-pixels arranged in first and second pixel rows (R1, R2) located in one area of ​​a display area (DA) of a display device according to one embodiment.

[0311] In Fig. 22, in order to avoid redundant explanation, the differences from the above-described embodiment will be explained.

[0312] Referring to FIG. 22, in the first pixel row (R1), the 11th sub-pixel (SPX11) and the 12th sub-pixel (SPX12) may constitute a first sub-pixel unit (see "SPU1" in FIG. 19), and the 13th sub-pixel (SPX13) and the 14th sub-pixel (SPX14) may constitute a second sub-pixel unit (see "SPU2" in FIG. 19). In the second pixel row (R2), the 21st sub-pixel (SPX21) and the 22nd sub-pixel (SPX22) may constitute a first sub-pixel unit (SPU1), and the 23rd sub-pixel (SPX23) and the 24th sub-pixel (SPX24) may constitute a second sub-pixel unit (SPU2).

[0313] In each of the first and second pixel rows (R1, R2), a dummy electrode (DME) may be positioned at a boundary between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2). For example, in the first pixel row (R1), the first dummy electrode (DME1) may be positioned at a boundary between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) (or a boundary between the 12th sub-pixel (SPX12) and the 13th sub-pixel (SPX13)). In the second pixel row (R2), the second dummy electrode (DME2) may be positioned at a boundary between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) (or a boundary between the 22nd sub-pixel (SPX22) and the 23rd sub-pixel (SPX23)).

[0314] The first dummy electrode (DME1) can be electrically connected to the first horizontal bridge line (BRL1_H) (or the 13th wiring (WL13)) through an 11th via hole (VIH11) at the boundary between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) of the first pixel row (R1) (or the boundary between the 12th sub-pixel (SPX12) and the 13th sub-pixel (SPX13)). The second dummy electrode (DME2) can be electrically connected to the second horizontal bridge line (BRL2_H) (or the 13th wiring (WL13)) through one twelfth via hole (VIH12) at the boundary between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) of the second pixel row (R2) (or the boundary between the 22nd sub-pixel (SPX22) and the 23rd sub-pixel (SPX23)).

[0315] The first dummy electrode (DME1) may be formed integrally with the third connection pattern (CNP3) (or the second additional conductive pattern (ACP2)) of the 13th sub-pixel (SPX13). The third connection pattern (CNP3) (or the second additional conductive pattern (ACP2)) may be electrically connected to the third vertical bridge line (BRL3_V) through the 22nd via hole (VIH22). As the first dummy electrode (DME1) is electrically connected to the first horizontal bridge line (BRL1_H) through the 11th via hole (VIH11), the first horizontal bridge line (BRL1_H) may be electrically connected to the third vertical bridge line (BRL3_V).

[0316] The second dummy electrode (DME2) may be formed integrally with the third connection pattern (CNP3) (or the first additional conductive pattern (ACP1)) of the 22nd sub-pixel (SPX22). The third connection pattern (CNP3) (or the first additional conductive pattern (ACP1)) may be electrically connected to the second vertical bridge line (BRL2_V) through the 21st via hole (VIH21). As the second dummy electrode (DME2) is electrically connected to the second horizontal bridge line (BRL2_H) through the 12th via hole (VIH12), the second horizontal bridge line (BRL2_H) may be electrically connected to the second vertical bridge line (BRL2_V).

[0317] In an odd-numbered pixel row (e.g., a first pixel row R1) of a display area (DA), two vertical bridge lines, for example, a second vertical bridge line (BRL2_V) and a third vertical bridge line (BRL3_V), located at a boundary between a first sub-pixel unit (SPU1) and a second sub-pixel unit (SPU2), may be electrically connected to a first dummy electrode (DME1) through a 22nd via hole (VIH22) (or a second via hole (VIH2)). Among the second vertical bridge line (BRL2_V) and the third vertical bridge line (BRL3_V) located at the boundary between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) in the even pixel row (for example, the second pixel row (R2)) of the display area (DA), the second vertical bridge line (BRL2_V) may be electrically connected to the second dummy electrode (DME2) through the 21st via hole (VIH21) (or the second via hole (VIH2)).

[0318] In one embodiment, a separate conductive pattern corresponding to the third connection pattern (CNP3) (or the second additional conductive pattern (ACP2)) of the 13th sub-pixel (SPX13) may not be arranged in the 12th sub-pixel (SPX12) arranged in the first pixel row (R1). In this case, one second via hole for electrically connecting the second vertical bridge line (BRL2_V) and the conductive pattern in the first pixel row (R1) may be omitted. Accordingly, design constraints on the position of the one second via hole are reduced, and thus, more effective space in the 12th sub-pixel (SPX12) can be secured.

[0319] In one embodiment, a separate conductive pattern corresponding to the third connection pattern (CNP3) (or the first additional conductive pattern (ACP1)) of the 22nd sub-pixel (SPX22) may not be arranged in the 23rd sub-pixel (SPX23) arranged in the 2nd pixel row (R2). In this case, one second via hole for electrically connecting the third vertical bridge line (BRL3_V) and the conductive pattern in the 2nd pixel row (R2) may be omitted. Accordingly, design constraints on the position of the one second via hole are reduced, and thus, more effective space in the 23rd sub-pixel (SPX23) can be secured.

[0320] FIG. 23 is a schematic drawing showing the positions of a first via hole (VIH1) and a second via hole (VIH2) in one area of ​​a display area (DA) of a display device according to one embodiment.

[0321] In Fig. 23, for convenience of explanation, only some signal wirings in the sub-pixels arranged in each of the first to fourth pixel rows (R1 to R4) are illustrated.

[0322] In Fig. 23, in order to avoid redundant explanation, the differences from the above-described embodiment will be explained.

[0323] Referring to FIG. 23, a first via hole (VIH1) may be positioned at a boundary portion between a first sub-pixel unit (see "SPU1" of FIG. 19) and a second sub-pixel unit (see "SPU2" of FIG. 19) in each of the first to fourth pixel rows (R1 to R4). The first via hole (VIH1) may be formed by removing a portion of an insulating layer, for example, a seventh insulating layer (see "INS7" of FIG. 16), located between a horizontal bridge line and a dummy electrode arranged in each pixel row, and may be a connection point that electrically connects the horizontal bridge line and the dummy electrode.

[0324] In each of the first to fourth pixel rows (R1 to R4), one second via hole (VIH2) may be arranged in a diagonal direction of the first via hole (VIH1). For example, one second via hole (VIH2) may be arranged in a right diagonal direction of the first via hole (VIH1) in odd-numbered pixel rows (e.g., each of the first and third pixel rows (R1, R3)). In addition, one second via hole (VIH2) may be arranged in a left diagonal direction of the first via hole (VIH1) in even-numbered pixel rows (e.g., each of the second and fourth pixel rows (R2, R4)). Accordingly, the second via hole (VIH2) located in the odd-numbered pixel rows and the second via hole (VIH2) located in the even-numbered pixel rows may not be located in the same column (or on the same line) but in different columns. In addition, the second via hole (VIH2) of the first pixel row (R1), which is an odd pixel row, and the second via hole (VIH2) of the third pixel row (R3) may be located in the same column (or on the same line), and the second via hole (VIH2) of the second pixel row (R2), which is an even pixel row, and the second via hole (VIH2) of the fourth pixel row (R4) may be located in the same column (or on the same line).

[0325] The first via holes (VIH1) located in the first pixel row (R1), the first via holes (VIH1) located in the second pixel row (R2), the first via holes (VIH1) located in the third pixel row (R3), and the first via holes (VIH1) arranged in the fourth pixel row (R4) may be located in the same column (or on the same line) in the second direction (DR2). Accordingly, the first via holes (VIH1) may be concentrated only in a specific area (for example, a boundary portion between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) of each of the first to fourth pixel rows (R1 to R4)) in the display area (DA). In this case, design constraints for electrical connection of the horizontal bridge line and the vertical bridge line in each pixel row may be reduced, and effective space may be secured for some sub-pixels included in each pixel row.

[0326] In the above-described embodiments, the vertical bridge lines are described as being arranged adjacent to the edges of the corresponding sub-pixel units, but this is not limited thereto. Depending on the embodiment, the data lines may also be arranged adjacent to the edges of the corresponding sub-pixel units. This will be described with reference to FIGS. 24 to 26.

[0327] FIG. 24 is a schematic plan view showing sub-pixels arranged in first and second pixel rows (R1, R2) located in one area of ​​a display area (DA) of a display device according to one embodiment, FIG. 25 is a schematic enlarged view showing part EA4 of FIG. 24, and FIG. 26 is a schematic cross-sectional view taken along lines Ⅱ to Ⅱ' of FIG. 25.

[0328] For convenience of explanation, in FIGS. 24 to 26, only the configurations included in the fourth conductive layer (CL4), the fifth conductive layer (CL5), and the sixth conductive layer (CL6) in the sub-pixels arranged in the same pixel row (e.g., the first pixel row) are illustrated.

[0329] In Figs. 24 to 26, in order to avoid redundant explanation, differences from the above-described embodiment will be mainly explained.

[0330] Referring to FIGS. 24 to 26, in the first pixel row (R1), the 11th sub-pixel (SPX11) and the 12th sub-pixel (SPX12) may constitute a first sub-pixel unit (see "SPU1" in FIG. 19), and the 13th sub-pixel (SPX13) and the 14th sub-pixel (SPX14) may constitute a second sub-pixel unit (see "SPU2" in FIG. 19). In the second pixel row (R2), the 21st sub-pixel (SPX21) and the 22nd sub-pixel (SPX22) may constitute a first sub-pixel unit (SPU1), and the 23rd sub-pixel (SPX23) and the 24th sub-pixel (SPX24) may constitute a second sub-pixel unit (SPU2).

[0331] In each of the first and second pixel rows (R1, R2), a dummy electrode (DME) may be positioned at a boundary between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2). For example, in the first pixel row (R1), the first dummy electrode (DME1) may be positioned at a boundary between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) (or a boundary between the 12th sub-pixel (SPX12) and the 13th sub-pixel (SPX13)). In the second pixel row (R2), the second dummy electrode (DME2) may be positioned at a boundary between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) (or a boundary between the 22nd sub-pixel (SPX22) and the 23rd sub-pixel (SPX23)).

[0332] The first dummy electrode (DME1) and the second dummy electrode (DME2) may be formed of a fifth conductive layer (CL5). The first dummy electrode (DME1) may be electrically connected to the first horizontal bridge line (BRL1_H) (or the 13th wiring (WL13)) through an 11th via hole (VIH11) at a boundary between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) of the first pixel row (R1) (or a boundary between the 12th sub-pixel (SPX12) and the 13th sub-pixel (SPX13)). The second dummy electrode (DME2) can be electrically connected to the second horizontal bridge line (BRL2_H) (or the 13th wiring (WL13)) through one twelfth via hole (VIH12) at the boundary between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) of the second pixel row (R2) (or the boundary between the 22nd sub-pixel (SPX22) and the 23rd sub-pixel (SPX23)).

[0333] In each of the first and second sub-pixel units (SPU1, SPU2), the data line may be positioned adjacent to an edge of the corresponding sub-pixel unit. For example, in each of the first and second pixel rows (R1, R2), the first data line (D1) in the first sub-pixel unit (SPU1) may be positioned adjacent to a right edge of the first sub-pixel unit (SPU1), and the second data line (D2) in the first sub-pixel unit (SPU1) may be positioned adjacent to a left edge of the second sub-pixel unit (SPU1). In each of the first and second pixel rows (R1, R2), the third data line (D3) in the second sub-pixel unit (SPU2) may be positioned adjacent to the rightmost side of the second sub-pixel unit (SPU2), and the fourth data line (D4) in the second sub-pixel unit (SPU2) may be positioned adjacent to the leftmost side of the second sub-pixel unit (SPU2).

[0334] In one embodiment, in each of the first and second sub-pixel units (SPU1, SPU2), the vertical bridge line may be positioned further away from the edge of the corresponding sub-pixel unit than the data line. For example, the first vertical bridge line (BRL1_V) may be positioned further away from the edge of the first sub-pixel unit (SPU1) than the first data line (D1), and the second vertical bridge line (BRL2_V) may be positioned further away from the edge of the first sub-pixel unit (SPU1) than the second data line (D2). The third vertical bridge line (BRL3_V) may be positioned further away from the edge of the second sub-pixel unit (SPU2) than the third data line (D3), and the fourth vertical bridge line (BRL4_V) may be positioned further away from the edge of the second sub-pixel unit (SPU2) than the fourth data line (D4). That is, the first vertical bridge line (BRL1_V) may be located inward in the first sub-pixel unit (SPU1) relative to the first data line (D1), and the second vertical bridge line (BRL2_V) may be located inward in the first sub-pixel unit (SPU1) relative to the second data line (D2). The third vertical bridge line (BRL3_V) may be located inward in the second sub-pixel unit (SPU2) relative to the third data line (D3), and the fourth vertical bridge line (BRL4_V) may be located inward in the second sub-pixel unit (SPU2) relative to the fourth data line (D4).

[0335] In one embodiment, when viewed on a plane, the second data line (D2) and the third data line (D3) may be spaced apart from each other with a dummy electrode (DME) therebetween.

[0336] When viewed in a plan view, the second data line (D2) is located on the left side of each of the first and second dummy electrodes (DME1, DME2), and may be located on the inner side of the second vertical bridge line (BRL2_V) with respect to the first and second dummy electrodes (DME1, DME2). That is, when viewed in a plan view, the second data line (D2) may be located closer to each of the first and second dummy electrodes (DME1, DME2) than to the second vertical bridge line (BRL2_V).

[0337] When viewed in a plan view, the third data line (D3) is located on the right side of each of the first and second dummy electrodes (DME1, DME2), and may be located on the inner side of the third vertical bridge line (BRL3_V) with respect to the first and second dummy electrodes (DME1, DME2). That is, when viewed in a plan view, the third data line (D3) may be located closer to each of the first and second dummy electrodes (DME1, DME2) than to the third vertical bridge line (BRL3_V).

[0338] The spacing between the second data line (D2) and the third data line (D3) may be smaller than the spacing between the second vertical bridge line (BRL2_V) and the third vertical bridge line (BRL3_V).

[0339] In one embodiment, the first dummy electrode (DME1) may be formed integrally with the second additional conductive pattern (ACP2) disposed in the 13th sub-pixel (SPX13). The second additional conductive pattern (ACP2) may be electrically connected to the third vertical bridge line (BRL3_V) through the 22nd via hole (VIH22). As the first dummy electrode (DME1) is electrically connected to the first horizontal bridge line (BRL1_H) through the 11th via hole (VIH11), the first horizontal bridge line (BRL1_H) may be electrically connected to the third vertical bridge line (BRL3_V).

[0340] In one embodiment, the second dummy electrode (DME2) may be formed integrally with the first additional conductive pattern (ACP1) disposed in the 22nd sub-pixel (SPX22). The first additional conductive pattern (ACP1) may be electrically connected to the second vertical bridge line (BRL2_V) through the 21st via hole (VIH21). As the second dummy electrode (DME2) is electrically connected to the second horizontal bridge line (BRL2_H) through the 12th via hole (VIH12), the second horizontal bridge line (BRL2_H) may be electrically connected to the second vertical bridge line (BRL2_V).

[0341] FIG. 27 is a block diagram showing an electronic device according to one embodiment. FIG. 28 is a schematic diagram showing an example of a smartphone that can be implemented using the electronic device of FIG. 27. FIG. 29 is a schematic diagram showing an example of a tablet computer that can be implemented using the electronic device of FIG. 27.

[0342] Referring to FIGS. 27 to 29, the electronic device (1000) may include a processor (1010), a memory device (1020), a storage device (1030), an input / output device (1040), a power supply device (1050), and a display device (1060). The display device (1060) may be the display device (DD) of FIGS. 1 and 2 . The electronic device (1000) may additionally include various ports for communication with a video card, a sound card, a memory card, a USB device, or other systems. In one embodiment, as illustrated in FIG. 28 , the electronic device (1000) may be implemented as a smartphone. In one embodiment, as illustrated in FIG. 29 , the electronic device (1000) may be implemented as a tablet computer. However, this is merely exemplary, and the electronic device (1000) is not limited thereto. For example, the electronic device (1000) may be implemented as a mobile phone, a video phone, a smart pad, a smart watch, a vehicle navigation device, a computer monitor, a laptop computer, a head-mounted display device, etc.

[0343] The processor (1010) can perform various tasks and calculations. In one embodiment, the processor (1010) may include a microprocessor, a central processing unit (CPU), an application processor, etc. The processor (1010) may be connected to other components via an address bus, a control bus, a data bus, etc. In one embodiment, the processor (1010) may be connected to an expansion bus, such as a peripheral interconnect (PCI) bus.

[0344] The memory device (1020) may store data necessary to perform the operation of the electronic device (1000). For example, the memory device (1020) may include a non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, and / or a volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, and the like.

[0345] The storage device (1030) may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc.

[0346] The input / output device (1040) may include user input devices such as a keyboard, keypad, touchpad, touchscreen, mouse, etc., and output devices such as speakers, printers, etc. In one embodiment, a display device (1060) may be included in the input / output device (1040).

[0347] The power supply unit (1050) can supply power required for the operation of the electronic device (1000). For example, the power supply unit (1050) can be a power management integrated circuit (PMIC).

[0348] The display device (1060) can display an image corresponding to visual information of the electronic device (1000). Here, the display device (1060) may be an organic light emitting diode (OLED) display device or a quantum dot light emitting display device, but is not necessarily limited thereto. The display device (1060) can be connected to other components via a bus or other communication link.

[0349] Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art or having ordinary knowledge in the art that the present invention can be variously modified and changed within a scope that does not depart from the technical scope of the present invention as set forth in the claims to be described below.

[0350] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the patent claims and their equivalents.

Claims

1. A first sub-pixel and a second sub-pixel arranged along a first direction and constituting a first sub-pixel unit; A third sub-pixel and a fourth sub-pixel arranged along the first direction and constituting a second sub-pixel unit adjacent to the first sub-pixel unit; Pixel circuits of each of the first to fourth sub-pixels; A vertical bridge line extending in the second direction and arranged in each of the first and second sub-pixel units; A data line extending in the second direction and spaced apart from the vertical bridge line; a horizontal bridge line extending along the first direction; and A dummy electrode is located at a boundary portion between the first sub-pixel unit and the second sub-pixel unit and is electrically connected to the horizontal bridge line, A display device, wherein the dummy electrode is electrically connected to at least one of the first and second sub-pixel units.

2. In paragraph 1, A display device, wherein when viewed on a plane, the vertical bridge line is positioned closer to the edge of each of the first and second sub-pixel units than the data line.

3. In paragraph 2, The above vertical bridge lines include a first vertical bridge line, a second vertical bridge line, a third vertical bridge line, and a fourth vertical bridge line arranged along the first direction, The first vertical bridge line overlaps the pixel circuit of the first sub-pixel, The second vertical bridge line overlaps the pixel circuit of the second sub-pixel, The third vertical bridge line overlaps the pixel circuit of the third sub-pixel, The fourth vertical bridge line overlaps the pixel circuit of the fourth sub-pixel, A display device, wherein when viewed on a plane, the dummy electrode is positioned between the second vertical bridge line and the third vertical bridge line.

4. In paragraph 3, The data line includes a first data line spaced apart from the first vertical bridge line, a second data line spaced apart from the second vertical bridge line, a third data line spaced apart from the third vertical bridge line, and a fourth data line spaced apart from the fourth vertical bridge line, A display device, wherein when viewed on a plane, the second vertical bridge line is closer to the dummy electrode than the second data line, and the third vertical bridge line is closer to the dummy electrode than the third data line.

5. In paragraph 4, A first via layer including a first via hole disposed on the horizontal bridge line and exposing an area of ​​the horizontal bridge line; and Further comprising a second via layer including a second via hole disposed on the dummy electrode and exposing an area of ​​the dummy electrode, The first to fourth vertical bridge lines are arranged on the second via layer, and the dummy electrode is arranged between the first via layer and the second via layer. A display device, wherein the dummy electrode is electrically connected to the horizontal bridge line through the first via hole.

6. In paragraph 5, One end of the above dummy electrode is electrically connected to the horizontal bridge line through the first via hole, A display device, wherein the other end of the dummy electrode is electrically connected to at least one of the second vertical bridge line and the third vertical bridge line through the second via hole.

7. In paragraph 6, A first additional conductive pattern disposed below the second vertical bridge line between the first via layer and the second via layer of the second sub-pixel and electrically connected to the second vertical bridge line; and Further comprising a second additional conductive pattern disposed below the third vertical bridge line between the first via layer and the second via layer of the third sub-pixel and electrically connected to the third vertical bridge line; The first and second additional challenge patterns are arranged on the same layer as the dummy electrode, A display device, wherein the dummy electrode is formed integrally with at least one of the first and second additional conductive patterns.

8. In paragraph 6, Further comprising an additional conductive pattern disposed below at least one of the second and third vertical bridge lines between the first via layer and the second via layer, A display device in which the above additional challenge pattern is arranged on the same layer as the dummy electrode and is formed integrally with the dummy electrode.

9. In paragraph 1, A display device, wherein when viewed on a plane, the data line is positioned closer to the edge of each of the first and second sub-pixel units than the vertical bridge line.

10. A substrate including a display area including a first area and a second area, and a non-display area surrounding at least one side of the display area; A first sub-pixel and a second sub-pixel arranged along a first direction in each of the first and second pixel rows of the substrate, and forming a first sub-pixel unit; A third sub-pixel and a fourth sub-pixel are arranged along the first direction in each of the first and second pixel rows of the substrate, and constitute a second sub-pixel unit adjacent to the first sub-pixel unit; A pixel circuit provided in each of the first to fourth sub-pixels; A vertical bridge line extending in the second direction and arranged in each of the first and second sub-pixel units; A data line extending in the second direction and spaced apart from the vertical bridge line; A first horizontal bridge line extending along the first direction in the first pixel row; A second horizontal bridge line extending along the first direction in the second pixel row; A first dummy electrode located at a boundary portion between the first sub-pixel unit and the second sub-pixel unit in the first pixel row and electrically connected to the first horizontal bridge line; and A second dummy electrode is located at a boundary portion between the first sub-pixel unit and the second sub-pixel unit in the second pixel row and is electrically connected to the second horizontal bridge line. A display device, wherein when viewed on a plane, the first dummy electrode and the second dummy electrode are located in the same column.

11. In paragraph 10, A display device, wherein when viewed on a plane, the vertical bridge line is positioned closer to the edge of each of the first and second sub-pixel units than the data line.

12. In paragraph 11, The vertical bridge line includes a first vertical bridge line, a second vertical bridge line, a third vertical bridge line, and a fourth vertical bridge line arranged along the first direction in each of the first and second pixel rows, The first vertical bridge line overlaps the pixel circuit of the first sub-pixel, The second vertical bridge line overlaps the pixel circuit of the second sub-pixel, The third vertical bridge line overlaps the pixel circuit of the third sub-pixel, The fourth vertical bridge line overlaps the pixel circuit of the fourth sub-pixel, A display device, wherein when viewed on a plane, each of the first and second dummy electrodes is positioned between the second vertical bridge line and the third vertical bridge line.

13. In paragraph 12, The data line includes a first data line spaced apart from the first vertical bridge line, a second data line spaced apart from the second vertical bridge line, a third data line spaced apart from the third vertical bridge line, and a fourth data line spaced apart from the fourth vertical bridge line, A display device, wherein, when viewed on a plane, the second vertical bridge line is positioned closer to the first and second dummy electrodes than the second data line, and the third bridge line is positioned closer to the first and second dummy electrodes than the third data line.

14. In paragraph 12, The first dummy electrode is electrically connected to at least one of the second and third vertical bridge lines, A display device, wherein the second dummy electrode is electrically connected to the remaining of the second and third vertical bridge lines.

15. In paragraph 14, A first additional conductive pattern overlapping an area of ​​the second vertical bridge line in each of the second sub-pixels of the first and second pixel rows; and Further comprising a second additional conductive pattern overlapping an area of ​​the third vertical bridge line in the third sub-pixel of each of the first and second pixel rows, The first and second additional challenge patterns are arranged on the same layer as the first and second dummy electrodes, The above first dummy electrode is formed integrally with the second additional conductive pattern, A display device wherein the second dummy electrode is formed integrally with the first additional conductive pattern.

16. In paragraph 15, A first via layer disposed on the first and second horizontal bridge lines, the first via layer including an eleventh via hole exposing an area of ​​the first horizontal bridge line and a twelfth via hole exposing an area of ​​the second horizontal bridge line; and Further comprising a second via layer disposed on the first and second additional conductive patterns, the second via layer including a twenty-first via hole exposing an area of ​​the first additional conductive pattern and a twenty-second via hole exposing an area of ​​the second additional conductive pattern, The first to fourth vertical bridge lines are arranged on the second via layer, A display device, wherein the first and second dummy electrodes and the first and second additional conductive patterns are disposed between the first via layer and the second via layer.

17. In paragraph 16, The first dummy electrode is electrically connected to the first horizontal bridge line through the 11th via hole, and the second additional conductive pattern formed integrally with the first dummy electrode is electrically connected to the third vertical bridge line through the 22nd via hole. A display device, wherein the second dummy electrode is electrically connected to the second horizontal bridge line through the 12th via hole, and the first additional conductive pattern formed integrally with the second dummy electrode is electrically connected to the second vertical bridge line through the 21st via hole.

18. In paragraph 17, The above 11th via hole and the above 12th via hole are located at the boundary portion between the first sub-pixel unit and the second sub-pixel unit, A display device, wherein when viewed on a plane, the 11th via hole and the 12th via hole are located in the same row.

19. In paragraph 14, A second additional conductive pattern positioned below the third vertical bridge line in the first pixel row and overlapping an area of ​​the third vertical bridge line; and Further comprising a first additional conductive pattern positioned below the second vertical bridge line in the second pixel row and overlapping an area of ​​the second vertical bridge line, The above first dummy electrode is formed integrally with the second additional conductive pattern, A display device wherein the second dummy electrode is formed integrally with the first additional conductive pattern.

20. In paragraph 10, A display device, wherein when viewed on a plane, the data line is closer to the edge of each of the first and second sub-pixel units than the vertical bridge line.

21. A processor configured to provide input image data to a display device; and A display device configured to display an image based on the above input image data, The above display device, A first sub-pixel and a second sub-pixel arranged in a first direction and forming a first sub-pixel unit; A third sub-pixel and a fourth sub-pixel constituting a second sub-pixel unit arranged in the first direction and positioned adjacent to the first sub-pixel unit; A pixel circuit provided in each of the first to fourth sub-pixels; A vertical bridge line extending in the second direction and arranged in each of the first and second sub-pixel units; A data line extending in the second direction and arranged spaced apart from the vertical bridge line; a horizontal bridge line extending along the first direction; and A dummy electrode is located at a boundary portion between the first sub-pixel unit and the second sub-pixel unit and is electrically connected to the horizontal bridge line, An electronic device wherein the dummy electrode is electrically connected to at least one of the first and second sub-pixel units.

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