Semiconductor device and manufacturing method therefor, and electronic device

Abstract

The present application relates to the technical field of semiconductors, and provides a semiconductor device and a manufacturing method therefor, and an electronic device. The method comprises: forming a stack structure (12) on one side of a substrate (11); patterning to form a plurality of bit lines (13) arranged in an array; patterning to form a plurality of first trenches (14) arranged in an array; forming a second trench (18) in the stack structure (12) between two adjacent columns of bit lines (13); etching back the sidewall of the second trench (18) to form a plurality of second recesses (19); and sequentially depositing a semiconductor layer (23), a gate dielectric layer (24), and a gate (25) in each second recess (19).

Description

Semiconductor device, manufacturing method thereof, and electronic device

[0001] Related applications

[0002] The present application claims priority to the Chinese patent application No. 2024107331935, filed on June 6, 2024, and entitled "Semiconductor device, manufacturing method thereof, and electronic device", the contents of which are hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of semiconductor devices, in particular, the present application relates to a semiconductor device, a manufacturing method thereof, and an electronic device. BACKGROUND

[0004] With the development of integrated circuit technology, the critical dimension of semiconductor devices is becoming smaller and smaller, and the types and number of device units contained in a single chip are increasing, so that any slight difference in process production can affect the performance of the device.

[0005] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet people's current product needs.

[0006] SUMMARY

[0007] According to various embodiments of the present application, a semiconductor device, a manufacturing method thereof, and an electronic device are provided, which can effectively improve the performance of the semiconductor device.

[0008] In a first aspect, the embodiments of the present application provide a manufacturing method of a semiconductor device, comprising:

[0009] forming a stack structure on one side of a substrate, the stack structure comprising a plurality of first dielectric layers and a plurality of first sacrificial layers alternately stacked;

[0010] forming a plurality of bit lines arranged in an array by patterning, the bit lines extending along a third direction perpendicular to the substrate;

[0011] forming a plurality of first trenches arranged in an array by patterning; along a first direction, at least two of the first trenches are arranged in the same column and spaced apart from at least two of the bit lines; etching back the plurality of first sacrificial layers exposed by the sidewalls of the first trenches to form a corresponding plurality of first recesses; depositing a first capacitor electrode in the first recesses; forming a first isolation layer filling the first trenches;

[0012] A second trench extending along the first direction is formed at the stack structure between two adjacent bit lines; all the first sacrificial layers exposed by the sidewall of the second trench are etched back to form a plurality of second recesses; and a semiconductor layer, a gate dielectric layer and a gate electrode are sequentially deposited in the second recesses.

[0013] In some embodiments, after forming the stack structure on one side of the substrate and before patterning the plurality of bit lines arranged in an array, the method further comprises:

[0014] The stack structure is patterned to form two third trenches on both sides of the stack structure along a second direction, the third trenches extending along the first direction, the first direction intersecting the second direction and both being parallel to the substrate.

[0015] A second isolation layer is deposited in the third trenches.

[0016] The stack structure is patterned to form a plurality of fourth trenches arranged in an array, at least two of the fourth trenches being spaced apart along the first direction, the fourth trenches extending along a third direction.

[0017] A second dielectric layer is deposited in the fourth trenches.

[0018] In some embodiments, patterning the plurality of bit lines arranged in an array comprises:

[0019] The stack structure is patterned to form a plurality of first vias arranged in an array.

[0020] A bit line filling the first via is formed.

[0021] In some embodiments, after forming the plurality of first vias arranged in an array and before forming the bit line filling the first via, the method further comprises:

[0022] The plurality of layers of the first sacrificial layers exposed by the sidewall of the first via are etched back to form a plurality of third recesses; and a plurality of first source / drain electrodes are synchronously deposited in the plurality of third recesses.

[0023] In some embodiments, patterning the plurality of first trenches arranged in an array comprises:

[0024] The stack structure is patterned to form a plurality of first trenches arranged in an array.

[0025] After forming the plurality of first recesses and before depositing a first capacitor electrode in the first recess, the method further comprises:

[0026] A second source / drain electrode is deposited in the first recess.

[0027] In some embodiments, after sequentially depositing a semiconductor layer, a gate dielectric layer and a gate electrode in the second recess, the method further comprises:

[0028] depositing a third isolation layer in the second trench;

[0029] removing the first isolation layer in the first trench;

[0030] sequentially depositing a ferroelectric layer and a second capacitor electrode in the first trench.

[0031] In some embodiments, patterning the second isolation layer to form a plurality of first vias arranged in an array comprises:

[0032] patterning the second isolation layer to form a plurality of first vias arranged in an array.

[0033] etching back the first sacrificial layer exposed by the sidewall of the first via to form a corresponding plurality of third recesses; and synchronously depositing a plurality of first source / drain electrodes in the plurality of third recesses.

[0034] forming a bit line filling the first via and connected to the plurality of first source / drain electrodes.

[0035] In some embodiments, after forming the bit line filling the first via, and before patterning a plurality of first trenches arranged in an array, the method further comprises:

[0036] depositing a fourth dielectric layer away from the substrate on a side of the stack structure, the second isolation layer, the bit line, and the second dielectric layer;

[0037] and patterning the second isolation layer to form a plurality of first trenches arranged in an array.

[0038] patterning the second isolation layer to form a plurality of first trenches arranged in an array.

[0039] In some embodiments, after forming the corresponding plurality of first recesses, and before forming a first isolation layer filling the first trench, the method further comprises:

[0040] depositing a first capacitor electrode on sidewalls of the first trench and the first recess;

[0041] and, after forming the first isolation layer filling the first trench, and before opening a second trench extending in the first direction at the stack structure between two adjacent columns of the bit line, the method further comprises:

[0042] removing the first capacitor electrode on the sidewall of the first trench; and removing the first isolation layer in the first recess.

[0043] depositing a ferroelectric layer covering the first capacitor electrode in the first recess;

[0044] depositing a protection layer on the fourth dielectric layer, the ferroelectric layer and the second capacitor electrode away from the substrate.

[0045] In some embodiments, after sequentially depositing a semiconductor layer, a gate dielectric layer and a gate electrode in the second recess, the method further comprises:

[0046] removing the semiconductor layer along the second direction in the second recess to obtain a fourth recess;

[0047] depositing a third isolation layer in the second trench and the fourth recess.

[0048] In some embodiments, after sequentially depositing a ferroelectric layer and a second capacitor electrode in the first trench, or after depositing a third isolation layer in the second trench and the fourth recess, the method further comprises:

[0049] opening a fifth trench extending along a third direction at the second dielectric layer between any two adjacent memory cell stack regions along the first direction;

[0050] etching back to remove the semiconductor layer exposed by the sidewall of the fifth trench;

[0051] depositing a third dielectric layer in the fifth trench.

[0052] In some embodiments, the material of the gate electrode comprises at least one of metal, metal alloy, metal nitride, metal-semiconductor compound and conductive doped semiconductor.

[0053] The material of the bit line comprises at least one of metal, metal alloy, metal nitride, metal silicide, metal carbide and conductive doped semiconductor material.

[0054] The material of the first dielectric layer, the second dielectric layer and the third dielectric layer each comprises at least one of oxide or nitride; the oxide comprises SiO2, F-doped porous SiO2, C-doped porous SiO2, HfOx.

[0055] The material of the ferroelectric layer comprises at least one of hafnium-based oxide, lead zirconate titanate and strontium bismuth tantalate.

[0056] In a second aspect, embodiments of the present application provide a semiconductor device, comprising:

[0057] a substrate;

[0058] a plurality of layers of first dielectric layers and a plurality of layers of transistors are alternately stacked on one side of the substrate; the transistors include a semiconductor layer, a gate dielectric layer and a gate electrode, all extending along a first direction, and a first source / drain and a second source / drain, both located on one side of the semiconductor layer along a second direction; the first direction intersects the second direction and both are parallel to the substrate;

[0059] a plurality of bit lines extending along a third direction perpendicular to the substrate, and connected to the first source / drain of the plurality of layers of transistors in the same memory cell stack region;

[0060] a plurality of layers of first capacitor electrodes, each connected to a plurality of the second source / drain.

[0061] In some embodiments, along the first direction, at least two of the bit lines and at least two of the plurality of layers of first capacitor electrodes are located in the same column and arranged at intervals.

[0062] In some embodiments, the semiconductor device further includes:

[0063] a plurality of layers of second capacitor electrodes, a central axis of the second capacitor electrodes being perpendicular to the substrate;

[0064] a plurality of layers of ferroelectric layers, the ferroelectric layers surrounding the periphery of the second capacitor electrodes, and the first capacitor electrodes surrounding the periphery of the ferroelectric layers.

[0065] In some embodiments, the semiconductor device further includes:

[0066] a plurality of layers of second capacitor electrodes, an extension direction of the second capacitor electrodes being parallel to the substrate;

[0067] a plurality of layers of ferroelectric layers, the ferroelectric layers surrounding the periphery of the second capacitor electrodes, and the first capacitor electrodes surrounding the periphery of the ferroelectric layers.

[0068] In some embodiments, in one of the plurality of layers of transistors in the memory cell stack region, along the second direction, a relationship between two adjacent transistors is selected from the group consisting of: the semiconductor layers of the two adjacent transistors being close to each other, and the semiconductor layer of one transistor being close to the bit line of the other adjacent transistor.

[0069] In some embodiments, the extension direction of the bit line is perpendicular to the extension direction of the gate electrode.

[0070] In a third aspect, embodiments of the present application provide an electronic device, including the semiconductor device described above, or a semiconductor device formed by the manufacturing method described above.

[0071] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the application will be apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF DRAWINGS

[0072] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only part of the embodiments of the present application, and all other drawings obtained by those of ordinary skill in the art without creative effort based on the disclosed drawings also belong to the protection scope of the present application.

[0073] Fig. 1 is a flow diagram of a semiconductor device manufacturing method according to an embodiment of the present application;

[0074] Figs. 2a-42d are schematic diagrams of intermediate structures obtained in a semiconductor device manufacturing method according to an embodiment of the present application.

[0075] Reference signs: 11-substrate; 12-stacked structure; 121-first dielectric layer; 122-first sacrificial layer; 13-bit line; 14-first trench; 15-first recess; 16-first capacitor electrode; 17-first isolation layer; 18-second trench; 19-second recess; 2-transistor; 21-first source / drain electrode; 22-second source / drain electrode; 23-semiconductor layer; 24-gate dielectric layer; 25-gate electrode; 31-third trench; 32-second isolation layer; 33-fourth trench; 34-second dielectric layer; 35-first via hole; 36-third recess; 37-protection layer; 38-third isolation layer; 39-ferroelectric layer; 41-second capacitor electrode; 42-fifth trench; 43-third dielectric layer; 44-fourth dielectric layer; 45-fourth recess. a-first direction; b-second direction; c-third direction. DETAILED DESCRIPTION

[0076] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the protection scope of the present application.

[0077] The embodiments of the present application will be described below with reference to the drawings in the present application. It should be understood that the embodiments described below with reference to the drawings are exemplary descriptions of the technical solutions of the embodiments of the present application, and do not limit the technical solutions of the embodiments of the present application.

[0078] It is to be understood that the terms "said", "this" and "that" as used herein can include plural forms unless otherwise stated. It should be further understood that the term "comprise" used in the specification of the present application means that the features, integers, steps, operations, elements, and / or components described in the specification exist, but does not exclude other features, information, data, steps, operations, elements, components, and / or combinations thereof that are supported by the specification. The term "and / or" used herein means at least one of the terms defined by the term, for example, "A and / or B" can be implemented as "A", or as "B", or as "A and B".

[0079] For the purpose, technical solutions and advantages of the present application to be clearer, the embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

[0080] The technical solutions of the present application and how the technical solutions of the present application solve the above technical problems will be described in detail below with specific examples. It should be noted that the following embodiments can be mutually referenced, borrowed or combined, and the same terms, similar features and similar implementation steps in different embodiments will not be described repeatedly.

[0081] In the embodiments of the present application, FIGS. 2a-23c are schematic diagrams of intermediate structures obtained in each step of a manufacturing method of a semiconductor device provided by the embodiments of the present application; FIGS. 2a-6c and FIGS. 24a-42e are schematic diagrams of intermediate structures obtained in each step of another manufacturing method of a semiconductor device provided by the embodiments of the present application.

[0082] The embodiments of the present application provide a manufacturing method of a semiconductor device, as shown in FIG. 1, which comprises the following steps:

[0083] S101: forming a stacked structure 12 on one side of a substrate 11, the stacked structure 12 comprising a plurality of first dielectric layers 121 and a plurality of first sacrificial layers 122 alternately stacked.

[0084] S102: patterning to form a plurality of bit lines 13 arranged in an array, the bit lines 13 extending along a third direction c perpendicular to the substrate 11.

[0085] S103: patterning to form a plurality of first trenches 14 arranged in an array; along a first direction a, at least two first trenches 14 are arranged in the same column and spaced apart from at least two bit lines 13; etching back the plurality of first sacrificial layers 122 exposed by the sidewalls of the first trenches 14 to form a plurality of first recesses 15 corresponding to the plurality of first trenches 14; depositing a first capacitor electrode 16 in the first recesses 15; forming a first isolation layer 17 filling the first trenches 14.

[0086] S104: at the stack structure 12 between two adjacent bit lines 13, a second trench 18 extending along the first direction a is opened; all first sacrifice layers 122 exposed by etching back the sidewall of the second trench 18 are removed to form a plurality of second grooves 19; a semiconductor layer 23, a gate dielectric layer 24 and a gate 25 are sequentially deposited in the second grooves 19

[0087] In the method for manufacturing the semiconductor device provided in the embodiments of the present application, the bit line 13 extends along the third direction c perpendicular to the substrate 11, and the semiconductor layer 23 and the gate 25 extend along the first direction a parallel to the substrate 11, so that the semiconductor device with the vertical bit line 13 is obtained. The semiconductor device with the vertical bit line 13 manufactured in the embodiments of the present application is provided with the semiconductor layer 23, the gate dielectric layer 24 and the gate 25 between two adjacent bit lines 13, so that the distance between the two adjacent bit lines 13 is relatively large, and the parasitic capacitance between the bit lines 13 is small, thereby improving the circuit load problem. Moreover, in the embodiments of the present application, the bit line 13 is manufactured without a complicated bit line step manufacturing process, and the process is simple.

[0088] In the embodiments of the present application, the number of layers of the stack structure 12 is not limited to five, and the number of layers of the stack structure 12 is designed according to the actual application, which is not limited in the present application.

[0089] FIG. 2a is a top view of the stack structure 12 formed on one side of the substrate 11, FIG. 2b is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in FIG. 2a, FIG. 2c is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in FIG. 2a, FIG. 2d is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 2a, and FIG. 2e is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in FIG. 2a.

[0090] In the embodiments of the present application, referring to FIGS. 2a-2e, the multilayer first dielectric layer 121 and the multilayer first sacrifice layer 122 are periodically deposited on one side of the substrate 11 to form the stack structure 12. The deposition mode of the first dielectric layer 121 includes: using tetraethoxysilane as a silicon source, and depositing silicon dioxide as the first dielectric layer 121 by the reaction of tetraethoxysilane and oxygen in a plasma-enhanced chemical vapor deposition reactor, and the deposition mode of the first sacrifice layer 122 includes: plasma-enhanced chemical vapor deposition, etc. In the embodiments of the present application, the substrate 11 is a single crystal silicon substrate, or the substrate 11 contains a single crystal silicon material, or the substrate 11 contains a single crystal silicon film layer; and the material of the first sacrifice layer 122 includes: silicon nitride, silicon nitride, etc.

[0091] Optionally, in one embodiment of the present application, after the step S101 of forming the stack structure 12 on one side of the substrate 11, and before the step S102 of patterning the plurality of bit lines 13 arranged in an array, as shown in FIGS. 2d-6c, further comprising:

[0092] Patterning the stack structure 12 to form two third trenches 31 on both sides of the stack structure 12 along the second direction b, the third trenches 31 extending along the first direction a, the first direction a intersecting the second direction b and both being parallel to the substrate 11.

[0093] Depositing a second isolation layer 32 in the third trenches 31.

[0094] Patterning the stack structure 12 to form a plurality of fourth trenches 33 arranged in an array, at least two fourth trenches 33 being spaced apart along the first direction a, the fourth trenches 33 extending along the third direction c.

[0095] Depositing a second dielectric layer 34 in the fourth trenches 33.

[0096] In one embodiment of the present application, as shown in FIGS. 2d and 3a-3d, on the side of the stack structure 12 away from the substrate 11, two third trenches 31 are formed on both sides of the stack structure 12 along the second direction b by photolithography and etching processes. FIG. 3a is a top view of the two third trenches 31 formed on both sides of the stack structure 12 along the second direction b, FIG. 3b is a cross-sectional structural schematic view along the second direction A-A of FIG. 3a perpendicular to the substrate 11, FIG. 3c is a cross-sectional structural schematic view along the second direction B-B of FIG. 3a perpendicular to the substrate 11, FIG. 3d is a cross-sectional structural schematic view along the second direction C-C of FIG. 3a perpendicular to the substrate 11, and a cross-sectional structural schematic view along the first direction D-D of FIG. 3a perpendicular to the substrate 11 is shown in FIG. 2e.

[0097] In one embodiment of the present application, as shown in FIGS. 2d and 4a-4d, a second isolation layer 32 is deposited in the two third trenches 31. The deposition method of the second isolation layer 32 includes, for example, spin coating. The material of the second isolation layer 32 includes at least one of an oxide or a nitride; the oxide includes SiO2 (silicon dioxide), porous SiO2 doped with F (fluorine), porous SiO2 doped with C (carbon), HfOx (hafnium oxide). The material of the second isolation layer 32 can also be other low dielectric constant materials, which are not limited in the present application. FIG. 4a is a top view after the second isolation layer 32 is deposited in the third trenches 31, FIG. 4b is a cross-sectional structural schematic view along the second direction A-A of FIG. 4a perpendicular to the substrate 11, FIG. 4c is a cross-sectional structural schematic view along the second direction B-B of FIG. 4a perpendicular to the substrate 11, FIG. 4d is a cross-sectional structural schematic view along the second direction C-C of FIG. 4a perpendicular to the substrate 11, and a cross-sectional structural schematic view along the first direction D-D of FIG. 4a perpendicular to the substrate 11 is shown in FIG. 2e.

[0098] In the embodiment of the present application, referring to FIGS. 4b, 4d and FIGS. 5a-5c, a plurality of fourth grooves 33 arranged in an array are obtained on the side of the superposition structure 12 away from the substrate 11 by a photolithography and etching process. FIG. 5a is a top view of the plurality of fourth grooves 33 arranged in an array, FIG. 5b is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along a second direction B-B of FIG. 5a, FIG. 5c is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along a first direction D-D of FIG. 5a, and FIG. 5b and FIG. 5c are shown in FIG. 4b and FIG. 4d, respectively.

[0099] In the embodiment of the present application, referring to FIGS. 4b, 4d and FIGS. 6a-6c, a second dielectric layer 34 is deposited in the fourth grooves 33, and the deposition of the second dielectric layer 34 includes, for example, spin coating. FIG. 6a is a top view of the second dielectric layer 34 deposited in the fourth grooves 33, FIG. 6b is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along a second direction B-B of FIG. 6a, FIG. 6c is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along a first direction D-D of FIG. 6a, and FIG. 6b and FIG. 6c are shown in FIG. 4b and FIG. 4d, respectively.

[0100] Optionally, in one embodiment of the present application, the patterning to form the plurality of bit lines 13 arranged in an array in step S102 includes:

[0101] The superposition structure 12 is patterned to form a plurality of first vias 35 arranged in an array, as shown in FIGS. 4b, 6b-6c and FIGS. 7a-7c.

[0102] The bit lines 13 filling the first vias 35 are formed, as shown in FIGS. 4b, 6b and FIGS. 9a-9d.

[0103] In the embodiment of the present application, referring to FIGS. 4b, 6b-6c and FIGS. 7a-7c, a plurality of first vias 35 arranged in an array are obtained on the side of the superposition structure 12 away from the substrate 11 by a photolithography and etching process. FIG. 7a is a top view of the plurality of first vias 35 arranged in an array, FIG. 7b is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along a second direction C-C of FIG. 7a, FIG. 7c is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along a first direction E-E of FIG. 7a, and FIG. 7b and FIG. 7c are shown in FIG. 4b and FIG. 6b, respectively.

[0104] Optionally, in one embodiment of the present application, after forming the plurality of first vias 35 arranged in an array, and before filling the first vias 35 with the bit lines 13, further comprising:

[0105] etching back the plurality of layers of the first sacrificial layer 122 exposed by the sidewalls of the first vias 35 to form a corresponding plurality of third recesses 36; and simultaneously depositing the plurality of first source-drain electrodes 21 in the plurality of third recesses 36, as shown in FIGS. 4b, 6a-6b, 7c, and 8a-8b.

[0106] In one embodiment of the present application, as shown in FIGS. 4b, 6a-6b, 7c, and 8a-8b, the plurality of layers of the first sacrificial layer 122 exposed by the sidewalls of the first vias 35 are etched back to form a plurality of third recesses 36 spaced along a third direction c, and the plurality of first source-drain electrodes 21 are simultaneously deposited in the plurality of third recesses 36. The first source-drain electrodes 21 are made of heavily doped phosphorus silicon, and are formed by a metal silicide process to obtain metal silicide, thereby reducing the contact resistance between the bit lines 13 and the first source-drain electrodes 21. A top view of the plurality of first source-drain electrodes 21 simultaneously deposited in the plurality of third recesses 36 is shown in FIG. 7a, a cross-sectional structure perpendicular to the substrate 11 along a second direction A-A in FIG. 7a is shown in FIG. 4b, a cross-sectional structure perpendicular to the substrate 11 along a second direction B-B in FIG. 7a is shown in FIG. 6b, a cross-sectional structure perpendicular to the substrate 11 along a second direction C-C in FIG. 7a is shown in FIG. 8a, a cross-sectional structure perpendicular to the substrate 11 along a first direction D-D in FIG. 7a is shown in FIG. 8b, and a cross-sectional structure perpendicular to the substrate 11 along a first direction E-E in FIG. 7a is shown in FIG. 7c.

[0107] In one embodiment of the present application, as shown in FIGS. 4b, 6b, and 9a-9d, the first vias 35 are filled with the bit lines 13. A top view of the first vias 35 filled with the bit lines 13 is shown in FIG. 9a, a cross-sectional structure perpendicular to the substrate 11 along a second direction A-A in FIG. 9a is shown in FIG. 4b, a cross-sectional structure perpendicular to the substrate 11 along a second direction B-B in FIG. 9a is shown in FIG. 6b, a cross-sectional structure perpendicular to the substrate 11 along a second direction C-C in FIG. 9a is shown in FIG. 9b, a cross-sectional structure perpendicular to the substrate 11 along a first direction D-D in FIG. 9a is shown in FIG. 9c, and a cross-sectional structure perpendicular to the substrate 11 along a first direction E-E in FIG. 9a is shown in FIG. 9d.

[0108] Optionally, in one embodiment of the present application, in the step S103 of patterning to form the plurality of first trenches 14 arranged in an array, the step of patterning to form the plurality of first trenches 14 arranged in an array comprises:

[0109] The stack structure 12 is patterned to form the plurality of first trenches 14 arranged in an array, as shown in FIGS. 6b, 9b, and 10a-10c.

[0110] After forming the corresponding plurality of first recesses 15, and before depositing the first capacitor electrode 16 in the first recesses 15, the method further comprises:

[0111] Depositing the second source / drain 22 in the first recesses 15, as shown in FIGS. 10a, 6b, 9b, and FIGS. 12a-12b.

[0112] In the embodiment of the present application, as shown in FIGS. 6b, 9b, and FIGS. 10a-10c, the plurality of first trenches 14 arranged in an array are obtained by photolithography and etching process on the side of the stack structure 12 away from the substrate 11. FIG. 10a is a top view of the plurality of first trenches 14 arranged in an array, FIG. 10b is a cross-sectional structure schematic view perpendicular to the substrate 11 along the second direction A-A of FIG. 10a, a cross-sectional structure schematic view perpendicular to the substrate 11 along the second direction B-B of FIG. 10a is shown in FIG. 6b, a cross-sectional structure schematic view perpendicular to the substrate 11 along the second direction C-C of FIG. 10a is shown in FIG. 9b, and FIG. 10c is a cross-sectional structure schematic view perpendicular to the substrate 11 along the first direction D-D of FIG. 10a.

[0113] In the embodiment of the present application, as shown in FIGS. 10a, 6b, 9b, and FIGS. 11a-11b, the plurality of first recesses 15 spaced along the third direction c are formed by etching the partial first sacrificial layer 122 exposed on the sidewall of the first trench 14. The etching depth of the first sacrificial layer 122 along the second direction b is 20-50 nm. The top view of the plurality of first recesses 15 is shown in FIG. 10a, FIG. 11a is a cross-sectional structure schematic view perpendicular to the substrate 11 along the second direction A-A of FIG. 10a, a cross-sectional structure schematic view perpendicular to the substrate 11 along the second direction B-B of FIG. 10a is shown in FIG. 6b, a cross-sectional structure schematic view perpendicular to the substrate 11 along the second direction C-C of FIG. 10a is shown in FIG. 9b, and FIG. 11b is a cross-sectional structure schematic view perpendicular to the substrate 11 along the first direction D-D of FIG. 10a.

[0114] In the embodiment of the present application, referring to FIG. 10a, 6b, 9b and FIG. 12a-12b, the second source / drain 22 is synchronously deposited in the first recess 15. The second source / drain 22 is made of heavily doped phosphorus silicon, and a metal silicide is obtained through a metal silicide process, so as to reduce the contact resistance between the second source / drain 22 and the first capacitor electrode 16. The top view of the synchronously deposited second source / drain 22 in the first recess 15 is shown in FIG. 10a, the cross-sectional structure view of FIG. 10a along the second direction A-A perpendicular to the substrate 11 is shown in FIG. 12a, the cross-sectional structure view of FIG. 10a along the second direction B-B perpendicular to the substrate 11 is shown in FIG. 6b, the cross-sectional structure view of FIG. 10a along the second direction C-C perpendicular to the substrate 11 is shown in FIG. 9b, and the cross-sectional structure view of FIG. 10a along the first direction D-D perpendicular to the substrate 11 is shown in FIG. 12b.

[0115] In the embodiment of the present application, referring to FIG. 6b, 9b and FIG. 13a-13c, the first capacitor electrode 16 is synchronously deposited in the first recess 15 along the second direction b, near one side of the second source / drain 22, and then the first isolation layer 17 is filled in the first trench 14. The material of the first capacitor electrode 16 includes titanium nitride, etc. The first capacitor electrode 16 is used as a lower plate of a capacitor, and the plurality of first capacitor electrodes 16 are separated by a first dielectric layer 121, so as to remove the parasitic of the metal of the lower plate of the capacitor between adjacent layers. The first isolation layer 17 is temporarily filled in the position of the capacitor.

[0116] The material of the first capacitor electrode 16 includes: TiN, Cu, Al, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Ag, Au, Co-based alloy, Fe-based alloy, Ni-based alloy, FeNi-based alloy, CoNi-based alloy, and FeCo-based alloy, etc. The material of the first isolation layer 17 includes at least one of an oxide or a nitride; the oxide includes: SiO2, F-doped porous SiO2, C-doped porous SiO2, HfOx. The material of the first isolation layer 17 can also be other low dielectric constant materials, which are not limited in the present application. The top view of the first isolation layer 17 filled in the first trench 14 is shown in FIG. 13a, the cross-sectional structure view of FIG. 13a along the second direction A-A perpendicular to the substrate 11 is shown in FIG. 13b, the cross-sectional structure view of FIG. 13a along the second direction B-B perpendicular to the substrate 11 is shown in FIG. 6b, the cross-sectional structure view of FIG. 13a along the second direction C-C perpendicular to the substrate 11 is shown in FIG. 9b, and the cross-sectional structure view of FIG. 13a along the first direction D-D perpendicular to the substrate 11 is shown in FIG. 13c.

[0117] In the embodiment of the present application, referring to FIGS. 14a-14e, a protective layer 37 is deposited on the side of the stack structure 12, the second isolation layer 32, the bit line 13, and the second dielectric layer 34 away from the substrate 11; then, the second trench 18 is obtained by etching the stack structure 12 between two adjacent bit lines 13. The material of the protective layer 37 includes silicon dioxide and the like. FIG. 14a is a top view of the obtained second trench 18, FIG. 14b is a schematic view of the cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in FIG. 14a, FIG. 14c is a schematic view of the cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in FIG. 14a, FIG. 14d is a schematic view of the cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 14a, and FIG. 14e is a schematic view of the cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in FIG. 14a.

[0118] In the embodiment of the present application, referring to FIGS. 14a, 14e, and FIGS. 15a-15c, the first sacrificial layer 122 exposed by etching the sidewall of the second trench 18 is removed to form a plurality of second recesses 19 spaced along the third direction c. The etching depth of the first sacrificial layer 122 along the second direction b is 20-50 nm. Part of the first source / drain electrode 21 and part of the second source / drain electrode 22 are exposed in the second recess 19. The top view of the obtained plurality of second recesses 19 is shown in FIG. 14a, FIG. 15a is a schematic view of the cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in FIG. 14a, FIG. 15b is a schematic view of the cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in FIG. 14a, FIG. 15c is a schematic view of the cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 14a, and the schematic view of the cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in FIG. 14a is shown in FIG. 14e.

[0119] In the embodiment of the present application, referring to FIGS. 14a, 14e, and FIGS. 16a-16c, the silicon semiconductor layer 23 with low-concentration boron doping is grown in the second recess 19, and then the parasitic MOS (diode) between layers is removed by an in-dig method. The material of the semiconductor layer 23 is not limited to silicon, and the material of the semiconductor layer 23 also includes Ge (germanium), GaAs (gallium arsenide), and other semiconductor materials, and can also be Indium Gallium Zinc Oxide (IGZO) and other metal oxide materials.

[0120] For example, the material of the semiconductor layer 23 can be a wide-bandgap material, such as a metal oxide material with a band gap greater than 1.65 eV.

[0121] For example, the material of the metal oxide semiconductor layer or channel can include a metal oxide of at least one of indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, and the like. Of course, the metal oxide can also include a compound containing other elements, such as N, Si, and the like, and can also include a small amount of a doped element.

[0122] In some embodiments, the material of the metal oxide semiconductor layer or channel can include any one or more of indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and the like, as long as the leakage current of the transistor meets the requirements. The specific material can be adjusted according to the actual situation.

[0123] These materials have a wide band gap and low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10-15A to 10-18A, thereby improving the working performance of the dynamic memory.

[0124] A plan view of the semiconductor layer 23 is shown in FIG. 14a, a cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in FIG. 14a is shown in FIG. 16a, a cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in FIG. 14a is shown in FIG. 16b, a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 14a is shown in FIG. 16c, and a cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in FIG. 14a is shown in FIG. 14e.

[0125] In the embodiment of the present application, referring to FIGS. 14a, 14e and 17a-17c, the gate dielectric layer 24 and the gate electrode 25 are sequentially deposited in the second groove 19 near the side of the semiconductor layer 23 along the second direction b. The top view of sequentially depositing the gate dielectric layer 24 and the gate electrode 25 is shown in FIG. 14a, FIG. 17a is a schematic diagram of the cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in FIG. 14a, FIG. 17b is a schematic diagram of the cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in FIG. 14a, FIG. 17c is a schematic diagram of the cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 14a, and the schematic diagram of the cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in FIG. 14a is shown in FIG. 14e.

[0126] Optionally, in one embodiment of the present application, after sequentially depositing the semiconductor layer 23, the gate dielectric layer 24 and the gate electrode 25 in the second groove 19 in the step S104, the method further comprises:

[0127] Depositing a third isolation layer 38 in the second groove 18, as shown in FIGS. 14e and 18a-18d.

[0128] Removing the first isolation layer 17 in the first groove 14, as shown in FIGS. 18c-18d and 19a-19c.

[0129] Sequentially depositing a ferroelectric layer 39 and a second capacitor electrode 41 in the first groove 14, as shown in FIGS. 18c-18d and 20a-20c.

[0130] In the embodiment of the present application, referring to FIGS. 14e and 18a-18d, the third isolation layer 38 is deposited in the second groove 18, and the deposition method of the third isolation layer 38 includes plasma enhanced chemical vapor deposition, etc. The material of the third isolation layer 38 includes at least one of oxide or nitride; the oxide includes SiO2, F-doped porous SiO2, C-doped porous SiO2, HfOx. The material of the third isolation layer 38 can also be other low dielectric constant materials, which are not limited in the present application. FIG. 18a is a top view of depositing the third isolation layer 38 in the second groove 18, FIG. 18b is a schematic diagram of the cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in FIG. 18a, FIG. 18c is a schematic diagram of the cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in FIG. 18a, FIG. 18d is a schematic diagram of the cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 18a, and the schematic diagram of the cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in FIG. 18a is shown in FIG. 14e.

[0131] In the embodiment of the present application, referring to FIGS. 18c-18d and 19a-19c, the first isolation layer 17 at the capacitor position is removed by a photolithography and etching process. FIG. 19a is a top view of the first isolation layer 17 removed in the first trench 14, FIG. 19b is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in FIG. 19a, a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in FIG. 19a is shown in FIG. 18c, a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 19a is shown in FIG. 18d, and FIG. 19c is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in FIG. 19a.

[0132] In the embodiment of the present application, referring to FIGS. 18c-18d and 20a-20c, the ferroelectric layer 39 and the second capacitor electrode 41 are sequentially deposited in the first trench 14. The second capacitor electrode 41 includes a plate line, and the second capacitor electrode 41 serves as an upper plate of the capacitor. The material of the second capacitor electrode 41 includes TiN, Cu, Al, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Ag, Au, Co-based alloy, Fe-based alloy, Ni-based alloy, FeNi-based alloy, CoNi-based alloy, FeCo-based alloy, etc. FIG. 20a is a top view of the ferroelectric layer 39 and the second capacitor electrode 41 sequentially deposited in the first trench 14, FIG. 20b is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in FIG. 20a, a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in FIG. 20a is shown in FIG. 18c, a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 20a is shown in FIG. 18d, and FIG. 20c is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in FIG. 20a.

[0133] In the embodiment of the present application, the bit line 13 is arranged to extend along a third direction c perpendicular to the substrate 11, the bit line 13 is connected to the first source-drain electrode 21 of the multi-layer transistor 2 in the same memory cell stack region, and the semiconductor layer 23 and the gate 25 are arranged to extend along a first direction a parallel to the substrate 11. The semiconductor layer 23 and the gate 25 of the transistor 2 are designed to extend in a plane parallel to the substrate 11, and the bit line 13 is designed to be perpendicular to the substrate 11, so that the semiconductor layer 23 and the gate 25 are both orthogonal to the bit line 13, which can effectively reduce the coupling effect between the bit line 13 and the semiconductor layer 23 and the gate 25. Moreover, in the plane parallel to the substrate 11, along the first direction a, there is a certain spacing between the bit line 13, the second source-drain electrode 22 and the capacitor electrode, which can effectively reduce the coupling effect between the bit line 13, the second source-drain electrode 22 and the capacitor electrode. Along the second direction b, any two adjacent bit lines 13 are spaced by the semiconductor layer 23 and the gate 25 of the two back-to-back transistors and the third isolation layer 38 between the two transistors 2, which can effectively reduce the coupling effect between any two bit lines 13 along the second direction b. Thus, the performance of the semiconductor device can be effectively improved.

[0134] In the embodiment of the present application, the capacitor electrode includes a first capacitor electrode 16 and a second capacitor electrode 41.

[0135] In the ferroelectric semiconductor device with a vertical bit line of a polysilicon transistor manufactured in the embodiment of the present application, the non-volatile storage characteristics of the ferroelectric can reduce the leakage index of the channel of the transistor 2, so that the Si / SiGe epitaxial silicon channel scheme of the three-dimensional semiconductor device structure is not needed, thereby reducing the production cost. The semiconductor layer 23 is the channel.

[0136] Optionally, in one embodiment of the present application, after the ferroelectric layer 39 and the second capacitor electrode 41 are sequentially deposited in the first trench 14, referring to FIGS. 21a-23c, it further includes:

[0137] Along the first direction a, a fifth trench 42 extending along the third direction c is opened at the second dielectric layer 34 between any two adjacent memory cell stack regions.

[0138] The semiconductor layer 23 exposed by the side wall of the fifth trench 42 is removed by etching back.

[0139] A third dielectric layer 43 is deposited in the fifth trench 42.

[0140] In the embodiment of the present application, referring to FIG. 20b, 18d and FIG. 21a-21c, the fifth groove 42 extending along the third direction c is opened at the second dielectric layer 34 between any two adjacent memory cell stack regions along the first direction a by means of photolithography and etching process, so as to remove the parasitic MOS (diode) between the memory cells. FIG. 21a is a top view of the fifth groove 42, the cross-sectional structure along the second direction A-A in FIG. 21a perpendicular to the substrate 11 is shown in FIG. 20b, the cross-sectional structure along the second direction B-B in FIG. 21a perpendicular to the substrate 11 is shown in FIG. 21b, the cross-sectional structure along the second direction C-C in FIG. 21a perpendicular to the substrate 11 is shown in FIG. 18d, and the cross-sectional structure along the first direction D-D in FIG. 21a perpendicular to the substrate 11 is shown in FIG. 21c.

[0141] In the embodiment of the present application, referring to FIG. 18d, 20b, 21a, 21c and FIG. 22a, the semiconductor layer 23 exposed by the sidewall of the fifth groove 42 is removed by etching back, so as to remove the parasitic silicon channel. The top view of the semiconductor layer 23 exposed by the sidewall of the fifth groove 42 is shown in FIG. 21a, the cross-sectional structure along the second direction A-A in FIG. 21a perpendicular to the substrate 11 is shown in FIG. 20b, the cross-sectional structure along the second direction B-B in FIG. 21a perpendicular to the substrate 11 is shown in FIG. 22a, the cross-sectional structure along the second direction C-C in FIG. 21a perpendicular to the substrate 11 is shown in FIG. 18d, and the cross-sectional structure along the first direction D-D in FIG. 21a perpendicular to the substrate 11 is shown in FIG. 21c.

[0142] In the embodiment of the present application, referring to FIG. 18d, 20b and FIG. 23a-23c, the third dielectric layer 43 is deposited in the fifth groove 42, the third dielectric layer 43 is selected from low dielectric constant and insulating materials, and the deposition method of the third dielectric layer 43 includes PECVD (Plasma Enhanced Chemical Vaper Deposition) and the like. FIG. 23a is a top view of the third dielectric layer 43 deposited in the fifth groove 42, the cross-sectional structure along the second direction A-A in FIG. 23a perpendicular to the substrate 11 is shown in FIG. 20b, the cross-sectional structure along the second direction B-B in FIG. 23a perpendicular to the substrate 11 is shown in FIG. 23b, the cross-sectional structure along the second direction C-C in FIG. 23a perpendicular to the substrate 11 is shown in FIG. 18d, and the cross-sectional structure along the first direction D-D in FIG. 23a perpendicular to the substrate 11 is shown in FIG. 23c.

[0143] Optionally, the embodiment of the present application further provides another method for manufacturing a semiconductor device, which is described as follows. It should be noted that in the following manufacturing method, the step of depositing the second dielectric layer 34 in the fourth groove 33 and the steps before this step are the same as those of the above method, which are not described herein again.

[0144] In the embodiment of the present application, referring to FIGS. 4b, 6b and 24a-24c, the superposed structure 12 is subjected to a patterning process by a photolithography and etching process to obtain the arrayed first vias 35. FIG. 24a is a top view of the arrayed first vias 35, a cross-sectional structure perpendicular to the substrate 11 along the second direction A-A of FIG. 24a is shown in FIG. 4b, a cross-sectional structure perpendicular to the substrate 11 along the second direction B-B of FIG. 24a is shown in FIG. 6b, FIG. 24b is a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C of FIG. 24a, and FIG. 24c is a cross-sectional structure perpendicular to the substrate 11 along the first direction D-D of FIG. 24a.

[0145] In the embodiment of the present application, referring to FIGS. 4b, 6b and 25a-25c, the bit lines 13 are filled in the first vias 35. FIG. 25a is a top view of the bit lines 13 filled in the first vias 35, a cross-sectional structure perpendicular to the substrate 11 along the second direction A-A of FIG. 25a is shown in FIG. 4b, a cross-sectional structure perpendicular to the substrate 11 along the second direction B-B of FIG. 25a is shown in FIG. 6b, FIG. 25b is a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C of FIG. 25a, and FIG. 25c is a cross-sectional structure perpendicular to the substrate 11 along the first direction D-D of FIG. 25a.

[0146] Optionally, in one embodiment of the present application, the patterning to form the arrayed bit lines 13 in step S102 comprises:

[0147] The second isolation layer 32 is patterned to form the arrayed first vias 35, as shown in FIGS. 26a-26b.

[0148] The first sacrificial layer 122 exposed by the etching of the side wall of the first via 35 is etched back to form a corresponding plurality of third grooves 36, and the plurality of first source-drain electrodes 21 are simultaneously deposited in the plurality of third grooves 36, as shown in FIGS. 26a and 26c-26d.

[0149] The bit lines 13 filling the first vias 35 and connected to the plurality of first source-drain electrodes 21 are formed, as shown in FIGS. 26e-26f.

[0150] In the embodiment of the present application, the manufacturing of the bit line 13 can also adopt the following steps. The second isolation layer 32 is subjected to a patterning treatment through a photolithography and etching process to obtain a plurality of first vias 35 arranged in an array. FIG. 26a is a top view of the formation of the plurality of first vias 35 arranged in an array, and FIG. 26b is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 26a. The plurality of first vias 35 are subjected to a back-etching process to expose the plurality of first sacrificial layers 122 on the sidewalls of the first vias 35, thereby forming a plurality of third grooves 36 corresponding thereto. FIG. 26a is a top view of the formation of the plurality of third grooves 36 corresponding thereto, and FIG. 26c is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 26a. The plurality of first source-drain electrodes 21 are synchronously deposited in the plurality of third grooves 36. FIG. 26a is a top view of the deposition of the plurality of first source-drain electrodes 21, and FIG. 26d is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 26a. The bit line 13 is filled in the first via 35. FIG. 26e is a top view of the filling of the bit line 13 in the first via 35, and FIG. 26f is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 26e. Since the schematic views of the cross-sectional structures along the A-A, B-B and D-D directions do not change, they are not described herein.

[0151] Optionally, in one embodiment of the present application, after the formation of the bit line 13 filling the first via 35, and before the patterning to form the plurality of first trenches 14 arranged in an array, the method further comprises:

[0152] The fourth dielectric layer 44 is deposited on the side of the stack structure 12, the second isolation layer 32, the bit line 13 and the second dielectric layer 34 away from the substrate 11, as shown in FIGS. 27a-27e.

[0153] Furthermore, the patterning to form the plurality of first trenches 14 arranged in an array comprises:

[0154] The second isolation layer 32 is patterned to form the plurality of first trenches 14 arranged in an array, as shown in FIGS. 27c-27e and 28a-28b.

[0155] In the embodiment of the present application, referring to FIGS. 27a-27e, the fourth dielectric layer 44 is deposited on the side of the stack structure 12, the second isolation layer 32, the bit line 13 and the second dielectric layer 34 away from the substrate 11. The material of the fourth dielectric layer 44 includes silicon dioxide and the like. FIG. 27a is a top view of the deposition of the fourth dielectric layer 44, the schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in FIG. 27a is shown in FIG. 27b, the schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in FIG. 27a is shown in FIG. 27c, FIG. 27d is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 27a, and FIG. 27e is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in FIG. 27a.

[0156] In the embodiment of the present application, referring to FIGS. 27c-27e and 28a-28b, the second isolation layer 32 is patterned by a photolithography and etching process to form the arrayed first trenches 14. FIG. 28a is a top view of the arrayed first trenches 14, FIG. 28b is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in FIG. 28a, FIG. 27c is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in FIG. 28a, FIG. 27d is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 28a, and FIG. 27e is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in FIG. 28a.

[0157] In the embodiment of the present application, referring to FIGS. 27c-27d, 28a and 29a-29b, the first sacrificial layer 122 exposed by the sidewalls of the first trenches 14 is etched back to form the corresponding first recesses 15. FIG. 28a is a top view of the corresponding first recesses 15, FIG. 29a is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in FIG. 28a, FIG. 27c is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in FIG. 28a, FIG. 27d is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 28a, and FIG. 29b is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in FIG. 28a.

[0158] Optionally, in one embodiment of the present application, after forming the corresponding first recesses 15, before forming the first isolation layer 17 filling the first trenches 14, further comprising:

[0159] Depositing the first capacitor electrode 16 on the sidewalls of the first trenches 14 and the first recesses 15, as shown in FIGS. 28a and 30a-30d.

[0160] And, after forming the first isolation layer 17 filling the first trenches 14, before opening the second trenches 18 extending along the first direction a at the overlapping structure 12 between two adjacent columns of bit lines 13, further comprising:

[0161] Removing the first capacitor electrode 16 on the sidewalls of the first trenches 14; removing the first isolation layer 17 in the first recesses 15, as shown in FIGS. 27c-27d, 28a and 31a-31b.

[0162] Depositing a ferroelectric layer 39 covering the first capacitor electrode 16 in the first recesses 15; depositing a second capacitor electrode 41 in the first recesses 15 and the first trenches 14, as shown in FIGS. 27c-27d, 32a-32d.

[0163] A protective layer 37 is deposited on the side of the fourth dielectric layer 44, the ferroelectric layer 39, and the second capacitor electrode 41 away from the substrate 11, as shown in FIGS. 33a-33e.

[0164] In the embodiment of the present application, referring to FIGS. 28a and 30a-30d, the first capacitor electrode 16 is deposited on the sidewall of the first trench 14 and the first recess 15; then the first isolation layer 17 is filled in the first trench 14. FIG. 28a is a top view after the first isolation layer 17 is filled, a cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in FIG. 28a is shown in FIG. 30a, a cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in FIG. 28a is shown in FIG. 30b, a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 28a is shown in FIG. 30c, and a cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in FIG. 28a is shown in FIG. 30d.

[0165] In the embodiment of the present application, referring to FIGS. 27c-27d, 28a and 31a-31b, the first capacitor electrode 16 on the sidewall of the first trench 14 is removed; then the first isolation layer 17 in the first recess 15 is removed. FIG. 28a is a top view after the first isolation layer 17 in the first recess 15 is removed, a cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in FIG. 28a is shown in FIG. 31a, a cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in FIG. 28a is shown in FIG. 27c, a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 28a is shown in FIG. 27d, and a cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in FIG. 28a is shown in FIG. 31b.

[0166] In the embodiment of the present application, referring to FIGS. 27c-27d, 32a-32c, the ferroelectric layer 39 covering the first capacitor electrode 16 is deposited on the sidewall of the first recess 15 and the sidewall of the first trench 14; then the second capacitor electrode 41 is deposited in the first recess 15 and the first trench 14, and the ferroelectric layer 39 covering the fourth dielectric layer 44 and the second capacitor electrode 41 are removed to expose the fourth dielectric layer 44 by a chemical mechanical polishing process and etching and re-etching. The material of the second capacitor electrode 41 includes TiN or a combination of TiN / W. When the material of the second capacitor electrode 41 is the combination of TiN / W. FIG. 32a is a top view after the second capacitor electrode 41 is deposited, a cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in FIG. 32a is shown in FIG. 32b, a cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in FIG. 32a is shown in FIG. 27c, a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 32a is shown in FIG. 27d, and a cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in FIG. 32a is shown in FIG. 32c.

[0167] In the embodiment of the present application, the ferroelectric layer 39 on the sidewall of the first trench 14 in Fig. 32b can be removed by a wet etching process to obtain a ferroelectric layer 39 which is not a continuous structure, and then a second capacitor electrode 41 is deposited in the first recess 15 and the first trench 14, as shown in Fig. 32d.

[0168] In the embodiment of the present application, referring to Figs. 33a-33e, a protective layer 37 is deposited on the side of the fourth dielectric layer 44, the ferroelectric layer 39, and the second capacitor electrode 41 away from the substrate 11. The protective layer 37 is used to protect the bit line 13 and the capacitor. The material of the protective layer 37 includes silicon dioxide, etc. Fig. 33a is a top view after the deposition of the protective layer 37, Fig. 33b is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in Fig. 33a, Fig. 33c is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in Fig. 33a, Fig. 33d is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in Fig. 33a, and Fig. 33e is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in Fig. 33a.

[0169] In the embodiment of the present application, referring to Figs. 33e and 34a-34d, a second trench 18 extending along the first direction a is formed at the stacked structure 12 between two adjacent bit lines 13 by a photolithography and etching process. Fig. 34a is a top view after the formation of the second trench 18, Fig. 34b is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in Fig. 34a, Fig. 34c is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in Fig. 34a, Fig. 34d is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in Fig. 33a, and Fig. 33e is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in Fig. 34a.

[0170] In the embodiment of the present application, referring to Figs. 33e, 34a, and 35a-35c, all the first sacrificial layers 122 exposed by the sidewall of the second trench 18 are etched back to form a plurality of second recesses 19. The etching size along the second direction includes 20-50 nm. Fig. 34a is a top view after the formation of the plurality of second recesses 19, Fig. 35a is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in Fig. 34a, Fig. 35b is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in Fig. 34a, Fig. 35c is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in Fig. 34a, and Fig. 33e is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in Fig. 34a.

[0171] In the embodiment of the present application, referring to FIG. 33e, 34a and FIG. 36a-36c, the semiconductor layer 23, the gate dielectric layer 24 and the gate electrode 25 are sequentially deposited in the second recess 19. FIG. 34a is a top view after the deposition of the gate electrode 25, FIG. 36a is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in FIG. 34a, FIG. 36b is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in FIG. 34a, FIG. 36c is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 34a, and FIG. 33e is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in FIG. 34a. The semiconductor layer 23 can serve as a channel of the transistor 2, and the channel structure in the embodiment of the present application is not limited to a single-sided structure, but can also be a C-shaped structure. The material of the semiconductor layer 23 is not limited to IGZO, but also includes metal oxide materials such as ITO, ITZO, and other semiconductor materials such as Si, Ge and GaAs.

[0172] Optionally, in one embodiment of the present application, after the semiconductor layer 23, the gate dielectric layer 24 and the gate electrode 25 are sequentially deposited in the second recess 19, the method further includes:

[0173] The semiconductor layer 23 extending along the second direction b in the second recess 19 is removed to obtain a fourth recess 45, as shown in FIG. 33e, 34a and FIG. 37a-37c.

[0174] The third isolation layer 38 is deposited in the second trench 18 and the fourth recess 45, as shown in FIG. 33e and FIG. 38a-38d.

[0175] In the embodiment of the present application, referring to FIG. 33e, 34a and FIG. 37a-37c, the semiconductor layer 23 extending along the second direction b in the second recess 19 is removed to remove the parasitic MOS (diode) between the upper and lower semiconductor layers 23, thereby obtaining the fourth recess 45. FIG. 34a is a top view after the fourth recess 45 is obtained, FIG. 37a is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in FIG. 34a, FIG. 37b is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in FIG. 34a, FIG. 37c is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 34a, and FIG. 33e is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in FIG. 34a.

[0176] In the embodiment of the present application, referring to FIG. 33e and FIG. 38a-38d, the third isolation layer 38 is deposited in the second trench 18 and the fourth groove 45. The third isolation layer 38 is made of low dielectric constant dielectric material. FIG. 38a is a top view after the third isolation layer 38 is deposited, FIG. 38b is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in FIG. 38a, FIG. 38c is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in FIG. 38a, FIG. 38d is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 34a, and FIG. 33e is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in FIG. 38a.

[0177] Optionally, in one embodiment of the present application, after the third isolation layer 38 is deposited in the second trench 18 and the fourth groove 45, further comprising:

[0178] Along the first direction a, fifth trenches 42 extending along the third direction c are formed at the second dielectric layer 34 between any two adjacent memory cell stack regions, as shown in FIG. 38b, 38d and FIG. 39a-39c.

[0179] The semiconductor layer 23 exposed by the sidewall of the fifth trench 42 is removed by etching back, as shown in FIG. 38b, 38d, 39a, 39c and FIG. 40a.

[0180] The third dielectric layer 43 is deposited in the fifth trench 42, as shown in FIG. 38b, 38d and FIG. 41a-41c.

[0181] In the embodiment of the present application, by forming the fifth trench 42 at the second dielectric layer 34 between any two adjacent memory cell stack regions, part of the semiconductor layer 23 is exposed in the fifth trench 42, and by removing the semiconductor layer 23 exposed in the fifth trench 42, the parasitic MOS in the horizontal direction of the channel is removed. The semiconductor layer 23 can serve as the channel.

[0182] In the embodiment of the present application, referring to FIG. 38b, 38d and FIG. 39a-39c, by the photolithography and etching process, along the first direction a, the fifth trenches 42 extending along the third direction c are formed at the second dielectric layer 34 between any two adjacent memory cell stack regions. FIG. 39a is a top view after the fifth trench 42 is formed, FIG. 38b is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in FIG. 39a, FIG. 39b is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in FIG. 39a, FIG. 38d is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 39a, and FIG. 39c is a schematic view of a cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in FIG. 39a.

[0183] In the embodiment of the present application, referring to FIG. 38b, 38d, 39a, 39c and FIG. 40a, the semiconductor layer 23 exposed by the sidewall of the fifth trench 42 is removed by a wet etching process, so as to remove the horizontal channel parasitic MOS, and the semiconductor layer 23 can be used as a channel. The top view after the semiconductor layer 23 exposed by the sidewall of the fifth trench 42 is removed is shown in FIG. 39a, the cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in FIG. 39a is shown in FIG. 38b, the cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in FIG. 39a is shown in FIG. 40a, the cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 39a is shown in FIG. 38d, and the cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in FIG. 39a is shown in FIG. 39c.

[0184] In the embodiment of the present application, referring to FIG. 38b, 38d and FIG. 41a-41c, the third dielectric layer 43 is deposited in the fifth trench 42, and the material of the third dielectric layer 43 is selected from a low dielectric constant material. FIG. 41a is a top view after the third dielectric layer 43 is deposited, the cross-sectional structure perpendicular to the substrate 11 along the second direction A-A in FIG. 41a is shown in FIG. 38b, the cross-sectional structure perpendicular to the substrate 11 along the second direction B-B in FIG. 41a is shown in FIG. 41b, the cross-sectional structure perpendicular to the substrate 11 along the second direction C-C in FIG. 41a is shown in FIG. 38d, and FIG. 41c is a cross-sectional structure perpendicular to the substrate 11 along the first direction D-D in FIG. 41a.

[0185] Optionally, in the embodiment of the present application, the semiconductor device manufactured by the above-mentioned manufacturing method of a semiconductor device can also be arranged in the structure shown in FIG. 41c and FIG. 42a-42d. Since the manufacturing method of the semiconductor device arranged in this structure is the same as the above-mentioned second manufacturing method of a semiconductor device, details are not repeated here.

[0186] Optionally, in one embodiment of the present application, the material of the gate 25 includes at least one of a metal, a metal alloy, a metal nitride, a metal semiconductor compound, and a conductive doped semiconductor.

[0187] The material of the bit line 13 includes at least one of a metal, a metal alloy, a metal nitride, a metal silicide, a metal carbide, and a conductive doped semiconductor material.

[0188] The material of the first dielectric layer 121, the second dielectric layer 34 and the third dielectric layer 43 respectively includes at least one of an oxide or a nitride; the oxide includes SiO2, F-doped porous SiO2, C-doped porous SiO2, HfOx.

[0189] The material of the ferroelectric layer 39 includes at least one of hafnium-based oxide, lead zirconate titanate, and doped strontium titanate.

[0190] In the embodiments of the present application, the material of the gate 25 includes W, Cu, Al, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Ag, Au, Co-based alloy, Fe-based alloy, Ni-based alloy, FeNi-based alloy, CoNi-based alloy, FeCo-based alloy, Al-based alloy, Cu-based alloy, Mg-based alloy, Ti-based alloy, low carbon steel, stainless steel, conductive metal nitride such as titanium nitride TiN, conductive metal silicide, conductive metal carbide, conductive doped semiconductor such as doped polysilicon, conductive metal oxide semiconductor such as indium tin oxide, and the like conductive materials.

[0191] In the embodiments of the present application, the material of the bit line 13 includes W, Cu, Al, Ti, Mo, Nb, V, Hf, Ta, Cr, Zr, Fe, Ru, Os, Co, Rh, Ir, Ni, Pa, Pt, Ag, Au, Co-based alloy, Fe-based alloy, Ni-based alloy, FeNi-based alloy, CoNi-based alloy, FeCo-based alloy, Al-based alloy, Cu-based alloy, Mg-based alloy, Ti-based alloy, low carbon steel, stainless steel, conductive metal nitride such as titanium nitride TiN, conductive metal silicide, conductive metal carbide, conductive doped semiconductor such as doped polysilicon, conductive metal oxide semiconductor such as indium tin oxide, and the like conductive materials.

[0192] In the embodiments of the present application, the material of the first dielectric layer 121, the second dielectric layer 34, and the third dielectric layer 43 each includes at least one of oxide or nitride; the oxide includes SiO2, F-doped porous SiO2, C-doped porous SiO2, HfOx. The material of the first dielectric layer 121, the second dielectric layer 34, and the third dielectric layer 43 can also be other low dielectric constant materials, which are not limited in the present application.

[0193] In the embodiments of the present application, the material of the ferroelectric layer 39 includes HfZrO, HfAlO, HfLaO, and other Hf-based oxides, PZT (lead zirconate titanate) of perovskite structure, doped strontium titanate, and the like materials, or ferroelectric / dielectric composite structure, different ferroelectric stack structure, and the like, and is not limited to ferroelectric materials, but can also be anti-ferroelectric materials.

[0194] Based on the same inventive concept, the embodiments of the present application provide a semiconductor device, as shown in FIGS. 16a-23c, 38b, 38c, and 41a-42d, which includes a substrate 11, a multilayer first dielectric layer 121, a multilayer transistor 2, a bit line 13, and a multilayer first capacitor electrode 16.

[0195] The multilayer first dielectric layer 121 and the multilayer transistor 2 are alternately stacked on one side of the substrate 11; the transistor 2 includes a semiconductor layer 23, a gate dielectric layer 24 and a gate 25 all extending along a first direction a, and a first source-drain 21 and a second source-drain 22 both located on one side of the semiconductor layer 23 along a second direction b; the first direction a intersects the second direction b and is parallel to the substrate 11.

[0196] The bit line 13 extends along a third direction c perpendicular to the substrate 11 and is connected to the first source-drain 21 of the multilayer transistor 2 in the same memory cell stack region.

[0197] The multilayer first capacitor electrode 16 is connected to the plurality of second source-drains 22 respectively.

[0198] In the embodiment of the present application, the bit line 13 of the semiconductor device extends along the third direction c perpendicular to the substrate 11, the bit line 13 is connected to the first source-drain 21 of the multilayer transistor 2, the semiconductor layer 23 and the gate 25 extend along the first direction a, so that the semiconductor device has a vertical bit line structure which can improve the problem of excessive load caused by serious bit line coupling in the circuit.

[0199] In the embodiment of the present application, the transistor 2 is not limited to the NPN structure, but can also be the PNP type or the N+NN+ or P+PP+ doping type.

[0200] Optionally, in one embodiment of the present application, as shown in FIGS. 9a-23c and 25a-42d, along the first direction a, at least two bit lines 13 and at least two multilayer first capacitor electrodes 16 are located in the same column and arranged at intervals.

[0201] In the embodiment of the present application, the first capacitor electrode 16 serves as the lower plate of the capacitor, the gate 25 includes a word line, the bit line 13 extends along the third direction c perpendicular to the substrate 11, the bit line 13 is connected to the first source-drain 21 of the multilayer transistor 2, the multilayer first capacitor electrode 16 is connected to the plurality of second source-drains 22 respectively, the semiconductor layer 23 and the gate 25 extend along the first direction a, and the first source-drain 21 and the second source-drain 22 are both located on one side of the semiconductor layer 23 along the second direction b, so that the bit line 13 and the capacitor are located on the same side of the word line.

[0202] Optionally, in one embodiment of the present application, as shown in FIGS. 20a-20c, the semiconductor device further includes a multilayer ferroelectric layer 39 and a multilayer second capacitor electrode 41.

[0203] The multilayer second capacitor electrode 41 has a central axis perpendicular to the substrate 11.

[0204] The multilayer ferroelectric layer 39 surrounds the periphery of the second capacitor electrode 41, and the first capacitor electrode 16 surrounds the periphery of the multilayer ferroelectric layer 39.

[0205] In the embodiment of the present application, the second capacitor electrode 41 serves as the upper plate of the capacitor. The semiconductor device with vertical bit line provided in the embodiment of the present application utilizes the nonvolatile storage characteristic of the ferroelectric material, and can reduce the leakage requirement of the transistor 2, enhance the replaceability of the polysilicon transistor to the epitaxial silicon, thereby greatly reducing the production cost. Meanwhile, the vertical bit line structure can improve the situation of excessive load caused by the serious coupling of the bit line in the circuit, and can reduce the requirement for the capacity of the capacitor, thereby reducing the volume of the capacitor and improving the integration density.

[0206] Optionally, in one embodiment of the present application, as shown in FIGS. 32a-32d, the semiconductor device further comprises a multilayer ferroelectric layer 39 and a multilayer second capacitor electrode 41.

[0207] The multilayer second capacitor electrode 41 has an extending direction parallel to the substrate 11.

[0208] The multilayer ferroelectric layer 39 surrounds the periphery of the second capacitor electrode 41, and the first capacitor electrode 16 surrounds the periphery of the multilayer ferroelectric layer 39.

[0209] In the embodiment of the present application, the combination with the sleeve type capacitor can improve the capacity of the capacitor in unit surface size, thereby effectively improving the integration density.

[0210] Optionally, in one embodiment of the present application, as shown in FIGS. 32a-32d, 41d and 42a-42d, in one layer of the transistor 2 in the storage unit stack region, the semiconductor layers 23 of two adjacent transistors 2 are close to each other along the second direction b; or the semiconductor layer 23 of one transistor 2 is close to the bit line 13 of another adjacent transistor 2.

[0211] In the embodiment of the present application, the horizontal side gate controls the switching of the channel, and realizes the access of information between the bit line 13 and the capacitor, wherein the gate 25 is the horizontal side gate, and the semiconductor layer 23 can serve as the channel of the transistor 2.

[0212] Optionally, in one embodiment of the present application, as shown in FIGS. 14a-17c and FIGS. 34a-42d, the extending direction of the bit line 13 is perpendicular to the extending direction of the gate 25.

[0213] In the embodiment of the present application, the extending direction of the bit line 13 is perpendicular to the extending direction of the gate 25. Compared with the vertical gate structure, there is no harsh and complex manufacturing process of the bit line step, and other structures such as the semiconductor layer 23, the gate dielectric layer 24 and the gate 25 are arranged between the adjacent bit lines 13, thereby reducing the parasitic capacitance between the bit lines 13.

[0214] Based on the same inventive concept, the embodiment of the present application provides an electronic device comprising the semiconductor device of any of the above embodiments.

[0215] It should be noted that since the electronic device of the embodiment of the present application comprises the semiconductor device of the embodiment of the present application, the electronic device of the embodiment of the present application also has the above beneficial effects of the semiconductor device of the embodiment of the present application, which will not be repeated here.

[0216] In some optional embodiments of the present application, the electronic device comprises a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a smart mobile terminal, etc.

[0217] By applying the embodiment of the present application, at least the following beneficial effects can be achieved:

[0218] In the manufacturing method of the semiconductor device provided by the embodiment of the present application, the bit line 13 extends along the third direction c perpendicular to the substrate 11, and the semiconductor layer 23 and the gate 25 extend along the first direction a parallel to the substrate 11, so as to obtain a semiconductor device with vertical bit lines 13. The semiconductor device with vertical bit lines 13 manufactured by the embodiment of the present application is provided with a semiconductor layer 23, a gate dielectric layer 24 and a gate 25 between the two adjacent columns of bit lines 13, so that the distance between the two adjacent columns of bit lines 13 is relatively large, thereby reducing the parasitic capacitance between the bit lines 13, and further improving the circuit load problem. Moreover, in the present application, there is no harsh and complex bit line step manufacturing process when manufacturing the bit line 13, and the process is simple.

[0219] Those skilled in the art can understand that the steps, measures and schemes in the various operations, methods and processes discussed in the present application can be alternated, changed, combined or deleted. Further, other steps, measures and schemes in the various operations, methods and processes discussed in the present application can also be alternated, changed, rearranged, decomposed, combined or deleted. Further, the steps, measures and schemes in the various operations, methods and processes in the related art can also be alternated, changed, rearranged, decomposed, combined or deleted.

[0220] In the description of the present application, the directions or position relationships indicated by the words "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are the example directions or position relationships based on the drawings, which are used for the convenience of description or simplification of the description of the embodiments of the present application, and are not intended to indicate or imply that the devices or components referred to must have a particular orientation or be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0221] The terms "first", "second", etc. are used only for the purpose of description and do not connote or imply any relative importance or imply a specific number of features being referred to. Thus, features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0222] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood in a broad sense, for example, can be fixed connection, can also be detachable connection, or integral connection; can be direct connection, can also be indirect connection through intermediate medium, can be internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0223] In the description of the present application, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0224] The technical features of the above-described embodiments can be combined in any manner. In order to make the description simple, all possible combinations of the technical features in the above-described embodiments are not described, however, as long as the combinations of the technical features do not contradict, they should be considered as the scope of the present application.

[0225] The above-described embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent application. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of the patent protection of the present application should be subject to the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a stack structure on a side of a substrate, the stack structure comprising a plurality of first dielectric layers and a plurality of first sacrificial layers alternately stacked; patterning a plurality of bit lines arranged in an array, the bit lines extending along a third direction perpendicular to the substrate; patterning a plurality of first trenches arranged in an array; in a first direction, at least two of the first trenches are arranged in a same column with at least two of the bit lines; etching back a plurality of the first sacrificial layers exposed by sidewalls of the first trenches to form a corresponding plurality of first recesses; depositing first capacitor electrodes in the first recesses; and forming first isolation layers filling the first trenches; and forming a second trench extending along the first direction at the stack structure between two adjacent columns of the bit lines; etching back all of the first sacrificial layers exposed by sidewalls of the second trench to form a corresponding plurality of second recesses; and sequentially depositing a semiconductor layer, a gate dielectric layer, and a gate electrode in the second recesses. 2.The method of claim 1, wherein after forming the stack structure on the side of the substrate and before patterning the plurality of bit lines arranged in the array, further comprising: patterning the stack structure to form two third trenches on both sides of the stack structure along a second direction, the third trenches extending along the first direction; the first direction and the second direction are both perpendicular to the substrate; depositing second isolation layers in the third trenches; patterning the stack structure to form a plurality of fourth trenches arranged in an array, at least two of the fourth trenches being arranged in the first direction, the fourth trenches extending along a third direction; depositing second dielectric layers in the fourth trenches. 3.The method of claim 2, wherein patterning the plurality of bit lines arranged in the array comprises: patterning the stack structure to form a plurality of first vias arranged in an array; and forming the bit lines filling the first vias. 4.The method of claim 3, wherein after forming the plurality of first vias arranged in the array and before forming the bit lines filling the first vias, further comprising: etching back a plurality of the first sacrificial layers exposed by sidewalls of the first vias to form a corresponding plurality of third recesses; synchronously depositing a plurality of first source-drain electrodes in the plurality of third recesses. 5.The method of claim 1, wherein patterning the plurality of first trenches arranged in an array comprises: patterning the stack structure to form a plurality of first trenches arranged in an array; and after forming the corresponding plurality of first recesses and before depositing the first capacitor electrodes in the first recesses, further comprising: depositing second source-drain electrodes in the first recesses. 6.The method of claim 5, wherein after sequentially depositing the semiconductor layer, the gate dielectric layer, and the gate electrode in the second recesses, further comprising: depositing third isolation layers in the second trenches; removing the first isolation layers in the first trenches; and sequentially depositing a ferroelectric layer and a second capacitor electrode in the first trenches. ​ ​ ​ ​ 7. The method of claim 2, wherein the patterning to form the plurality of bit lines in an array arrangement comprises: patterning the second isolation layer to form a plurality of first vias in an array arrangement; etching back the plurality of first sacrificial layers exposed by the sidewalls of the first vias to form a corresponding plurality of third recesses; and simultaneously depositing a plurality of first source-drain electrodes in the plurality of third recesses; and forming a bit line filling the first vias and electrically connected to the plurality of first source-drain electrodes.

8. The method of claim 3, wherein after forming the bit line filling the first vias, and before patterning to form the plurality of first trenches in an array arrangement, further comprising: depositing a fourth dielectric layer on a side of the stack structure, the second isolation layer, the bit line, and the second dielectric layer away from the substrate; and patterning to form the plurality of first trenches in an array arrangement comprises: patterning the second isolation layer to form the plurality of first trenches in an array arrangement.

9. The method of claim 8, wherein after forming the corresponding plurality of first recesses, and before forming the first isolation layer filling the first trenches, further comprising: depositing a first capacitor electrode on sidewalls of the first trenches and the first recesses; and after forming the first isolation layer filling the first trenches, and before opening the second trench extending in the first direction at the stack structure between two adjacent columns of the bit lines, further comprising: removing the first capacitor electrode from the sidewalls of the first trenches; and removing the first isolation layer from the first recesses; depositing a ferroelectric layer covering the first capacitor electrode in the first recesses; depositing a second capacitor electrode in the first recesses and the first trenches; and depositing a protection layer on a side of the fourth dielectric layer, the ferroelectric layer, and the second capacitor electrode away from the substrate.

10. The method of claim 9, wherein after sequentially depositing a semiconductor layer, a gate dielectric layer, and a gate electrode in the second recesses, further comprising: removing the semiconductor layer extending in the second direction in the second recesses to form fourth recesses; and depositing a third isolation layer in the second trenches and the fourth recesses.

11. The method of claim 6 or 10, wherein after sequentially depositing a ferroelectric layer and a second capacitor electrode in the first trenches, or after depositing a third isolation layer in the second trenches and the fourth recesses, further comprising: opening a fifth trench extending in a third direction at the second dielectric layer between any two adjacent memory cell stack regions in the first direction; etching back to remove the semiconductor layer exposed by sidewalls of the fifth trench; and depositing a third dielectric layer in the fifth trench.

12. The method of claim 11, wherein at least one of a metal, a metal alloy, a metal nitride, a metal-semiconductor compound, and an electrically conductive doped semiconductor; a material of the bit line comprises at least one of a metal, a metal alloy, a metal nitride, a metal silicide, a metal carbide, and an electrically conductive doped semiconductor material; The material of the gate includes: ​ ​ The material of the first, second and third dielectric layers each comprises at least one of an oxide or a nitride; the oxide comprises SiO2, F-doped porous SiO2, C-doped porous SiO2, HfOx, and The material of the ferroelectric layer comprises at least one of hafnium-based oxide, lead zirconate titanate, and strontium bismuth tantalate.

13. A semiconductor device, comprising: a substrate; a plurality of first dielectric layers and a plurality of transistors alternately stacked on one side of the substrate; the transistors each comprise a semiconductor layer, a gate dielectric layer and a gate electrode extending along a first direction, and a first source / drain and a second source / drain each located on one side of the semiconductor layer along a second direction; the first direction intersects the second direction and is parallel to the substrate; a plurality of bit lines extending along a third direction perpendicular to the substrate, each connected to the first source / drain of the transistors in the same memory cell stack region; and a plurality of first capacitor electrodes each connected to a plurality of the second source / drain.

14. The semiconductor device of claim 13, wherein in the first direction, at least two of the bit lines and at least two of the first capacitor electrodes are located in the same column and are spaced apart.

15. The semiconductor device of claim 13, further comprising: a plurality of second capacitor electrodes each having a central axis perpendicular to the substrate; a plurality of ferroelectric layers each surrounding the second capacitor electrode and each surrounded by the first capacitor electrode.

16. The semiconductor device of claim 13, further comprising: a plurality of second capacitor electrodes each extending parallel to the substrate; and a plurality of ferroelectric layers each surrounding the second capacitor electrode and each surrounded by the first capacitor electrode.

17. The semiconductor device of claim 13, wherein in one of the transistors in the memory cell stack region, along the second direction, the relationship between two adjacent transistors is selected from the group consisting of the semiconductor layers of the two adjacent transistors being close to each other and the semiconductor layer of one transistor being close to the bit line of the other adjacent transistor.

18. The semiconductor device of claim 13, wherein the bit line is perpendicular to the extension direction of the gate electrode.

19. An electronic device comprising a semiconductor device selected from the group consisting of the semiconductor device manufactured by the semiconductor manufacturing method of any one of claims 1-12 and the semiconductor device of any one of claims 13-18. ​

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