Display panel and display apparatus

Abstract

A display panel and a display apparatus. The display panel comprises a display area and a non-display area surrounding the display area, the non-display area comprising a binding area located on a side of the display area and a first peripheral area located between the binding area and the display area; a driving circuit located in the non-display area and electrically connected to a plurality of sub-pixels of the display area; a plurality of data lines located in the display area and extending to the non-display area, the plurality of sub-pixels being electrically connected to the plurality of data lines; a plurality of binding bonding pads located in the binding area; a first power line located in the non-display area and electrically connected to the binding bonding pads; and a plurality of signal transmission lines at least located in the first peripheral area and electrically connected to the driving circuit, in the direction perpendicular to the display panel, the plurality of signal transmission lines and the first power line overlapping each other, wherein the ratio of the overlapping areas of any two signal transmission lines and the first power line is greater than or equal to 0.95 but less than or equal to 1.05.

Description

Display panel and display device

[0001] The present application claims priority to the Chinese patent application No. 202410741142.7, filed on June 7, 2024, and entitled "Display panel and display device", the content of which is understood to be incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to, but is not limited to, display technology, and in particular to a display panel and a display device. BACKGROUND

[0003] An organic light emitting diode (OLED) is an active light emitting display device, which has the advantages of self-emission, wide viewing angle, high contrast, low power consumption, and extremely high response speed. With the continuous development of display technology, a display device using an OLED as a light emitting element and controlled by a thin film transistor (TFT) has become a mainstream product in the current display field. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, the embodiments of the present disclosure provide a display panel, comprising: a display area and a non-display area surrounding the display area, the non-display area comprising a binding area located at one side of the display area and a first peripheral area located between the binding area and the display area; a plurality of sub-pixels located in the display area; a plurality of driving signal lines located in the display area and extending along a first direction, the plurality of driving signal lines being electrically connected with the plurality of sub-pixels; a driving circuit located in the non-display area, the driving circuit being electrically connected with the plurality of driving signal lines; a plurality of data lines located in the display area and extending to the non-display area along a second direction, the plurality of sub-pixels and the plurality of data lines being electrically connected, the first direction and the second direction intersecting; a plurality of first power supply sub-lines located in the display area and extending along the second direction, the plurality of sub-pixels being electrically connected with the plurality of first power supply sub-lines; a plurality of binding pads located in the binding area; a first power supply line located in the non-display area, the first power supply line being electrically connected with the plurality of first power supply sub-lines and the binding pads; a plurality of signal transmission lines located at least in the first peripheral area, the plurality of signal transmission lines being electrically connected with the driving circuit; in a direction perpendicular to the display panel, the plurality of signal transmission lines and the first power supply line overlap with each other; wherein a ratio of an overlapping area of any two of the plurality of signal transmission lines and the first power supply line is greater than or equal to 0.95 and less than or equal to 1.05.

[0006] In an exemplary embodiment, the first power supply line comprises a first main body part extending along the first direction and a first extension part extending along the second direction, the first main body part being located in the first peripheral area, the first extension part being located in the first peripheral area and extending to the binding area, one end of the first extension part being connected with the first main body part, the other end of the first extension part being electrically connected with the binding pad; the first direction is parallel to an extension direction of an edge of the display area close to the first peripheral area; each of the plurality of signal transmission lines comprises a first straight line part, a second straight line part and a connecting part, the first straight line part and the second straight line part extending along the first direction, the second straight line part being located on one side of the first straight line part in the second direction, the first straight line part and the second straight line part being connected with each other through the connecting part, the first straight line part being electrically connected with the driving circuit, the second straight line part being configured to be electrically connected with an integrated circuit; the first main body part overlaps with the first straight line part of a part of the plurality of signal transmission lines, the first extension part overlaps with the second straight line part of the plurality of signal transmission lines.

[0007] In an exemplary embodiment, the first power line further comprises at least one first compensation portion connected with the first extension portion, the first compensation portion overlaps the second linear portion of another portion of the signal transmission lines in a direction perpendicular to the display panel; the ratio of the overlapping area of any two signal transmission lines to the first power line is greater than or equal to 0.95 and less than or equal to 1.05, including: the overlapping area of each signal transmission line to the first main portion is a first area, the overlapping area of each signal transmission line to the first compensation portion is a second area, the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.05.

[0008] In an exemplary embodiment, the first compensation portion is distributed on one side or both sides of the first extension portion along the first direction, and a single first compensation portion overlaps the second linear portion of at least one signal transmission line.

[0009] In an exemplary embodiment, the first power line further comprises at least one second compensation portion connected with the first extension portion, the second compensation portion and the first compensation portion are distributed on both sides of the first extension portion along the first direction; the second compensation portion overlaps the second linear portion of another portion of the signal transmission lines in a direction perpendicular to the display panel; the ratio of the overlapping area of any two signal transmission lines to the first power line is greater than or equal to 0.95 and less than or equal to 1.05, including: the overlapping area of each signal transmission line to the first main portion is a first area, the sum of the overlapping area of each signal transmission line to the first compensation portion and the second compensation portion is a second area, the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.05.

[0010] In an example embodiment, the first power line further comprises at least one third compensation portion, the third compensation portion overlaps with the second straight portion of a part of the signal transmission lines, the signal transmission lines overlapping with the third compensation portion are the same as the signal transmission lines overlapping with the first main body portion; the ratio of the overlapping area of any two signal transmission lines and the first power line is greater than or equal to 0.95 and less than or equal to 1.05, including: the sum of the overlapping area of each signal transmission line and the first main body portion and the third compensation portion is a first area, the overlapping area of each signal transmission line and the first compensation portion is a second area, the ratio of the first area and the second area is greater than or equal to 0.95 and less than or equal to 1.05; or, the sum of the overlapping area of each signal transmission line and the first main body portion and the third compensation portion is a first area, the sum of the overlapping area of each signal transmission line and the first compensation portion and the second compensation portion is a second area, the ratio of the first area and the second area is greater than or equal to 0.95 and less than or equal to 1.05.

[0011] In an example embodiment, a plurality of the third compensation portions are distributed on both sides of the first extension portion along the first direction, and a single third compensation portion overlaps with at least one second straight portion.

[0012] In an example embodiment, in the second direction, the line width of the second straight portion of the signal transmission line not overlapping with the first main body portion is greater than the line width of the second straight portion of the signal transmission line overlapping with the first main body portion.

[0013] In an example embodiment, the line width of the second straight portion of the signal transmission line not overlapping with the first main body portion is equal, and the line width of the second straight portion of the signal transmission line overlapping with the first main body portion is equal.

[0014] In an example embodiment, the first extension portion comprises a first narrow neck portion and a first wide neck portion, in the first direction, the line width of the first narrow neck portion is less than the line width of the first wide neck portion; in the direction perpendicular to the display panel, the second straight portion of the signal transmission line overlapping with the first main body portion overlaps with the first narrow neck portion; the second straight portion of the signal transmission line not overlapping with the first main body portion overlaps with the first wide neck portion.

[0015] In an example embodiment, the first power line comprises one first main body portion and two first extension portions, the two first extension portions are arranged along the first direction and electrically connected with different binding pads; the two first extension portions are respectively located on both sides of the integrated circuit along the first direction.

[0016] In an exemplary embodiment, the display panel further comprises a second power supply line, the second power supply line is located in the non-display area and surrounds the display area, the second power supply line is located on both sides of the first extension part along the first direction in the part of the first peripheral area, and the second power supply line and the plurality of signal transmission lines are mutually overlapped.

[0017] In an exemplary embodiment, the part of the first peripheral area where the second power supply line is located comprises a second main body part extending along the first direction and a second extension part extending along the second direction, one end of the second extension part is connected with the second main body part, and the other end of the second extension part is electrically connected with the binding pad; in the direction perpendicular to the display panel, the second main body part overlaps with the connection part, and the second extension part overlaps with the second straight line part.

[0018] In an exemplary embodiment, the non-display area further comprises a second peripheral area surrounding the display area and away from one side of the binding area; the second peripheral area comprises the driving circuit, and the driving circuit comprises at least one of a gate driving circuit or a light-emitting control driving circuit.

[0019] In an exemplary embodiment, the plurality of signal transmission lines comprise at least one of a gate driving control line and a light-emitting control line; the gate driving control line is electrically connected with the gate driving circuit, and the light-emitting control line is electrically connected with the light-emitting control driving circuit.

[0020] In a second aspect, the embodiments of the present disclosure provide a display device comprising the display panel.

[0021] The display panel provided by the embodiments of the present disclosure makes the ratio of the overlapping area of any two signal transmission lines and the first power supply line in the first peripheral area greater than or equal to 0.95 and less than or equal to 1.05, so that the capacitance generated by each signal transmission line in the plurality of signal transmission lines and the first power supply line due to overlapping is similar in size, thereby reducing the difference between the signals transmitted by the plurality of signal transmission lines, ensuring the display effect of the display panel, and solving the problem of uneven brightness of the display panel.

[0022] Other aspects can become apparent from the following drawings and detailed description.

[0023] SUMMARY

[0024] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0025] Figure 1 is a schematic diagram of the structure of the display panel in an embodiment of this disclosure;

[0026] Figure 2 is a schematic diagram of the display panel structure in yet another exemplary embodiment;

[0027] Figure 3 is an enlarged schematic diagram of the dashed area C in Figure 2 in an exemplary embodiment;

[0028] Figure 4 is an enlarged schematic diagram of the dashed area C in Figure 2 in yet another exemplary embodiment;

[0029] Figure 5 is an enlarged schematic diagram of the dashed area C in Figure 2 in yet another exemplary embodiment;

[0030] Figure 6 is an enlarged schematic diagram of the dashed area C in Figure 2 in yet another exemplary embodiment;

[0031] Figure 7 is an enlarged schematic diagram of the dashed region C in Figure 2 in yet another exemplary embodiment;

[0032] Figure 8 is an equivalent circuit diagram of the gate drive circuit in an exemplary embodiment.

[0033] Detailed Explanation

[0034] This disclosure describes several embodiments, but these descriptions are exemplary and not restrictive, and many more embodiments and implementations are possible within the scope of the embodiments described herein, which will be apparent to those skilled in the art. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with or in lieu of any other feature or element in any other embodiment.

[0035] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0036] Furthermore, in describing representative embodiments, the specification can have presented the method and / or process as a particular sequence of steps. However, to the extent that the method or process depends on the performance of such steps, the method or process is not limited to the performance of the steps in the specific order described. One of ordinary skill in the art, based on the present description and teachings, can recognize that other steps can be performed and / or described in other sequences, as appropriate. The recitation of steps in the claims does not imply that the order of the steps is important to the claims. Furthermore, the claims can be written to cover a process performed in different orders or permutations, as the spirit and scope of the disclosure will encompass such orderings and permuta tions.

[0037] In the drawings, the size, the thickness or the region of one or plural constituent elements, a layer, or the like, is sometimes exaggerated for the sake of clarity in some cases. Furthermore, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to shapes or numerical values shown in the drawings and the like.

[0038] The ordinal numbers "first", "second", "third", and the like, in the specification are used to avoid confusion among constituent elements, and are not intended to indicate or imply a relative importance of the constituent elements. "A plurality of" in the present disclosure means two or more.

[0039] In the present specification, words "central", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, which indicate the orientation or positional relationship of the constituent elements, are used to describe the positional relationship of the constituent elements with reference to the drawings, and are merely intended to facilitate the description of the specification and simplify the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction of the constituent elements described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0040] In the present specification, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connected" should be interpreted broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate, or communication between two elements inside. For those of ordinary skill in the art, the meaning of the above terms in the present disclosure can be understood according to the situation.

[0041] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain terminal, a drain region, or a drain electrode) and the source electrode (a source terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region refers to a region where current flows mainly.

[0042] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In the case of using a transistor having opposite polarity or in the case of changing the direction of current flowing in a circuit, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other.

[0043] In this specification, "electrically connected" includes the case where components are connected through an element having some function. The element having some function is not particularly limited as long as it can transmit an electrical signal between components to be connected. Examples of the element having some function include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0044] In this specification, "parallel" refers to a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" refers to a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0045] Embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0046] FIG. 1 is a structural schematic diagram of a display panel in an embodiment of the present disclosure. As shown in FIG. 1, the display panel provided in the embodiment includes a display area 100 and a non-display area located at the periphery of the display area 100. The non-display area includes a binding area 700 located at one side of the display area 100 along a second direction Y, a first peripheral area 200 located between the display area 100 and the binding area 700, and a second peripheral area 300 located at the periphery of the display area 100 and away from one side of the binding area 400. The first peripheral area 200 and the second peripheral area 300 are in communication and surround the display area 100. The display area 100 includes at least a plurality of sub-pixels P arranged regularly, for example, the plurality of sub-pixels P can be arranged in an array along a first direction X and the second direction Y, and the first direction X and the second direction Y are perpendicular to each other. The plurality of sub-pixels P are configured to display dynamic pictures or still images, and the display area 100 can be referred to as an active area (AA). A column of sub-pixels P arranged along the second direction Y can be connected to the same data line 101, and a plurality of data lines 101 can be connected to an integrated circuit 120 subsequently bound to the display panel. The integrated circuit 120 provides a data signal to the corresponding sub-pixel P through the data line 101 to drive the sub-pixel P to display. In an exemplary embodiment, the display panel can be deformable, for example, curled, bent, folded or rolled up. The display panel includes an upper frame and a lower frame oppositely arranged along the second direction Y, and a left frame and a right frame oppositely arranged along the first direction X. The lower frame is the frame on the side where the binding area 700 is located, and the frame opposite to the binding area 700 along the second direction Y can be referred to as the upper frame. The right frame is located at one side of the left frame along the first direction X.

[0047] In an exemplary embodiment, the shape of the display area 100 can be a quadrilateral, a circle, an ellipse, a polygon of other shapes, or an irregular shape, and the corner shape of the display area 100 can be a rounded corner. The present disclosure does not limit the shape of the display area 100. In an exemplary embodiment, the shape of the display area edge at different frames is different from the shape of the display area, for example, it can be a straight line, a curve, a broken line, or other shapes. The present disclosure does not limit the shape of the display area edge.

[0048] In an example embodiment, the first peripheral area 200 can include, in sequence along a direction away from the display area 100, a fan-out area 400, a bending area 500, and a driving chip area 600. The fan-out area 400 is connected to the display area 100 and can include at least a plurality of data lead-out lines. The signal lines such as the power lines, the data lines 101 of the display area 100 can pass through the fan-out area 400 in a fan-out manner and be connected to corresponding signal providing ends. A subsequent integrated circuit (IC) 120 can be connected to the driving chip area 600 in a binding manner. The integrated circuit 120 is configured to be connected to the plurality of data lead-out lines. The binding area 700 can include at least a plurality of bonding pads 701. A flexible printed circuit (FPC) or a chip on flex (COF) can be connected to the bonding pads 701 of the binding area 700 in a binding manner.

[0049] In an example embodiment, the first peripheral area 200 includes at least a power line configured to transmit a voltage signal to the plurality of sub-pixels P. As shown in FIG. 1, the power line can include a first power line 210. The first power line 210 can be connected to a high-voltage power line (VDD) of the display area 100 and configured to transmit a high-voltage signal, for example, a positive voltage signal, to the plurality of sub-pixels P of the display area 100. The first power line 210 is connected to the bonding pads 701 of the binding area 700.

[0050] In an example embodiment, the second peripheral area 300 includes at least a circuit area 301. The circuit area 301 can be disposed on both sides of the display area 100 along the first direction X and connected to the display area 100. The circuit area 301 includes a plurality of driving circuits, for example, gate driving circuits. A plurality of signal transmission lines S1 of the plurality of driving circuits can pass through the fan-out area 400 in a fan-out manner and be connected to the integrated circuit 120, so as to receive signals from the integrated circuit 120 and drive the sub-pixels P.

[0051] With the improvement of the display quality requirement of the display panel, the resolution and refresh rate of the display panel are higher and higher, the number of sub-pixels P of each row of the display area 100 along the first direction X increases, the load of the wire of the driving circuit connected with the row of sub-pixels P increases, the rising edge and falling edge in the pixel charging process increase, which leads to the shortening of the charging time of the pixel and the poor display effect. In the structure shown in FIG. 1, the number of signal transmission lines S1 increases, for example, four clock signal lines are used to provide clock signals for the gate driving circuit. However, in the case that the frame of the display panel is narrowed, the size of the fan-out area 400 along the second direction Y is small, which is not conducive to the arrangement of the wires in the fan-out area 400. As shown in FIG. 1, taking the signal transmission line S1 as the clock signal line as an example, part of the clock signal lines overlap with the first power line 210, and the other part of the clock signal lines do not overlap with the first power line 210. Capacitance will be generated at the overlapping part of the clock signal line and the first power line 210, so that the loads on different clock signal lines are different, which will further lead to different charging times of the pixels by different clock signal lines, and the brightness of the display panel is uneven, especially the brightness difference at low gray scale is obvious.

[0052] The display panel provided by the embodiment of the present disclosure comprises: a display area and a non-display area surrounding the display area, the non-display area comprising a binding area located at one side of the display area and a first peripheral area located between the binding area and the display area; a plurality of sub-pixels located in the display area; a plurality of driving signal lines located in the display area and extending along a first direction, the plurality of driving signal lines being electrically connected with the plurality of sub-pixels; a driving circuit located in the non-display area, the driving circuit being electrically connected with the plurality of driving signal lines; a plurality of data lines located in the display area and extending to the non-display area along a second direction, the plurality of sub-pixels and the plurality of data lines being electrically connected, the first direction and the second direction intersecting; a plurality of first power sub-lines located in the display area and extending along the second direction, the plurality of sub-pixels being electrically connected with the plurality of first power sub-lines; a plurality of binding pads located in the binding area; a first power line located in the non-display area, the first power line being electrically connected with the plurality of first power sub-lines and the binding pads; a plurality of signal transmission lines located at least in the first peripheral area, the plurality of signal transmission lines being electrically connected with the driving circuit; in the direction perpendicular to the display panel, the plurality of signal transmission lines and the first power line overlap with each other; wherein the ratio of the overlapping area of any two of the plurality of signal transmission lines and the first power line is greater than or equal to 0.95 and less than or equal to 1.05.

[0053] The display panel provided by the embodiments of the present disclosure is characterized in that the ratio of the overlapping area of any two signal transmission lines to the first power line located in the first peripheral area is greater than or equal to 0.95 and less than or equal to 1.05, so that the capacitance generated by the overlapping of each signal transmission line in the plurality of signal transmission lines and the first power line is similar in size, thereby reducing the difference in signals transmitted by the plurality of signal transmission lines and ensuring the display effect of the display panel.

[0054] In an example embodiment, the first power line includes a first main body portion extending along the first direction and a first extension portion extending along a second direction, the first main body portion is located in the first peripheral area, the first extension portion is located in the first peripheral area and extends to the binding area, one end of the first extension portion is connected to the first main body portion, and the other end of the first extension portion is electrically connected to the binding pad; the first direction is parallel to the extension direction of the edge of the display area close to the first peripheral area; each of the plurality of signal transmission lines includes a first straight line portion, a second straight line portion, and a connecting portion, the first straight line portion and the second straight line portion extend along the first direction, the second straight line portion is located on one side of the second direction of the first straight line portion, the first straight line portion and the second straight line portion are connected to each other through the connecting portion, the first straight line portion is electrically connected to the driving circuit, and the second straight line portion is configured to be electrically connected to an integrated circuit; the first main body portion overlaps the first straight line portion of a part of the plurality of signal transmission lines, and the first extension portion overlaps the second straight line portion of the plurality of signal transmission lines.

[0055] In an example embodiment, the first power line further includes at least one first compensation portion, the first compensation portion is connected to the first extension portion, and in a direction perpendicular to the display panel, the first compensation portion overlaps the second straight line portion of another part of the plurality of signal transmission lines; the ratio of the overlapping area of any two signal transmission lines to the first power line is greater than or equal to 0.95 and less than or equal to 1.05, including: the overlapping area of each signal transmission line and the first main body portion is a first area, the overlapping area of each signal transmission line and the first compensation portion is a second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.05.

[0056] In an example embodiment, the first compensation portion is distributed on one side or both sides of the first extension portion along the first direction, and a single first compensation portion overlaps the second straight line portion of at least one signal transmission line.

[0057] In an exemplary embodiment, the first power line further comprises at least one second compensation portion, the second compensation portion is connected with the first extension portion, the second compensation portion and the first compensation portion are distributed on both sides of the first extension portion along the first direction; in a direction perpendicular to the display panel, the second compensation portion overlaps with another part of the second linear portions of the signal transmission lines; the ratio of the overlapping area of any two signal transmission lines and the first power line is greater than or equal to 0.95 and less than or equal to 1.05, including: the overlapping area of each signal transmission line and the first main body portion is a first area, the sum of the overlapping areas of each signal transmission line and the first compensation portion and the second compensation portion is a second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.05.

[0058] In an exemplary embodiment, the first power line further comprises at least one third compensation portion, the third compensation portion overlaps with the second linear portions of a part of the signal transmission lines, and the signal transmission lines overlapping with the third compensation portion are the same as the signal transmission lines overlapping with the first main body portion; the ratio of the overlapping area of any two signal transmission lines and the first power line is greater than or equal to 0.95 and less than or equal to 1.05, including: the sum of the overlapping areas of each signal transmission line and the first main body portion and the third compensation portion is a first area, the overlapping area of each signal transmission line and the first compensation portion is a second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.05; or, the sum of the overlapping areas of each signal transmission line and the first main body portion and the third compensation portion is a first area, the sum of the overlapping areas of each signal transmission line and the first compensation portion and the second compensation portion is a second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.05.

[0059] In an exemplary embodiment, a plurality of the third compensation portions are distributed on both sides of the first extension portion along the first direction, and a single third compensation portion overlaps with at least one second linear portion.

[0060] In an exemplary embodiment, in the second direction, the line width of the second linear portion of the signal transmission line that does not overlap with the first main body portion is greater than the line width of the second linear portion of the signal transmission line overlapping with the first main body portion.

[0061] In an example embodiment, the line width of the second straight portion of the signal transmission line not overlapping with the first main portion is equal to the line width of the second straight portion of the signal transmission line overlapping with the first main portion.

[0062] In an example embodiment, the first extension portion includes a first narrow neck portion and a first wide neck portion, the line width of the first narrow neck portion is smaller than the line width of the first wide neck portion in the first direction, the second straight portion of the signal transmission line overlapping with the first main portion overlaps with the first narrow neck portion in a direction perpendicular to the display panel, and the second straight portion of the signal transmission line not overlapping with the first main portion overlaps with the first wide neck portion.

[0063] In an example embodiment, the first power supply line includes one first main portion and two first extension portions, the two first extension portions are arranged in the first direction and electrically connected with different bonding pads, and the two first extension portions are respectively located on both sides of the integrated circuit in the first direction.

[0064] In an example embodiment, the display panel further includes a second power supply line, the second power supply line is located in the non-display area and surrounds the display area, the second power supply line is located in the part of the first peripheral area on both sides of the first extension portion in the first direction, and the second power supply line overlaps with each of the plurality of signal transmission lines.

[0065] In an example embodiment, the part of the first peripheral area where the second power supply line is located includes a second main portion extending in the first direction and a second extension portion extending in the second direction, one end of the second extension portion is connected with the second main portion, and the other end of the second extension portion is electrically connected with the bonding pad; in a direction perpendicular to the display panel, the second main portion overlaps with the connection portion, and the second extension portion overlaps with the second straight portion.

[0066] In an example embodiment, the non-display area further includes a second peripheral area surrounding the display area and away from one side of the bonding area; the second peripheral area includes the driving circuit, and the driving circuit includes at least one of a gate driving circuit or a light emitting control driving circuit.

[0067] In an example embodiment, the plurality of signal transmission lines include at least one of a gate driving control line and a light emitting control line; the gate driving control line is electrically connected with the gate driving circuit, and the light emitting control line is electrically connected with the light emitting control driving circuit.

[0068] FIG. 2 is a structural schematic diagram of a display panel in another exemplary embodiment. As shown in FIG. 2, the display area 100 includes a plurality of first power supply sub-lines 230 extending along the second direction Y, a column of sub-pixels P arranged along the second direction Y is electrically connected to the same first power supply sub-line 230, and the plurality of first power supply sub-lines 230 are electrically connected to the first power supply line 210. The power supply lines of the first peripheral area 200 further include a second power supply line 220 connected to the low-voltage power supply line (VSS) of the second peripheral area 300 to transmit a low-voltage signal, for example, a negative voltage signal, to the plurality of sub-pixels P of the display area 100. The second power supply line 220 can be distributed in the first peripheral area 200 and the second peripheral area 300, and the second power supply line 220 can surround the display area 100. The first power supply line 210 and the second power supply line 220 are respectively connected to the bonding pad 701 of the bonding area 700.

[0069] In the exemplary embodiment, the plurality of drive circuits can at least include a gate drive circuit (Gate GOA) 310 and an emission control drive circuit (EM GOA) 320. The display area 100 further includes a plurality of drive signal lines extending along the first direction X, and the pixel drive circuit of a row of sub-pixels P arranged along the first direction X is electrically connected to the same drive signal line. The plurality of drive signal lines can include a scan signal line (Gate line) 330, an emission signal line (EM line) 340, a reset signal line (not shown in the figure), and the like. As shown in FIG. 2, the scan signal line 330 and the gate drive circuit 310 are electrically connected, and the emission signal line 340 and the emission control drive circuit 320 are electrically connected.

[0070] In the exemplary embodiment, the plurality of signal transmission lines are at least located in the first peripheral area 200, one end of the plurality of signal transmission lines is electrically connected to the drive circuit, and the other end can be electrically connected to the integrated circuit 120 or the bonding pad 701 to receive the corresponding signal. For example, the plurality of signal transmission lines can include the gate drive control lines of the gate drive circuit 310, the gate drive control lines include a clock signal line T, a high-voltage transmission line, and a low-voltage transmission line, and the like. The clock signal line T can be connected to the first clock signal end GCK1 and the second clock signal end GCK2 of the gate drive circuit 310, the high-voltage transmission line can connect the first power supply line 210 and the first power supply end VGH of the gate drive circuit 310, and the low-voltage transmission line can connect the second power supply line 220 and the second power supply end VGL. The plurality of signal transmission lines can further include the emission control line 340 of the emission control drive circuit 320, and the like. In the following figures, the signal transmission line is taken as the clock signal line T as an example to describe the scheme of the embodiments of the present disclosure, and the type of the signal transmission line is not limited in the present disclosure.

[0071] In the example embodiment, the plurality of clock signal lines T of the gate drive circuit 310 and / or the light-emitting control drive circuit can pass through the fan-out region 400 in the manner of fan-out routing and be electrically connected with the integrated circuit 120. In FIG. 2, the plurality of clock signal lines T are overlapped with the first power supply line 210 and the second power supply line 220, respectively. Since the line width of the routing is substantially uniform in the direction perpendicular to the direction in which the routing extends, in the case where the first power supply line 210 or the second power supply line 220 is overlapped with the plurality of signal transmission lines T, the capacitance generated at the overlapping of the routing is substantially the same, and no difference in load of the different clock signal lines T is caused.

[0072] In the example embodiment, the plurality of clock signal lines T, the first power supply line 210, and the second power supply line 220, and the like on the display panel can be arranged symmetrically left and right along the first direction X, and the present disclosure does not limit this. FIG. 3 is an enlarged schematic view of the dashed area C of FIG. 2 in the example embodiment. As shown in FIG. 3, the first power supply line 210 of the first peripheral area 200 includes a first main body portion 211 and a first extension portion 212, the first main body portion 211 can extend along the first direction X, the first extension portion 212 can extend along the second direction Y, one end of the first extension portion 212 can be connected to the first main body portion 211, and the other end of the first extension portion 212 can be connected to the corresponding binding pad 701 to receive the corresponding high-voltage signal. In the example embodiment, the first direction X can be the extension direction parallel to the edge of the display area 100 close to the first peripheral area 200, and the second direction Y can be perpendicular to the first direction X. The first peripheral area 200 can include a plurality of clock signal lines T arranged in sequence along the second direction Y. In the direction perpendicular to the display panel, the first extension portion 212 overlaps the plurality of clock signal lines T, the first main body portion 211 overlaps a part of the plurality of clock signal lines T, and the first power supply line 210 further includes a first compensation portion 213 connected to the first extension portion 212, the first compensation portion 213 overlaps another part of the plurality of clock signal lines T, the overlapping area of each clock signal line T with the first main body portion 211 is a first area, and the overlapping area of each clock signal line T with the first compensation portion 213 is a second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.05. In this embodiment, by providing the first compensation portion 213 on the first power supply line 210, and setting the first area of each clock signal line T overlapping the first main body portion 211 and the second area of each clock signal line T overlapping the first compensation portion 213 to be approximately equal, the first compensation portion 213 compensates for the clock signal lines T that do not overlap the first main body portion 211, so that the overlapping area of each clock signal line T with the first power supply line 210 is greater than or equal to 0.95 and less than or equal to 1.05, avoiding the inconsistency in the transmission of the plurality of clock signal lines T caused by the different capacitances at the overlapping positions, and helping to ensure the uniformity of the display brightness of the display panel. Furthermore, by providing the first compensation portion 213, the path for water vapor to invade the display panel can be increased, which helps to prevent water vapor from invading and improves the display defects caused by water vapor invasion of the display panel.

[0073] In the example embodiment, the first area is equal to the second area.

[0074] In an example embodiment, as shown in FIG. 3, the plurality of clock signal lines T includes the first signal line 11, the second signal line 12, the third signal line 13, and the fourth signal line 14 arranged in sequence along the second direction Y. In a direction perpendicular to the display panel, the first main body portion 211 can overlap with the first signal line 11 and the second signal line 12, and there is no overlap with the third signal line 13 and the fourth signal line 14. The first compensation portion 213 overlaps with the third signal line 13 and the fourth signal line 14, and there is no overlap with the first signal line 11 and the second signal line 12. The first extension portion 212 overlaps with the first signal line 11, the second signal line 12, the third signal line 13, and the fourth signal line 14. In other embodiments, the plurality of clock signal lines T can include n signal lines, the first main body portion 211 can overlap with 1 to n-1 signal lines, and the first compensation portion 213 overlaps with the remaining signal lines of the n signal lines. n is an integer greater than or equal to 2, for example, n can be greater than or equal to 4, and the present disclosure does not limit this.

[0075] In an example embodiment, as shown in FIG. 3, each clock signal line T can include a first straight portion L1, a second straight portion L2, and a connecting portion L3. The first straight portion L1 and the second straight portion L2 can extend along the first direction X. The second straight portion L2 is located on one side of the first straight portion L1 along the second direction Y. The first straight portion L1 and the second straight portion L2 are connected to each other through the connecting portion L3. The first straight portion L1 can be electrically connected to the driving circuit, and the second straight portion L2 can be electrically connected to the integrated circuit 120 in the subsequent process. The first main body portion 211 can overlap with the first straight portion L1 of the first signal line 11 and the first straight portion L1 of the second signal line 12. The first compensation portion 213 can overlap with the second straight portion L2 of the third signal line 13 and the second straight portion L2 of the fourth signal line 14. The first extension portion 212 overlaps with the second straight portion L2 of the first signal line 11, the second straight portion L2 of the second signal line 12, the second straight portion L2 of the third signal line 13, and the second straight portion L2 of the fourth signal line 14. In other embodiments, the first power supply line 210 can include a plurality of first compensation portions 213, and each first compensation portion 213 can overlap with at least one second straight portion L2, and the present disclosure does not limit this.

[0076] In an example embodiment, the first compensation portion 213 can be located on one side of the first extension portion 212 along the first direction X, for example, the first compensation portion 213 can be located on the left side or the right side of the first extension portion 212 along the first direction X, or a plurality of first compensation portions 213 can be distributed on one side or both sides of the first extension portion 212 along the first direction X. The orthographic projection of the first compensation portion 213 on the display panel can be a rectangle, a circle, an ellipse, a triangle, other shapes of quadrilaterals and polygons, and irregular shapes, and the present disclosure does not limit this.

[0077] In the example embodiment, the second power supply line 220 located in the first peripheral area 200 can be arranged on both sides of the first extension part 212 along the first direction X, i.e., the second power supply line 220 can be arranged on the side of the first extension part 212 close to the left or right frame of the display panel. The second power supply line 220 of the first peripheral area 200 includes a second main body part 221 and a second extension part 222, the second main body part 221 can extend along the first direction X, the second extension part 222 can extend along the second direction Y, one end of the second extension part 222 can be connected with the second main body part 221, and the other end of the second extension part 222 can be connected with the corresponding bonding pad 701 to receive the corresponding low-voltage signal. The second power supply line 220 can overlap with the first signal line 11, the second signal line 12, the third signal line 13 and the fourth signal line 14, as shown in FIG. 3, the second main body part 221 of the second power supply line 220 can overlap with the connection part L3 of the first signal line 11, the connection part L3 of the second signal line 12, the connection part L3 of the third signal line 13 and the connection part L3 of the fourth signal line 14, and the second power supply line 220 can overlap with the second straight part L2 of the first signal line 11, the second straight part L2 of the second signal line 12, the second straight part L2 of the third signal line 13 and the second straight part L2 of the fourth signal line 14, and the present disclosure does not limit this.

[0078] In the example embodiment, the first power supply line 210 can include two first extension parts 212, and the two first extension parts 212 can be arranged in sequence along the first direction X and connected with different bonding pads 701. After the display panel is bonded and connected with the integrated circuit 120, the two first extension parts 212 can be distributed on both sides of the integrated circuit 120 along the first direction X.

[0079] FIG. 4 is an enlarged schematic view of the dashed line area C of FIG. 2 in another example embodiment. The difference between FIG. 4 and FIG. 3 is that the shape of the first compensation part 213 is different, and the first power supply line 210 further includes a second compensation part 214, and other contents can refer to the description of FIG. 3 above, which will not be repeated here.

[0080] In the example embodiment, as shown in FIG. 4, the first main portion 211 can overlap with the first straight portion L1 of the first signal line 11 and the first straight portion L1 of the second signal line 12, the first compensation portion 213 can overlap with the second straight portion L2 of the third signal line 13 and the second straight portion L2 of the fourth signal line 14, and the second compensation portion 214 can overlap with the second straight portion L2 of the third signal line 13 and the second straight portion L2 of the fourth signal line 14. The overlapping area of each clock signal line T with the first main portion 211 is a first area, the sum of the overlapping areas of each clock signal line T with the first compensation portion 213 and the second compensation portion 214 is a second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.05. By arranging the first compensation portion 213 and the second compensation portion 214 on the first power supply line 210, the clock signal lines T that do not overlap with the first main portion 211 are compensated by the first compensation portion 213 and the second compensation portion 214, so that the overlapping area of the first power supply line 210 with each clock signal line T is approximately equal, avoiding the inconsistency of transmission signals between the plurality of clock signal lines T caused by the different capacitances at the overlapping positions, and helping to ensure the uniformity of the display brightness of the display panel. Compared with the scheme shown in FIG. 3, the scheme of the present embodiment helps to reduce the size of the compensation portion located on one side of the first extension portion 212, facilitating the wiring design.

[0081] In the example embodiment, as shown in FIG. 4, the first compensation portion 213 and the second compensation portion 214 are both connected with the first extension portion 212, and the first compensation portion 213 and the second compensation portion 214 can be located at both ends of the first extension portion 212 along the first direction X. As shown in FIG. 4, the orthographic projection of the first compensation portion 213 and the second compensation portion 214 on the display panel is a rectangle with one side being a curve. In other embodiments, the shapes of the first compensation portion 213 and the second compensation portion 214 can be different, and the orthographic projections of the first compensation portion 213 and the second compensation portion 214 can have other shapes, which are not limited in the present disclosure.

[0082] FIG. 5 is an enlarged schematic view of the dashed area C of FIG. 2 in another example embodiment. The difference between FIG. 5 and FIG. 4 is that the first power supply line 210 further includes a plurality of third compensation portions 215, and other contents can be referred to the description of FIG. 4 above, which will not be repeated here.

[0083] In the example embodiment, the plurality of third compensation portions 215 can be connected with the first extension portion 212, and the plurality of third compensation portions 215 can be distributed on one side or both sides of the first extension portion 212 along the first direction X. The third compensation portions 215 overlap the second straight portion L2. The clock signal lines T overlapping the third compensation portions 215 are the same as the clock signal lines T overlapping the first main body portion 211. The sum of the overlapping areas of each clock signal line T with the first main body portion 211 and the third compensation portions 215 is a first area, and the sum of the overlapping areas of each clock signal line T with the first compensation portion 213 and the second compensation portion 214 is a second area. The ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.05. In this embodiment, by adding the third compensation portions 215, the paths of the water vapor invading the display panel can be increased at different positions, which helps to prevent water vapor invasion and improve display defects caused by water vapor invasion of the display panel.

[0084] In the example embodiment, as shown in FIG. 5, four third compensation portions 215 can be distributed on both sides of the first extension portion 212 along the first direction X. Two of the third compensation portions 215 can overlap the first signal lines 11, and the other two third compensation portions 215 can overlap the second signal lines 12. In other embodiments, any number of third compensation portions 215 can be provided as needed, and a single third compensation portion 215 can overlap a larger number of signal lines. The present disclosure does not limit this.

[0085] FIG. 6 is an enlarged schematic view of the dashed area C of FIG. 2 in another example embodiment. The difference between FIG. 6 and FIG. 3 is the structure of the first power supply line 210 and the clock signal line T. Other contents can be referred to the description of FIG. 3 above, and will not be repeated here.

[0086] In the example embodiment, as shown in FIG. 6, the first main body portion 211 of the first power supply line 210 overlaps with the first straight line portion L1 of the first signal line 11 and the first straight line portion L1 of the second signal line 12, and does not overlap with the third signal line 13 and the fourth signal line 14. The first extension portion 212 of the first power supply line 210 overlaps with the second straight line portion L2 of the first signal line 11, the second straight line portion L2 of the second signal line 12, the second straight line portion L2 of the third signal line 13 and the second straight line portion L2 of the fourth signal line 14. In the second direction Y, the line width of the second straight line portion L2 of the first signal line 11 can be the first width d1, the line width of the second straight line portion L2 of the second signal line 12 can be the second width d2, the line width of the second straight line portion L2 of the third signal line 13 can be the third width d3, and the line width of the second straight line portion L2 of the fourth signal line 14 can be the fourth width d4. The first width d1 and the second width d2 can be equal, the third width d3 and the fourth width d4 can be equal, and the third width d3 can be greater than the first width d1, so that the ratio of the overlapping area of any two clock signal lines T and the first power supply line 210 is greater than or equal to 0.95 and less than or equal to 1.05, and the overlapping area of each clock signal line T and the first power supply line 210 is substantially equal.

[0087] In FIG. 6, the first width d1 and the second width d2 can remain unchanged, the third width d3 and the fourth width d4 can be increased, or the third width d3 and the fourth width d4 can remain unchanged, and the first width d1 and the second width d2 can be reduced, and the present disclosure does not limit this.

[0088] FIG. 7 is an enlarged schematic view of the dashed line region C of FIG. 2 in another example embodiment. The difference between FIG. 7 and FIG. 3 is the structure of the first power supply line 210, and other contents can refer to the description of FIG. 3 above, which will not be repeated here.

[0089] In the example embodiment, as shown in FIG. 7, the first main body portion 211 of the first power supply line 210 overlaps with the first linear portion L1 of the first signal line 11 and the first linear portion L1 of the second signal line 12, and does not overlap with the third signal line 13 and the fourth signal line 14. The first extension portion 212 of the first power supply line 210 includes a first narrow neck portion 216 and a first wide neck portion 217. In the first direction X, the line width between the opposite side surfaces of the first narrow neck portion 216 is a fifth width d5, the line width between the opposite side surfaces of the first wide neck portion 217 is a sixth width d6, the fifth width d5 is smaller than the sixth width d6, the first narrow neck portion 216 overlaps with the second linear portion L2 of the first signal line 11 and the second linear portion L2 of the second signal line 12, and the first wide neck portion 217 overlaps with the second linear portion L2 of the third signal line 13 and the second linear portion L2 of the fourth signal line 14. The overlapping area between the first narrow neck portion 216 and the second linear portion L2 of the first signal line 11 and the second linear portion L2 of the second signal line 12 is smaller than the overlapping area between the first wide neck portion 217 and the second linear portion L2 of the third signal line 13 and the second linear portion L2 of the fourth signal line 14, so that the overlapping area between each clock signal line T and the first power supply line 210 is substantially equal, and the ratio of the overlapping area between any two clock signal lines T and the first power supply line 210 is greater than or equal to 0.95 and smaller than or equal to 1.05.

[0090] In the example embodiment, the schemes in FIGS. 3 to 7 can be combined with each other at will, for example, the compensation portion can be increased while the line width is changed, and the present disclosure does not limit this. In the above figures, the signal transmission line is taken as the clock signal line T for example, and the signal transmission line can also be a signal line for transmitting other signals. The number of signal transmission lines and the overlapping relationship with the first power supply line can be set as needed, and the present disclosure does not limit this.

[0091] FIG. 8 is an equivalent circuit diagram of a gate drive circuit in an example embodiment. As shown in FIG. 8, the gate drive circuit includes first to eighth scan transistors GT1 to GT8, a first scan capacitor GC1 and a second scan capacitor GC2.

[0092] In an example embodiment, the gate electrode of the first scanning transistor GT1 is electrically connected with the first clock signal terminal GCK1, the first electrode of the first scanning transistor GT1 is electrically connected with the input terminal GIN, and the second electrode of the first scanning transistor GT1 is electrically connected with the first node G1; the gate electrode of the second scanning transistor GT2 is electrically connected with the first node G1, the first electrode of the second scanning transistor GT2 is electrically connected with the first clock signal terminal GCK1, and the second electrode of the second scanning transistor GT2 is electrically connected with the second node G2; the gate electrode of the third scanning transistor GT3 is electrically connected with the first clock signal terminal GCK1, the first electrode of the third scanning transistor GT3 is electrically connected with the second power supply terminal VGL, and the second electrode of the third scanning transistor GT3 is electrically connected with the second node G2; the gate electrode of the fourth scanning transistor GT4 is electrically connected with the second node G2, the first electrode of the fourth scanning transistor GT4 is electrically connected with the first power supply terminal VGH, and the second electrode of the fourth scanning transistor GT4 is electrically connected with the output terminal GOUT; the gate electrode of the fifth scanning transistor GT5 is electrically connected with the third node G3, the first electrode of the fifth scanning transistor GT5 is electrically connected with the second clock signal terminal GCK2, and the second electrode of the fifth scanning transistor GT5 is electrically connected with the output terminal GOUT; the gate electrode of the sixth scanning transistor GT6 is electrically connected with the second node G2, the first electrode of the sixth scanning transistor GT6 is electrically connected with the first power supply terminal VGH, and the second electrode of the sixth scanning transistor GT6 is electrically connected with the first electrode of the seventh scanning transistor GT7; the gate electrode of the seventh scanning transistor GT7 is electrically connected with the second clock signal terminal GCK2, and the second electrode of the seventh scanning transistor GT7 is electrically connected with the first node G1; the gate electrode of the eighth scanning transistor GT8 is electrically connected with the second power supply terminal VGL, the first electrode of the eighth scanning transistor GT8 is electrically connected with the first node G1, and the second electrode of the eighth scanning transistor GT8 is electrically connected with the third node G3; one end of the first scanning capacitor GC1 is electrically connected with the first power supply terminal VGH, and the other end of the first scanning capacitor GC1 is electrically connected with the second node G2; the first plate GC21 of the second scanning capacitor GC2 is electrically connected with the output terminal GOUT, and the second plate GC22 of the second scanning capacitor GC2 is electrically connected with the third node G3.

[0093] In an example embodiment, the first scanning transistor GT1 to the eighth scanning transistor GT8 can be P-type transistors or can be N-type transistors.

[0094] In an example embodiment, the first power supply terminal VGH can be connected through a high-voltage transmission line and a first power supply line 210 to continuously provide a high-level signal, and the second power supply terminal VGL can be connected through a low-voltage transmission line and a second power supply line 220 to continuously provide a low-level signal.

[0095] In an exemplary embodiment, four clock signal lines can be employed to provide clock signals for the gate driving circuit 310, and six, eight or more clock signal lines can also be employed to provide clock signals for the gate driving circuit 310, and the number of clock signal lines employed by the gate driving circuit 310 is not limited in the present disclosure.

[0096] The display device can be an OLED display, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function, and the embodiments of the present disclosure are not limited thereto.

[0097] Although the embodiments of the present disclosure are disclosed as above, the content described is only the embodiments adopted for facilitating the understanding of the embodiments of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, and the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A display panel, comprising: A display region and a non-display region surrounding the display region, the non-display region including a binding region located at one side of the display region and a first peripheral region located between the binding region and the display region; A plurality of sub-pixels located in the display region; A plurality of drive signal lines located in the display region and extending along a first direction, the plurality of drive signal lines being electrically connected with the plurality of sub-pixels; A drive circuit located in the non-display region, the drive circuit being electrically connected with the plurality of drive signal lines; A plurality of data lines located in the display region and extending to the non-display region along a second direction, the plurality of sub-pixels and the plurality of data lines being electrically connected, the first direction and the second direction intersecting; A plurality of first power supply sub-lines located in the display region and extending along the second direction, the plurality of sub-pixels being electrically connected with the plurality of first power supply sub-lines; A plurality of binding pads located in the binding region; A first power supply line located in the non-display region, the first power supply line being electrically connected with the plurality of first power supply sub-lines and the binding pads; A plurality of signal transmission lines located at least in the first peripheral region, the plurality of signal transmission lines being electrically connected with the drive circuit; in a direction perpendicular to the display panel, the plurality of signal transmission lines and the first power supply line overlap each other; Wherein, a ratio of an overlapping area of any two of the plurality of signal transmission lines and the first power supply line is greater than or equal to 0.95 and less than or equal to 1.

05.

2. The display panel of claim 1, wherein, The first power supply line includes a first main body part extending along the first direction and a first extension part extending along the second direction, the first main body part being located in the first peripheral region, the first extension part being located in the first peripheral region and extending to the binding region, one end of the first extension part being connected with the first main body part, the other end of the first extension part being electrically connected with the binding pads; the first direction is parallel to an extension direction of an edge of the display region close to the first peripheral region; Each of the plurality of signal transmission lines includes a first straight line part, a second straight line part and a connecting part, the first straight line part and the second straight line part extending along the first direction, the second straight line part being located at one side of the second direction of the first straight line part, the first straight line part and the second straight line part being connected with each other through the connecting part, the first straight line part being electrically connected with the drive circuit, the second straight line part being configured to be electrically connected with an integrated circuit; The first main body part overlaps with the first straight line part of a part of the plurality of signal transmission lines, the first extension part overlaps with the second straight line part of the plurality of signal transmission lines.

3. The display panel of claim 2, wherein, The first power supply line further includes at least one first compensation part, the first compensation part being connected with the first extension part, in a direction perpendicular to the display panel, the first compensation part overlapping with the second straight line part of another part of the plurality of signal transmission lines; The ratio of the overlapping area of any two of the signal transmission lines and the first power line is greater than or equal to 0.95 and less than or equal to 1.05, including: The overlapping area of each of the signal transmission lines and the first main body part is a first area, and the overlapping area of each of the signal transmission lines and the first compensation part is a second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.

05.

4. The display panel of claim 3, wherein, The first compensation part is distributed on one side or both sides of the first extension part along the first direction, and a single first compensation part overlaps the second linear part of at least one signal transmission line.

5. The display panel of claim 3, wherein, The first power line further comprises at least one second compensation part, the second compensation part is connected with the first extension part, and the second compensation part and the first compensation part are distributed on both sides of the first extension part along the first direction; in the direction perpendicular to the display panel, the second compensation part overlaps the second linear part of another part of the signal transmission lines. The ratio of the overlapping area of any two of the signal transmission lines and the first power line is greater than or equal to 0.95 and less than or equal to 1.05, including: The overlapping area of each of the signal transmission lines and the first main body part is a first area, and the sum of the overlapping area of each of the signal transmission lines and the first compensation part and the second compensation part is a second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.

05.

6. The display panel of claim 3 or 5, wherein, The first power line further comprises at least one third compensation part, the third compensation part overlaps the second linear part of a part of the signal transmission lines, and the signal transmission lines overlapping with the third compensation part are the same as the signal transmission lines overlapping with the first main body part; The ratio of the overlapping area of any two of the signal transmission lines and the first power line is greater than or equal to 0.95 and less than or equal to 1.05, including: The sum of the overlapping area of each of the signal transmission lines and the first main body part and the third compensation part is a first area, and the overlapping area of each of the signal transmission lines and the first compensation part is a second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.05; or, The sum of the overlapping area of each of the signal transmission lines and the first main body part and the third compensation part is a first area, and the sum of the overlapping area of each of the signal transmission lines and the first compensation part and the second compensation part is a second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.

05.

7. The display panel of claim 6, wherein, A plurality of the third compensation parts are distributed on both sides of the first extension part along the first direction, and a single third compensation part overlaps at least one second linear part.

8. The display panel of claim 2, wherein, In the second direction, the line width of the second linear part of the signal transmission line without overlapping with the first main body part is greater than the line width of the second linear part of the signal transmission line overlapping with the first main body part.

9. The display panel of claim 8, wherein, The line width of the second straight part of the signal transmission line not overlapping with the first main part is equal to the line width of the second straight part of the signal transmission line overlapping with the first main part.

10. The display panel of claim 2, wherein, The first extension part includes a first narrow neck part and a first wide neck part, and the line width of the first narrow neck part is smaller than the line width of the first wide neck part in the first direction. In a direction perpendicular to the display panel, the second straight part of the signal transmission line overlapping with the first main part overlaps with the first narrow neck part, and the second straight part of the signal transmission line not overlapping with the first main part overlaps with the first wide neck part.

11. The display panel of claim 2, wherein, The first power supply line includes one first main part and two first extension parts arranged in the first direction and electrically connected to different bonding pads. The two first extension parts are respectively located on two sides of the integrated circuit in the first direction.

12. The display panel of claim 2, wherein, The display panel further includes a second power supply line located in the non-display area and surrounding the display area, and the part of the second power supply line located in the first peripheral area is located on both sides of the first extension part in the first direction, and the second power supply line overlaps with the plurality of signal transmission lines.

13. The display panel of claim 12, wherein, The part of the second power supply line located in the first peripheral area includes a second main part extending in the first direction and a second extension part extending in the second direction, one end of the second extension part is connected to the second main part, and the other end of the second extension part is electrically connected to the bonding pad. In a direction perpendicular to the display panel, the second main part overlaps with the connection part, and the second extension part overlaps with the second straight part.

14. The display panel of claim 1, wherein, The non-display area further includes a second peripheral area surrounding the display area and away from one side of the bonding area, and the second peripheral area includes the drive circuit, and the drive circuit includes at least one of a gate drive circuit or a light-emitting control drive circuit.

15. The display panel of claim 14, wherein, The plurality of signal transmission lines include at least one of a gate drive control line and a light-emitting control line, the gate drive control line is electrically connected to the gate drive circuit, and the light-emitting control line is electrically connected to the light-emitting control drive circuit.

16. A display device comprising the display panel according to any one of claims 1 to 15.

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