Display panel and manufacturing method therefor, display device, and display control method

Abstract

A display panel (1), relating to the technical field of display. The display panel (1) comprises a base substrate (11), a first lead (1201), a control signal input end (1401), a first inverter (131), and a plurality of gate drive circuits (15). The base substrate (11) has a first side edge (111) and a second side edge (112) which are adjacent to each other; the control signal input end (1401) is located between a display region (A) and the first side edge (111); a peripheral region (B) comprises a first peripheral sub-region (B1) located between the display region (A) and the second side edge (112); a first target gate drive circuit (151) is located at the end of the first peripheral sub-region (B1) distant from the first side edge (111); and the first inverter (131) is located on the outer side of the first peripheral sub-region (B1) and the display region (A) distant from the first side edge (111). At least a portion of the first lead (1201) is located in the first peripheral sub-region (B1), and two ends of the first lead (1201) are electrically connected to the control signal input end (1401) and a first frame start signal input end (1402) of the first target gate drive circuit (151), respectively. The first inverter (131) is electrically connected to the first lead (1201) and a second frame start signal input end (1403) of the first target gate drive circuit (151), separately. The present application is conducive to the narrow bezel design of display panels.

Description

Display panel, manufacturing method thereof, display device, and display control method

[0001] The present application claims priority from the Chinese patent application No. 202410741429.X, filed on June 7, 2024, and entitled "Display panel, manufacturing method thereof, display device, and display control method", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel, a manufacturing method thereof, and a display device. BACKGROUND

[0003] Display devices have a wide range of application scenarios in life, such as electronic devices such as mobile phones and tablet computers. A display panel is an important component of a display device.

[0004] In the related art, a display panel includes a substrate substrate having a display area and a peripheral area located outside the display area. The display panel also includes a control signal input end and a plurality of gate drive circuits located on the substrate substrate and located in the peripheral area. The control signal input end is located at the bottom of the display panel, and a first target gate drive circuit in the plurality of gate drive circuits is located at the upper left corner of the display panel. The first target gate drive circuit has a first frame start signal input end and a second frame start signal input end. The display panel also includes a first lead line electrically connected to the first frame start signal input end and the control signal input end, and a second lead line electrically connected to the second frame start signal input end and the control signal input end. The first lead line and the second lead line both pass through the side frame of the display panel.

[0005] However, since there are many lead lines at the side frame of the display panel, it is not conducive to the narrow frame design of the display panel. SUMMARY

[0006] The present application provides a display panel, a display device, and a display control method, which are conducive to the narrow frame design of the display panel. The technical solutions are as follows:

[0007] In one aspect, a display panel is provided, which includes a substrate substrate having a display area and a peripheral area outside the display area; the display panel further includes a first lead line, a control signal input, at least one inverter and a plurality of gate drive circuits on the substrate substrate and in the peripheral area, the at least one inverter includes a first inverter; the substrate substrate has adjacent first and second side edges, the control signal input is between the display area and the first side edge, the peripheral area includes a first sub-peripheral area between the display area and the second side edge, a first target gate drive circuit of the plurality of gate drive circuits is at an end of the first sub-peripheral area away from the first side edge, and the first inverter is outside the first sub-peripheral area and the display area away from the first side edge; at least part of the first lead line is in the first sub-peripheral area, the first target gate drive circuit has a first frame start signal input and a second frame start signal input, two ends of the first lead line are electrically connected with the control signal input and the first frame start signal input of the first target gate drive circuit respectively, and the first inverter is electrically connected with the first lead line and the second frame start signal input of the first target gate drive circuit respectively.

[0008] Optionally, the substrate substrate further has a third side edge opposite to the first side edge; and the first inverter is between the first sub-peripheral area and the third side edge.

[0009] Optionally, the first inverter includes N single-stage amplifiers connected in series, N is a positive odd number and N is greater than 1.

[0010] Optionally, the display panel further includes a second lead line and a third lead line on the substrate substrate and in the peripheral area, the at least one inverter further includes a second inverter and a third inverter, at least part of the second lead line and at least part of the third lead line are in the first sub-peripheral area, the plurality of gate drive circuits include a plurality of first gate drive circuits in the first sub-peripheral area, the first gate drive circuits have a first clock signal input, a second clock signal input, a third clock signal input and a fourth clock signal input; two ends of the second lead line are electrically connected with the control signal input and the first clock signal input of the plurality of first gate drive circuits respectively, the second inverter is electrically connected with the second lead line and the second clock signal input of the first gate drive circuits; two ends of the third lead line are electrically connected with the control signal input and the third clock signal input of the plurality of first gate drive circuits respectively, and the third inverter is electrically connected with the third lead line and the fourth clock signal input of the first gate drive circuits.

[0011] Optionally, the second inverter is electrically connected with the second clock signal input end of the plurality of first gate drive circuits, and the third inverter is electrically connected with the fourth clock signal input end of the plurality of first gate drive circuits; the second inverter and the third inverter are located between the first sub-peripheral area and the first side edge.

[0012] Optionally, the second inverter is electrically connected with the second clock signal input end of the plurality of first gate drive circuits, and the third inverter is electrically connected with the fourth clock signal input end of the plurality of first gate drive circuits; the second inverter and the third inverter are located between the first sub-peripheral area and the third side edge.

[0013] Optionally, the number of the second inverters is a plurality, and the number of the third inverters is a plurality; the plurality of second inverters are respectively electrically connected with the second clock signal input end of the plurality of first gate drive circuits, and the plurality of third inverters are respectively electrically connected with the fourth clock signal input end of the plurality of first gate drive circuits; the plurality of second inverters and the plurality of third inverters are located in the first sub-peripheral area.

[0014] Optionally, the second inverter comprises P single-stage amplifiers connected in series, and P is a positive odd number greater than 1; the third inverter comprises Q single-stage amplifiers connected in series, and Q is a positive odd number greater than 1.

[0015] Optionally, the display panel further comprises a fourth lead line on the substrate and in the peripheral area, and the at least one inverter further comprises a fourth inverter; the substrate further has a fourth side opposite to the second side, and the peripheral area further comprises a second sub-peripheral area between the display area and the fourth side, a second target gate drive circuit in the plurality of gate drive circuits is located at one end of the second sub-peripheral area away from the first side, and the fourth inverter is located at the outer side of the second sub-peripheral area and the display area away from the first side; at least part of the fourth lead line is located in the second sub-peripheral area, the second target gate drive circuit has a first frame start signal input end and a second frame start signal input end, two ends of the fourth lead line are electrically connected with the control signal input end and the first frame start signal input end of the second target gate drive circuit respectively, and the fourth inverter is electrically connected with the fourth lead line and the second frame start signal input end of the second target gate drive circuit respectively; the display panel further comprises a plurality of pixel drive circuits on the substrate and in the display area, the pixel drive circuit has an input end, the pixel drive circuit comprises a plurality of first pixel drive circuits, the first target gate drive circuit has an output end, the second target gate drive circuit has an output end, and the output end of the first target gate drive circuit, the output end of the second target gate drive circuit and the input end of the plurality of first pixel drive circuits are electrically connected.

[0016] Optionally, the display panel further comprises a fifth lead line and a sixth lead line on the substrate and in the peripheral area, and the at least one inverter further comprises a fifth inverter and a sixth inverter, at least part of the fifth lead line and at least part of the sixth lead line are located in the second sub-peripheral area, the plurality of gate drive circuits further comprises a plurality of second gate drive circuits in the second sub-peripheral area, and the second gate drive circuit has a first clock signal input end, a second clock signal input end, a third clock signal input end and a fourth clock signal input end; two ends of the fifth lead line are electrically connected with the control signal input end and the first clock signal input end of the plurality of second gate drive circuits respectively, and the fifth inverter is electrically connected with the fifth lead line and the second clock signal input end of the second gate drive circuit; two ends of the sixth lead line are electrically connected with the control signal input end and the third clock signal input end of the plurality of second gate drive circuits respectively, and the sixth inverter is electrically connected with the sixth lead line and the fourth clock signal input end of the second gate drive circuit.

[0017] Optionally, the inverter has an input end and an output end, the inverter comprises an N-type thin film transistor and a P-type thin film transistor, the input end of the inverter is electrically connected with the gate of the N-type thin film transistor and the gate of the P-type thin film transistor respectively, and the output end of the inverter is electrically connected with the drain of the N-type thin film transistor and the drain of the P-type thin film transistor respectively; the display panel further comprises a first power line and a second power line on the substrate, the potential of the electrical signal transmitted by the first power line is higher than the potential of the electrical signal transmitted by the second power line, the first power line is electrically connected with the source of the P-type thin film transistor, and the second power line is electrically connected with the source of the N-type thin film transistor.

[0018] Optionally, the display panel comprises a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer and a first source-drain layer which are sequentially stacked on the substrate; the active layer of the P-type thin film transistor is located on the first active layer, the gate of the P-type thin film transistor is located on the first gate layer, the source and the drain of the P-type thin film transistor are located on the first source-drain layer, the active layer of the N-type thin film transistor is located on the second active layer, the gate of the N-type thin film transistor is located on the third gate layer, and the source and the drain of the N-type thin film transistor are located on the first source-drain layer; the normal projection of the active layer of the N-type thin film transistor on the substrate at least partially overlaps with the normal projection of the second gate layer on the substrate.

[0019] Optionally, the display panel further comprises a seventh lead line on the substrate and located in the peripheral area, the at least one inverter further comprises a seventh inverter, at least part of the seventh lead line is located in the first sub-peripheral area, the plurality of gate driving circuits comprises a plurality of first gate driving circuits located in the first sub-peripheral area, and the first gate driving circuit has a fifth clock signal input end and a sixth clock signal input end; two ends of the seventh lead line are electrically connected with the control signal input end and the fifth clock signal input end of the plurality of first gate driving circuits respectively, and the seventh inverter is electrically connected with the seventh lead line and the sixth clock signal input end of the first gate driving circuit.

[0020] In another aspect, a manufacturing method of a display panel is provided. The method includes providing a substrate, the substrate having a display area and a peripheral area outside the display area; manufacturing a first lead line, a control signal input, at least one inverter, and a plurality of gate drive circuits on the substrate; wherein the first lead line, the control signal input, the at least one inverter, and the plurality of gate drive circuits are located in the peripheral area, the at least one inverter includes a first inverter, the substrate has a first side edge and a second side edge adjacent to each other, the control signal input is located between the display area and the first side edge, the peripheral area includes a first sub-peripheral area between the display area and the second side edge, a first target gate drive circuit of the plurality of gate drive circuits is located at an end of the first sub-peripheral area away from the first side edge, the first inverter is located at an outer side of the first sub-peripheral area and the display area away from the first side edge, at least part of the first lead line is located in the first sub-peripheral area, the first target gate drive circuit has a first frame start signal input and a second frame start signal input, two ends of the first lead line are electrically connected to the control signal input and the first frame start signal input of the first target gate drive circuit respectively, and the first inverter is electrically connected to the first lead line and the second frame start signal input of the first target gate drive circuit respectively.

[0021] In yet another aspect, a display device is provided. The display device includes a driving chip and any of the display panels described above, and the driving chip is electrically connected to the control signal input.

[0022] In yet another aspect, a display control method is provided. The display control method is used for controlling any of the display devices described above. The display control method includes obtaining a control instruction; based on the control instruction, inputting a first frame start signal to the first lead line, so as to input the first frame start signal to the first target gate drive circuit through the first lead line, and sequentially inputting a second frame start signal to the first target gate drive circuit through the first lead line and the first inverter.

[0023] The technical scheme provided by the embodiments of the present application has at least the following beneficial effects: by arranging the first inverter, the first inverter is connected to the first lead line and the second frame start signal input of the first target gate drive circuit respectively, and the first inverter is located at an outer side of the first sub-peripheral area and the display area away from the first side edge. Therefore, the present application can not arrange a lead line for inputting the second frame start signal to the first target gate drive circuit in the first sub-peripheral area, so as to reduce the number of lead lines in the first sub-peripheral area.

[0024] In addition, the number of leads of the first sub-peripheral area is reduced, so that the frame of the display panel can be reduced, and a narrow frame design of the display panel is realized. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0026] FIG. 1 is a schematic diagram of a planar structure of a display panel provided in the related art;

[0027] FIG. 2 is a schematic diagram of a planar structure of a substrate provided in an embodiment of the present application;

[0028] FIG. 3 is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present application;

[0029] FIG. 4 is a schematic diagram of a structure of a first inverter provided in an embodiment of the present application;

[0030] FIG. 5 is a schematic diagram of a planar structure of another display panel provided in an embodiment of the present application;

[0031] FIG. 6 is a schematic diagram of a planar structure of another display panel provided in an embodiment of the present application;

[0032] FIG. 7 is a schematic diagram of a planar structure of another display panel provided in an embodiment of the present application;

[0033] FIG. 8 is a schematic diagram of a structure of a second inverter and a third inverter provided in an embodiment of the present application;

[0034] FIG. 9 is a schematic diagram of a circuit structure of a first-stage gate drive circuit provided in an embodiment of the present application;

[0035] FIG. 10 is a schematic diagram of a transistor structure of a first-stage gate drive circuit provided in an embodiment of the present application;

[0036] FIG. 11 is a schematic diagram of a structure of a second-stage gate drive circuit provided in an embodiment of the present application;

[0037] FIG. 12 is a timing diagram of a first frame start signal, a second frame start signal, and a clock signal provided in an embodiment of the present application;

[0038] FIG. 13 is a schematic diagram of a planar structure of another display panel provided in an embodiment of the present application;

[0039] FIG. 14 is a schematic diagram of a planar structure of another display panel provided in an embodiment of the present application;

[0040] FIG. 15 is a schematic view of a planar structure of another display panel according to an embodiment of the present application;

[0041] FIG. 16 is a schematic view of a planar structure of another display panel according to an embodiment of the present application;

[0042] FIG. 17 is a schematic view of a planar structure of another display panel according to an embodiment of the present application;

[0043] FIG. 18 is a schematic view of a structure of an inverter according to an embodiment of the present application;

[0044] FIG. 19 is a schematic view of a cross-sectional structure of a display panel according to an embodiment of the present application;

[0045] FIGS. 20 and 21 are schematic views of film layer structures of a first inverter, a first power line and a second power line according to an embodiment of the present application;

[0046] FIG. 22 is a flowchart of a manufacturing method of a display panel according to an embodiment of the present application;

[0047] FIG. 23 is a schematic view of a structure of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the objectives, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0049] FIG. 1 is a schematic diagram of a planar structure of a display panel provided in the related art. As shown in FIG. 1, the display panel 1' includes a substrate 11' having a display area A' and a peripheral area B' located outside the display area A'. The display panel 1' further includes a first lead wire 1201', a second lead wire 1202', a control signal input end 1401', and a plurality of gate driving circuits 15' located on the substrate 1' and in the peripheral area B'. The substrate 11' has a first side edge 111' and a second side edge 112' adjacent to each other, the control signal input end 1401' is located between the display area A' and the first side edge 111', and the peripheral area B' includes a first sub-peripheral area B1' located between the display area A' and the second side edge 112'. A first target gate driving circuit 151' of the plurality of gate driving circuits 15' is located at an end of the first sub-peripheral area B1' away from the first side edge 111'. At least part of the first lead wire 1201' and the second lead wire 1202' are located in the first sub-peripheral area B1', the first target gate driving circuit 151' has a first frame start signal input end 1402' and a second frame start signal input end 1403', and two ends of the first lead wire 1201' are electrically connected to the control signal input end 1401' and the first frame start signal input end 1402' of the first target gate driving circuit 151', respectively, and two ends of the second lead wire 1202' are electrically connected to the control signal input end 1401' and the second frame start signal input end 1403' of the first target gate driving circuit 151', respectively.

[0050] As the first target gate driving circuit 151' is located at an end of the first sub-peripheral area B1' away from the first side edge 111', and the control signal input end 1401' is located between the display area A' and the first side edge 111', as shown in FIG. 1, assuming that the first side edge 111' is a lower side edge and the second side edge 112' is a left side edge, the first target gate driving circuit 151' is located at the upper left, and therefore the first lead wire 1201' must be at least partially located in the first sub-peripheral area B1', and the second lead wire 1202' is the same, so as to transmit the first frame start signal and the second frame start signal. However, the first lead wire 1201' and the second lead wire 1202' are both at least partially located in the first sub-peripheral area B1', which causes the side frame of the display panel to be relatively wide, which is not conducive to the narrow frame design of the display panel.

[0051] Therefore, embodiments of the present application provide a first inverter in the display panel, the first inverter is electrically connected to the first lead wire and the second frame start signal input end of the first target gate driving circuit, respectively, so that the second frame start signal can be obtained from the first frame start signal, and therefore it is not necessary to provide a lead wire for electrically connecting the control signal input end and the second frame start signal input end of the first target gate driving circuit, and therefore the number of lead wires provided in the first sub-peripheral area B1' can be reduced, which is conducive to the narrow frame design of the display panel.

[0052] FIG. 2 is a schematic diagram of a planar structure of a substrate provided in an embodiment of the present application. As shown in FIG. 2, the display panel 1 includes a substrate 11 having a display area A and a peripheral area B outside the display area A. The substrate 11 has a first side edge 111 and a second side edge 112 adjacent to each other. FIG. 3 is a schematic diagram of a planar structure of a display panel provided in an embodiment of the present application. In combination with FIG. 2 and FIG. 3, the display panel 1 further includes a first lead line 1201, a control signal input end 1401, at least one inverter and a plurality of gate drive circuits 15 on the substrate 11 and in the peripheral area B, the at least one inverter 13 includes a first inverter 131. The control signal input end 1401 is between the display area A and the first side edge 111, the peripheral area B includes a first sub-peripheral area B1 between the display area A and the second side edge 112, a first target gate drive circuit 151 of the plurality of gate drive circuits 15 is at an end of the first sub-peripheral area B1 away from the first side edge 111, and the first inverter 131 is outside the first sub-peripheral area B1 and the display area A away from the first side edge 111. At least part of the first lead line 1201 is in the first sub-peripheral area B1, the first target gate drive circuit 151 has a first frame start signal input end 1402 and a second frame start signal input end 1403, two ends of the first lead line 1201 are electrically connected to the control signal input end 1401 and the first frame start signal input end 1402 of the first target gate drive circuit 151 respectively, and the first inverter 131 is electrically connected to the first lead line 1201 and the second frame start signal input end 1403 of the first target gate drive circuit 151 respectively.

[0053] In the embodiment of the present application, since the two ends of the first lead line 1201 are electrically connected with the control signal input end 1401 and the first frame start signal input end 1402 of the first target gate driving circuit 151 respectively, after the first frame start signal STV1 is input to the display panel by the control signal input end 1401, the first frame start signal STV1 enters the first target gate driving circuit 151 through the first lead line 1201. Since the first inverter 131 is electrically connected with the first lead line 1201 and the second frame start signal input end 1403 of the first target gate driving circuit 151 respectively, after the first frame start signal STV1 is input to the display panel by the control signal input end 1401, the second frame start signal STV2 is generated by the first lead line 1201 and the first inverter 131, and the second frame start signal STV2 enters the first target gate driving circuit. Compared with the related art, by adding the first inverter 131, the second lead line 1202' passing through the first sub-peripheral area B1' between the control signal input end 1401 and the second frame start signal input end 1403 of the first target gate driving circuit 151 in the related art can be avoided, that is, the lead line for inputting the second frame start signal to the first target gate driving circuit 151 in the first sub-peripheral area B1 can be avoided, so that the number of lead lines in the first sub-peripheral area B1 can be reduced. In addition, since the number of lead lines in the first sub-peripheral area is reduced, the frame of the display panel can be conveniently reduced, and the narrow frame design of the display panel can be realized, especially the narrow frame design of the side frame where the first sub-peripheral area B1 is located.

[0054] In summary, the display panel provided by the embodiment of the present application includes a substrate, a first lead line, a control signal input end, a first inverter and a first target gate driving circuit. The first target gate driving circuit is located at one end of the first sub-peripheral area away from the first side, the two ends of the first lead line are electrically connected with the control signal input end and the first frame start signal input end of the first target gate driving circuit respectively, the first inverter is connected with the first lead line and the second frame start signal input end of the first target gate driving circuit respectively, and the first inverter is located outside the first sub-peripheral area and the display area away from the first side. Therefore, the lead line for inputting the second frame start signal to the first target gate driving circuit in the first sub-peripheral area can be avoided, so that the number of lead lines in the first sub-peripheral area can be reduced, and the frame of the display panel can be conveniently reduced, and the narrow frame design of the display panel can be realized, especially the narrow frame design of the side frame where the first sub-peripheral area is located.

[0055] Exemplarily, the first target gate driving circuit 151 is also called a first-stage gate driving circuit.

[0056] Exemplarily, the phase of the first frame start signal STV1 is opposite to that of the second frame start signal STV2, so that the first frame start signal STV1 after passing through the first inverter 131 can be the second frame start signal STV2.

[0057] Exemplarily, the driving chip is electrically connected with the control signal input end 1401 of the display panel 1, so that the driving chip inputs signals to the plurality of gate driving circuits.

[0058] In a possible embodiment, in combination with FIG. 2 and FIG. 3, the substrate substrate further has a third side edge 113 opposite to the first side edge 111, and the first inverter 131 is located between the first sub-peripheral area B1 and the third side edge 113, that is, the first inverter 131 is arranged directly above the first sub-peripheral area B1, so that the distance between the first inverter 131 and the first target gate driving circuit 151 can be shortened as much as possible, thereby saving the wiring space and facilitating the narrow frame design of the display panel.

[0059] In other possible embodiments, part of the first inverter 131 is located between the first sub-peripheral area B1 and the third side edge 113, and another part of the first inverter 131 is located between the display area A and the third side edge 113. In other possible embodiments, the first inverter 131 is located between the display area A and the third side edge 113.

[0060] FIG. 4 is a structural schematic diagram of the first inverter provided by the embodiment of the present application. In a possible embodiment, as shown in part (a) of FIG. 4, the first inverter 131 only includes one single-stage amplifier. In another possible embodiment, the first inverter 131 includes N single-stage amplifiers connected in series, N is an odd positive integer, and N is greater than 1, for example, in the embodiment shown in part (b) of FIG. 4, N is equal to 3. Since the phase of the first frame start signal STV1 is opposite to that of the second frame start signal STV2, the number of single-stage amplifiers needs to be an odd number, so that the phase of the signal output by the first inverter 131 is opposite to that of the first frame start signal STV1. Compared with the embodiment shown in part (a) of FIG. 4, in the embodiment shown in part (b) of FIG. 4, the second frame start signal (STV2) obtained by gradually amplifying through multiple single-stage amplifiers is more stable, and the gain is higher.

[0061] Exemplarily, the first inverter 131 only includes one single-stage amplifier, and the channel width of the thin film transistor in the single-stage amplifier is 10 microns to 500 microns.

[0062] Exemplarily, the first inverter 131 includes three single-stage amplifiers connected in series, and the channel width of the thin film transistor in the three single-stage amplifiers gradually increases, for example, the widths are 8 microns, 40 microns and 300 microns, respectively.

[0063] Fig. 5 is a schematic view of a planar structure of another display panel according to an embodiment of the present application. In combination with Fig. 2 and Fig. 5, the display panel 1 further includes a second lead line 1202 and a third lead line 1203 located on the substrate 11 and located in the peripheral area B, the at least one inverter 13 further includes a second inverter 132 and a third inverter 133, at least part of the second lead line 1202 and at least part of the third lead line 1203 are located in the first sub-peripheral area B1, and the plurality of gate driving circuits 15 include a plurality of first gate driving circuits 152 located in the first sub-peripheral area B1, the first gate driving circuit 152 has a first clock signal input end 1404, a second clock signal input end 1405, a third clock signal input end 1406 and a fourth clock signal input end 1407. Two ends of the second lead line 1202 are electrically connected with the control signal input end 1401 and the first clock signal input end 1404 of the plurality of first gate driving circuits 152 respectively, and the second inverter 132 is electrically connected with the second lead line 1202 and the second clock signal input end 1405 of the first gate driving circuit 152. Two ends of the third lead line 1203 are electrically connected with the control signal input end 1401 and the third clock signal input end 1406 of the plurality of first gate driving circuits 152 respectively, and the third inverter 133 is electrically connected with the third lead line 1203 and the fourth clock signal input end 1407 of the first gate driving circuit 152.

[0064] In the related art, the control signal input end is electrically connected with the first clock signal input end, the second clock signal input end, the third clock signal input end and the fourth clock signal input end of the first gate driving circuit respectively, that is, in the related art, the driving chip inputs four clock signals to the first gate driving circuit through the control signal input end, and the four clock signals are the first clock signal, the second clock signal, the third clock signal and the fourth clock signal respectively.

[0065] In the embodiment of the present application, since the control signal input end 1401 is electrically connected with the first clock signal input end 1404 through the second lead line 1202 and is electrically connected with the third clock signal input end 1406 through the third lead line 1203, in the embodiment of the present application, the driving chip inputs two clock signals to the first gate driving circuit through the control signal input end 1401, which are the first clock signal and the third clock signal respectively. The first clock signal generates the second clock signal after passing through the second inverter 132, and the third clock signal generates the fourth clock signal after passing through the third inverter 133. In this way, the number of clock signals output by the driving chip can be reduced without affecting the input of four clock signals to the four clock signal input ends of the first gate driving circuit 152 respectively, thereby facilitating the reduction of the power consumption of the driving chip and the reduction of the area of the driving chip.

[0066] Exemplarily, the first clock signal is CKp, the second clock signal is CBn, the third clock signal is CBp, and the fourth clock signal is CKn.

[0067] Exemplarily, in combination with FIG. 2 and FIG. 5, the first target gate drive circuit 151 is also one of the plurality of first gate drive circuits 152 located in the first sub-peripheral area B1, and the first target gate drive circuit 151 is the first gate drive circuit 152 farthest from the first side edge 111 in the plurality of first gate drive circuits 152.

[0068] It should be noted that in FIG. 5, only two ends of the second lead line 1202 are electrically connected to the control signal input end and the first clock signal input end 1404 of one first gate drive circuit 152 (the first target gate drive circuit 151) respectively, and in FIG. 5, only two ends of the third lead line 1203 are electrically connected to the control signal input end and the third clock signal input end 1406 of one first gate drive circuit 152 (the first target gate drive circuit 151) respectively.

[0069] In a possible embodiment, in combination with FIG. 2 and FIG. 5, the second inverter 132 is electrically connected to the second clock signal input end 1405 of the plurality of first gate drive circuits 152, and the third inverter 133 is electrically connected to the fourth clock signal input end 1407 of the plurality of first gate drive circuits 152. The second inverter 132 and the third inverter 133 are both located between the first sub-peripheral area B1 and the third side edge 113. FIG. 6 is a schematic view of a planar structure of another display panel provided in an embodiment of the present application. Compared with the embodiment shown in FIG. 5, in another possible embodiment, in combination with FIG. 2 and FIG. 6, the second inverter 132 and the third inverter 133 are both located between the first sub-peripheral area B1 and the first side edge 111. Only one second inverter 132 and one third inverter 133 need to be provided, so as to input the second clock signal to the second clock signal input end 1405 of the plurality of first gate drive circuits 152 and input the fourth clock signal to the fourth clock signal input end 1407 of the plurality of first gate drive circuits 152. In addition, the second inverter 132 and the third inverter 133 are arranged above the first sub-peripheral area B1 and the display area A, or arranged below the first sub-peripheral area B1 and the display area A, instead of being arranged in the first sub-peripheral area B1, which is conducive to the narrow frame design of the display panel, especially the narrow frame design of the side frame where the first sub-peripheral area B1 is located.

[0070] It should be noted that in FIG. 6, only two ends of the second lead line 1202 are electrically connected to the control signal input end and the first clock signal input end 1404 of one first gate drive circuit 152 (the first target gate drive circuit 151) respectively, and in FIG. 6, only two ends of the third lead line 1203 are electrically connected to the control signal input end and the third clock signal input end 1406 of one first gate drive circuit 152 (the first target gate drive circuit 151) respectively.

[0071] FIG. 7 is a schematic view of a planar structure of another display panel provided by an embodiment of the present application. In combination with FIG. 2 and FIG. 7, the number of the second inverters 132 is multiple, and the number of the third inverters 133 is multiple, the multiple second inverters 132 are electrically connected to the second clock signal input ends 1405 of the multiple first gate drive circuits 152 respectively, and the multiple third inverters 133 are electrically connected to the fourth clock signal input ends 1407 of the multiple first gate drive circuits 152 respectively. The multiple second inverters 132 and the multiple third inverters 133 are located in the first sub-peripheral area B1. By arranging the multiple second inverters 132 and the multiple third inverters 133 in the first sub-peripheral area B1, the multiple second inverters 132 and the second clock signal input ends 1405 of the multiple first gate drive circuits 152 are electrically connected one by one, each second inverter 132 is used to generate a second clock signal from a first clock signal, the multiple third inverters 133 and the fourth clock signal input ends 1407 of the multiple first gate drive circuits 152 are electrically connected one by one, and each third inverter 133 is used to generate a fourth clock signal from a third clock signal, so that the number of clock signals output by the driving chip is reduced without affecting the input of the four clock signals to the four clock signal input ends of the first gate drive circuit 152, thereby facilitating the reduction of the power consumption of the driving chip and the reduction of the area of the driving chip. Alternatively, the number of the second inverters 132 is equal to the number of the first gate drive circuits 152, and the number of the third inverters 133 is equal to the number of the first gate drive circuits 152.

[0072] It should be noted that in FIG. 7, only two ends of the second lead line 1202 are electrically connected to the control signal input end and the first clock signal input end 1404 of one first gate drive circuit 152 (the first target gate drive circuit 151) respectively, and in FIG. 7, only two ends of the third lead line 1203 are electrically connected to the control signal input end and the third clock signal input end 1406 of one first gate drive circuit 152 (the first target gate drive circuit 151) respectively.

[0073] It should be noted that in FIG. 2, FIG. 3, FIG. 5, FIG. 6, FIG. 7 and other drawings, the relative positions of the display area A and the peripheral area B are only exemplarily shown, and do not represent the actual area ratio of the display area A to the peripheral area B. In fact, the peripheral area B is smaller than the display area A.

[0074] FIG. 8 is a structural schematic diagram of a second inverter and a third inverter according to an embodiment of the present application. In one possible embodiment, as shown in part (a) of FIG. 8, the second inverter 132 includes only one single-stage amplifier, and the third inverter 133 includes only one single-stage amplifier. In another possible embodiment, the second inverter 132 includes P single-stage amplifiers connected in series, where P is an odd positive integer greater than 1; and the third inverter 133 includes Q single-stage amplifiers connected in series, where Q is an odd positive integer greater than 1. For example, in the embodiment shown in part (b) of FIG. 8, P is equal to 3 and Q is equal to 3. Since the phases of the first clock signal CKp and the second clock signal CBn are opposite, the number of single-stage amplifiers in the second inverter 132 needs to be odd, so that the phase of the signal output by the second inverter 132 is opposite to the phase of the first clock signal CKp. Similarly, since the phases of the third clock signal CBp and the fourth clock signal CKn are opposite, the number of single-stage amplifiers in the third inverter 133 needs to be odd, so that the phase of the signal output by the third inverter 133 is opposite to the phase of the third clock signal CBp. Compared with the embodiment shown in part (a) of FIG. 8, in the embodiment shown in part (b) of FIG. 8, the second clock signal CBn and the fourth clock signal CKn obtained by gradually amplifying through multiple single-stage amplifiers are more stable, and have higher gain.

[0075] Hereinafter, the internal structure of the gate driving circuit is exemplarily described by taking one of the plurality of first gate driving circuits 152, i.e., a first target gate driving circuit 151 farthest from the first side edge 111, and a first gate driving circuit 152 adjacent to the first target gate driving circuit 151 as examples. Here, the first target gate driving circuit 151 is a first-stage gate driving circuit, and the first gate driving circuit 152 adjacent to the first target gate driving circuit 151 is a second-stage gate driving circuit.

[0076] FIG. 9 is a circuit structural schematic diagram of a first-stage gate driving circuit according to an embodiment of the present application, FIG. 10 is a transistor structural schematic diagram of a first-stage gate driving circuit according to an embodiment of the present application, and FIG. 11 is a structural schematic diagram of a second-stage gate driving circuit according to an embodiment of the present application.

[0077] As shown in FIGS. 9 and 10, the first-stage gate drive circuit (the first target gate drive circuit 151) needs to be inputted with the first frame start signal STV1 and the second frame start signal STV2. As shown in FIGS. 9 to 11, the first target gate drive circuit 151 needs to be inputted with four clock signals, i.e., the first clock signal CKp, the second clock signal CBn, the third clock signal CBp and the fourth clock signal CKn, and the first-stage gate drive circuit 152 adjacent to the first target gate drive circuit 151 needs to be inputted with four clock signals, i.e., the first clock signal CKp, the second clock signal CBn, the third clock signal CBp and the fourth clock signal CKn. The other first-stage gate drive circuits 152 are the same, and thus no further description is given herein.

[0078] As shown in FIGS. 9 and 10, the first-stage gate drive circuit includes an input shift module, a control module and an output amplification module. The input shift module includes a first transmission gate Tg1, a first NOR gate NOR1, a first inverter INV1 and a second transmission gate Tg2. For the two transistors in the first transmission gate Tg1, when the third clock signal CBp is at a low potential (active), the fourth clock signal CKn is at a high potential (active) because the phase of the fourth clock signal CKn is opposite to that of the third clock signal CBp, and the first transmission gate Tg1 is turned on; similarly, when the third clock signal CBp is at a high potential (inactive), the fourth clock signal CKn is at a low potential (inactive), and the first transmission gate Tg1 is turned off. Similarly, when the first clock signal CKp is at a low potential (active), the second clock signal CBn is at a high potential (active), and the second transmission gate Tg2 is turned on; when the first clock signal CKp is at a high potential (inactive), the second clock signal CBn is at a low potential (inactive), and the second transmission gate Tg2 is turned off. The first transmission gate Tg1 has a shift function, and when the third clock signal CBp and the fourth clock signal CKn are active at the same time, the first transmission gate Tg1 is turned on, so that the input end GPc_m-1 is connected to the node Q_m, the first frame start signal STV1 is inputted, and the phase of the signal at the node Q_m is shifted by one unit to the right compared with the phase of the first frame start signal STV1, thereby realizing the shift function. The first NOR gate NOR1, the first inverter INV1 and the second transmission gate Tg2 have a latching function, and can latch the signal at the node Q_m. When the third clock signal CBp is inactive and the fourth clock signal CKn is inactive, the first clock signal CKp is active and the second clock signal CBn is active, the first transmission gate Tg1 is turned off, the input end GPC_m-1 is disconnected from the node Q_m, and the second transmission gate Tg2 is turned on, so that the node Q_m is connected to the node GPC_m, thereby latching the potential of the node Q_m as the potential of the node GPC_m, until the third clock signal CBp and the fourth clock signal CKn are active.

[0079] The control module comprises a second NOR gate NOR2, a third transmission gate Tg3 and a fourth transmission gate Tg4. When the first frame start signal STV1 and the second frame start signal STV2 are active at the same time, i.e., the first frame start signal STV1 is at a low potential and the second frame start signal STV2 is at a high potential, the third transmission gate Tg3 is open. When the signal at the node GNc_m and the signal at the node GPc_m are active at the same time, i.e., the signal at the node GNc_m is at a low potential and the signal at the node GPc_m is at a high potential, the fourth transmission gate Tg4 is open. When the control signal EN1 passing through the third transmission gate Tg3 and the fourth transmission gate Tg4 in turn is at a low potential, the signal output by the first-stage gate drive circuit at the node GP_m is determined by the signal at the node GPc_m, and an effective signal is output. When the control signal EN1 is at a high potential, the signal output by the first-stage gate drive circuit at the node GP_m is set to be high, and an ineffective signal is output.

[0080] The output amplification module comprises a second inverter INV2, a third inverter INV3 and a fourth inverter INV4, which amplify the signal in stages to realize the function of amplifying the output signal.

[0081] Exemplarily, the signal output by the first-stage gate drive circuit at the node GP_m can be used as the gate input signal of a P-type thin film transistor in the pixel drive circuit, or can be used as the gate input signal of an N-type thin film transistor in the pixel drive circuit, or can be used as a reset signal in the pixel drive circuit, or can be used as a light-emitting control signal in the pixel drive circuit.

[0082] FIG. 12 is a timing diagram of a first frame start signal, a second frame start signal and a clock signal according to an embodiment of the present application. FIG. 12 shows the timing of a first frame start signal STV1, a second frame start signal STV2, a first clock signal CKp, a second clock signal CBn, a third clock signal CBp and a fourth clock signal CKn, and also shows the timing of a control signal EN1, a signal at a node GPC_m, a global reset signal Trst and a signal output by a first-stage gate drive circuit at a node GP_m. Wherein, EN1(L) means that the control signal EN1 is at a low potential.

[0083] In the embodiment shown in FIG. 3, the plurality of gate drive circuits includes a first target gate drive circuit 151 located in the first sub-peripheral region B1. FIG. 13 is a schematic diagram of a planar structure of another display panel according to an embodiment of the present application. In combination with FIG. 2 and FIG. 13, the display panel 1 further includes a fourth lead line 1204 located on the substrate 11 and located in the peripheral region B, and the at least one inverter 13 further includes a fourth inverter 134. The substrate 11 further has a fourth side 114 opposite to the second side 112, and the peripheral region B further includes a second sub-peripheral region B2 between the display region A and the fourth side 114. A second target gate drive circuit 153 in the plurality of gate drive circuits 15 is located at an end of the second sub-peripheral region B2 away from the first side 111, and the fourth inverter 134 is located outside the second sub-peripheral region B2 and the display region A away from the first side 111. At least part of the fourth lead line 1204 is located in the second sub-peripheral region B2. The second target gate drive circuit 153 has a first frame start signal input end 1402 and a second frame start signal input end 1403. Two ends of the fourth lead line 1204 are electrically connected to the control signal input end 1401 and the first frame start signal input end 1402 of the second target gate drive circuit 153, respectively. The fourth inverter 134 is electrically connected to the fourth lead line 1204 and the second frame start signal input end 1403 of the second target gate drive circuit 153, respectively. The display panel 1 includes a plurality of pixel drive circuits (not shown in FIG. 13) located on the substrate 11 and located in the display region A. The pixel drive circuits have input ends. The pixel drive circuits include a plurality of first pixel drive circuits. The first target gate drive circuit 151 has output ends. The second target gate drive circuit 153 has output ends. The output ends of the first target gate drive circuit 151, the output ends of the second target gate drive circuit 153, and the input ends of the plurality of first pixel drive circuits 151 are electrically connected. That is, the first target gate drive circuit 151 and the second target gate drive circuit 153 jointly drive the plurality of first pixel drive circuits. The first pixel drive circuits are the pixel drive circuits corresponding to the first row of pixels.

[0084] The first target gate drive circuit 151 located in the first sub-peripheral area B1 and the second target gate drive circuit B3 located in the second sub-peripheral area B2 jointly drive the plurality of first pixel drive circuits in this driving mode, also known as double-side driving. The double-side driving can improve the driving capability of the gate drive circuit, and avoid that in the display panel, especially in a medium or large size display panel, due to the large number of sub-pixels in a row and the large number of pixel drive circuits corresponding to the sub-pixels in a row, the load of the gate line is too large to normally provide the gate signal for the transistor in the pixel drive circuit. In the plurality of gate drive circuits located in the second sub-peripheral area B2, the second target gate drive circuit 153 is also a first-stage gate drive circuit, and therefore the second target gate drive circuit 153 also has a first frame start signal input end 1402 and a second frame start signal input end 1403. Similarly to the setting of the first inverter 131, the fourth inverter 134 is set in the embodiment of the application, so that the lead line electrically connecting the control signal input end 1401 and the second frame start signal input end 1403 of the second target gate drive circuit 153 can be omitted, thereby reducing the number of lead lines in the second sub-peripheral area B2, facilitating the narrow frame design of the display panel, and especially facilitating the narrow frame design of the side frame where the second sub-peripheral area B2 is located.

[0085] In the embodiment shown in FIG. 5, the plurality of gate drive circuits includes a plurality of first gate drive circuits 152 located in the first sub-peripheral area B1, and in other possible embodiments, the plurality of gate drive circuits 15 also includes a plurality of second gate drive circuits 154 located in the second sub-peripheral area B2. FIG. 14 is a schematic plan structure diagram of another display panel provided by an embodiment of the application. In combination with FIG. 2 and FIG. 14, the display panel 1 further includes a fifth lead line 1205 and a sixth lead line 1206 located on the substrate 11 and located in the peripheral area B, and the at least one inverter 13 further includes a fifth inverter 135 and a sixth inverter 136, and at least part of the fifth lead line 1205 and at least part of the sixth lead line 1206 are located in the second sub-peripheral area B2. The second gate drive circuit 154 has a first clock signal input end 1404, a second clock signal input end 1405, a third clock signal input end 1406, and a fourth clock signal input end 1407. Two ends of the fifth lead line 1205 are electrically connected to the control signal input end 1401 and the first clock signal input end 1404 of the plurality of second gate drive circuits 154, respectively, and the fifth inverter 135 is electrically connected to the fifth lead line 1205 and the second clock signal input end 1405 of the second gate drive circuit 154. Two ends of the sixth lead line 1206 are electrically connected to the control signal input end 1401 and the third clock signal input end 1406 of the plurality of second gate drive circuits 154, respectively, and the sixth inverter 136 is electrically connected to the sixth lead line 1206 and the fourth clock signal 1407 input end of the second gate drive circuit 154.

[0086] Compared with the embodiment shown in FIG. 5, in the embodiment shown in FIG. 14, the plurality of gate driving circuits 15 further include a plurality of second gate driving circuits 154 located in the second sub-peripheral area B2, and the fifth inverter 135 and the sixth inverter 136 are correspondingly arranged. FIG. 15 is a schematic diagram of a planar structure of another display panel provided in an embodiment of the present application. Compared with the embodiment shown in FIG. 6, in combination with FIG. 2 and FIG. 15, the plurality of gate driving circuits 15 further include a plurality of second gate driving circuits 154 located in the second sub-peripheral area B2, and the fifth inverter 135 and the sixth inverter 136 are correspondingly arranged. In the embodiment shown in FIG. 14 and the embodiment shown in FIG. 15, the number of clock signals output by the driving chip can be reduced without affecting the input of the four clock signals to the four clock signal input terminals of the second gate driving circuit 154, thereby facilitating the reduction of the power consumption of the driving chip and the reduction of the area of the driving chip.

[0087] In addition, in the embodiment shown in FIG. 14, the fifth inverter 135 and the sixth inverter 136 are arranged above the second sub-peripheral area B1 and the display area A, and in the embodiment shown in FIG. 15, the fifth inverter 135 and the sixth inverter 136 are arranged below the second sub-peripheral area B1 and the display area A, which is beneficial to the narrow-frame design of the display panel, especially the narrow-frame design of the side frame where the second sub-peripheral area B2 is located.

[0088] FIG. 16 is a schematic diagram of a planar structure of another display panel provided in an embodiment of the present application. Compared with the embodiment shown in FIG. 7, in combination with FIG. 2 and FIG. 16, the plurality of gate driving circuits 15 further include a plurality of second gate driving circuits 154 located in the second sub-peripheral area B2, and the fifth inverter 135 and the sixth inverter 136 are correspondingly arranged, so as to reduce the number of clock signals output by the driving chip without affecting the input of the four clock signals to the four clock signal input terminals of the second gate driving circuit 154, thereby facilitating the reduction of the power consumption of the driving chip and the reduction of the area of the driving chip.

[0089] In the embodiments shown in FIGS. 5-7, or in the embodiments shown in FIGS. 14-16, each gate drive circuit 15 has four clock signal input terminals, and of the four clock signals, two clock signals are respectively opposite to the other two clock signals. In other possible embodiments, each gate drive circuit has two clock signal input terminals, and one clock signal is opposite to the other clock signal. FIG. 17 is a schematic view of a planar structure of another display panel provided in an embodiment of the present application. In combination with FIGS. 2 and 17, the display panel 1 further includes a seventh lead line 1207 located on the substrate 11 and located in the peripheral area B, the at least one inverter further includes a seventh inverter 137, and at least part of the seventh lead line 1207 is located in the first sub-peripheral area B1. The plurality of gate drive circuits 15 includes a plurality of first gate drive circuits 152 located in the first sub-peripheral area B1, and the first gate drive circuit 152 has a fifth clock signal input terminal 1408 and a sixth clock signal input terminal 1409. Two ends of the seventh lead line 1207 are electrically connected to the control signal input terminal 1401 and the fifth clock signal input terminal 1408 of the plurality of first gate drive circuits 152, respectively, and the seventh inverter 137 is electrically connected to the seventh lead line 1207 and the sixth clock signal input terminal 1409 of the first gate drive circuit 152. In the embodiment shown in FIG. 17, an inverter can also be provided to generate the sixth clock signal after the fifth clock signal passes through the inverter. In the related art, the control signal input terminal is electrically connected to the fifth clock signal input terminal and the sixth clock signal input terminal of the first gate drive circuit, respectively, that is, in the related art, the driving chip inputs two clock signals to the first gate drive circuit through the control signal input terminal, and the two clock signals are the fifth clock signal and the sixth clock signal. In the embodiment of the present application, since the control signal input terminal 1401 is electrically connected to the fifth clock signal input terminal 1408 through the seventh lead line 1207, in the embodiment of the present application, the driving chip inputs one clock signal to the first gate drive circuit through the control signal input terminal 1401, which is the fifth clock signal. The sixth clock signal is generated after the fifth clock signal passes through the seventh inverter 137. In this way, the number of clock signals output by the driving chip can be reduced without affecting the input of two clock signals to the two clock signal input terminals of the first gate drive circuit 152, thereby facilitating the reduction of the power consumption of the driving chip and the reduction of the area of the driving chip.

[0090] For example, the fifth clock signal is CK, and the sixth clock signal is CB; or the fifth clock signal is CB, and the sixth clock signal is CK.

[0091] Exemplarily, as shown in FIG. 17, the seventh inverter 137 is located between the first sub-peripheral area and the third side edge 113. Alternatively, the seventh inverter 137 can also be located between the first sub-peripheral area B1 and the first side edge 111. Alternatively, the seventh inverter 137 can also be located in the first sub-peripheral area B1.

[0092] The internal structure of the inverter is exemplarily described below. FIG. 18 is a structural schematic diagram of an inverter according to an embodiment of the present application. As shown in FIG. 18, the inverter 13 has an input end 1301 and an output end 1302, and includes an N-type thin film transistor and a P-type thin film transistor. The input end 1301 of the inverter 13 is electrically connected to the gate 1303 of the N-type thin film transistor and the gate 1304 of the P-type thin film transistor, respectively. The output end 1302 of the inverter is electrically connected to the drain 1305 of the N-type thin film transistor and the drain 1306 of the P-type thin film transistor, respectively. The display panel 1 further includes a first power line VGH and a second power line VGL on the substrate 11. The first power line VGH transmits an electric signal with a higher potential than the electric signal transmitted by the second power line VGL. The first power line VGH is electrically connected to the source 1308 of the P-type thin film transistor, and the second power line is electrically connected to the source 1307 of the N-type thin film transistor. When a low potential signal is input to the input end 1301, the source 1308 and the drain 1306 of the P-type thin film transistor are turned on, and the source 1307 and the drain 1305 of the N-type thin film transistor are turned off. The first power line VGH outputs a high potential through the P-type thin film transistor, so that when a low potential signal is input to the input end 1301 of the inverter 13, a high potential signal is output from the output end 1302 of the inverter 13. When a high potential signal is input to the input end 1301, the source 1308 and the drain 1306 of the P-type thin film transistor are turned off, and the source 1307 and the drain 1305 of the N-type thin film transistor are turned on. The second power line VGL outputs a low potential through the N-type thin film transistor, so that when a high potential signal is input to the input end 1301 of the inverter 13, a low potential signal is output from the output end 1302 of the inverter 13. In this way, the phase of the electric signal output from the output end 1302 of the inverter 13 is opposite to the phase of the electric signal input to the input end 1301 of the inverter 13, so that the second frame start signal STV2 opposite to the first frame start signal STV1 is obtained through the first inverter 131, the second clock signal CBn opposite to the first clock signal CKp is obtained through the second inverter 132, and the fourth clock signal CKn opposite to the third clock signal CBp is obtained through the third inverter 133. The fourth inverter, the fifth inverter and the sixth inverter are the same, and are not described herein.

[0093] FIG. 19 is a schematic view of a cross-sectional structure of a display panel according to an embodiment of the present application. As shown in FIG. 19, the display panel includes, in sequence, a first active layer 1701, a first gate layer 1702, a second gate layer 1703, a second active layer 1704, a third gate layer 1705, and a first source-drain layer 1706, which are stacked on a substrate 11. FIGS. 20 and 21 are schematic views of film layer structures of a first inverter, a first power supply line, and a second power supply line according to an embodiment of the present application. In combination with FIGS. 18, 19, 20, and 21, in the first inverter 131, the active layer 1310 of the P-type thin film transistor is located on the first active layer 1701, the gate 1304 of the P-type thin film transistor is located on the first gate layer 1702, the source 1306 and the drain 1308 of the P-type thin film transistor are located on the first source-drain layer 1706, the active layer 1309 of the N-type thin film transistor is located on the second active layer 1704, the gate 1303 of the N-type thin film transistor is located on the third gate layer 1705, and the source 1307 and the drain 1305 of the N-type thin film transistor are located on the first source-drain layer 1706. In combination with FIGS. 18, 19, and 20(b), the active layer 1309 of the N-type thin film transistor is located on the second active layer 1704, and the orthogonal projection of the active layer 1309 of the N-type thin film transistor on the substrate 11 at least partially overlaps the orthogonal projection of the second gate layer 1703 on the substrate 11. Since the material for manufacturing the active layer 1309 of the N-type thin film transistor generally includes metal oxide semiconductor material such as indium gallium zinc oxide (IGZO), and the material for manufacturing the active layer 1310 of the P-type thin film transistor generally includes low-temperature polysilicon material, IGZO is more active than low-temperature polysilicon material, and thus the active layer 1309 of the N-type thin film transistor is more likely to be affected by light. By making the orthogonal projection of the active layer 1309 of the N-type thin film transistor on the substrate 11 at least partially overlap the orthogonal projection of the second gate layer 1703 on the substrate 11, the second gate layer 1703 can shield light for the active layer 1309 of the N-type thin film transistor, and reduce the influence of external light on the N-type thin film transistor, for example, reduce the degree of shift of the threshold voltage of the N-type thin film transistor.

[0094] It should be noted that in FIGS. 20 and 21, a via for electrically connecting structures located at different layers is also shown, and the via is schematically shown as a rectangle or a circle.

[0095] Exemplarily, the active layer of the N-type thin film transistor in the second inverter, the third inverter, and other inverters can also be arranged to have an orthogonal projection on the substrate at least partially overlap the orthogonal projection of the second gate layer on the substrate.

[0096] Exemplarily, as shown in FIG. 19, the display panel further includes a first gate insulating layer 1709, a second gate insulating layer 1710, a buffer layer 1711, a third gate insulating layer 1712, an interlayer dielectric layer 1713, a first planarization layer 1714, a second source-drain layer 1707, a second planarization layer 1715, a third source-drain layer 1708, and a third planarization layer 1716. As shown in FIG. 19, on the substrate 11, the first active layer 1701, the first gate insulating layer 1709, the first gate layer 1702, the second gate insulating layer 1710, the second gate layer 1703, the buffer layer 1711, the second active layer 1704, the third gate insulating layer 1712, the third gate layer 1705, the interlayer dielectric layer 1713, the first source-drain layer 1706, the first planarization layer 1714, the second source-drain layer 1707, the second planarization layer 1715, the third source-drain layer 1708, and the third planarization layer 1716 are sequentially stacked. Among them, the first power line VGH and the second power line VGL are located in the second source-drain layer 1707.

[0097] Exemplarily, the substrate 11 can be a hard substrate or a flexible substrate, such as a glass substrate, a quartz substrate, a plastic substrate, etc. The substrate 11 can be a single-layer or a multi-layer structure. Taking the multi-layer structure as an example, the substrate 11 includes a first polyimide layer, a first protective layer, a second polyimide layer, and a second protective layer which are sequentially stacked from bottom to top. The two protective layers are used to protect the polyimide layer and prevent the polyimide layer from being damaged by subsequent processes. The substrate 11 is also covered with a buffer layer which can block water and oxygen and block alkali ions.

[0098] Exemplarily, the manufacturing materials of the first gate insulating layer 1709, the second gate insulating layer 1710, the third gate insulating layer 1712, and the interlayer dielectric layer 1713 include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0099] Exemplarily, the manufacturing materials of the first gate layer 1702, the second gate layer 1703, and the third gate layer 1705 include metal materials, such as one or more of molybdenum, copper, and aluminum.

[0100] Exemplarily, the manufacturing materials of the first planarization layer 1714, the second planarization layer 1715, and the third planarization layer 1716 include organic insulating materials, such as resin, etc.

[0101] Exemplarily, the first source-drain layer 1706, the second source-drain layer 1707, and the third source-drain layer 1708 include metal materials, such as a molybdenum layer, an aluminum layer, and a molybdenum layer which are sequentially stacked, or a titanium layer, an aluminum layer, and a titanium layer which are sequentially stacked.

[0102] FIG. 22 is a flowchart of a manufacturing method of a display panel according to an embodiment of the present application. As shown in FIG. 22, the method comprises the following steps.

[0103] In step 2201, a substrate is provided, which has a display area and a peripheral area outside the display area.

[0104] In step 2202, a first lead line, a control signal input end, at least one inverter and a plurality of gate drive circuits are manufactured on the substrate.

[0105] In the above embodiment, the first lead line, the control signal input end, the at least one inverter and the plurality of gate drive circuits are located in the peripheral area, the at least one inverter comprises a first inverter, the substrate has a first side edge and a second side edge adjacent to each other, the control signal input end is located between the display area and the first side edge, the peripheral area comprises a first sub-peripheral area located between the display area and the second side edge, a first target gate drive circuit of the plurality of gate drive circuits is located at one end of the first sub-peripheral area away from the first side edge, the first inverter is located at an outer side of the first sub-peripheral area and the display area away from the first side edge, at least part of the first lead line is located in the first sub-peripheral area, the first target gate drive circuit has a first frame start signal input end and a second frame start signal input end, two ends of the first lead line are electrically connected to the control signal input end and the first frame start signal input end of the first target gate drive circuit respectively, and the first inverter is electrically connected to the first lead line and the second frame start signal input end of the first target gate drive circuit respectively.

[0106] In summary, the manufacturing method of the display panel according to the embodiments of the present application manufactures a display panel comprising a substrate, a first lead line, a control signal input end, a first inverter and a first target gate drive circuit. The first target gate drive circuit is located at one end of the first sub-peripheral area away from the first side edge, two ends of the first lead line are electrically connected to the control signal input end and the first frame start signal input end of the first target gate drive circuit respectively, the first inverter is connected to the first lead line and the second frame start signal input end of the first target gate drive circuit respectively by setting the first inverter, and the first inverter is located at an outer side of the first sub-peripheral area and the display area away from the first side edge. Therefore, the present application can not set a lead line for inputting the second frame start signal to the first target gate drive circuit in the first sub-peripheral area, so as to reduce the number of lead lines in the first sub-peripheral area, and further to facilitate the reduction of the frame of the display panel, and to realize the narrow frame design of the display panel, especially the narrow frame design of the side frame where the first sub-peripheral area is located.

[0107] The embodiments of the present application further provide a display control method for controlling any of the above display panels, which comprises the following steps.

[0108] In the first step, a control instruction is obtained.

[0109] Second step: based on the control instruction, input the first frame start signal to the first lead line, so as to input the first frame start signal to the first target gate drive circuit through the first lead line, and input the second frame start signal to the first target gate drive circuit through the first lead line and the first inverter in turn.

[0110] In summary, the display control method provided by the embodiments of the present application controls a display panel including a substrate, a first lead line, a control signal input end, a first inverter and a first target gate drive circuit. The first target gate drive circuit is located at one end of the first sub-peripheral area away from the first side edge. The two ends of the first lead line are electrically connected to the control signal input end and the first frame start signal input end of the first target gate drive circuit, respectively. The first inverter is connected to the first lead line and the second frame start signal input end of the first target gate drive circuit, respectively, and is located outside the first sub-peripheral area and the display area away from the first side edge. Therefore, the present application can not set a lead line for inputting the second frame start signal to the first target gate drive circuit in the first sub-peripheral area, so as to reduce the number of lead lines in the first sub-peripheral area, and further facilitate the reduction of the frame of the display panel, and achieve the narrow frame design of the display panel, especially the narrow frame design of the side frame where the first sub-peripheral area is located.

[0111] FIG. 23 is a structural schematic diagram of a display device provided by an embodiment of the present application. As shown in FIG. 23, the display device includes a driving chip 2 and any of the aforementioned display panels. The driving chip 2 is electrically connected to the control signal input end 1401.

[0112] Exemplarily, the display device provided by the embodiments of the present application can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

[0113] The display device has the same effects as the aforementioned display panel, and will not be described here again.

[0114] It should be noted that the terms used in the description of the embodiments of the present application are only used to explain the embodiments of the present application, and are not intended to limit the present application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be understood as the usual meaning understood by those skilled in the art to which the embodiments of the present application belong. The terms "first", "second", "third" and the like used in the patent application description and claims of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. Similarly, "one" or "a" and the like do not represent a quantity limit, but represent the existence of at least one. The terms "include" or "contain" and the like mean that the elements or objects appearing before "include" or "contain" cover the elements or objects listed after "include" or "contain" and their equivalents, and do not exclude other elements or objects. The orientation language mentioned in the present application, such as "top", "bottom", "upper", "lower", "left" or "right", etc. is only the direction of the drawing, therefore, the orientation language used is to better, more clearly explain and understand the present application, and is not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0115] The above is only an optional embodiment of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A display panel, characterized by, The display panel comprises a substrate substrate having a display area and a peripheral area outside the display area; The display panel further comprises a first lead wire, a control signal input end, at least one inverter and a plurality of gate drive circuits on the substrate substrate and in the peripheral area, the at least one inverter comprising a first inverter; The substrate substrate has adjacent first and second side edges, the control signal input end is between the display area and the first side edge, the peripheral area comprises a first sub-peripheral area between the display area and the second side edge, a first target gate drive circuit in the plurality of gate drive circuits is at one end of the first sub-peripheral area away from the first side edge, and the first inverter is at an outer side of the first sub-peripheral area and the display area away from the first side edge; At least part of the first lead wire is in the first sub-peripheral area, the first target gate drive circuit has a first frame start signal input end and a second frame start signal input end, two ends of the first lead wire are electrically connected with the control signal input end and the first frame start signal input end of the first target gate drive circuit respectively, and the first inverter is electrically connected with the first lead wire and the second frame start signal input end of the first target gate drive circuit respectively.

2. The display panel of claim 1, wherein, The substrate substrate further has a third side edge opposite to the first side edge; The first inverter is between the first sub-peripheral area and the third side edge.

3. The display panel of claim 2, wherein, The first inverter comprises N single-stage amplifiers connected in series, N is a positive odd number and N is greater than 1.

4. The display panel of claim 2, wherein, The display panel further comprises a second lead wire and a third lead wire on the substrate substrate and in the peripheral area, the at least one inverter further comprises a second inverter and a third inverter, at least part of the second lead wire and at least part of the third lead wire are in the first sub-peripheral area, the plurality of gate drive circuits comprise a plurality of first gate drive circuits in the first sub-peripheral area, and the first gate drive circuit has a first clock signal input end, a second clock signal input end, a third clock signal input end and a fourth clock signal input end; Two ends of the second lead wire are electrically connected with the control signal input end and the first clock signal input end of the plurality of first gate drive circuits respectively, and the second inverter is electrically connected with the second lead wire and the second clock signal input end of the first gate drive circuit; Two ends of the third lead wire are electrically connected with the control signal input end and the third clock signal input end of the plurality of first gate drive circuits respectively, and the third inverter is electrically connected with the third lead wire and the fourth clock signal input end of the first gate drive circuit.

5. The display panel of claim 4, wherein, The second inverter is electrically connected with the second clock signal input end of the plurality of first gate drive circuits, and the third inverter is electrically connected with the fourth clock signal input end of the plurality of first gate drive circuits; The second inverter and the third inverter are both between the first sub-peripheral area and the first side edge.

6. The display panel of claim 4, wherein, The second inverter is electrically connected with the second clock signal input end of the plurality of first gate driving circuits, and the third inverter is electrically connected with the fourth clock signal input end of the plurality of first gate driving circuits. The second inverter and the third inverter are located between the first sub-peripheral area and the third side edge.

7. The display panel of claim 4, wherein, The number of the second inverters is a plurality, and the number of the third inverters is a plurality, the plurality of second inverters are respectively electrically connected with the second clock signal input end of the plurality of first gate driving circuits, and the plurality of third inverters are respectively electrically connected with the fourth clock signal input end of the plurality of first gate driving circuits. The plurality of second inverters and the plurality of third inverters are located in the first sub-peripheral area.

8. The display panel of claim 4, wherein, The second inverter comprises P single-stage amplifiers connected in series, and P is a positive odd number greater than 1. The third inverter comprises Q single-stage amplifiers connected in series, and Q is a positive odd number greater than 1.

9. The display panel of claim 4, wherein, The display panel further comprises a fourth lead line located on the substrate and located in the peripheral area, and the at least one inverter further comprises a fourth inverter. The substrate further has a fourth side edge opposite to the second side edge, the peripheral area further comprises a second sub-peripheral area between the display area and the fourth side edge, a second target gate driving circuit in the plurality of gate driving circuits is located at one end of the second sub-peripheral area away from the first side edge, and the fourth inverter is located at the outer side of the second sub-peripheral area and the display area away from the first side edge. At least part of the fourth lead line is located in the second sub-peripheral area, the second target gate driving circuit has a first frame start signal input end and a second frame start signal input end, two ends of the fourth lead line are respectively electrically connected with the control signal input end and the first frame start signal input end of the second target gate driving circuit, and the fourth inverter is respectively electrically connected with the fourth lead line and the second frame start signal input end of the second target gate driving circuit. The display panel further comprises a plurality of pixel driving circuits located on the substrate and located in the display area, the pixel driving circuit has an input end, the pixel driving circuit comprises a plurality of first pixel driving circuits, the first target gate driving circuit has an output end, the second target gate driving circuit has an output end, and the output end of the first target gate driving circuit, the output end of the second target gate driving circuit and the input end of the plurality of first pixel driving circuits are electrically connected.

10. The display panel of claim 9, wherein, The display panel further comprises a fifth lead line and a sixth lead line located on the substrate and located in the peripheral area, the at least one inverter further comprises a fifth inverter and a sixth inverter, at least part of the fifth lead line and at least part of the sixth lead line are located in the second sub-peripheral area, and the plurality of gate driving circuits further comprise a plurality of second gate driving circuits located in the second sub-peripheral area, the second gate driving circuit has a first clock signal input end, a second clock signal input end, a third clock signal input end and a fourth clock signal input end. Two ends of the fifth lead line are electrically connected with the control signal input end and first clock signal input ends of the plurality of second gate driving circuits respectively, and the fifth inverter is electrically connected with the fifth lead line and second clock signal input ends of the second gate driving circuits; Two ends of the sixth lead line are electrically connected with the control signal input end and third clock signal input ends of the plurality of second gate driving circuits respectively, and the sixth inverter is electrically connected with the sixth lead line and fourth clock signal input ends of the second gate driving circuits.

11. The display panel of claim 4, wherein, The inverter has an input end and an output end, and comprises an N-type thin film transistor and a P-type thin film transistor. The input end of the inverter is electrically connected with the gate of the N-type thin film transistor and the gate of the P-type thin film transistor respectively. The output end of the inverter is electrically connected with the drain of the N-type thin film transistor and the drain of the P-type thin film transistor respectively. The display panel further comprises a first power line and a second power line on the substrate. The electric potential of the electric signal transmitted by the first power line is higher than the electric potential of the electric signal transmitted by the second power line. The first power line is electrically connected with the source of the P-type thin film transistor, and the second power line is electrically connected with the source of the N-type thin film transistor.

12. The display panel of claim 11, wherein, The display panel comprises, in sequence, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer and a first source-drain layer on the substrate. The active layer of the P-type thin film transistor is located in the first active layer, the gate of the P-type thin film transistor is located in the first gate layer, the source and the drain of the P-type thin film transistor are located in the first source-drain layer, the active layer of the N-type thin film transistor is located in the second active layer, the gate of the N-type thin film transistor is located in the third gate layer, and the source and the drain of the N-type thin film transistor are located in the first source-drain layer. The active layer of the N-type thin film transistor has a projection on the substrate, and the projection at least partially overlaps with a projection of the second gate layer on the substrate.

13. The display panel of claim 2, wherein, The display panel further comprises a seventh lead line on the substrate and located in the peripheral area. The at least one inverter further comprises a seventh inverter. At least part of the seventh lead line is located in the first sub-peripheral area. The plurality of gate driving circuits comprises a plurality of first gate driving circuits located in the first sub-peripheral area. The first gate driving circuit has a fifth clock signal input end and a sixth clock signal input end. Two ends of the seventh lead line are electrically connected with the control signal input end and the fifth clock signal input ends of the plurality of first gate driving circuits respectively, and the seventh inverter is electrically connected with the seventh lead line and the sixth clock signal input ends of the first gate driving circuits.

14. A manufacturing method of a display panel, comprising: The method comprises: providing a substrate having a display area and a peripheral area outside the display area; manufacturing a first lead line, a control signal input end, at least one inverter and a plurality of gate driving circuits on the substrate; and The first lead, the control signal input end, the at least one inverter and the plurality of gate drive circuits are located in the peripheral area, the at least one inverter comprises a first inverter, the substrate substrate has adjacent first and second side edges, the control signal input end is located between the display area and the first side edge, the peripheral area comprises a first sub-peripheral area located between the display area and the second side edge, a first target gate drive circuit in the plurality of gate drive circuits is located at one end of the first sub-peripheral area away from the first side edge, the first inverter is located at an outer side of the first sub-peripheral area and the display area away from the first side edge, at least part of the first lead is located in the first sub-peripheral area, the first target gate drive circuit has a first frame start signal input end and a second frame start signal input end, two ends of the first lead are electrically connected with the control signal input end and the first frame start signal input end of the first target gate drive circuit respectively, and the first inverter is electrically connected with the first lead and the second frame start signal input end of the first target gate drive circuit respectively.

15. A display device comprising: The display device comprises a driving chip and the display panel as claimed in any one of claims 1 to 13, and the driving chip is electrically connected with the control signal input end.

16. A display control method characterized by comprising: The display control method is used for controlling the display device as claimed in any one of claims 1 to 13, and the display control method comprises: obtaining a control instruction; based on the control instruction, inputting a first frame start signal to the first lead, so as to input the first frame start signal to the first target gate drive circuit through the first lead, and in turn input a second frame start signal to the first target gate drive circuit through the first lead and the first inverter.

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