Display panel

Abstract

A display panel, comprising a plurality of display panel regions. The plurality of display panel regions comprise a display region, a first encapsulation transition region surrounding the display region, and a second encapsulation transition region surrounding the first encapsulation transition region. The display panel comprises a substrate, pixel units disposed on the substrate, an encapsulation layer, and a first power bus. The pixel units are located in the display region, and the encapsulation layer is located on the side of the pixel units facing away from the substrate and extends from the display region to the first encapsulation transition region. The first power bus comprises a plurality of first traces located in the second encapsulation transition region and a first connection portion located in the first encapsulation transition region. In a first direction, the plurality of first traces are arranged side by side, and the plurality of first traces are in one-to-one correspondence with the display panel regions. The pixel units located in the display panel regions are electrically connected to the first traces corresponding to the display panel regions. Two adjacent first traces are connected by means of the first connection portion. The first traces are closer to the substrate than the first connection portion.

Description

Display panel TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a display panel. BACKGROUND

[0002] With the development of display technology, in order to improve the preparation efficiency of multi-size display products, generally, a small-size display panel can be cut from a large-size display panel to form a multi-size display panel.

[0003] However, due to the complexity of the peripheral wiring of the non-display area of the large-size display panel, the hard conditions of the wiring structure itself and the layout space of the non-display area, etc., the cutting process is easy to affect the packaging of the small-size display panel, thereby affecting the yield and reliability of the product. SUMMARY

[0004] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a display panel.

[0005] In a first aspect, a technical solution adopted to solve the technical problems of the present disclosure is a display panel, comprising a plurality of display panel areas, and the plurality of display panel areas are arranged side by side along a first direction; the plurality of display panel areas comprise a display area, a first packaging transition area surrounding the display area, and a second packaging transition area surrounding the first packaging transition area.

[0006] The display panel comprises a substrate, a pixel unit arranged on the substrate, a packaging layer, and a first power bus; the pixel unit is located in the display area, the packaging layer is located on a side of the pixel unit away from the substrate, and extends from the display area to the first packaging transition area;

[0007] The first power bus comprises a plurality of first wires located in the second packaging transition area, and a first adapter located in the first packaging transition area; in the first direction, the plurality of first wires are arranged side by side, and the plurality of first wires correspond one-to-one to the display panel areas; each pixel unit located in the display panel area is electrically connected to the corresponding first wire of the display panel area; the first wires of two adjacent segments are connected through the first adapter; the first wires are closer to the substrate than the first adapter.

[0008] In some embodiments, the display panel further comprises a second power bus located in the first packaging transition area; the first power bus and the second power bus are respectively located on two opposite sides of the display area;

[0009] Each pixel unit located in the display area is electrically connected to the second power bus.

[0010] In some embodiments, the second power bus includes a plurality of second traces and a second adapter; in the first direction, the plurality of second traces are arranged side by side, and two adjacent second traces are connected by the second adapter; the second adapter is closer to the substrate than the second trace.

[0011] In some embodiments, the second trace is arranged in the same layer as the first adapter; and the second adapter is arranged in the same layer as the first trace.

[0012] In some embodiments, the plurality of pixel units in the display area are arranged in a plurality of rows and a plurality of columns; the row direction represents the first direction, and the column direction represents the second direction; the first direction and the second direction intersect.

[0013] The display panel further includes a plurality of first power lines arranged on the substrate, the first power lines extending in the second direction, and the pixel units in the same column being electrically connected to the same first power line.

[0014] The first power line is arranged in the same layer as the second trace; and two ends of the first power line are electrically connected to the first trace and the second trace in the same display panel area, respectively.

[0015] In some embodiments, the display panel includes a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer arranged in sequence on a side of the substrate close to the encapsulation layer.

[0016] The first trace and the second adapter are both located in the first conductive layer; and the first power line, the second trace, and the first adapter are all located in the third conductive layer.

[0017] In some embodiments, the display panel further includes a third power bus extending in the first direction; and a projection of the third power bus on the substrate is closer to the display area than a projection of the first trace on the substrate.

[0018] Each pixel unit in the display area is electrically connected to the third power bus.

[0019] In some embodiments, the third power bus is arranged in the same layer as the first adapter.

[0020] In some embodiments, the display panel further comprises a fourth power bus; the third power bus and the fourth power bus are respectively located at two opposite sides of the display area, and a projection of the fourth power bus on the substrate is farther away from the display area than a projection of the second power bus on the substrate;

[0021] Each pixel unit located in the display area is electrically connected to the fourth power bus.

[0022] In some embodiments, the layer where the fourth power bus is located is farther away from the substrate than the layer where the third power bus is located.

[0023] In some embodiments, the third power bus is located in the third conductive layer, and the fourth power bus is located in the fourth conductive layer.

[0024] In some embodiments, the display panel further comprises a plurality of second power lines arranged on the substrate, the second power lines extend along a second direction, and the pixel units located in the same column are electrically connected to the same second power line.

[0025] The second power lines are arranged in the same layer as the third power bus, and the two ends of the second power lines are respectively electrically connected to the third power bus and the fourth power bus located in the same display panel area.

[0026] In some embodiments, the fourth power bus comprises a plurality of fourth traces and a fourth adapter located in the first packaging transition area; in the first direction, the plurality of fourth traces are arranged side by side, and the fourth traces correspond one-to-one to the display panel area; each second power line located in the display panel area is electrically connected to the fourth trace corresponding to the display panel area.

[0027] Two adjacent fourth traces are connected by the fourth adapter, and the fourth adapter is closer to the substrate than the fourth trace.

[0028] In some embodiments, the fourth trace is located in the fourth conductive layer, and the fourth adapter is arranged in the same layer as the first adapter.

[0029] In some embodiments, the display panel further comprises a fifth power bus;

[0030] The fifth power bus includes a fifth trace and a sixth trace oppositely arranged in the first direction, and a seventh trace extending along the first direction and connecting the fifth trace and the sixth trace; the fifth trace and the sixth trace are both located in the second packaging transition region; a projection of the seventh trace on the substrate substrate is farther away from the display area than a projection of the first power bus on the substrate substrate;

[0031] The first end and the second end of the third power bus are electrically connected with the fifth trace and the sixth trace respectively; the first end and the second end of the fourth power bus are electrically connected with the fifth trace and the sixth trace respectively.

[0032] In some embodiments, the fifth trace, the sixth trace and the seventh trace are all located in the second conductive layer; the first end of the third power bus and the first end of the fourth power bus are electrically connected with the fifth trace through a third connection via and a fourth connection via respectively; the second end of the third power bus and the second end of the fourth power bus are electrically connected with the sixth trace through a fifth connection via and a sixth connection via respectively.

[0033] In some embodiments, the seventh trace includes a plurality of first sub-traces located in the second packaging transition region and a third adapter located in the first packaging transition region; in the first direction, a plurality of the first sub-traces are arranged side by side, and the first sub-traces correspond one by one to the display panel area; adjacent two of the first sub-traces are connected through the third adapter; the first sub-trace is closer to the substrate substrate than the third adapter.

[0034] In some embodiments, the fifth trace, the sixth trace and the first sub-trace are all located in the second conductive layer; the third adapter is located in the third conductive layer.

[0035] In some embodiments, the display panel further includes a plurality of groups of first connection structures, each first adapter corresponds to two groups of first connection structures; each group of first connection structures includes a plurality of first connection portions arranged side by side in the first direction, the first connection portion extends from the first packaging transition region to the second packaging transition region, and electrically connects the first adapter and the first trace;

[0036] Different groups of first connection structures electrically connect different first traces.

[0037] In some embodiments, a projection of the packaging layer on the substrate substrate covers the projections of the first adapter, the second power bus and the third power bus on the substrate substrate.

[0038] In a second aspect, the present disclosure provides another display panel, which comprises a sub-display region and a peripheral region surrounding the sub-display region; the peripheral region comprises a cutting transition region adjacent to the sub-display region, a first encapsulation sub-transition region semi-encircling the sub-display region and the cutting transition region, and a second encapsulation sub-transition region located on a side of the first encapsulation sub-transition region away from the display region.

[0039] The display panel comprises a substrate, pixel units arranged on the substrate, an encapsulation layer, and a first wire; the pixel units are located in the sub-display region; the encapsulation layer is located on a side of the pixel units away from the substrate, and extends from the sub-display region to the first encapsulation sub-transition region and the cutting transition region; and the first wire is located in the second encapsulation sub-transition region.

[0040] In some embodiments, the display panel further comprises a second power supply sub-bus in the first encapsulation sub-transition region; the second power supply sub-bus and the first wire are located on two opposite sides of the sub-display region, respectively.

[0041] Each pixel unit in the sub-display region is electrically connected to the second power supply sub-bus.

[0042] In some embodiments, the second power supply sub-bus comprises a plurality of second wires and a second adapter;

[0043] In the first direction, the plurality of second wires are arranged side by side, and two adjacent second wires are connected by the second adapter; the second adapter is closer to the substrate than the second wires;

[0044] The second adapter is arranged in the same layer as the first wire.

[0045] In some embodiments, the display panel further comprises a third power supply sub-bus extending in the first direction; a projection of the third power supply sub-bus on the substrate is closer to the sub-display region than a projection of the first wire on the substrate;

[0046] Each pixel unit in the sub-display region is electrically connected to the third power supply sub-bus; and the third power supply sub-bus is arranged in the same layer as the second wires.

[0047] In some embodiments, the display panel further comprises a fourth power supply sub-bus; the third power supply sub-bus and the fourth power supply sub-bus are located on two opposite sides of the sub-display region, respectively; and a projection of the fourth power supply sub-bus on the substrate is farther away from the sub-display region than a projection of the second power supply sub-bus on the substrate.

[0048] Each pixel unit located in the sub-display area is electrically connected to the fourth power supply sub-bus.

[0049] In some embodiments, the display panel further comprises a fifth power supply sub-bus;

[0050] The fifth power supply sub-bus comprises a sixth wire and a first sub-wire; the sixth wire is located in the second packaging sub-transition area, and a projection of the first sub-wire on the substrate substrate is farther away from the sub-display area than a projection of the first wire on the substrate substrate.

[0051] The first end of the third power supply sub-bus, the first end of the fourth power supply sub-bus, and the first end of the first sub-wire are all electrically connected to the sixth wire.

[0052] In a third aspect, the embodiments of the present disclosure further provide a second display panel, which is obtained by cutting the display panel according to the first aspect along a cutting line, wherein the cutting line is located between any two adjacent segments of the first wire and extends in a direction perpendicular to the first direction.

[0053] In some embodiments, before cutting, the first adapter is etched to form a first opening, and the cutting line extends through the first opening. BRIEF DESCRIPTION OF DRAWINGS

[0054] FIG. 1 is a driving circuit diagram of an OLED under an example;

[0055] FIG. 2 is a film layer stack diagram of a display panel;

[0056] FIG. 3 is a planar structure diagram of a first display panel under Example 1 according to the embodiments of the present disclosure;

[0057] FIG. 4a is a planar structure diagram of a first display panel under Example 2 according to the embodiments of the present disclosure;

[0058] FIG. 4b is a partial enlarged view of a via connection area of the first power supply line in FIG. 4a;

[0059] FIG. 4c is a partial enlarged view of a via connection area of the second power supply line in FIG. 4a;

[0060] FIGS. 5a-5d are schematic diagrams of the relative position relationship between the third power supply bus and the first power supply bus;

[0061] FIG. 6 is a planar structure diagram of a first display panel under Example 3 according to the embodiments of the present disclosure;

[0062] FIG. 7 is a planar structure diagram of a first display panel under Example 4 according to the embodiments of the present disclosure;

[0063] FIG. 8 is a schematic diagram of a planar structure of a first display panel according to an embodiment of the present disclosure under Example 5;

[0064] FIG. 9 is a schematic diagram of a planar structure of a first display panel according to an embodiment of the present disclosure under Example 6;

[0065] FIG. 10a is an enlarged view of the CC region shown in FIG. 9;

[0066] FIG. 10b is an enlarged view of the DD region shown in FIG. 9;

[0067] FIG. 10c is an enlarged view of the EE region shown in FIG. 9;

[0068] FIG. 11 is a schematic diagram of a planar structure of a first display panel after etching a third conductive layer according to an embodiment of the present disclosure under an example;

[0069] FIG. 12 is a schematic diagram of a planar structure of a first display panel after etching a third conductive layer according to an embodiment of the present disclosure under another example;

[0070] FIG. 13 is a schematic diagram of a planar structure of a second display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0071] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. The components of the embodiments of the present disclosure described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the claimed present disclosure, but only represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present disclosure.

[0072] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning as understood by a person having ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms "one", "a", or "the" and similar terms do not denote a quantity of particular mentioned items, but indicate the existence of at least one of the items. The terms "comprise", "comprising", and similar terms are intended to encompass the elements listed thereafter, and equivalents thereof, without excluding other elements. The terms "connected", "coupled", and similar terms are not limited to physical or mechanical connections or couplings, but can include electrical connections or couplings, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to indicate relative positions, and can change accordingly when the absolute positions of the described objects change.

[0073] In the present disclosure, "a plurality of or several" means two or more. The term "and / or" describes an associated relationship between associated objects, and means that three relationships can exist, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after it.

[0074] In the related art, the currently mature display products in the display field include liquid crystal displays (LCD) and active matrix organic light-emitting diode (OLED) display devices. Among them, the organic light-emitting diode (OLED) is a light-emitting device that uses organic solid-state semiconductors as light-emitting materials. By means of direct recombination of electrons and holes, various wavelengths of light spectrum are excited to form an image. Due to its simple preparation process, low cost, fast response speed, low power consumption, high luminous brightness, and maximum contrast ratio, it has a broad application prospect.

[0075] As shown in FIG. 1, it is a driving circuit under an example of OLED, which adopts a circuit design of 3T1C (i.e., three transistors T and one capacitor C). Since the OLED product itself needs a device to emit light, the required light-emitting current needs to be provided by the driving transistor T3, and the power signal lines (VDD and VSS) that can bear large current are also required. This is different from liquid crystal displays, since liquid crystal displays are backlit, the power signal lines (VDD and VSS) in liquid crystal displays do not usually need to bear large current.

[0076] Power signal lines (VDD and VSS) that need to carry large current in OLED products generally need to be wide enough in line width. However, a large amount of wide power signal lines connected to the display area can easily cause large cross talk. In general, a peripheral bus line is added in the non-display area to reduce poor cross talk.

[0077] With the development of display technology, in order to improve the preparation efficiency of multi-size display products, generally, a small-size display panel can be cut from a large-size display panel to form a multi-size display panel. However, due to the complex peripheral wiring of the non-display area of the large-size display panel and the limited frame space, part of the metal wiring cannot be encapsulated and protected by the organic film layer. After the peripheral metal wiring is cut, the exposed part of the metal material is easily invaded by water vapor and electrochemical corrosion occurs, thereby affecting the encapsulation of the small-size display panel and affecting the yield and reliability of the cut product.

[0078] In view of this, the display panel provided by the embodiments of the present disclosure substantially improves the peripheral wiring structure and its layout, ensures compatibility with multi-size display panels, and does not affect the display panel, that is, the large-size display panel after being cut to form a small-size display panel does not affect the encapsulation of the small-size display panel, ensuring the yield and reliability of the cut product.

[0079] FIG. 2 is a schematic diagram of a film layer stack of a display panel, and FIG. 3 is a schematic diagram of a planar structure of a display panel according to Example 1 provided by the embodiments of the present disclosure. For ease of understanding, the film layers between the layers in the plan view are represented by perspective film layers, that is, in the plan view, the lower film layer can be seen through the upper film layer.

[0080] For ease of understanding, the large-size display panel that can be cut to form a small-size display panel is denoted as a first display panel 100, and the small-size display panel is denoted as a second display panel 200.

[0081] As shown in FIG. 3, the first display panel 100 includes a plurality of display panel areas, and the plurality of display panel areas are arranged side by side along a first direction X, such as a first display panel area AA-1 and a second display panel area AA-2. The plurality of display panel areas include a display area AA, a first encapsulation transition area BB1 surrounding the display area AA, and a second encapsulation transition area BB2 surrounding the first encapsulation transition area BB1.

[0082] As shown in FIG. 2, the first display panel 100 includes a substrate 1, a first conductive layer 21, a second conductive layer 22, a third conductive layer 23 and a fourth conductive layer 24 which are sequentially arranged on the substrate 1. The first display panel 100 further includes a pixel unit P (see FIG. 3) which is located in a display area AA and includes a light emitting device and a pixel driving circuit for driving the light emitting device. The gate of each transistor in the pixel driving circuit is located in the second conductive layer 22, the source and the drain are located in the third conductive layer 23, the anode of the light emitting device is located in the fourth conductive layer 24, and the light emitting layer EL of the light emitting device is located on the side of the anode away from the substrate 1. The first conductive layer 21 at least includes a shielding portion for shielding the transistor.

[0083] As shown in FIG. 2, the first display panel 100 further includes an encapsulation layer 3 which is arranged on the side of the pixel unit P away from the substrate 1 and extends from the display area AA to a first encapsulation transition area BB1. The encapsulation layer 3 is used for encapsulating and protecting the pixel unit P located in the display area AA and the metal traces located in the first encapsulation transition area BB1. The encapsulation layer 3 can be a single-layer or a multi-layer structure and at least includes an organic material layer. In some embodiments, the encapsulation layer 3 is a single-layer structure, for example, including an organic material layer; in other embodiments, the encapsulation layer 3 is a multi-layer structure, for example, including a first inorganic material layer, an organic material layer and a second inorganic material layer which are arranged in a stack.

[0084] As shown in FIG. 3, the first display panel 100 further includes a first power bus Bus1 which is electrically connected with a first power line VDD. The first power line VDD is used for providing a first power signal to the pixel unit P. The line width of the first power bus Bus1 is wider than that of the first power line VDD, which is conducive to reducing crosstalk.

[0085] As shown in FIG. 3, the first power bus Bus1 includes a plurality of first traces 41 located in the second encapsulation transition area BB2 and a first adapter 42 located in the first encapsulation transition area BB1. In the first direction X, the plurality of first traces 41 are arranged side by side and correspond to the display panel area one by one; each pixel unit P located in the display panel area is electrically connected with the first trace 41 corresponding to the display panel area; and two adjacent first traces 41 are connected through the first adapter 42.

[0086] The first trace 41 is closer to the substrate 1 than the first via 42. For example, as shown in FIG. 2, the first trace 41 is located in the first conductive layer 21. The first via 42 is located in the third conductive layer 23 or the second conductive layer 22. In order to facilitate the subsequent etching process of the first via 42, the first via 42 is located in the third conductive layer 23 which is closer to the top layer (i.e., farther away from the substrate 1). For another example, the first trace 41 is located in the second conductive layer 22, and the first via 42 is located in the third conductive layer 23. The following disclosure is described by way of example with the first trace 41 located in the first conductive layer 21 and the first via 42 located in the third conductive layer 23.

[0087] For example, the first via 42 is located in the third conductive layer 23.

[0088] The first display panel 100 provided by the embodiments of the present disclosure can be understood as a large-size display panel, which can be used as an independent display panel and a display mother board of a small-size display panel (i.e., a second display panel 200) to be cut subsequently. The first display panel 100 is divided into a plurality of display panel regions arranged side by side along a first direction X, and the structure in each display panel region can be understood as a small-size display panel to be cut, which has a smaller size than the large-size display panel. The first power bus Bus1 includes a plurality of first wires 41, and the plurality of first wires 41 are arranged one by one corresponding to the display panel regions, that is, one second display panel 200 includes one first wire 41. Limited by the limited frame wiring space, the first wire 41 is located in the second packaging transition area BB2, although the first wire 41 is not covered and protected by the packaging layer 3, in the present disclosure, the first wire 41 is arranged close to the conductive layer of the substrate 1 (compared with the first transition part 42), and the side of the first wire 41 close to the first transition part 42 of the first display panel 100 or the second display panel 200 at least includes an insulating protective layer (such as the first insulating wire 25 and the second insulating layer 26 described below), which is beneficial to protect the first wire 41. At the same time, the first display panel 100 serves as a display mother board of two adjacent second display panels 200, and the two adjacent first wires 41 are arranged to be disconnected near the cutting line S, which can avoid the electrochemical corrosion of the first wire 41 in the process of cutting to form the second display panel 200. In addition, for the independent first display panel 100, the first wires 41 are connected through the first transition part 42 between the two first wires 41, and the packaging layer 3 can protect the first transition part 42 located in the first packaging transition area BB1 to avoid water and oxygen corrosion. The first display panel 100 as a display mother board will preferentially etch the first transition part 42 near the cutting line S to form a first opening 42a (see FIG. 12 described below) before the first display panel 100 is cut to form the second display panel 200, so as to avoid the electrochemical corrosion of the first transition part 42 in the cutting process. It can be seen that the present disclosure improves the peripheral wiring structure and layout of the first display panel 100, so that it is compatible with multiple-size display panels (such as itself and multiple second display panels 200), ensures that the peripheral layout of the first power bus Bus1 does not affect the packaging of the large-size display panel and the second display panel 200, and does not affect the cutting of the second display panel 200, and guarantees the yield and reliability of the compatible multiple-size display panels.

[0089] For example, as shown in FIG. 3, the two adjacent first wires 41 are arranged at intervals in the first direction X. The distance from the end of the single first wire 41 close to the cutting line S to the cutting line S is greater than 1.5 mm, which ensures that the subsequent cutting process has no effect on the first wire 41.

[0090] In some embodiments, as shown in FIG. 3, the first display panel 100 further includes a second power bus Bus2 located in the first packaging transition area BB1. The second power bus Bus2 extends in the first direction X. The first power bus Bus1 and the second power bus Bus2 are located on two opposite sides of the display area AA, respectively. Specifically, the first power bus Bus1 and the second power bus Bus2 are located on two opposite sides of the display area AA in the second direction Y, respectively. The second direction Y intersects the first direction X. For example, the first direction X and the second direction Y are perpendicular to each other in the horizontal plane. Each pixel unit P located in the display area AA is electrically connected to the second power bus Bus2.

[0091] The second power bus Bus2 is electrically connected to the first power line VDD.

[0092] For example, as shown in FIG. 3, the first display panel 100 includes a first bezel area and a second bezel area located opposite to each other in the first direction X, and a third bezel area and a fourth bezel area located opposite to each other in the second direction Y. For example, the first bezel area is an upper bezel area, the second bezel area is a lower bezel area, the third bezel area is a left bezel area, and the fourth bezel area is a right bezel area. The first bezel area, the second bezel area, the third bezel area, and the fourth bezel area are connected to form a non-display area surrounding the display area AA. The non-display area includes the first packaging transition area BB1 surrounding the display area AA, and the second packaging transition area BB2 surrounding the first packaging transition area BB1. The first power bus Bus1 is located in the first bezel area, and the second power bus Bus2 is located in the second bezel area.

[0093] The second power bus Bus2 added in the second bezel area can reduce the voltage attenuation of the first power signal in each pixel unit P, average the voltage of the first power signal in each pixel unit P, and reduce the influence of IR drop.

[0094] For example, the orthographic projection of the packaging layer 3 on the substrate substrate covers the orthographic projection of the second power bus Bus2 on the substrate substrate.

[0095] In some embodiments, as shown in FIG. 3, since the second power bus Bus2 is located in the lower bezel area, the layer (the third conductive layer 23) in which the second power bus Bus2 in the lower bezel area is located has more crossing lines, such as data lines located in the third conductive layer 23. The data lines extend from the display area AA to the lower bezel area and are electrically connected to the source driver (Source IC). During the extension, the data lines need to cross the second power bus Bus2. Since the number of data lines is large, electrostatic discharge (ESD) is prone to occur at the crossing position. Therefore, the second power bus Bus2 is connected in a crossing manner to reduce the probability of ESD.

[0096] Specifically, FIG. 4a is a schematic diagram of a planar structure of the first display panel under Example 2 provided by the embodiment of the present disclosure, as shown in FIG. 4a, the second power bus Bus2 includes a plurality of second wires 51 and a second adapter 52; in the first direction X, the plurality of second wires 51 are arranged side by side, and two adjacent second wires 51 are connected by the second adapter 52; the second adapter 52 is closer to the substrate 1 than the second wire 51.

[0097] Compared with the structure shown in FIG. 3, the second power bus Bus2 in the third conductive layer 23 is broken to obtain a plurality of second wires 51, and two adjacent second wires 51 are arranged with a spacing. The number of the segments of the second wire 51 obtained by breaking is much smaller than the number of the data lines in the display area AA, and compared with the structure shown in FIG. 3, the probability of ESD occurring across the wires is reduced. Reducing the length of the second power bus Bus2 in the third conductive layer 23 can avoid high incidence of ESD at the cross-connection position.

[0098] Optionally, as shown in FIG. 2, the second wire 51 is arranged in the same layer as the first adapter 42, for example, both are in the third conductive layer 23. For the preparation of the second display panel 200, in the subsequent etching process of the second wire 51 and the first adapter 42 along the cutting line S, the second wire 51 and the first adapter 42 can be etched synchronously, thereby improving the process efficiency.

[0099] Optionally, as shown in FIG. 2, the second adapter 52 is arranged in the same layer as the first wire 41, that is, both are in the first conductive layer 21. The first conductive layer 21 and the third conductive layer 23 are provided with a first insulating layer 25 and a second insulating layer 26, and the cross-connection position of the second adapter 52 and the second wire 51 is protected by the multi-layer insulating protective layer, thereby further reducing the probability of ESD occurring across the wires. In addition, the first conductive layer 21 serves as a bottom metal layer, and the wiring is relatively less than that of the upper metal layer, so that the pattern of the second adapter 52 is arranged in the first conductive layer 21, thereby reducing signal interference.

[0100] In some embodiments, as shown in FIG. 3 or FIG. 4a, a plurality of pixel units P in the display area AA are arranged in a multi-row and multi-column array; the row direction represents the first direction X, and the column direction represents the second direction Y; the first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y can be perpendicular to each other; the first display panel 100 further includes a plurality of first power lines VDD arranged on the substrate 1, the first power lines VDD extend along the second direction Y, and the pixel units P in the same column are electrically connected to the same first power line VDD. The pixel units P in the same column receive a first power signal through the first power line VDD, and the first power signal can be, for example, a positive power signal.

[0101] Optionally, as shown in FIG. 4a, the first power line VDD is arranged in the same layer as the second trace 51, for example, both are located in the third conductive layer 23, without a via connection, so as to facilitate the electrical connection between the second trace 51 and the first power line VDD, and facilitate the use of the same preparation process to prepare them at the same time.

[0102] The first trace 41 is located in the first conductive layer 21; the first power line VDD and the second trace 51 are located in the third conductive layer 23. The two ends of the first power line VDD are respectively electrically connected to the first trace 41 and the second trace 51 located in the same display panel area.

[0103] FIG. 4b is a partial enlarged view of the via connection area of the first power line in FIG. 4a, and FIG. 4c is a partial enlarged view of the via connection area of the second power line in FIG. 4a. As shown in FIG. 4b and FIG. 4c, the first end of the first power line VDD is electrically connected to the first trace 41 through the first adapter via V1, and the second end of the first power line VDD is electrically connected to the second trace 51. As shown in FIG. 2, the first adapter via V1 is a via that penetrates the first insulating layer 25 and the second insulating layer 26 in the direction away from the substrate 1, wherein the first insulating layer 25 is arranged between the first conductive layer 21 and the second conductive layer 22, and the second insulating layer 26 is arranged between the second conductive layer 22 and the third conductive layer 23.

[0104] In some embodiments, as shown in FIG. 3 or FIG. 4a, the first display panel 100 further comprises a third power bus Bus3 extending along the first direction X; the orthogonal projection of the third power bus Bus3 on the substrate 1 is closer to the display area AA than the orthogonal projection of the first trace 41 on the substrate 1. Each pixel unit P located in the display area AA is electrically connected to the third power bus Bus3.

[0105] As shown in FIG. 4b, the third power bus Bus3 is electrically connected to the second power line VSS.

[0106] FIGS. 5a-5d are schematic diagrams of the relative position relationship between the third power bus Bus3 and the first power bus Bus1.

[0107] Optionally, as shown in FIG. 5a, the orthogonal projection of the third power bus Bus3 on the substrate 1 is closer to the display area AA than the orthogonal projection of the first adapter portion 42 on the substrate 1.

[0108] Optionally, as shown in FIG. 5b, the orthogonal projection of the third power bus Bus3 on the substrate 1 is farther away from the display area AA than the orthogonal projection of the first adapter portion 42 on the substrate 1.

[0109] Optionally, as shown in FIG. 5c, the third power bus Bus3 includes a main body part Bus31 provided with a second opening D1 penetrating through in a thickness direction thereof, and the first adapter part 42 is arranged in the second opening D1. The orthographic projection of the main body part Bus31 on the substrate 1 does not overlap the orthographic projection of the first adapter part 42 on the substrate 1.

[0110] Optionally, the second opening D1 can be a closed opening as shown in FIG. 5c, or a non-closed opening as shown in FIG. 5d, for example, an opening facing the first trace 41.

[0111] Optionally, as shown in FIG. 4a and FIG. 4b, the third power bus Bus3 is electrically connected with a second power line VSS. The second power line VSS is configured to provide a second power signal to the pixel unit P, and the second power signal can be a negative power signal for example. The line width of the third power bus Bus3 is greater than the line width of the second power line VSS, which is conducive to reducing resistance and crosstalk.

[0112] Exemplarily, the orthographic projection of the packaging layer 3 on the substrate 1 covers the orthographic projection of the third power bus Bus3 on the substrate 1.

[0113] In some embodiments, as shown in FIG. 3 or FIG. 4a, the third power bus Bus3 is arranged in the same layer as the first adapter part 42. Optionally, as shown in FIG. 2, the third power bus Bus3 and the first adapter part 42 are both located in the third conductive layer 23. When the first display panel 100 is used as a display master panel of the second display panel 200, the third power bus Bus3 and the first adapter part 42 can be etched synchronously in a subsequent etching process along the cutting line S, thereby improving process efficiency.

[0114] In some embodiments, as shown in FIG. 3 or FIG. 4a, the first display panel 100 further includes a fourth power bus Bus4. The fourth power bus Bus4 extends in the first direction X. The third power bus Bus3 and the fourth power bus Bus4 are respectively located on two opposite sides of the display area AA. Specifically, the third power bus Bus3 and the fourth power bus Bus4 are respectively located on two opposite sides of the display area AA in the second direction Y. Each pixel unit P located in the display area AA is electrically connected with the fourth power bus Bus4.

[0115] As shown in FIG. 4c, the fourth power bus Bus4 is electrically connected with the second power line VSS.

[0116] Optionally, the fourth power bus Bus4 has a projection on the substrate 1 that is farther away from the display area AA than the projection of the second power bus Bus2 on the substrate 1. The fourth power bus Bus4 is used to transmit a second power signal, which is a ground signal and has a small current. In addition, the fourth power bus Bus4 is affected by its material, for example, the fourth power bus Bus4 is made of a material that is not prone to oxidation and is not prone to electrochemical corrosion, so the fourth power bus Bus4 can be located in the second packaging transition area BB2 and is not protected by the packaging layer 3.

[0117] Of course, if the space of the second frame area is sufficient, the fourth power bus Bus4 can be located in the first packaging transition area BB1.

[0118] Optionally, the layer where the fourth power bus Bus4 is located is farther away from the substrate 1 than the layer where the third power bus Bus3 is located. For example, as shown in FIG. 2, the third power bus Bus3 is located in the third conductive layer 23, and the fourth power bus Bus4 can be located in the fourth conductive layer 24 or other conductive layer farther away from the third conductive layer 23 on the side of the fourth conductive layer 24.

[0119] Optionally, the fourth power bus Bus4 is a whole line, and the structure of the embodiment is applied to a bottom emission type transistor. The fourth power bus Bus4 and the anode of the light emitting device are both located in the fourth conductive layer 24. The material of the fourth conductive layer 24 can be indium tin oxide (ITO) material, which is not prone to electrochemical corrosion.

[0120] For example, as shown in FIG. 2, the first adapter 42, the second line 51, and the third power bus Bus3 are located in the same layer and are located in the third conductive layer 23. When the first display panel 100 is used as a display master of the second display panel 200, the first adapter 42, the second line 51, and the third power bus Bus3 can be etched synchronously, thereby improving the preparation efficiency.

[0121] Optionally, the line width of the fourth power bus Bus4 is greater than the line width of the second power line VSS.

[0122] In some embodiments, as shown in FIG. 3 or FIG. 4a, the first display panel 100 further includes a plurality of second power lines VSS arranged on the substrate 1, the second power lines VSS extend along the second direction Y, and the pixel units P located in the same column are electrically connected to the same second power line VSS. The pixel units P located in the same column are electrically connected to receive a second power signal through the second power line VSS. The second power signal is a ground signal.

[0123] Optionally, as shown in FIG. 2, FIG. 3 or FIG. 4a, the second power supply line VSS is arranged in the same layer as the third power bus Bus3, for example, both are located in the third conductive layer 23, without a cross-line connection, facilitating the electrical connection between the third power bus Bus3 and the second power supply line VSS, and facilitating the simultaneous preparation of the two.

[0124] Optionally, as shown in FIG. 3 or FIG. 4a, the fourth power bus Bus4 is located in the fourth conductive layer 24. The two ends of the second power supply line VSS are respectively electrically connected to the third power bus Bus3 and the fourth power bus Bus4 located in the same display panel area. As shown in FIG. 4b and FIG. 4c, the first end of the second power supply line VSS is electrically connected to the third power bus Bus3, and the second end of the second power supply line VSS is electrically connected to the fourth power bus Bus4 through the second adapter via hole V2. As shown in FIG. 2, the second adapter via hole V2 is a via hole penetrating through the third insulating layer 27, wherein the third insulating layer 27 is arranged between the third conductive layer 23 and the fourth conductive layer 24.

[0125] In some embodiments, FIG. 6 is a schematic diagram of the planar structure of the first display panel under Example 3 provided by the embodiments of the present disclosure, which is different from the structure shown in FIG. 4a in that the fourth power bus Bus4 is arranged in segments, and adjacent two segments of the fourth trace 61 are connected through other film layer conductors. The specific structure is as follows.

[0126] As shown in FIG. 6, the fourth power bus Bus4 includes a plurality of fourth traces 61 and a fourth adapter 62 located in the first packaging transition area BB1; in the first direction X, the plurality of fourth traces 61 are arranged side by side, and the plurality of fourth traces 61 correspond one-to-one to the display panel areas (AA-1 or AA-2); each second power supply line VSS located in the display panel area is electrically connected to the fourth trace 61 corresponding to the display panel area; and adjacent two segments of the fourth trace 61 are connected through the fourth adapter 62.

[0127] The fourth adapter 62 is closer to the substrate 1 than the fourth trace 61. Optionally, as shown in FIG. 2, the fourth trace 61 is located in the fourth conductive layer 24; the fourth adapter 62 is arranged in the same layer as the first adapter 42, for example, both are located in the third conductive layer 23 or the second conductive layer 22. In order to facilitate the subsequent etching process of the conductive material near the cutting line S, the first adapter 42 and the fourth adapter 62 are arranged in the third conductive layer 23 which is closer to the top layer (i.e., farther away from the substrate 1).

[0128] The embodiment is applied to a top emission transistor. The fourth conductive layer 24 is the layer where the anode of the light emitting device is located. At this time, the fourth conductive layer 24 is doped with a metal such as copper. Corrosion is prone to occur near the cutting line S. Therefore, the fourth conductive layer 24 is arranged with a spacing between two adjacent fourth wires 61, and the fourth adapter 62 is used for bridging. The fourth adapter 62 is arranged on the third conductive layer 23 and located in the first packaging transition area BB1. The fourth adapter 62 is packaged and protected by the packaging layer 3.

[0129] Optionally, the fourth adapter 62, the first adapter 42 and the second power supply line VSS are all located on the third conductive layer 23.

[0130] In some embodiments, FIG. 7 is a planar structure schematic diagram of a first display panel under Example 4 provided by the embodiment of the present disclosure. FIG. 8 is a planar structure schematic diagram of a first display panel under Example 5 provided by the embodiment of the present disclosure. FIG. 9 is a planar structure schematic diagram of a first display panel under Example 6 provided by the embodiment of the present disclosure. Compared with the structure shown in FIG. 6, a fifth power bus is additionally arranged.

[0131] As shown in FIG. 7, the first display panel 100 further includes a fifth power bus. The fifth power bus includes a fifth wire 71 and a sixth wire 72 arranged opposite to each other in the first direction X, and a seventh wire 73 extending along the first direction X and connecting the fifth wire 71 and the sixth wire 72. The fifth wire 71 and the sixth wire 72 are both located in the second packaging transition area BB2. The orthogonal projection of the seventh wire 73 on the substrate 1 is farther away from the display area AA than the orthogonal projection of the first power bus Bus1 on the substrate 1. The first end and the second end of the third power bus Bus3 are electrically connected with the fifth wire 71 and the sixth wire 72 respectively. The first end and the second end of the fourth power bus Bus4 are electrically connected with the fifth wire 71 and the sixth wire 72 respectively.

[0132] As shown in FIG. 7, the seventh wire 73, the fifth wire 71, the fourth power bus Bus4 and the sixth wire 72 are sequentially connected at the first end and the second end to form a first electrostatic ring structure, which is conducive to improving ESD.

[0133] As shown in FIG. 7, the seventh wire 73, a part of the fifth wire 71, the third power bus Bus3 and a part of the sixth wire 72 are sequentially connected at the first end and the second end to form a second electrostatic ring structure, which is conducive to improving ESD.

[0134] Optionally, as shown in FIG. 7, the fifth power bus is located in the second conductive layer 22. For a large-size display panel, the fifth trace 71, the sixth trace 72 and the seventh trace 73 can be arranged in the second packaging transition area BB2. Although not protected by the packaging layer 3, the fifth trace 71, the sixth trace 72 and the seventh trace 73 are located in the second conductive layer 22 closer to the substrate 1, and the upper layer has multiple insulation protective layers (the second insulation layer 26 and the third insulation layer 27), and in addition, the fifth power bus is a ground line, and the current is small, so it is not easy to be corroded by water and oxygen.

[0135] In addition, it should be noted that the first display panel 100 is a display mother panel of the second display panel 200. Before cutting, the sixth opening 732a (see FIG. 11 or 12) needs to be etched near the cutting line S where the seventh trace 73 is located, so as to avoid poor electrochemical corrosion of the cutting surface.

[0136] Optionally, as shown in FIG. 8, the first display panel 100 is a display mother panel of the second display panel 200, and the edge wiring of the first display panel 100 can be further improved. Specifically, the seventh trace 73 includes multiple first sub-traces 731 located in the second packaging transition area BB2 and a third adapter 732. In the first direction X, the multiple first sub-traces 731 are arranged side by side, and the multiple first sub-traces 731 correspond to the display panel area one by one. The extension direction of the first sub-trace 731 is the same as the first direction X. The adjacent two first sub-traces 731 are connected through the third adapter 732. The first sub-trace 731 is closer to the substrate 1 than the third adapter 732.

[0137] As shown in FIG. 8, the third adapter 732 is located in the second packaging transition area BB2. The orthogonal projection of the third adapter 732 on the substrate 1 overlaps the orthogonal projection of the first sub-trace 731 on the substrate 1.

[0138] For example, the first sub-trace 731 is located in the second conductive layer 22, and the third adapter 732 is located in the third conductive layer 23. The third adapter 732, the first adapter 42, the second trace 51 and the third power bus Bus3 are arranged in the same layer, i.e., the third conductive layer 23. When the first display panel 100 is a display mother panel of the second display panel 200, the third adapter 732, the first adapter 42, the second trace 51 and the third power bus Bus3 can be etched synchronously during the etching of the second trace 51 and the first adapter 42 along the cutting line S, so as to improve the process efficiency.

[0139] For example, as shown in FIG. 8 or FIG. 10c, the first sub-trace 731 is electrically connected to the third adapter 732 through an eighth connection via V8. The eighth connection via V8 is a via penetrating the second insulation layer 26.

[0140] Optionally, as shown in FIG. 9, based on the structure of FIG. 8, the edge wiring of the first display panel 100 can be further improved, specifically: the third adapter is located at 732 in the first packaging transition area BB1. The first sub-wire 731 is electrically connected with the third adapter located at 732 through the second connection structure 90. The third adapter 732 is connected between two adjacent first sub-wires 731, and the packaging layer 3 can protect the third adapter 732 located in the first packaging transition area BB1, avoiding water and oxygen corrosion.

[0141] Optionally, as shown in FIG. 2, the fifth wire 71, the sixth wire 72 and the first sub-wire 731 are all located in the second conductive layer 22; and the third adapter 732 is located in the third conductive layer 23.

[0142] FIG. 10a is an enlarged view of the CC area shown in FIG. 9, and FIG. 10b is an enlarged view of the DD area shown in FIG. 9. As shown in FIG. 10a and FIG. 10b, the first end of the third power bus Bus3 and the first end of the fourth power bus Bus4 are electrically connected with the fifth wire 71 through the third connection via V3 and the fourth connection via V4 respectively; similarly, the second end of the third power bus Bus3 and the second end of the fourth power bus Bus4 are electrically connected with the sixth wire 72 through the fifth connection via V5 and the sixth connection via V6 respectively. The third connection via V3 and the fifth connection via V5 are vias penetrating through the second insulating layer 26. The fourth connection via V4 and the sixth connection via V6 are vias penetrating through the second insulating layer 26 and the third insulating layer 27 in sequence in the direction away from the substrate 1.

[0143] In some embodiments, as shown in FIG. 5a-5d, the first display panel 100 further comprises a plurality of groups of first connection structures 80, each first adapter corresponds to two groups of first connection structures 80; each group of first connection structures 80 comprises a plurality of first connection parts 81 arranged side by side in the first direction X, the first connection part 81 is extended from the second packaging transition area BB2 to the first packaging transition area BB1, and is electrically connected with the first adapter 42 and the first wire 41; different groups of first connection structures 80 are electrically connected with different first wires 41.

[0144] Optionally, the first connection part 81 is arranged in the same layer as the first wire 41, and the electrically connected first connection part 81 and the first wire 41 are connected as an integrated structure. The first connection part 81 is electrically connected with the first adapter 42 through the seventh connection via V7. The seventh connection via V7 is a via penetrating through the second insulating layer 26 and the third insulating layer 27 in sequence in the direction away from the substrate 1.

[0145] In this embodiment, each group of first connection structures 80 comprises a plurality of first connection parts 81, which improves the electrical connection stability between different segments of the first wire 41.

[0146] In some embodiments, as shown in FIG. 9, the first display panel 100 further comprises a plurality of groups of second connecting structures 90, each third adapter 732 corresponds to two groups, each group of second connecting structures 90 comprises a plurality of second connecting portions 91 arranged side by side along the first direction X, the second connecting portion 91 extends from the second packaging transition area BB2 to the first packaging transition area BB1, and electrically connects the third adapter 732 and the first sub-wire 731; different groups of second connecting structures 90 electrically connect different first sub-wires 731.

[0147] Optionally, the second connecting portion 91 is arranged in the same layer as the first sub-wire 731, and the electrically connected second connecting portion 91 and the first sub-wire 731 are connected as an integrated structure. FIG. 10c is an enlarged view of the EE area shown in FIG. 9, as shown in FIG. 10c, the second connecting portion 91 is electrically connected with the third adapter 732 through the eighth connecting via V8. Wherein, the eighth connecting via V8 is a via penetrating through the second insulating layer 26 in a direction away from the substrate 1.

[0148] In the embodiment, each group of second connecting structures 90 comprises a plurality of second connecting portions 91, which improves the electrical connection stability between different segments of the first sub-wire 731.

[0149] In some embodiments, two adjacent first wires 41 are connected through a first adapter 42. One first display panel 100 actually comprises at least two display panel areas. When the first display panel 100 is used as a display motherboard of the second display panel 200, the at least two display panel areas correspond to at least two second display panels 200 to be cut.

[0150] For example, the first display panel 100 is divided into three display panel areas arranged side by side along the first direction X; the first power bus Bus1 comprises three segments of first wires 41 located in the second packaging transition area BB2, and two first adapters 42 located in the first packaging transition area BB1; along the first direction X, the three segments of first wires 41 are arranged side by side, and each segment of first wire 41 corresponds to a display panel area; the extension direction of the first wire 41 is the same as the first direction X. Along the first direction X, two adjacent first wires 41 are overlapped through different groups of first connecting structures 80 and the first adapter 42.

[0151] For example, the first display panel 100 is a 48-inch display panel, and each display panel area corresponds to a 26.3-inch second display panel 200.

[0152] Exemplarily, for a bottom emission type device, the process preparation sequence of the partial film layers of the first display panel 100 includes: a substrate substrate→a first conductive layer 21 (e.g., a light shielding layer)→a first insulating layer 25→an active layer→a second conductive layer 22 (i.e., a gate electrode layer)→a second insulating layer 26→a third conductive layer 23 (i.e., a source-drain electrode layer)→a passivation layer (a third insulating layer 27)→a color filter layer→a planarization layer (a third insulating layer 27)→a fourth conductive layer 24 (an anode layer of a light emitting device)→a pixel definition layer→a light emitting layer→an encapsulation layer 3→a cover plate.

[0153] The third insulating layer 27 includes a multi-layer structure, for example, the passivation layer and the planarization layer.

[0154] Exemplarily, for a top emission type device, the process preparation sequence of the partial film layers of the first display panel 100 includes: a substrate substrate→a first conductive layer 21 (e.g., a light shielding layer)→a first insulating layer 25→an active layer→a second conductive layer 22 (i.e., a gate electrode layer)→a second insulating layer 26→a third conductive layer 23 (i.e., a source-drain electrode layer)→a passivation layer (a third insulating layer 27)→a fourth conductive layer 24 (an anode layer of a light emitting device)→a pixel definition layer→a light emitting layer→a planarization layer (a fourth insulating layer)→a color filter layer→an encapsulation layer 3→a cover plate.

[0155] In addition, the embodiment of the present disclosure further provides a second display panel 200, which can be cut from the first display panel 100 obtained by the above-mentioned various embodiments and combinations thereof. Specifically, a preparation method of a second display panel 200 includes steps S11-S13, wherein:

[0156] S11, as shown in FIG. 9, a first display panel 100 is provided.

[0157] A cutting line S is formed between two adjacent display panel regions arranged side by side in the first direction X, and the cutting line S passes through the first adapter 42.

[0158] S12, as shown in FIG. 11, the first adapter 42 is etched to form a first opening 42a.

[0159] The cutting line S passes through the first opening 42a.

[0160] In some embodiments, as shown in FIG. 11, the first display panel 100 includes the third transfer part 732 on the third conductive layer 23, the first transfer part 42, the third power bus Bus3 and the second trace 51. For S12, taking a bottom emission type device as an example, the third transfer part 732, the first transfer part 42, the third power bus Bus3 and the second trace 51 are patterned by one patterning process to form the sixth opening 732a, the first opening 42a, the third opening Bus31 and the fourth opening Bus21 respectively. In the second direction Y, from the upper frame to the lower frame, the cutting line S passes through the sixth opening 732a, the first opening 42a, the third opening Bus31 and the fourth opening Bus21 in turn.

[0161] In some embodiments, as shown in FIG. 12, the first display panel 100 includes the third transfer part 732 on the third conductive layer 23, the first transfer part 42, the third power bus Bus3, the second trace 51 and the fourth transfer part 62. For S12, taking a top emission type device as an example, the third transfer part 732, the first transfer part 42, the third power bus Bus3, the second trace 51 and the fourth transfer part 62 are patterned by one patterning process to form the sixth opening 732a, the first opening 42a, the third opening Bus31, the fourth opening Bus21 and the fifth opening Bus41 respectively. In the second direction Y, from the upper frame to the lower frame, the cutting line S passes through the sixth opening 732a, the first opening 42a, the third opening Bus31, the fourth opening Bus21 and the fifth opening Bus41 in turn.

[0162] S13, as shown in FIG. 13, the first display panel 100 after etching is cut along the cutting line S to obtain a plurality of second display panels 200.

[0163] The first display panel 100 provided by the embodiments of the present disclosure is compatible with display panels of multiple sizes, for example, can be a large-size display panel of 48 inches or two second display panels 200 of 26.3 inches. The first display panel 100 serves as a display motherboard of the second display panel 200, and the first wire 41 is located in the second packaging transition area BB2. Although the first wire 41 is not covered and protected by the packaging layer 3, the first wire 41 is arranged relatively close to the conductive layer of the substrate 1 (compared with the first adapter 42), and the side of the first wire 41 close to the first adapter 42 includes at least one insulating protective layer (for example, the first insulating layer 25, the second insulating layer 26 and the third insulating layer 27), which is conducive to protecting the first wire 41. The two adjacent first wires 41 in the first display panel 100 are arranged to be disconnected near the cutting line S, and the distance from the end of the single-segment first wire 41 close to the cutting line S to the cutting line S is greater than 1.5 mm, so as to avoid poor corrosion of the cutting process on the cutting surface of the first power bus Bus1. The first display panel 100 serves as a display motherboard, and the first adapter 42 is etched near the cutting line S before the actual cutting process, to form the first opening 42a, so as to avoid corrosion of the cutting surface. It can be seen that the peripheral wire structure and the layout thereof are improved, the display panels of multiple sizes are compatible, the peripheral layout of the first power bus Bus1 does not affect the packaging and cutting of the second display panel 200, and the product yield and reliability are ensured.

[0164] In some embodiments, as shown in FIG. 13, the second display panel 200 includes a sub-display area AA0 and a peripheral area surrounding the sub-display area AA0; the peripheral area includes a cutting transition area AA01 adjacent to the sub-display area AA0, a first packaging sub-transition area BB01 surrounding the sub-display area AA0 and the cutting transition area AA01, and a second packaging sub-transition area BB02 located on the side of the first packaging sub-transition area BB01 away from the display area; the second display panel 200 includes a substrate, a pixel unit P arranged on the substrate, a packaging layer 3 and a first wire 41; the pixel unit P is located in the sub-display area AA0; the packaging layer 3 is located on the side of the pixel unit P away from the substrate, and extends from the sub-display area AA0 to the first packaging sub-transition area BB01 and the cutting transition area AA01; and the first wire 41 is located in the second packaging sub-transition area BB02.

[0165] For example, the first wire 41 belongs to a part of the first power sub-bus Bus01, and the first power sub-bus Bus01 further includes a first residual part 421 of the first adapter 42 remaining after cutting.

[0166] It should be noted that the cutting transition area AA01 belongs to a part of the display area AA of the first display panel 100; the cutting transition area AA01 includes a virtual pixel unit located near the cutting line S and not used for display.

[0167] In some embodiments, as shown in FIG. 13, the second display panel 200 further includes a second power supply sub-bus Bus02 located at the first encapsulation sub-transition region BB01, the second power supply sub-bus Bus02 and the first wire 41 are located at two opposite sides of the sub-display region AA0 respectively; each pixel unit P located in the sub-display region AA0 is electrically connected to the second power supply sub-bus Bus02.

[0168] Each column of pixel units P is electrically connected to a same first power supply line VDD, two ends of each first power supply line VDD are electrically connected to the first wire 41 and the second power supply sub-bus Bus02 respectively.

[0169] In some embodiments, as shown in FIG. 13, the second power supply sub-bus Bus02 includes a plurality of second wires 51 and a second adapter 52; in the first direction X, the plurality of second wires 51 are arranged side by side, and adjacent two second wires 51 are connected through the second adapter 52; the second adapter 52 is closer to the substrate than the second wire 51. Optionally, the second adapter 52 is arranged in the same layer as the first wire 41.

[0170] For example, as shown in FIG. 13, the second power supply sub-bus Bus02 further includes a second residual part 511 left after the second wire 51 (or the second adapter 52) is cut.

[0171] In some embodiments, as shown in FIG. 13, the plurality of pixel units P located in the sub-display region AA0 are arranged in a plurality of rows and a plurality of columns; the row direction represents the first direction X, and the column direction represents the second direction Y. The second display panel 200 further includes a plurality of first power supply lines VDD arranged on the substrate, the first power supply lines VDD extend along the second direction Y, and the pixel units P located in a same column are electrically connected to a same first power supply line VDD; the first power supply line VDD is arranged in the same layer as the second wire 51; two ends of the first power supply line VDD are electrically connected to the first wire 41 and the second wire 51 respectively.

[0172] In some embodiments, as shown in FIG. 13, the second display panel 200 includes a first conductive layer 21, a second conductive layer 22, a third conductive layer 23 and a fourth conductive layer 24 arranged in sequence on a side of the substrate close to the encapsulation layer 3; the first wire 41 and the second adapter 52 are located in the first conductive layer 21; the first power supply line VDD, the second wire 51 and the first residual part 421 are located in the third conductive layer 23.

[0173] In some embodiments, as shown in FIG. 13, the second display panel 200 further includes a third power supply sub-bus Bus03 extending along the first direction X; a projection of the third power supply sub-bus Bus03 on the substrate substrate is closer to the sub-display area AA0 than a projection of the first trace 41 on the substrate substrate; each pixel unit P located in the sub-display area AA0 is electrically connected to the third power supply sub-bus Bus03; and the third power supply sub-bus Bus03 is disposed in the same layer as the second trace 51.

[0174] In some embodiments, as shown in FIG. 13, the second display panel 200 further includes a fourth power supply sub-bus Bus04; the third power supply sub-bus Bus03 and the fourth power supply sub-bus Bus04 are located at two opposite sides of the sub-display area AA0, respectively, and a projection of the fourth power supply sub-bus Bus04 on the substrate substrate is farther away from the sub-display area AA0 than a projection of the second power supply sub-bus Bus02 on the substrate substrate; each pixel unit P located in the sub-display area AA0 is electrically connected to the fourth power supply sub-bus Bus04.

[0175] In some embodiments, the layer where the fourth power supply sub-bus Bus04 is located is farther away from the substrate substrate than the layer where the third power supply sub-bus Bus03 is located.

[0176] In some embodiments, the third power supply sub-bus Bus03 is located in the third conductive layer 32, and the fourth power supply sub-bus Bus04 is located in the fourth conductive layer 24.

[0177] In some embodiments, as shown in FIG. 13, the second display panel 200 further includes a plurality of second power supply lines VSS disposed on the substrate substrate, the second power supply lines VSS extending along the second direction Y, and the pixel units P located in the same column are electrically connected to the same second power supply line VSS; the second power supply lines VSS are disposed in the same layer as the third power supply sub-bus Bus03; and the two ends of the second power supply lines VSS are electrically connected to the third power supply sub-bus Bus03 and the fourth power supply sub-bus Bus04, respectively.

[0178] In some embodiments, as shown in FIG. 13, the second display panel 200 further includes a fifth power supply sub-bus; the fifth power supply sub-bus includes a sixth trace 72 and a first sub-trace 731; the sixth trace 72 is located in the second packaging sub-transition area BB02, and a projection of the first sub-trace 731 on the substrate substrate is farther away from the sub-display area AA0 than a projection of the first trace 41 on the substrate substrate; a first end of the third power supply sub-bus Bus03, a first end of the fourth power supply sub-bus Bus04, and a first end of the first sub-trace 731 are electrically connected to the sixth trace 72.

[0179] For example, the first sub-trace 731 belongs to a part of the seventh trace 73, and the first sub-trace 731 is further connected to a third residual part 7321 remaining after cutting the third adapter 732.

[0180] In addition, the disclosure embodiments further provide another second display panel 200, which is obtained by the preparation method of the first display panel shown in FIG. 12 as described above, and the repeated parts are not described herein again.

[0181] In addition, the disclosure embodiments further provide a display device, which comprises the first display panel 100 or the second display panel 200 of any one of the above embodiments. The display device may, for example, be a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a vehicle-mounted device, or any product with a display function. Other essential components of the display device should be understood by those skilled in the art, and are not described herein again, nor should they be considered as a limitation on the disclosure.

[0182] It can be understood that the above embodiments are only exemplary embodiments adopted for illustrating the principles of the disclosure, and the disclosure is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and essence of the disclosure, and these modifications and improvements are also considered as the protection scope of the disclosure.

Claims

1. A display panel comprising a plurality of display panel regions arranged side by side along a first direction, wherein the plurality of display panel regions comprise a display region, a first encapsulation transition region surrounding the display region, and a second encapsulation transition region surrounding the first encapsulation transition region; the display panel comprises a substrate, pixel units arranged on the substrate, an encapsulation layer, and a first power bus; the pixel units are located in the display region, the encapsulation layer is located on a side of the pixel units away from the substrate, and extends from the display region to the first encapsulation transition region; the first power bus comprises a plurality of first wires located in the second encapsulation transition region, and a first adapter located in the first encapsulation transition region; in the first direction, the plurality of first wires are arranged side by side, and the plurality of first wires correspond to the display panel regions one by one; each pixel unit located in the display panel region is electrically connected to the corresponding first wire of the display panel region; two adjacent first wires are connected through the first adapter; the first wire is closer to the substrate than the first adapter.

2. The display panel of claim 1, wherein, The display panel further comprises a second power bus located in the first encapsulation transition region; the first power bus and the second power bus are respectively located on two opposite sides of the display region; each pixel unit located in the display region is electrically connected to the second power bus.

3. The display panel of claim 2, wherein, The second power bus comprises a plurality of second wires and a second adapter; in the first direction, the plurality of second wires are arranged side by side, and two adjacent second wires are connected through the second adapter; the second adapter is closer to the substrate than the second wire.

4. The display panel of claim 3, wherein, The second wire and the first adapter are arranged in the same layer; the second adapter and the first wire are arranged in the same layer.

5. The display panel of claim 4, wherein, The plurality of pixel units located in the display region are arranged in a plurality of rows and a plurality of columns; the row direction represents the first direction, and the column direction represents a second direction; the first direction and the second direction intersect; The display panel further comprises a plurality of first power lines arranged on the substrate, wherein the first power lines extend along the second direction, and the pixel units located in the same column are electrically connected to the same first power line; The first power line and the second wire are arranged in the same layer; the two ends of the first power line are respectively electrically connected to the first wire and the second wire located in the same display panel region.

6. The display panel of claim 5, wherein, The display panel comprises a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer arranged in sequence on a side of the substrate close to the encapsulation layer; The first wire and the second adapter are located in the first conductive layer; the first power line, the second wire, and the first adapter are located in the third conductive layer.

7. The display panel of claim 6, wherein, The display panel further comprises a third power bus extending along the first direction; the orthographic projection of the third power bus on the substrate is closer to the display region than the orthographic projection of the first wire on the substrate; each pixel unit located in the display region is electrically connected to the third power bus.

8. The display panel of claim 7, wherein, The third power bus is arranged in the same layer as the first transition part.

9. The display panel of claim 7, wherein, The display panel further comprises a fourth power bus; the third power bus and the fourth power bus are respectively located at two opposite sides of the display area, and the orthogonal projection of the fourth power bus on the substrate is farther away from the display area than the orthogonal projection of the second power bus on the substrate. Each pixel unit located in the display area is electrically connected to the fourth power bus.

10. The display panel of claim 9, wherein, The layer where the fourth power bus is located is farther away from the substrate than the layer where the third power bus is located.

11. The display panel of claim 10, wherein, The third power bus is located in the third conductive layer, and the fourth power bus is located in the fourth conductive layer.

12. The display panel of claim 10, wherein, The display panel further comprises a plurality of second power lines arranged on the substrate, the second power lines extend along a second direction, and the pixel units located in the same column are electrically connected to the same second power line. The second power lines are arranged in the same layer as the third power bus; the two ends of the second power lines are respectively electrically connected to the third power bus and the fourth power bus located in the same display panel area.

13. The display panel of claim 12, wherein, The fourth power bus comprises a plurality of fourth traces and a fourth transition part located in the first packaging transition area; in the first direction, the plurality of fourth traces are arranged side by side, and the fourth traces correspond one by one to the display panel area; each second power line located in the display panel area is electrically connected to the fourth trace corresponding to the display panel area. The fourth transition part is closer to the substrate than the fourth traces.

14. The display panel of claim 13, wherein, The fourth traces are located in the fourth conductive layer; the fourth transition part is arranged in the same layer as the first transition part.

15. The display panel of claim 9, wherein, The display panel further comprises a fifth power bus. The fifth power bus comprises fifth traces and sixth traces arranged opposite to each other in the first direction, and a seventh trace extending in the first direction and connecting the fifth traces and the sixth traces; the fifth traces and the sixth traces are located in the second packaging transition area; the orthogonal projection of the seventh trace on the substrate is farther away from the display area than the orthogonal projection of the first power bus on the substrate. The first end and the second end of the third power bus are respectively electrically connected to the fifth traces and the sixth traces; the first end and the second end of the fourth power bus are respectively electrically connected to the fifth traces and the sixth traces.

16. The display panel of claim 15, wherein, The fifth traces, the sixth traces and the seventh trace are located in the second conductive layer; the first end of the third power bus and the first end of the fourth power bus are respectively electrically connected to the fifth traces through third connection vias and fourth connection vias; the second end of the third power bus and the second end of the fourth power bus are respectively electrically connected to the sixth traces through fifth connection vias and sixth connection vias.

17. The display panel of claim 15, wherein, The seventh trace includes a plurality of first sub-traces located in the second packaging transition region and a third adapter located in the first packaging transition region; in the first direction, the plurality of first sub-traces are arranged side by side, and the first sub-traces correspond to the display panel region one by one; two adjacent first sub-traces are connected through the third adapter; the first sub-trace is closer to the substrate than the third adapter.

18. The display panel of claim 17, wherein, The fifth trace, the sixth trace and the first sub-trace are located in the second conductive layer; and the third adapter is located in the third conductive layer.

19. The display panel according to any one of claims 2 to 18, wherein, The display panel further includes a plurality of groups of first connection structures, each first adapter corresponds to two groups of first connection structures; each group of first connection structures includes a plurality of first connection portions arranged side by side in a first direction, the first connection portions extend from the first packaging transition region to the second packaging transition region, and electrically connect the first adapter and the first trace; Different groups of first connection structures electrically connect different first traces.

20. The display panel according to any one of claims 7 to 18, wherein, The orthogonal projection of the packaging layer on the substrate covers the orthogonal projection of the first adapter, the second power bus and the third power bus on the substrate.

21. A display panel comprising a sub-display region and a peripheral region surrounding the sub-display region; the peripheral region comprises a cutting transition region adjacent to the sub-display region, a first packaging sub-transition region semi-encircling the sub-display region and the cutting transition region, and a second packaging sub-transition region located on the side of the first packaging sub-transition region away from the display region. The display panel comprises a substrate, a pixel unit arranged on the substrate, a packaging layer and a first trace; the pixel unit is located in the sub-display region; the packaging layer is located on the side of the pixel unit away from the substrate, and extends from the sub-display region to the first packaging sub-transition region and the cutting transition region; and the first trace is located in the second packaging sub-transition region.

22. The display panel of claim 21, wherein, The display panel further comprises a second power sub-bus located in the first packaging sub-transition region, and the second power sub-bus and the first trace are respectively located on two opposite sides of the sub-display region. Each pixel unit located in the sub-display region is electrically connected to the second power sub-bus.

23. The display panel of claim 22, wherein, The second power sub-bus includes a plurality of second traces and a second adapter; In a first direction, the plurality of second traces are arranged side by side, and two adjacent second traces are connected through the second adapter; the second adapter is closer to the substrate than the second trace; The second adapter is arranged in the same layer as the first trace.

24. The display panel of claim 23, wherein, The display panel further comprises a third power sub-bus extending in the first direction; the orthogonal projection of the third power sub-bus on the substrate is closer to the sub-display region than the orthogonal projection of the first trace on the substrate; Each pixel unit located in the sub-display region is electrically connected to the third power sub-bus; and the third power sub-bus is arranged in the same layer as the second trace.

25. The display panel of claim 24, wherein, The display panel further comprises a fourth power supply sub-bus; the third power supply sub-bus and the fourth power supply sub-bus are respectively located at two opposite sides of the sub-display area, and a projection of the fourth power supply sub-bus on the substrate is farther away from the sub-display area than a projection of the second power supply sub-bus on the substrate; Each pixel unit located in the sub-display area is electrically connected to the fourth power supply sub-bus.

26. The display panel of claim 25, wherein, The display panel further comprises a fifth power supply sub-bus; The fifth power supply sub-bus comprises a sixth wire and a first sub-wire; the sixth wire is located in the second packaging sub-transition area, and a projection of the first sub-wire on the substrate is farther away from the sub-display area than a projection of the first wire on the substrate; A first end of the third power supply sub-bus, a first end of the fourth power supply sub-bus, and a first end of the first sub-wire are electrically connected to the sixth wire.

27. A second display panel obtained by cutting the display panel according to any one of claims 1 to 20 along a cutting line, wherein The cutting line is located between any two adjacent segments of the first wire and extends in a direction perpendicular to the first direction.

28. The second display panel of claim 27, wherein, Before cutting, the first adapter is etched to form a first opening, and the cutting line extends through the first opening.

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