Shift register and driving method therefor, gate driving circuit, and display apparatus

Abstract

A shift register and a driving method therefor, a gate driving circuit, and a display apparatus, relating to the technical field of display. The shift register comprises an input sub-circuit (1), a reset sub-circuit (2) and an output sub-circuit (3). The input sub-circuit (1) is configured to: in response to a first clock signal (CK1), use an input signal to control the potential of a first node (N1); and, in response to the input signal, use a third clock signal (CK3) to control the potential of a second node (N2), or in response to the third clock signal (CK3), use the third clock signal (CK3) to control the potential of the second node (N2). The reset sub-circuit (2) is configured to: in response to a first reset signal (dual channels), use the second clock signal (CK2) to control the potential of the first node (N1). The output sub-circuit (3) is configured to: in response to the potential of the first node (N1), output the second clock signal (CK2) by means of a signal output terminal (OUT(i)); or in response to the potential of the second node (N2), output a power supply control signal (VST) by means of the signal output terminal (OUT(i)), the power supply control signal (VST) being a non-constant voltage signal.

Description

Shift register and driving method thereof, gate drive circuit and display device TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a shift register and a driving method thereof, a gate drive circuit and a display device. BACKGROUND

[0002] Gate Drive on Array (GOA) technology is a technology commonly used in current display products to realize the row-by-row scanning driving of the gate of a transistor in a pixel driving circuit by manufacturing a gate drive circuit on a substrate. The gate drive circuit includes a plurality of cascaded shift registers, and each shift register usually needs to be electrically connected to a plurality of power signal lines transmitting constant voltage signals for its own power supply. However, due to the constant voltage difference between the plurality of power signal lines transmitting constant voltage signals for a long time, electrochemical corrosion is prone to occur between the power signal lines, causing signal short circuit, and further leading to the failure of the shift register. SUMMARY

[0003] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a shift register and a driving method thereof, a gate drive circuit and a display device.

[0004] In a first aspect, a technical solution adopted to solve the technical problems of the present disclosure is a shift register, comprising an input sub-circuit, a reset sub-circuit and an output sub-circuit.

[0005] The input sub-circuit is configured to control the potential of a first node using an input signal in response to a first clock signal, and control the potential of a second node using a third clock signal in response to the input signal, or control the potential of the second node using the third clock signal in response to the third clock signal.

[0006] The reset sub-circuit is configured to control the potential of the first node using a second clock signal in response to a first reset signal.

[0007] The output sub-circuit is configured to output the second clock signal through a signal output terminal in response to the potential of the first node, or output a power supply control signal through the signal output terminal in response to the potential of the second node; the power supply control signal is a signal of non-constant voltage.

[0008] In some embodiments, the input sub-circuit includes an eighth transistor, a twelfth transistor and a thirteenth transistor.

[0009] The first electrode of the eighth transistor is electrically connected with the first node, the second electrode is electrically connected with a signal input terminal transmitting the input signal, and the gate is electrically connected with a first clock signal line transmitting the first clock signal;

[0010] The first electrode and the gate of the twelfth transistor are both electrically connected with a third clock signal line transmitting the third clock signal, and the second electrode is electrically connected with the second node;

[0011] The first electrode of the thirteenth transistor is electrically connected with the second node, the second electrode is electrically connected with the third clock signal line, and the gate is electrically connected with the signal input terminal.

[0012] In some embodiments, the input sub-circuit is further configured to control a potential of a third node by using the second clock signal in response to the second clock signal.

[0013] In some embodiments, the input sub-circuit comprises a seventh transistor, an eighth transistor, a ninth transistor, a twelfth transistor and a thirteenth transistor;

[0014] The first electrode of the seventh transistor is electrically connected with the third node, the second electrode is electrically connected with a signal input terminal transmitting the input signal, and the gate is electrically connected with a first clock signal line transmitting the first clock signal;

[0015] The first electrode of the eighth transistor is electrically connected with the first node, the second electrode is electrically connected with the third node, and the gate is electrically connected with the first clock signal line;

[0016] The first electrode and the gate of the ninth transistor are both electrically connected with a second clock signal line transmitting the second clock signal, and the second electrode is electrically connected with the third node;

[0017] The first electrode and the gate of the twelfth transistor are both electrically connected with a third clock signal line transmitting the third clock signal, and the second electrode is electrically connected with the second node;

[0018] The first electrode of the thirteenth transistor is electrically connected with the second node, the second electrode is electrically connected with a third clock signal line transmitting the third clock signal, and the gate is electrically connected with the signal input terminal.

[0019] In some embodiments, the reset sub-circuit comprises a tenth transistor;

[0020] The first electrode of the tenth transistor is electrically connected with the first node, the second electrode is electrically connected with a second clock signal line transmitting the second clock signal, and the gate is electrically connected with a first reset signal line transmitting the first reset signal.

[0021] In some embodiments, the reset sub-circuit is further configured to control a potential of the fourth node by using the first clock signal in response to the first clock signal.

[0022] In some embodiments, the reset sub-circuit comprises a tenth transistor, an eleventh transistor and a sixteenth transistor.

[0023] The first electrode of the tenth transistor is electrically connected to the first node, the second electrode is electrically connected to the fourth node, and the gate is electrically connected to a first reset signal line transmitting the first reset signal.

[0024] The first electrode of the eleventh transistor is electrically connected to the fourth node, the second electrode is electrically connected to a second clock signal line transmitting the second clock signal, and the gate is electrically connected to the first reset signal line.

[0025] The first electrode and the gate of the sixteenth transistor are both electrically connected to a first clock signal line transmitting the first clock signal, and the second electrode is electrically connected to the fourth node.

[0026] In some embodiments, the reset sub-circuit is further configured to control a potential of the first node by using the second clock signal in response to a potential of a second node.

[0027] In some embodiments, the reset sub-circuit comprises a tenth transistor and an eleventh transistor.

[0028] The first electrode of the tenth transistor is electrically connected to the first node, the second electrode is electrically connected to the first electrode of the eleventh transistor, and the gate is electrically connected to a first reset signal line transmitting the first reset signal.

[0029] The second electrode of the eleventh transistor is electrically connected to a second clock signal line transmitting the second clock signal, and the gate is electrically connected to the second node.

[0030] In some embodiments, the output sub-circuit comprises a fourteenth transistor, a fifteenth transistor and a second capacitor.

[0031] The first electrode of the fourteenth transistor is electrically connected to the signal output end, the second electrode is electrically connected to a second clock signal line transmitting the second clock signal, and the gate is electrically connected to the first node.

[0032] The first electrode of the fifteenth transistor is electrically connected to a power supply control signal line transmitting the power supply control signal, the second electrode is electrically connected to the signal output end, and the gate is electrically connected to the second node.

[0033] The first plate of the second capacitor is electrically connected to the first node, and the second plate is electrically connected to the signal output end.

[0034] In some embodiments, the shift register further comprises an external compensation sub-circuit; the external compensation sub-circuit comprises a first input unit, a second input unit, a third input unit and a pull-down unit;

[0035] The first input unit is configured to control the potential of the fifth node by using the input signal in response to the enable signal;

[0036] The second input unit is configured to control the potential of the first node by using the fourth clock signal in response to the potential of the fifth node and the fourth clock signal;

[0037] The third input unit is configured to control the potential of the second node by using the third clock signal in response to the potential of the fifth node and the fourth clock signal;

[0038] The pull-down unit is configured to control the potential of the first node by using the second clock signal in response to the second reset signal.

[0039] In some embodiments, the first input unit comprises a first transistor, a second transistor and a third transistor;

[0040] The first pole of the first transistor is electrically connected to the second pole of the second transistor and the second pole of the third transistor, the second pole is electrically connected to a signal input terminal transmitting the input signal, and the gate is electrically connected to an enable signal line transmitting the enable signal;

[0041] The first pole of the second transistor is electrically connected to the fifth node, and the gate is electrically connected to the enable signal line;

[0042] The first pole and the gate of the third transistor are both electrically connected to the fifth node.

[0043] In some embodiments, the second input unit comprises a fourth transistor, a fifth transistor, a sixth transistor, a seventeenth transistor and a first capacitor;

[0044] The first pole of the fourth transistor is electrically connected to the second pole of the fifth transistor, the second pole is electrically connected to a fourth clock signal line transmitting the fourth clock signal, and the gate is electrically connected to the fifth node;

[0045] The first pole of the fifth transistor is electrically connected to the second pole of the sixth transistor and the second pole of the seventeenth transistor, and the gate is electrically connected to the fourth clock signal line;

[0046] The first pole of the sixth transistor is electrically connected to the first node, and the gate is electrically connected to the fourth clock signal line;

[0047] The first electrode and the gate electrode of the seventeenth transistor are electrically connected with a second clock signal line which transmits the second clock signal.

[0048] The first plate of the first capacitor is electrically connected with the fifth node, and the second plate is electrically connected with the first electrode of the fourth transistor.

[0049] In some embodiments, the second input unit includes a fourth transistor, a fifth transistor, a sixth transistor, a seventeenth transistor and a first capacitor.

[0050] The first electrode of the fourth transistor is electrically connected with the second electrode of the fifth transistor, the second electrode is electrically connected with a fourth clock signal line which transmits the fourth clock signal, and the gate electrode is electrically connected with the fifth node.

[0051] The first electrode of the fifth transistor is electrically connected with the second electrode of the sixth transistor and the second electrode of the seventeenth transistor, and the gate electrode is electrically connected with the fourth clock signal line.

[0052] The first electrode of the sixth transistor is electrically connected with the first node, and the gate electrode is electrically connected with the fourth clock signal line.

[0053] The first electrode and the gate electrode of the seventeenth transistor are electrically connected with a second clock signal line which transmits the second clock signal.

[0054] The first plate of the first capacitor is electrically connected with the fifth node, and the second plate is electrically connected with the fourth clock signal line.

[0055] In some embodiments, the third input unit includes a nineteenth transistor and a twentieth transistor.

[0056] The first electrode of the nineteenth transistor is electrically connected with the second node, the second electrode is electrically connected with the first electrode of the twentieth transistor, and the gate electrode is electrically connected with the fifth node.

[0057] The second electrode of the twentieth transistor is electrically connected with a third clock signal line which transmits the third clock signal, and the gate electrode is electrically connected with the fourth clock signal line.

[0058] In some embodiments, the pull-down unit includes an eighteenth transistor.

[0059] The first electrode of the eighteenth transistor is electrically connected with the first node, the second electrode is electrically connected with a second clock signal line which transmits the second clock signal, and the gate electrode is electrically connected with a second reset signal line which transmits the second reset signal.

[0060] In a second aspect, the present disclosure also provides a driving method of a shift register, applied to the shift register of any one of the first aspect, wherein the working phase of the shift register comprises at least a display phase, and the display phase comprises a first sub-phase, a second sub-phase, a third sub-phase and a fourth sub-phase; and the driving method comprises:

[0061] In the first sub-phase, the input signal and the first clock signal are both first level signals, and the second clock signal, the third clock signal and the first reset signal are all second level signals; the input sub-circuit writes the first level signal to the first node under the control of the first clock signal; and the input sub-circuit writes the second level signal to the second node under the control of the input signal; the output sub-circuit outputs the second level signal to the signal output end under the control of the first level signal of the first node; wherein the first level signal is an effective level signal, and the second level signal is an ineffective level signal.

[0062] In the second sub-phase, the input signal, the first clock signal, the third clock signal and the first reset signal are all the second level signals, and the second clock signal is the first level signal; the output sub-circuit uses the bootstrap effect to pull the first potential of the first level signal of the first node to a second potential under the control of the second clock signal; and the output sub-circuit outputs the first level signal to the signal output end under the control of the second potential of the first node.

[0063] In the third sub-phase, the input signal, the first clock signal, the second clock signal, the third clock signal and the first reset signal are all the second level signals; the output sub-circuit pulls the second potential of the first node to the first potential under the control of the second clock signal; and the output sub-circuit outputs the second level signal to the signal output end under the control of the first potential of the first node.

[0064] In the fourth sub-phase, the input signal, the first clock signal, the second clock signal and the power control signal are all the second level signals, and the third clock signal and the first reset signal are both the first level signals; the reset sub-circuit writes the second level signal to the first node under the control of the first reset signal; the input sub-circuit writes the first level signal to the second node under the control of the third clock signal; and the output sub-circuit outputs the second level signal to the signal output end under the control of the first level signal of the second node.

[0065] In some embodiments, the driving method further comprises:

[0066] The first sub-stage: the reset sub-circuit writes the first level signal to the fourth node under the control of the first clock signal;

[0067] The second sub-stage: the input sub-circuit writes the first level signal to the third node under the control of the second clock signal.

[0068] In some embodiments, the working stage further includes a compensation stage; the compensation stage includes a fifth sub-stage, a sixth sub-stage, a seventh sub-stage and an eighth sub-stage; and the driving method further includes:

[0069] The first sub-stage: the enable signal is the first level signal, the second reset signal and the fourth clock signal are the second level signal; the first input unit writes the first level signal to the fifth node under the control of the enable signal;

[0070] The second sub-stage, the third sub-stage and the fourth sub-stage: the enable signal, the second reset signal and the fourth clock signal are the second level signal;

[0071] The fifth sub-stage: the input signal, the first clock signal, the second clock signal, the third clock signal, the first reset signal, the enable signal and the second reset signal are the second level signal, and the fourth clock signal is the first level signal; the second input unit uses the bootstrap effect to pull the first potential of the first level signal of the fifth node to the second potential under the control of the fourth clock signal; the second input unit writes the first level signal to the first node under the synchronous control of the second potential of the fifth node and the fourth clock signal; the third input unit writes the second level signal to the second node under the synchronous control of the first level signal of the fifth node and the fourth clock signal; the output sub-circuit outputs the second level signal to the signal output terminal under the control of the first level signal of the first node;

[0072] The sixth sub-stage: the input signal, the first clock signal, the third clock signal, the fourth clock signal, the first reset signal, the second reset signal and the enable signal are the second level signal, and the second clock signal is the first level signal; the second input unit pulls the second potential of the fifth node to the first potential under the control of the fourth clock signal; the output sub-circuit uses the bootstrap effect to pull the first potential of the first level signal of the first node to the second potential under the control of the second clock signal; the output sub-circuit outputs the first level signal to the signal output terminal under the control of the second potential of the first node;

[0073] the seventh sub-stage: the input signal, the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, the first reset signal, the second reset signal and the enable signal are the second level signal; the output sub-circuit, under the control of the second clock signal, pulls the second potential of the first node to the first potential; the output sub-circuit, under the control of the first potential of the first node, outputs the second level signal to the signal output end;

[0074] the eighth sub-stage: the input signal, the first clock signal, the second clock signal, the fourth clock signal, the first reset signal and the power control signal are the second level signal; the third clock signal, the second reset signal and the enable signal are the first level signal; the pull-down unit, under the control of the second reset signal, writes the second level signal to the first node; the first input unit, under the control of the enable signal, writes the second level signal to the fifth node; the input sub-circuit, under the control of the third clock signal, writes the first level signal to the second node; the output sub-circuit, under the control of the first level signal of the second node, outputs the second level signal to the signal output end.

[0075] In some embodiments, in the working stage, the input signal, the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, the first reset signal, the enable signal, the second reset signal and the power control signal are signals of non-constant voltage.

[0076] In a third aspect, the embodiments of the present disclosure further provide a gate drive circuit, which comprises N cascaded shift registers as any one of the first aspect.

[0077] In addition to the first-stage shift register, a signal input end of an i+1-stage shift register is electrically connected to a signal output end of an i-stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

[0078] In a fourth aspect, the embodiments of the present disclosure further provide a display device, which comprises the gate drive circuit as the third aspect.

[0079] In some embodiments, the display device further comprises a timing controller.

[0080] The timing controller is configured to output a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a first reset signal, an enable signal, a second reset signal and a power control signal to the gate drive circuit.

[0081] The input signal, the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, the first reset signal, the enable signal, the second reset signal and the power control signal are all non-constant voltage signals. BRIEF DESCRIPTION OF DRAWINGS

[0082] FIG. 1 is a schematic diagram of a shift register according to an embodiment of the present disclosure;

[0083] FIG. 2 is a circuit diagram of a shift register according to Example 1 of the present disclosure;

[0084] FIG. 3 is a circuit diagram of a shift register according to Example 2 of the present disclosure;

[0085] FIG. 4 is a circuit diagram of a shift register according to Example 3 of the present disclosure;

[0086] FIG. 5 is a circuit diagram of a shift register according to Example 4 of the present disclosure;

[0087] FIG. 6 is a circuit diagram of a shift register according to Example 5 of the present disclosure;

[0088] FIG. 7 is a circuit diagram of a shift register according to Example 6 of the present disclosure;

[0089] FIG. 8 is a timing diagram of an exemplary shift register according to an embodiment of the present disclosure;

[0090] FIG. 9 is a timing diagram of another exemplary shift register according to an embodiment of the present disclosure;

[0091] FIG. 10 is a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure;

[0092] FIG. 11 is a schematic diagram of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0093] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be combined with the accompanying drawings to make a clear and complete description of the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. The components of the embodiments of the present disclosure generally described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed present disclosure, but only represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0094] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms "one", "a" or "the" and similar terms do not denote a quantity limitation, but mean that there is at least one. The terms "include" or "contain" and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects.

[0095] In the present disclosure, "a plurality of or several" refers to two or more. The association relationship of the associated objects is described by "and / or", which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. The character " / " generally represents a "or" relationship between the associated objects before and after it.

[0096] In the related art, the gate drive circuit includes a plurality of cascaded shift registers, and the shift registers usually need to be electrically connected to a plurality of power signal lines transmitting constant voltage signals for their own power supply. The plurality of power signal lines transmitting constant voltage signals, for example, include a VGH power signal line providing a constant high level signal, and a VGL power signal line providing a constant low level signal. Among them, a constant voltage difference is generated between the plurality of power signal lines transmitting constant voltage signals for a long time, thereby generating a constant voltage stress effect, mainly manifested as: easy to break down the medium between the power signal lines, cause signal short circuit due to electrochemical corrosion, and then cause the shift register to fail.

[0097] In view of this, the present embodiment provides a shift register which essentially adjusts the constant voltage signal in the conventional technology for controlling the shift register to a non-constant voltage signal, so that the shift register in the present disclosure is introduced without constant voltage signal. The way of providing power to the shift register by using non-constant voltage signal makes that there is no constant voltage difference between the signal lines providing non-constant voltage signal, so there is no constant voltage stress between all signal lines, thereby avoiding the occurrence of electrochemical corrosion and causing signal short circuit problem.

[0098] Figure 1 is a schematic diagram of a shift register provided by the present embodiment, as shown in Figure 1, the input sub-circuit, reset sub-circuit and output sub-circuit.

[0099] The input sub-circuit 1 is electrically connected to the signal input end Input , a first clock signal line, a first node N1, and a third clock signal line and a second node N2. The input sub-circuit 1 can receive a signal from a signal input terminal Input The input sub-circuit 1 is electrically connected with the input signal line, the first clock signal line and the third clock signal line. The input sub-circuit 1 can receive the input signal STV transmitted from the input signal line, receive the first clock signal CK1 transmitted from the first clock signal line, and receive the third clock signal CK3 transmitted from the third clock signal line. Specifically, the input sub-circuit 1 is configured to control the potential of the first node N1 by using the input signal STV in response to the first clock signal CK1, and control the potential of the second node N2 by using the third clock signal CK3 in response to the input signal STV or the third clock signal CK3. For example, the input sub-circuit 1 can write the input signal STV into the first node N1 in response to the first clock signal CK1, and the potential of the first node N1 is the voltage of the input signal STV. The input sub-circuit 1 can also write the third clock signal CK3 into the second node N2 in response to the input signal STV in a certain period, and the potential of the second node N2 is the voltage of the third clock signal CK3; or the input sub-circuit 1 writes the third clock signal CK3 into the second node N2 in response to the third clock signal CK3 in other periods different from the certain period, and the potential of the second node N2 is the voltage of the third clock signal CK3.

[0100] The reset sub-circuit 2 is electrically connected with the first reset signal line, the second clock signal line and the first node N1. The reset sub-circuit 2 can receive the first reset signal STD transmitted from the first reset signal line, and receive the second clock signal CK2 transmitted from the second clock signal line. Specifically, the reset sub-circuit 2 is configured to control the potential of the first node N1 by using the second clock signal CK2 in response to the first reset signal STD. For example, the reset sub-circuit 2 can write the second clock signal CK2 into the first node N1 in response to the first reset signal STD, and the potential of the first node N1 is the voltage of the second clock signal CK2.

[0101] The output sub-circuit 3 is electrically connected with the first node N1, the second clock signal line, the second node N2 and the power control signal line. The output sub-circuit 3 can receive the second clock signal CK2 transmitted from the second clock signal line, and receive the power control signal VST transmitted from the power control signal line. Specifically, the output sub-circuit 3 is configured to output the second clock signal CK2 through the signal output terminal Out in response to the potential of the first node N1, and output the power control signal VST through the signal output terminal Out in response to the potential of the second node N2. output; or, in response to the potential of the second node N2, output the power supply control signal VST through the signal output terminal Out Output. Exemplarily, the output sub-circuit 3 can output the second clock signal CK2 through the signal output terminal Out in response to the potential of the first node N1 at a certain period output; or, the output sub-circuit 3 can output the power supply control signal VST through the signal output terminal Out in response to the potential of the second node N2 at other time periods other than a certain time period Output.

[0102] Optionally, the shift register is electrically connected with the timing controller (Tcon module) through the clock signal lines (the first clock signal line, the second clock signal line and the third clock signal line). The shift register receives the clock signals (the first clock signal CK1, the second clock signal CK2 and the third clock signal CK3) sent from the timing controller through the clock signal lines. The clock signal is a periodic pulse signal, which belongs to a non-constant voltage signal. The potentials of different clock signals are the same, and the timings are different. Here, "periodic" means that the time interval between adjacent pulse signals is constant.

[0103] Optionally, the signal input end Input The timing controller can be electrically connected, and the input signal STV provided by the timing controller is a non-constant voltage signal. The signal input end Input The signal output end Out of the upper stage shift register cascaded with the shift register can also be electrically connected <i-1>, signal output terminal Out The different signals are output at different time periods, such as a second clock signal CK2 and a power control signal VST. The second clock signal CK2 and the power control signal VST are both non-constant voltage signals.

[0104] Optionally, the shift register is electrically connected with the timing controller through a first reset signal line. The shift register receives a first reset signal STD from the timing controller through the first reset signal line. The first reset signal STD is a non-constant voltage signal.

[0105] The non-constant voltage signal referred to in the embodiments of the present disclosure refers to a signal whose potential changes between at least two different voltages, rather than a fixed potential. For example, the potential changes from A to B, or from B to A, where A is less than B.

[0106] For example, as shown in FIG. 8, in the non-working phase (for example, the t0 phase), the power control signal VST is a first level signal, and the potential of the first level signal is B, for example, 5V or 8V; in the first sub-phase t1 to the fourth sub-phase t4, the power control signal VST is a second level signal, and the potential of the second level signal is A, for example, 0. The first reset signal STD is a second level signal in the first sub-phase t1 to the third sub-phase t3, and the potential thereof is A. The first reset signal STD is a first level signal in the fourth sub-phase t4, and the potential thereof is B.

[0107] Optionally, the input signal STV, the first clock signal CK1, the second clock signal CK2 and the third clock signal CK3, the first reset signal STD and the power control signal VST are all non-constant voltage signals.

[0108] For example, as shown in FIG. 8, in the second sub-phase t2, the potential of the second clock signal CK2 is B. In the first sub-phase t1, the third sub-phase t3 and the fourth sub-phase t4, the potential of the second clock signal CK2 is A. For another example, as shown in FIG. 8, in the fourth sub-phase t4, the potential of the third clock signal CK3 is B. In the first sub-phase t1 to the third sub-phase t3, the potential of the third clock signal CK3 is A.

[0109] The shift register provided by the embodiments of the present disclosure is controlled by using non-constant voltage signals, and no constant voltage signal is introduced, so that no constant voltage difference is generated between the signal lines providing the non-constant voltage signals, and thus no constant voltage stress is generated between all the signal lines, thereby avoiding the problem of signal short circuit caused by electrochemical corrosion between the signal lines, reducing the risk of failure of the shift register, and improving the service life of the shift register.

[0110] It should be noted that the transistor in the embodiments of the present disclosure can adopt a thin film transistor or a field effect transistor or other switch devices with the same characteristics. The thin film transistor can include an oxide semiconductor thin film transistor, an amorphous silicon thin film transistor, a polycrystalline silicon thin film transistor, etc. The source and the drain of the transistor can be symmetrical in structure, so the source and the drain can be indistinguishable in physical structure. In the embodiments of the present disclosure, in order to distinguish the transistor, except for the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other electrode is directly described as the second electrode, so the first electrode and the second electrode of all or part of the transistors in the embodiments of the present disclosure can be interchangeable as needed.

[0111] It should be noted that the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor. The N-type thin film transistor refers to N-type ion doping in the active layer of the thin film transistor. The P-type thin film transistor refers to P-type ion doping in the active layer of the thin film transistor. The working level signal of the N-type thin film transistor is a high level signal. The working level signal of the P-type thin film transistor is a low level signal. Meanwhile, for the convenience of understanding, the present disclosure is described by taking the transistor as an N-type thin film transistor in the following embodiments, but the present disclosure is not limited to the N-type thin film transistor.

[0112] In some embodiments, FIG. 2 is a circuit diagram of a shift register under Example 1 provided by the embodiments of the present disclosure, as shown in FIG. 2, the input sub-circuit 1 includes the eighth transistor M8, the twelfth transistor M12 and the thirteenth transistor M13. Wherein, the first electrode of the eighth transistor M8 is electrically connected with the first node N1, the second electrode is electrically connected with the signal input end Input of the transmission input signal STV The first electrode and the gate electrode of the twelfth transistor M12 are electrically connected with the first clock signal line for transmitting the first clock signal CK1, and the second electrode is electrically connected with the second node N2. The first electrode of the thirteenth transistor M13 is electrically connected with the second node N2, the second electrode is electrically connected with the third clock signal line, and the gate electrode is electrically connected with the signal input terminal Input .

[0113] For example, the first clock signal CK1 can control the on-off of the eighth transistor M8, and when the eighth transistor M8 is turned on in response to the first clock signal CK1, the input signal STV can be transmitted to the first node N1 to control the potential of the first node N1. The third clock signal CK3 can not only control the on-off of the twelfth transistor M12, but also write the second node N2 when the twelfth transistor M12 is turned on in response to the third clock signal CK3, thereby controlling the potential of the second node N2. The input signal STV can control the on-off of the thirteenth transistor M13, and when the thirteenth transistor M13 is turned on in response to the input signal STV, the third clock signal CK3 writes the second node N2 to control the potential of the second node N2.

[0114] In some embodiments, as shown in FIG. 2, the reset sub-circuit 2 includes a tenth transistor M10, wherein the first electrode of the tenth transistor M10 is electrically connected to the first node N1, the second electrode is electrically connected to a second clock signal line for transmitting the second clock signal CK2, and the gate electrode is electrically connected to a first reset signal line for transmitting the first reset signal STD.

[0115] For example, the first reset signal STD can control the on-off of the tenth transistor M10, and when the tenth transistor M10 is turned on in response to the first reset signal STD, the second clock signal CK2 writes the first node N1 to control the potential of the first node N1.

[0116] In some embodiments, the transistor can be an oxide semiconductor transistor. Oxide semiconductor transistors are widely used in medium and large-sized display panels due to their good uniformity. The transistor is an oxide semiconductor transistor, i.e., the material of the active layer of the transistor is an oxide semiconductor material. For example, the oxide semiconductor material can include, but is not limited to, indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium tin oxide (ITO), etc.

[0117] Due to the characteristics of oxide semiconductor transistors, they are prone to negative bias. When the potential of one electrode is high, the oxide semiconductor transistor is prone to leakage, even though the gate electrode has not been written with a conductive signal.

[0118] FIG. 3 is a circuit diagram of a shift register according to Example 2 provided by the embodiments of the present disclosure. Different from the circuit structure shown in FIG. 2, Example 2 adds an anti-leakage structure compared to Example 1. As shown in FIG. 3, the input sub-circuit 1 is further configured to respond to the second clock signal CK2 and use the second clock signal CK2 to control the potential of the third node N3.

[0119] Optionally, as illustrated in FIG. 3, the input sub-circuit 1 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a twelfth transistor M12, and a thirteenth transistor M13. For example, at least part of the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the twelfth transistor M12, and the thirteenth transistor M13 are oxide semiconductor transistors.

[0120] wherein a first electrode of the seventh transistor M7 is electrically connected to the third node N3, a second electrode of the seventh transistor M7 is electrically connected to a signal input terminal Input which transmits an input signal STV The first electrode of the seventh transistor M7 is electrically connected with the first node N1, the second electrode is electrically connected with the third node N3, and the gate is electrically connected with the first clock signal line for transmitting the first clock signal CK1. The first electrode and the gate of the eighth transistor M8 are both electrically connected with the second clock signal line for transmitting the second clock signal CK2, and the second electrode is electrically connected with the third node N3.

[0121] Compared with the circuit structure of example 1, the seventh transistor M7 and the ninth transistor M9 are additionally arranged on the basis of the eighth transistor M8, so as to prevent the first node N1 from being transferred from the eighth transistor M8 to the signal input end Input Leakage. Specifically, when the ninth transistor M9 is turned on in response to the second clock signal CK2 (e.g., a high-level signal) and conducts, the second clock signal CK2 is written to the third node N3, thereby pulling up the potential of the third node N3, preventing the potential of the first node N1 from being pulled up from the eighth transistor M8 and the seventh transistor M7 to the signal input terminal Input Leakage current.

[0122] Alternatively, other leakage prevention structures can also be used to prevent the first node N1 from leaking. Here, the control signals used by the other leakage prevention structures include but are not limited to the first clock signal CK1 and the second clock signal CK2, and signals with non-constant voltage.

[0123] Continuing as shown in FIG. 3, the first electrode and the gate electrode of the twelfth transistor M12 are both electrically connected to the third clock signal line that transmits the third clock signal CK3, and the second electrode is electrically connected to the second node N2; the first electrode of the thirteenth transistor M13 is electrically connected to the second node N2, the second electrode is electrically connected to the third clock signal line that transmits the third clock signal CK3, and the gate electrode is electrically connected to the signal input end Input .

[0124] For example, the third clock signal CK3 can control the on-off of the twelfth transistor M12, and when the twelfth transistor M12 is turned on in response to the third clock signal CK3, the third clock signal CK3 can be written into the second node N2 to control the potential of the second node N2. The input signal STV can control the on-off of the thirteenth transistor M13, and when the thirteenth transistor M13 is turned on in response to the input signal STV, the third clock signal CK3 can be written into the second node N2 to control the potential of the second node N2.

[0125] In some embodiments, as shown in FIG. 3, the reset sub-circuit 2 is further configured to control the potential of the fourth node N4 by using the first clock signal CK1 in response to the first clock signal CK1.

[0126] Optionally, as shown in FIG. 3, the reset sub-circuit 2 includes the tenth transistor M10, the eleventh transistor M11 and the sixteenth transistor M16. For example, at least part of the tenth transistor M10, the eleventh transistor M11 and the sixteenth transistor M16 are oxide semiconductor transistors.

[0127] For example, the first electrode of the tenth transistor M10 is electrically connected to the first node N1, the second electrode is electrically connected to the fourth node N4, and the gate electrode is electrically connected to the first reset signal line for transmitting the first reset signal STD; the first electrode of the eleventh transistor M11 is electrically connected to the fourth node N4, the second electrode is electrically connected to the second clock signal line for transmitting the second clock signal CK2, and the gate electrode is electrically connected to the first reset signal line; the first electrode and the gate electrode of the sixteenth transistor M16 are both electrically connected to the first clock signal line for transmitting the first clock signal CK1, and the second electrode is electrically connected to the fourth node N4.

[0128] Compared with the circuit structure of Example 1, the tenth transistor M10 is added with the eleventh transistor M11 and the sixteenth transistor M16 in this embodiment, to prevent the first node N1 from leaking electricity to one end of the second clock signal line from the tenth transistor M10. Specifically, when the sixteenth transistor M16 is turned on in response to the first clock signal CK1 (for example, a high-level signal), the first clock signal CK1 is written into the fourth node N4, thereby pulling up the potential of the fourth node N4, and preventing the potential of the first node N1 from leaking electricity to one end of the second clock signal line from the tenth transistor M10 and the eleventh transistor M11 in the case of high level.

[0129] In some embodiments, FIG. 4 is a circuit diagram of a shift register according to Example 3 provided by the embodiments of the present disclosure. Different from the circuit structure shown in FIG. 2, Example 3 adds an anti-leakage structure compared with Example 1, as shown in FIG. 4, the reset sub-circuit 2 is further configured to control the potential of the first node N1 by using the second clock signal CK2 in response to the potential of the second node N2.

[0130] Optionally, as shown in FIG. 4, the reset sub-circuit 2 includes a tenth transistor M10 and an eleventh transistor M11. For example, at least part of the tenth transistor M10 and the eleventh transistor M11 is an oxide semiconductor transistor.

[0131] The first electrode of the tenth transistor M10 is electrically connected to the first node N1, the second electrode is electrically connected to the first electrode of the eleventh transistor M11, and the gate electrode is electrically connected to a first reset signal line that transmits a first reset signal STD. The second electrode of the eleventh transistor M11 is electrically connected to a second clock signal line that transmits a second clock signal CK2, and the gate electrode is electrically connected to the second node N2.

[0132] Compared with the circuit structure of Example 1, the eleventh transistor M11 is additionally provided on the basis of the tenth transistor M10 to prevent the first node N1 from leaking electricity to one end of the second clock signal line. Specifically, the eleventh transistor M11 lengthens the path from the first node N1 to the second clock signal line, which is conducive to preventing the potential of the first node N1 from leaking electricity to one end of the second clock signal line from the tenth transistor M10 and the eleventh transistor M11 when the potential of the first node N1 is at a high level. In addition, when the tenth transistor M10 and the eleventh transistor M11 are both turned on, the second clock signal CK2 writes a low potential to the first node N1. When the eleventh transistor M11 is turned on and the tenth transistor M10 is turned off, the voltage of the second clock signal CK2 is at a high level, which can prevent the first node N1 from leaking electricity to one end of the second clock signal line.

[0133] In some embodiments, as shown in FIGS. 2-4, the output sub-circuit 3 includes a fourteenth transistor M14, a fifteenth transistor M15, and a second capacitor C2. The first electrode of the fourteenth transistor M14 is electrically connected to the signal output terminal Out The second terminal is electrically connected to the second clock signal line transmitting the second clock signal CK2, and its gate is electrically connected to the first node N1; the first terminal of the fifteenth transistor M15 is electrically connected to the power control signal line transmitting the power control signal VST, and its second terminal is electrically connected to the signal output terminal Out. The gate of the second capacitor C2 is electrically connected to the second node N2; the first plate of the second capacitor C2 is electrically connected to the first node N1, and the second plate is electrically connected to the signal output terminal Out. .

[0134] For example, the potential of the first node N1 can control the on-off of the fourteenth transistor M14, and when the fourteenth transistor M14 is turned on in response to the potential of the first node N1, the second clock signal CK2 can be output through the signal output end Out Output. The potential of the second node N2 can control the on-off of the fifteenth transistor M15, and when the fifteenth transistor M15 is turned on in response to the potential of the second node N2, the power supply control signal VST can be output through the signal output terminal Out Output.

[0135] Here, the second capacitor C2 is mainly used to bootstrap the potential of the first node N1 to a higher potential, thereby ensuring that the fourteenth transistor M14 is continuously turned on, and further stabilizing the output of the second clock signal CK2.

[0136] In some embodiments, FIG. 5 is a circuit diagram of a shift register under Example 4 provided by an embodiment of the present disclosure, which is different from the circuit structure shown in FIG. 3. Compared with Example 2, Example 4 adds an external compensation sub-circuit 4. FIG. 6 is a circuit diagram of a shift register under Example 5 provided by an embodiment of the present disclosure, and FIG. 7 is a circuit diagram of a shift register under Example 6 provided by an embodiment of the present disclosure. Compared with the circuit structure shown in FIG. 4, both Example 5 and Example 6 add an external compensation sub-circuit 4, and the external compensation sub-circuit 4 of Example 5 and Example 6 is different.

[0137] As shown in FIGS. 5-7, the external compensation sub-circuit 4 is electrically connected to the signal input end Input , an enable signal line, a fourth clock signal line, a second clock signal line, a third clock signal line, and a second reset signal line. The external compensation sub-circuit 4 can receive a signal from the signal input end Input The input signal STV is received by the shift register, the enable signal OE is received by the shift register from the enable signal line, the fourth clock signal CKA is received by the shift register from the fourth clock signal line, the second clock signal CK2 is received by the shift register from the second clock signal line, the third clock signal CK3 is received by the shift register from the third clock signal line, and the second reset signal TRST is received by the shift register from the second reset signal line.

[0138] Specifically, the external compensation sub-circuit 4 is configured to control the potential of the first node N1 with the input signal STV and the second clock signal CK2 in response to the enable signal OE and the fourth clock signal CKA, or control the potential of the first node N1 with the second clock signal CK2 in response to the second reset signal TRST, and control the potential of the second node N2 with the third clock signal CK3 in response to the fourth clock signal CKA.

[0139] Optionally, the shift register is electrically connected with the timing controller through the enable signal line. The shift register receives the enable signal OE from the timing controller through the enable signal line. The enable signal OE is a non-constant voltage signal.

[0140] Optionally, the shift register is electrically connected with the timing controller through the second reset signal line. The shift register receives the second reset signal TRST from the timing controller through the second reset signal line. The second reset signal TRST is a non-constant voltage signal.

[0141] Optionally, the shift register is electrically connected with the timing controller through the fourth clock signal line. The shift register receives the fourth clock signal CKA from the timing controller through the fourth clock signal line. The fourth clock signal CKA is a non-constant voltage signal. For example, as shown in FIG. 9, in the fifth sub-stage t5, the fourth clock signal CKA is a first level signal, and the potential of the first level signal is B potential, for example, 5V or 8V; in the first sub-stage t1 to the fourth sub-stage t4 and the sixth sub-stage t6 to the eighth sub-stage t8, the fourth clock signal CKA is a second level signal, and the potential of the second level signal is A potential, for example, 0.

[0142] As shown in FIGS. 5-7, the external compensation sub-circuit 4 includes a first input unit 41, a second input unit 42, a third input unit 43, and a pull-down unit 44. The first input unit 41 is configured to control the potential of the fifth node N5 using the input signal STV in response to the enable signal OE; the second input unit 42 is configured to control the potential of the first node N1 using the fourth clock signal CKA in response to the potential of the fifth node N5 and the fourth clock signal CKA; the third input unit 43 is configured to control the potential of the second node N2 using the third clock signal CK3 in response to the potential of the fifth node N5 and the fourth clock signal CKA; and the pull-down unit 44 is configured to control the potential of the first node N1 using the second clock signal CK2 in response to the second reset signal TRST.

[0143] For the first input unit 41: as shown in FIGS. 5-7, the first input unit 41 includes a first transistor M1, a second transistor M2, and a third transistor M3; the first electrode of the first transistor M1 is electrically connected to the second electrode of the second transistor M2 and the second electrode of the third transistor M3, the second electrode is electrically connected to the signal input end Input The first electrode of the second transistor M2 is electrically connected to the fifth node N5, and the gate electrode is electrically connected to the enable signal line.

[0144] For example, when the first transistor M1 and the second transistor M2 are turned on in response to the enable signal OE, the input signal STV can be written to the fifth node N5. When the third transistor M3 is turned on in response to the potential of the fifth node N5, the potential of the fifth node can be written to the second electrode of the second transistor M2.

[0145] Optionally, the enable signal OE is a signal of non-constant voltage.

[0146] For example, the first transistor M1 and the third transistor M3 are oxide semiconductor transistors. The first transistor M1 and the third transistor M3 are used to block the potential of the fifth node N5 from the second transistor M2 to the signal input end Input Leakage.

[0147] For the second input unit 42: as shown in FIG. 5 and FIG. 6, the second input unit 42 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventeenth transistor M17, and a first capacitor C1; the first electrode of the fourth transistor M4 is electrically connected to the second electrode of the fifth transistor M5, the second electrode is electrically connected to a fourth clock signal line transmitting a fourth clock signal CKA, and the gate electrode is electrically connected to a fifth node N5; the first electrode of the fifth transistor M5 is electrically connected to the second electrode of the sixth transistor M6 and the second electrode of the seventeenth transistor M17, and the gate electrode is electrically connected to the fourth clock signal line; the first electrode of the sixth transistor M6 is electrically connected to the first node N1, and the gate electrode is electrically connected to the fourth clock signal line; the first electrode and the gate electrode of the seventeenth transistor M17 are both electrically connected to a second clock signal line transmitting a second clock signal CK2; the first plate of the first capacitor C1 is electrically connected to the fifth node N5, and the second plate is electrically connected to the first electrode of the fourth transistor M4.

[0148] For example, when the fourth transistor M4 is turned on in response to the potential of the fifth node N5, the fourth clock signal CKA is written to the second electrode of the fifth transistor M5; in the case that the fourth clock signal CKA is a valid level signal, the first capacitor C1 self-boosts the fifth node N5 to a higher potential to ensure the stable conduction of the fourth transistor M4. When the fifth transistor M5 and the sixth transistor M6 are turned on in response to the fourth clock signal CKA, the fourth clock signal CKA is written to the first node N1. When the seventeenth transistor M17 is turned on in response to the second clock signal CK2, the second clock signal CK2 is written to the second electrode of the sixth transistor M6 to prevent the high potential of the first node N1 from leaking to the fourth clock signal line through the sixth transistor M6.

[0149] Optionally, the fourth clock signal CKA is a signal with non-constant voltage.

[0150] Here, the first capacitor C1 is mainly used to self-boost the potential of the fifth node N5 to a higher potential, thereby ensuring the continuous conduction of the fourth transistor M4 and stabilizing the output of the fourth clock signal CKA.

[0151] For example, the fifth transistor M5 and the seventeenth transistor M17 are both oxide semiconductor transistors. Among them, the fifth transistor M5 and the seventeenth transistor M17 are used to block the potential of the first node N1 from leaking from the sixth transistor M6 to one end of the fourth clock signal line.

[0152] For the second input unit 42: as shown in FIG. 7, the second input unit 42 includes a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventeenth transistor M17, and a first capacitor C1; the first electrode of the fourth transistor M4 is electrically connected to the second electrode of the fifth transistor M5, the second electrode is electrically connected to a fourth clock signal line that transmits a fourth clock signal CKA, and the gate electrode is electrically connected to a fifth node N5; the first electrode of the fifth transistor M5 is electrically connected to the second electrode of the sixth transistor M6 and the second electrode of the seventeenth transistor M17, and the gate electrode is electrically connected to the fourth clock signal line; the first electrode of the sixth transistor M6 is electrically connected to the first node N1, and the gate electrode is electrically connected to the fourth clock signal line; the first electrode and the gate electrode of the seventeenth transistor M17 are both electrically connected to a second clock signal line that transmits a second clock signal CK2; and the first electrode plate of the first capacitor C1 is electrically connected to the fifth node N5, and the second electrode plate is electrically connected to the fourth clock signal line.

[0153] Here, the control principle of the circuit structure of the second input unit 42 is the same as that of the examples of FIGS. 5 and 6, and the repeated parts will not be described again.

[0154] For the third input unit 43: as shown in FIGS. 5 to 7, the third input unit 43 includes a nineteenth transistor M19 and a twentieth transistor M20; the first electrode of the nineteenth transistor M19 is electrically connected to the second node N2, the second electrode is electrically connected to the first electrode of the twentieth transistor M20, and the gate electrode is electrically connected to the fifth node N5; the second electrode of the twentieth transistor M20 is electrically connected to a third clock signal line that transmits a third clock signal CK3, and the gate electrode is electrically connected to the fourth clock signal line.

[0155] For example, when the twentieth transistor M20 is turned on in response to the fourth clock signal CKA, the third clock signal CK3 is written to the second electrode of the nineteenth transistor M19; when the nineteenth transistor M19 is turned on in response to the potential of the fifth node N5, the third clock signal CK3 is written to the second node N2.

[0156] For example, the nineteenth transistor M19 and the twentieth transistor M20 are both oxide semiconductor transistors. Among them, the twentieth transistor M20 is used to block the potential of the second node N2 from leaking to one end of the third clock signal line from the nineteenth transistor M19.

[0157] For the pull-down unit 44: as shown in FIGS. 5 to 7, the pull-down unit 44 includes an eighteenth transistor M18; the first electrode of the eighteenth transistor M18 is electrically connected to the first node N1, the second electrode is electrically connected to the second clock signal line that transmits the second clock signal CK2, and the gate electrode is electrically connected to the second reset signal line that transmits the second reset signal TRST.

[0158] For example, when the eighteenth transistor M18 is turned on in response to the second reset signal TRST, the second clock signal CK2 is written to the first node N1.

[0159] Optionally, the second reset signal TRST is a signal of non-constant voltage.

[0160] The above is the entire description of the circuit structure of the shift register according to the present disclosure.

[0161] In addition, the present disclosure also provides a driving method of the shift register, which is applied to the shift register of any one of the above embodiments and combinations thereof.

[0162] FIG. 8 is a timing diagram of an exemplary shift register according to an embodiment of the present disclosure. As shown in FIG. 8, taking the circuit structure shown in FIG. 2 as an example, the working phase includes a display phase. The display phase includes a first sub-phase t1, a second sub-phase t2, a third sub-phase t3, and a fourth sub-phase t4. The driving method includes:

[0163] The first sub-phase t1: the input signal STV and the first clock signal CK1 are both first level signals, the second clock signal CK2, the third clock signal CK3, and the first reset signal STD are all second level signals; the input sub-circuit 1 writes the first level signal to the first node N1 under the control of the first clock signal CK1; and the input sub-circuit 1 writes the second level signal to the second node N2 under the control of the input signal STV; the output sub-circuit 3 writes the first level signal to the signal output terminal Out under the control of the first level signal of the first node N1 output a second level signal.

[0164] The first level signal is a valid level signal, and the second level signal is an invalid level signal. Since the transistor of the present disclosure is taken as an example of an N-type thin film transistor, the valid level signal of the present disclosure is a high level signal, for example, the first potential H1 of the first level signal is 5V or 8V, and the invalid level signal is a low level signal, for example, the potential of the second level signal is 0.

[0165] Specifically, as shown in FIG. 2, the eighth transistor M8 writes the input signal STV to the first node N1 under the control of the first clock signal CK1, and the input signal STV in the first sub-stage t1 is the first level signal. The thirteenth transistor M13 writes the third clock signal CK3 to the second node N2 under the control of the input signal STV, and the third clock signal CK3 in the first sub-stage t1 is the second level signal. The fourteenth transistor M14 writes the signal output terminal Out under the control of the valid level signal of the first node N1 The output is the second clock signal CK2, and the second clock signal CK2 in the first sub-stage t1 is a second level signal.

[0166] The second sub-stage t2: the input signal STV, the first clock signal CK1, the third clock signal CK3 and the first reset signal STD are all second level signals, and the second clock signal CK2 is a first level signal; the output sub-circuit 3, under the control of the second clock signal CK2, uses the bootstrap effect to pull up the first potential H1 of the first level signal of the first node N1 to the second potential H2; the output sub-circuit 3, under the control of the second potential H2 of the first node N1, outputs the first level signal to the signal output end Out outputs the first level signal.

[0167] Specifically, as shown in FIG. 2, the first node N1 maintains the first potential H1 in the first sub-stage t1, the fourteenth transistor M14 is turned on, and in the case where the second clock signal CK2 is the first level signal, the second capacitor C2 is charged, the second capacitor C2 self-boosts the first node N1 to a higher second potential H2, thereby ensuring that the fourteenth transistor M14 is continuously turned on, and the signal output end Out is charged to the second potential H2 in the first sub-stage t1. The second clock signal CK2 is outputted, and the second clock signal CK2 is a first level signal at the second sub-stage t2. The second potential H2 is greater than the first potential H1.

[0168] The third sub-stage t3: the input signal STV, the first clock signal CK1, the second clock signal CK2, the third clock signal CK3 and the first reset signal STD are all second level signals; the output sub-circuit 3 pulls down the second potential H2 of the first node N1 to the first potential H1 under the control of the second clock signal CK2; the output sub-circuit 3 outputs the signal to the signal output end Out under the control of the first potential H1 of the first node N1 Output a second-level signal.

[0169] Specifically, as shown in Figure 2, the first node N1 maintains the second potential H2 of the second sub-stage t2, the fourteenth transistor M14 is turned on, and when the second clock signal CK2 is the second level signal, the second potential H2 of the first node N1 is pulled down to the first potential H1 through the action of the second capacitor C2. At this time, the fourteenth transistor M14 continues to be turned on, sending signals to the signal output terminal Out. The second clock signal CK2 is outputted, and in the third sub-stage t3, the second clock signal CK2 is a second level signal.

[0170] The fourth sub-stage t4: the input signal STV, the first clock signal CK1, the second clock signal CK2 and the power supply control signal VST are all second level signals, the third clock signal CK3 and the first reset signal STD are all first level signals; the reset sub-circuit 2 writes the second level signal to the first node N1 under the control of the first reset signal STD; the input sub-circuit 1 writes the first level signal to the second node N2 under the control of the third clock signal CK3; the output sub-circuit 3 writes the first level signal to the signal output terminal Out under the control of the first level signal of the second node N2 outputs the second level signal.

[0171] Specifically, as shown in Fig. 2, the tenth transistor M10 writes the second clock signal CK2 into the first node N1 under the control of the first reset signal STD, and the second clock signal CK2 is the second level signal at the fourth sub-stage t4. The twelfth transistor M12 writes the third clock signal CK3 into the second node N2 under the control of the third clock signal CK3, and the third clock signal CK3 is the first level signal at the fourth sub-stage t4. The fifteenth transistor M15 writes the first level signal of the second node N2 into the signal output terminal Out under the control of the first level signal of the second node N2, and the signal output terminal Out outputs the second level signal. The output power supply control signal VST is a second level signal in the fourth sub-stage t4.

[0172] In some embodiments, as shown in FIG. 8, taking the circuit structure of FIG. 3 as an example, compared with the driving method of the circuit shown in FIG. 2, the driving method further comprises:

[0173] The first sub-stage t1: the reset sub-circuit 2 writes a first level signal to the fourth node N4 under the control of the first clock signal CK1. Specifically, as shown in FIG. 3, the sixteenth transistor M16 writes the first clock signal CK1 to the fourth node N4 under the control of the first clock signal CK1, and the first clock signal CK1 in the first sub-stage t1 is a first level signal, thereby preventing the first node N1 from leaking to the end of the second clock signal line.

[0174] The second sub-stage t2: the input sub-circuit 1 writes a first level signal to the third node N3 under the control of the second clock signal CK2. Specifically, as shown in FIG. 3, the ninth transistor M9 writes the second clock signal CK2 to the third node N3 under the control of the second clock signal CK2, and the second clock signal CK2 in the second sub-stage t2 is a first level signal, thereby preventing the first node N1 from leaking to the signal input end Input Leakage.

[0175] In some embodiments, FIG. 9 is a timing diagram of another exemplary shift register provided by embodiments of the present disclosure. As shown in FIG. 9, taking the circuit structure of FIG. 5 as an example, the working stage further includes a compensation stage; the compensation stage includes a fifth sub-stage t5, a sixth sub-stage t6, a seventh sub-stage t7 and an eighth sub-stage t8; the driving method further includes:

[0176] The first sub-stage t1: the enable signal OE is a first level signal, the second reset signal TRST and the fourth clock signal CKA are both second level signals. The first input unit 41 writes the first level signal to the fifth node N5 under the control of the enable signal OE. Specifically, as shown in FIG. 5, the first transistor M1 and the second transistor M2 simultaneously write the input signal STV to the fifth node N5 under the control of the enable signal OE, and the input signal STV at the first sub-stage t1 is a first level signal. The working principle of other circuit structures is described in detail under the first sub-stage t1 as shown in FIG. 8, and the repeated parts are not described again.

[0177] The second sub-stage t2, the third sub-stage t3 and the fourth sub-stage t4: the enable signal OE, the second reset signal TRST and the fourth clock signal CKA are all second level signals. As shown in FIG. 5, at this time, the first transistor M1, the second transistor M2 and the eighteenth transistor M18 are all closed, and the working principle of other circuit structures is described in detail under the second sub-stage t2, the third sub-stage t3 and the fourth sub-stage t4 as shown in FIG. 8, and the repeated parts are not described again.

[0178] The fifth sub-stage t5: the input signal STV, the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the first reset signal STD, the enable signal OE and the second reset signal TRST are all second level signals, and the fourth clock signal CKA is a first level signal; the second input unit 42 pulls up the first potential H1 of the first level signal of the fifth node N5 to the second potential H2 by using the bootstrap effect under the control of the fourth clock signal CKA; the second input unit 42 writes the first level signal to the first node N1 under the synchronous control of the second potential H2 of the fifth node N5 and the fourth clock signal CKA; the third input unit 43 writes the second level signal to the second node N2 under the synchronous control of the first level signal of the fifth node N5 and the fourth clock signal CKA; the output sub-circuit 3 writes the first level signal to the signal output terminal Out outputting the second level signal.

[0179] Specifically, as shown in FIG. 5, the fifth node N5 keeps the first potential H1 of the first level signal in the first sub-stage t1, the fourth transistor M4 is continuously turned on, at this time the fourth clock signal CKA is the first level signal, the first capacitor C1 is charged, the first capacitor C1 boosts the fifth node N5 to a higher second potential H2, thereby ensuring that the fourth transistor M4 is continuously turned on. At the same time, the fifth transistor M5 and the sixth transistor M6 are synchronously turned on under the control of the fourth clock signal CKA, the fourth clock signal CKA, i.e. the first level signal, is written to the first node N1. The nineteenth transistor M19 is turned on under the control of the first potential H1 of the fifth node N5, the twentieth transistor M20 is turned on under the control of the fourth clock signal CKA, and the third clock signal CK3 is written to the second node N2, the third clock signal CK3 in the fifth sub-stage t5 is the second level signal. At this time, the fourteenth transistor M14 is controlled by the first level signal of the first node N1, and the signal output terminal Out is outputted with the second level signal. The output is the second clock signal CK2, and the second clock signal CK2 at the fifth sub-stage t5 is a second level signal.

[0180] The sixth sub-stage t6: the input signal STV, the first clock signal CK1, the third clock signal CK3, the fourth clock signal CKA, the first reset signal STD, the second reset signal TRST and the enable signal OE are all second level signals, and the second clock signal CK2 is a first level signal; the second input unit 42 pulls the second potential H2 of the fifth node N5 to the first potential H1 under the control of the fourth clock signal CKA; the output sub-circuit 3 pulls the first potential H1 of the first level signal of the first node N1 to the second potential H2 by using the bootstrap effect under the control of the second clock signal CK2; the output sub-circuit 3 outputs the signal output end Out outputting a first level signal.

[0181] Specifically, as shown in Fig. 5, the fifth node N5 keeps the second potential H2 in the fifth sub-stage t5, the fourth transistor M4 is turned on, and in the case that the fourth clock signal CKA is the second level signal, the second potential H2 of the fifth node N5 is pulled down to the first potential H1 through the action of the first capacitor C1, at this time the fourth transistor M4 is still continuously turned on, but since the fourth clock signal CKA is the second level signal, at this time the fifth transistor M5 and the sixth transistor M6 are turned off. The seventeenth transistor M17 writes the first level signal to the second electrode of the sixth transistor M6 under the control of the second clock signal CK2, preventing the first node N1 from leaking electricity to one end of the fourth clock signal line. In addition, the first node N1 keeps the first potential H1 in the fifth sub-stage t5, the fourteenth transistor M14 is turned on, and in the case that the second clock signal CK2 is the first level signal, the second capacitor C2 is charged, the second capacitor C2 self-boosts the first node N1 to a higher second potential H2, thereby ensuring that the fourteenth transistor M14 is continuously turned on, and the signal output end Out The second clock signal CK2 is output, and the second clock signal CK2 at the sixth sub-stage t6 is a first level signal.

[0182] The seventh sub-stage t7: the input signal STV, the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CKA, the first reset signal STD, the second reset signal TRST and the enable signal OE are all second level signals; the output sub-circuit 3 pulls down the second potential H2 of the first node N1 to the first potential H1 under the control of the second clock signal CK2; the output sub-circuit 3 outputs the signal OUT to the signal output end Out under the control of the first potential H1 of the first node N1 outputs the second level signal.

[0183] Specifically, as shown in Fig. 5, the first node N1 keeps the second potential H2 in the fifth sub-stage t5, the fourteenth transistor M14 is turned on, and in the case where the second clock signal CK2 is the second level signal, the second potential H2 of the first node N1 is pulled down to the first potential H1 through the action of the second capacitor C2, at this time the fourteenth transistor M14 is still continuously turned on, and the signal output terminal Out is pulled up to the first potential H1 through the action of the first capacitor C1, so that the signal output terminal Out outputs the first level signal. The second clock signal CK2 is outputted, and the second clock signal CK2 is a second level signal at the seventh sub-stage t7.

[0184] The eighth sub-stage t8: the input signal STV, the first clock signal CK1, the second clock signal CK2, the fourth clock signal CKA, the first reset signal STD and the power control signal VST are all second level signals; the third clock signal CK3, the second reset signal TRST and the enable signal OE are all first level signals; the pull-down unit 44 writes the second level signal to the first node N1 under the control of the second reset signal TRST; the first input unit 41 writes the second level signal to the fifth node N5 under the control of the enable signal OE; the input sub-circuit 1 writes the first level signal to the second node N2 under the control of the third clock signal CK3; the output sub-circuit 3 writes the first level signal to the signal output terminal Out outputs the second level signal.

[0185] Specifically, as shown in Fig. 5, the eighteenth transistor M18 writes the second clock signal CK2 into the first node Nl under the control of the second reset signal TRST, and the second clock signal CK2 is the second level signal in the eighth sub-stage t8. At this time, the first node Nl is at low potential, and the fourteenth transistor M14 is cut off. The first transistor Ml and the second transistor M2 write the input signal STV (i.e. the second level signal) into the fifth node N5 under the control of the enable signal OE, so that the fourth transistor M4 is cut off. The twelfth transistor M12 writes the first level signal into the second node N2 under the control of the third clock signal CK3, so that the fifteenth transistor M15 is turned on, and the signal output terminal Out outputs the input signal STV (i.e. the second level signal). The output power control signal VST is a second level signal in the eighth sub-stage t8.

[0186] In some embodiments, in the working stage, including but not limited to the display stage and the compensation stage, the input signal STV, the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CKA, the first reset signal STD, the enable signal OE, the second reset signal TRST and the power control signal VST are all non-constant voltage signals.

[0187] The driving method of the shift register provided by the embodiments of the present disclosure utilizes non-constant voltage signals for control, and no constant voltage signal is introduced, so that no constant voltage difference is generated between the signal lines providing the non-constant voltage signals, and thus no constant voltage stress exists between all the signal lines, thereby avoiding the problem of signal short circuit caused by electrochemical corrosion between the signal lines, reducing the risk of failure of the shift register, and improving the service life of the shift register.

[0188] In addition, the embodiments of the present disclosure also provide a gate driving circuit including N cascaded shift registers according to any of the above embodiments. FIG. 10 is a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure. As shown in FIG. 10, except for the first shift register, the signal input end Input ; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

[0189] The specific structure of the shift register can refer to the detailed description of the shift register, and the repeated part will not be described herein.

[0190] The gate drive circuit provided by the embodiments of the present disclosure is controlled by a non-constant voltage signal, and no constant voltage signal is introduced, so that no constant voltage difference is generated between the signal lines providing the non-constant voltage signal, and no constant voltage stress is generated between all the signal lines, thereby avoiding the problem of signal short circuit caused by electrochemical corrosion between the signal lines, reducing the risk of failure of the shift register, and improving the service life of the shift register.

[0191] In some embodiments, the gate drive circuit further comprises a signal input end Input an input signal line, a first clock signal line transmitting a first clock signal CK1, a second clock signal line transmitting a second clock signal CK2, a third clock signal line transmitting a third clock signal CK3, a fourth clock signal line transmitting a fourth clock signal CKA, a first reset signal line transmitting a first reset signal STD, an enable signal line transmitting an enable signal OE, a second reset signal line transmitting a second reset signal TRST, a power control signal line transmitting a power control signal VST, and an electrical connection between a signal input end Input of the i+1th shift register and a signal output end Out of the ith shift register a cascade signal line.

[0192] In addition, the display device provided by the embodiment of the present disclosure includes the gate drive circuit in any of the above embodiments.

[0193] FIG. 11 is a schematic diagram of a display device provided by an embodiment of the present disclosure. As shown in FIG. 11, the display device includes a gate drive circuit 100 and a timing controller 200.

[0194] In some embodiments, the display device further includes the timing controller 200; the timing controller 200 is electrically connected to the gate drive circuit 100, specifically: different ports on the timing controller 200 are respectively electrically connected to one end of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CKLA, the first reset signal line Lstd, the enable signal line Loe, the second reset signal line Ltrst and the power control signal line Lvst, and the other end of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CKLA, the first reset signal line Lstd, the enable signal line Loe, the second reset signal line Ltrst and the power control signal line Lvst are all electrically connected to the gate drive circuit 100.

[0195] The timing controller 200 is configured to output the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CKA, the first reset signal STD, the enable signal OE, the second reset signal TRST and the power control signal VST to the gate drive circuit 100 through the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CKLA, the first reset signal line Lstd, the enable signal line Loe, the second reset signal line Ltrst and the power control signal line Lvst, respectively.

[0196] The input signal STV, the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, the fourth clock signal CKA, the first reset signal STD, the enable signal OE, the second reset signal TRST and the power control signal VST are all signals of non-constant voltage.

[0197] The display device provided by the embodiment of the present disclosure is controlled by signals of non-constant voltage, and there is no constant voltage signal introduced, so that there is no constant voltage difference between the signal lines providing signals of non-constant voltage, and there is no constant voltage stress between all the signal lines, thereby avoiding the problem of signal short circuit caused by electrochemical corrosion between the signal lines, reducing the risk of failure of the shift register, and improving the service life of the shift register.

[0198] For example, the display device can be a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a vehicle-mounted device, or any product having a display function. Other essential components of the display device are understood by those skilled in the art and are not described here to avoid redundancy and should not be considered as a limitation on the present disclosure.

[0199] It can be understood that the above embodiments are only exemplary embodiments adopted for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also considered as the protection scope of the present disclosure.

Claims

1. A shift register comprising an input sub-circuit, a reset sub-circuit and an output sub-circuit; the input sub-circuit is configured to control the potential of the first node with the input signal in response to the first clock signal; and, in response to the input signal, controlling the potential of the second node with a third clock signal, or in response to the third clock signal, controlling the potential of the second node with the third clock signal; the reset sub-circuit is configured to control the potential of the first node with a second clock signal in response to a first reset signal; the output sub-circuit is configured to output the second clock signal through a signal output terminal in response to the potential of the first node; or, output a power control signal through the signal output terminal in response to the potential of the second node; the power control signal is a signal of non-constant voltage.

2. The shift register of claim 1, wherein, the input sub-circuit comprises an eighth transistor, a twelfth transistor and a thirteenth transistor; the first electrode of the eighth transistor is electrically connected to the first node, the second electrode is electrically connected to a signal input terminal transmitting the input signal, and the gate electrode is electrically connected to a first clock signal line transmitting the first clock signal; the first electrode and the gate electrode of the twelfth transistor are both electrically connected to a third clock signal line transmitting the third clock signal, and the second electrode is electrically connected to the second node; the first electrode of the thirteenth transistor is electrically connected to the second node, the second electrode is electrically connected to the third clock signal line, and the gate electrode is electrically connected to the signal input terminal.

3. The shift register of claim 1, wherein, the input sub-circuit is further configured to control the potential of a third node with the second clock signal in response to the second clock signal.

4. The shift register of claim 3, wherein, the input sub-circuit comprises a seventh transistor, an eighth transistor, a ninth transistor, a twelfth transistor and a thirteenth transistor; the first electrode of the seventh transistor is electrically connected to the third node, the second electrode is electrically connected to a signal input terminal transmitting the input signal, and the gate electrode is electrically connected to a first clock signal line transmitting the first clock signal; the first electrode of the eighth transistor is electrically connected to the first node, the second electrode is electrically connected to the third node, and the gate electrode is electrically connected to the first clock signal line; the first electrode and the gate electrode of the ninth transistor are both electrically connected to a second clock signal line transmitting the second clock signal, and the second electrode is electrically connected to the third node; the first electrode and the gate electrode of the twelfth transistor are both electrically connected to a third clock signal line transmitting the third clock signal, and the second electrode is electrically connected to the second node; the first electrode of the thirteenth transistor is electrically connected to the second node, the second electrode is electrically connected to the third clock signal line transmitting the third clock signal, and the gate electrode is electrically connected to the signal input terminal.

5. The shift register of claim 1, wherein, the reset sub-circuit comprises a tenth transistor; the first electrode of the tenth transistor is electrically connected to the first node, the second electrode is electrically connected to a second clock signal line transmitting the second clock signal, and the gate electrode is electrically connected to a first reset signal line transmitting the first reset signal.

6. The shift register of claim 1, wherein, the reset sub-circuit is further configured to control the potential of a fourth node with the first clock signal in response to the first clock signal.

7. The shift register of claim 6, wherein, the reset sub-circuit comprises a tenth transistor, an eleventh transistor and a sixteenth transistor; The first electrode of the tenth transistor is electrically connected with the first node, the second electrode is electrically connected with the fourth node, and the gate is electrically connected with a first reset signal line for transmitting the first reset signal; The first electrode of the eleventh transistor is electrically connected with the fourth node, the second electrode is electrically connected with a second clock signal line for transmitting the second clock signal, and the gate is electrically connected with the first reset signal line; The first electrode and the gate of the sixteenth transistor are both electrically connected with a first clock signal line for transmitting the first clock signal, and the second electrode is electrically connected with the fourth node.

8. The shift register of claim 1, wherein, The reset sub-circuit is further configured to control the potential of the first node by using the second clock signal in response to the potential of the second node.

9. The shift register of claim 8, wherein, The reset sub-circuit comprises a tenth transistor and an eleventh transistor; The first electrode of the tenth transistor is electrically connected with the first node, the second electrode is electrically connected with the first electrode of the eleventh transistor, and the gate is electrically connected with the first reset signal line for transmitting the first reset signal; The second electrode of the eleventh transistor is electrically connected with the second clock signal line for transmitting the second clock signal, and the gate is electrically connected with the second node.

10. The shift register of claim 1, wherein, The output sub-circuit comprises a fourteenth transistor, a fifteenth transistor and a second capacitor; The first electrode of the fourteenth transistor is electrically connected with the signal output end, the second electrode is electrically connected with the second clock signal line for transmitting the second clock signal, and the gate is electrically connected with the first node; The first electrode of the fifteenth transistor is electrically connected with a power control signal line for transmitting the power control signal, the second electrode is electrically connected with the signal output end, and the gate is electrically connected with the second node; The first plate of the second capacitor is electrically connected with the first node, and the second plate is electrically connected with the signal output end.

11. The shift register according to any one of claims 1 to 10, wherein The shift register further comprises an external compensation sub-circuit; the external compensation sub-circuit comprises a first input unit, a second input unit, a third input unit and a pull-down unit; The first input unit is configured to control the potential of a fifth node by using the input signal in response to an enable signal; The second input unit is configured to control the potential of the first node by using the fourth clock signal in response to the potential of the fifth node and the fourth clock signal; The third input unit is configured to control the potential of the second node by using the third clock signal in response to the potential of the fifth node and the fourth clock signal; The pull-down unit is configured to control the potential of the first node by using the second clock signal in response to a second reset signal.

12. The shift register of claim 11, wherein, The first input unit comprises a first transistor, a second transistor and a third transistor; The first electrode of the first transistor is electrically connected with the second electrode of the second transistor and the second electrode of the third transistor, the second electrode is electrically connected with a signal input end for transmitting the input signal, and the gate is electrically connected with an enable signal line for transmitting the enable signal; The first electrode of the second transistor is electrically connected with the fifth node, and the gate is electrically connected with the enable signal line; The first electrode and the gate of the third transistor are both electrically connected with the fifth node.

13. The shift register of claim 11, wherein, The second input unit comprises a fourth transistor, a fifth transistor, a sixth transistor, a seventeenth transistor and a first capacitor; The first electrode of the fourth transistor is electrically connected with the second electrode of the fifth transistor, the second electrode is electrically connected with a fourth clock signal line transmitting the fourth clock signal, and the gate electrode is electrically connected with the fifth node; The first electrode of the fifth transistor is electrically connected with the second electrode of the sixth transistor and the second electrode of the seventeenth transistor, and the gate electrode is electrically connected with the fourth clock signal line; The first electrode of the sixth transistor is electrically connected with the first node, and the gate electrode is electrically connected with the fourth clock signal line; The first electrode and the gate electrode of the seventeenth transistor are both electrically connected with a second clock signal line transmitting the second clock signal; and The first plate of the first capacitor is electrically connected with the fifth node, and the second plate is electrically connected with the first electrode of the fourth transistor.

14. The shift register of claim 11, wherein, The second input unit comprises a fourth transistor, a fifth transistor, a sixth transistor, a seventeenth transistor and a first capacitor; The first electrode of the fourth transistor is electrically connected with the second electrode of the fifth transistor, the second electrode is electrically connected with a fourth clock signal line transmitting the fourth clock signal, and the gate electrode is electrically connected with the fifth node; The first electrode of the fifth transistor is electrically connected with the second electrode of the sixth transistor and the second electrode of the seventeenth transistor, and the gate electrode is electrically connected with the fourth clock signal line; The first electrode of the sixth transistor is electrically connected with the first node, and the gate electrode is electrically connected with the fourth clock signal line; The first electrode and the gate electrode of the seventeenth transistor are both electrically connected with a second clock signal line transmitting the second clock signal; The first plate of the first capacitor is electrically connected with the fifth node, and the second plate is electrically connected with the fourth clock signal line.

15. The shift register of claim 11, wherein, The third input unit comprises a nineteenth transistor and a twentieth transistor; The first electrode of the nineteenth transistor is electrically connected with the second node, the second electrode is electrically connected with the first electrode of the twentieth transistor, and the gate electrode is electrically connected with the fifth node; The second electrode of the twentieth transistor is electrically connected with a third clock signal line transmitting the third clock signal, and the gate electrode is electrically connected with the fourth clock signal line.

16. The shift register of claim 11, wherein, The pull-down unit comprises an eighteenth transistor; The first electrode of the eighteenth transistor is electrically connected with the first node, the second electrode is electrically connected with a second clock signal line transmitting the second clock signal, and the gate electrode is electrically connected with a second reset signal line transmitting the second reset signal.

17. A driving method of a shift register, applied to the shift register according to any one of claims 1-16, wherein a working stage of the shift register comprises at least a display stage, and the display stage comprises a first sub-stage, a second sub-stage, a third sub-stage and a fourth sub-stage; wherein, The driving method comprises: The first sub-stage: the input signal and the first clock signal are both first level signals, the second clock signal, the third clock signal and the first reset signal are all second level signals; under the control of the first clock signal, the input sub-circuit writes the first level signal to the first node; and under the control of the input signal, the input sub-circuit writes the second level signal to the second node; under the control of the first level signal of the first node, the output sub-circuit outputs the second level signal to the signal output end; wherein, the first level signal is an effective level signal, and the second level signal is an ineffective level signal; The second sub-stage: the input signal, the first clock signal, the third clock signal and the first reset signal are the second level signals, and the second clock signal is the first level signal; the output sub-circuit, under the control of the second clock signal, uses a bootstrap effect to pull the first potential of the first level signal of the first node to a second potential; the output sub-circuit, under the control of the second potential of the first node, outputs a first level signal to the signal output end; The third sub-stage: the input signal, the first clock signal, the second clock signal, the third clock signal and the first reset signal are the second level signals; the output sub-circuit, under the control of the second clock signal, pulls the second potential of the first node to the first potential; the output sub-circuit, under the control of the first potential of the first node, outputs a second level signal to the signal output end; The fourth sub-stage: the input signal, the first clock signal, the second clock signal and the power supply control signal are the second level signals, and the third clock signal and the first reset signal are the first level signals; the reset sub-circuit, under the control of the first reset signal, writes the second level signal to the first node; the input sub-circuit, under the control of the third clock signal, writes the first level signal to the second node; the output sub-circuit, under the control of the first level signal of the second node, outputs the second level signal to the signal output end.

18. The driving method according to claim 17, wherein The driving method further comprises: The first sub-stage: the reset sub-circuit, under the control of the first clock signal, writes the first level signal to the fourth node; The second sub-stage: the input sub-circuit, under the control of the second clock signal, writes the first level signal to the third node.

19. The driving method according to claim 17 or 18, wherein The working stage further comprises a compensation stage; The compensation stage comprises a fifth sub-stage, a sixth sub-stage, a seventh sub-stage and an eighth sub-stage; the driving method further comprises: The first sub-stage: the enable signal is the first level signal, the second reset signal and the fourth clock signal are the second level signals; the first input unit, under the control of the enable signal, writes the first level signal to the fifth node; The second sub-stage, the third sub-stage and the fourth sub-stage: the enable signal, the second reset signal and the fourth clock signal are the second level signals; In the fifth sub-stage, the input signal, the first clock signal, the second clock signal, the third clock signal, the first reset signal, the enable signal and the second reset signal are the second level signal, and the fourth clock signal is the first level signal; the second input unit, under the control of the fourth clock signal, uses the bootstrap effect to pull the first potential of the first level signal of the fifth node to the second potential; the second input unit, under the synchronous control of the second potential of the fifth node and the fourth clock signal, writes the first level signal to the first node; the third input unit, under the synchronous control of the first level signal of the fifth node and the fourth clock signal, writes the second level signal to the second node; and the output sub-circuit, under the control of the first level signal of the first node, outputs the second level signal to the signal output terminal. In the sixth sub-stage, the input signal, the first clock signal, the third clock signal, the fourth clock signal, the first reset signal, the second reset signal and the enable signal are the second level signal, and the second clock signal is the first level signal; the second input unit, under the control of the fourth clock signal, pulls the second potential of the fifth node to the first potential; and the output sub-circuit, under the control of the second clock signal, uses the bootstrap effect to pull the first potential of the first level signal of the first node to the second potential; the output sub-circuit, under the control of the second potential of the first node, outputs the first level signal to the signal output terminal. In the seventh sub-stage, the input signal, the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, the first reset signal, the second reset signal and the enable signal are the second level signal; the output sub-circuit, under the control of the second clock signal, pulls the second potential of the first node to the first potential; and the output sub-circuit, under the control of the first potential of the first node, outputs the second level signal to the signal output terminal. In the eighth sub-stage, the input signal, the first clock signal, the second clock signal, the fourth clock signal, the first reset signal and the power control signal are the second level signal; the third clock signal, the second reset signal and the enable signal are the first level signal; the pull-down unit, under the control of the second reset signal, writes the second level signal to the first node; the first input unit, under the control of the enable signal, writes the second level signal to the fifth node; the input sub-circuit, under the control of the third clock signal, writes the first level signal to the second node; and the output sub-circuit, under the control of the first level signal of the second node, outputs the second level signal to the signal output terminal.

20. The driving method according to claim 19, wherein In the working phase, the input signal, the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, the first reset signal, the enable signal, the second reset signal and the power control signal are non-constant voltage signals.

21. A gate driving circuit comprising N cascaded shift registers according to any one of claims 1-16. In addition to the first stage shift register, the signal input end of the i+1 stage shift register is electrically connected to the signal output end of the i stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

22. A display device comprising the gate driving circuit according to claim 21.

23. The display device of claim 22, wherein, The display device further comprises a timing controller; The timing controller is configured to output a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a first reset signal, an enable signal, a second reset signal and a power control signal to the gate driving circuit; In the working phase, the input signal, the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, the first reset signal, the enable signal, the second reset signal and the power control signal are non-constant voltage signals.

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