Memory access information recording method, memory data analysis method, and related device

Abstract

Embodiments of the present application provide a memory access information recording method, a memory data analysis method, and a related device. The memory access information recording method comprises: acquiring an access request, wherein the access request at least comprises access address information and access data source information, and the access data source information at least comprises identifier information of a device issuing the access request; on the basis of the access request, generating data to be recorded and a write command corresponding to the data to be recorded, wherein the data to be recorded comprises the access address information and the access data source information of the access request; and on the basis of the write command corresponding to the data to be recorded, writing the data to be recorded into a preset address range of a memory, wherein the preset address range is a preset area for storing the data to be recorded, and an access permission is set for the preset address. According to the embodiments of the present application, the data to be recorded is written into the preset address range of the memory, thereby achieving recording of the source of memory data.

Description

Memory access information recording method, memory data analysis method and related device

[0001] Related applications

[0002] The present application claims priority to the Chinese patent application No. 202410740814.2, filed on June 7, 2024, entitled "Memory access information recording method, memory data analysis method and related device", the contents of which are hereby incorporated by reference in their entirety. TECHNICAL FIELD

[0003] Embodiments of the present application relate to the field of computer technology, in particular to a memory access information recording method, a memory data analysis method and related device. BACKGROUND

[0004] In today's highly complex processor systems, the interaction between upstream devices such as processor cores and memories becomes increasingly frequent and intensive. With the continuous improvement of computer system performance, the memory capacity continues to increase, and the transmission speed of commands and data continues to rise, making the data throughput of the memory also show an explosive growth trend.

[0005] In order to improve system performance, it is necessary to analyze memory data to reflect the characteristics of memory data, and analyzing memory data from the perspective of data source can intuitively reflect the data characteristics of each device interacting with the memory.

[0006] However, how to obtain the data source of the memory data is a technical problem to be solved by those skilled in the art.

[0007] Content of the present application

[0008] Therefore, embodiments of the present application provide a memory access information recording method, a memory data analysis method and related device, which realize the recording of the data source of the memory data.

[0009] To achieve the above object, the embodiments of the present application provide the following technical solutions.

[0010] In a first aspect, the embodiments of the present application provide a memory access information recording method, comprising:

[0011] obtaining an access request, the access request comprising at least access address information and access data source information, the access data source information comprising at least identification information of a device sending the access request;

[0012] generating to-be-recorded data and a write command corresponding to the to-be-recorded data according to the access request, the to-be-recorded data comprising the access address information and the access data source information of the access request;

[0013] write the to-be-recorded data into a preset address range of the memory based on the write command corresponding to the to-be-recorded data; the preset address range is a preset region for storing the to-be-recorded data, and the preset address is provided with an access permission.

[0014] Optionally, before the step of generating the to-be-recorded data and the write command corresponding to the to-be-recorded data according to the access request, the method further comprises:

[0015] obtaining a to-be-recorded data trigger command, the to-be-recorded data trigger command being used to trigger the step of generating the to-be-recorded data and the write command corresponding to the to-be-recorded data according to the access request;

[0016] Optionally, the to-be-recorded data trigger command comprises:

[0017] obtaining a to-be-recorded data prohibition command, the to-be-recorded data prohibition command being used to prohibit the step of generating the to-be-recorded data and the write command corresponding to the to-be-recorded data according to the access request.

[0018] Optionally, the step of writing the to-be-recorded data into the preset address range of the memory based on the write command corresponding to the to-be-recorded data comprises:

[0019] sending the write command to a command queue for arbitration, and if the write command is selected, writing the to-be-recorded data into the preset address range, so that the to-be-recorded data is recorded in the preset address range.

[0020] Optionally, the step of generating the to-be-recorded data and the write command corresponding to the to-be-recorded data according to the access request comprises:

[0021] decoding access address information of the access request;

[0022] generating the to-be-recorded data based on the decoded access address information and access data source information of the access request;

[0023] generating the write command corresponding to the to-be-recorded data.

[0024] Optionally, in the step of generating the to-be-recorded data and the write command corresponding to the to-be-recorded data according to the access request, an access address of the write command is incremented by a preset value within a preset address range.

[0025] Optionally, the step of generating the to-be-recorded data and the write command corresponding to the to-be-recorded data according to the access request further comprises:

[0026] if the access address of the write command reaches an upper limit of the preset address range, stopping generating the write command.

[0027] Optionally, after the step of stopping generating the write command, the method further comprises:

[0028] stopping generating the to-be-recorded data.

[0029] Optionally, in the step of writing the to-be-recorded data into the preset address range of the memory based on the write command corresponding to the to-be-recorded data, the data amount of the to-be-recorded data is less than or equal to the preset value.

[0030] Optionally, when the data amount of the to-be-recorded data is less than the preset value, the data amount of the to-be-recorded data is equal to the preset value by using a zero padding manner.

[0031] Optionally, after the step of generating the to-be-recorded data and the write command corresponding to the to-be-recorded data according to the access request, and before the step of writing the to-be-recorded data into the preset address range of the memory based on the write command corresponding to the to-be-recorded data, the method further comprises:

[0032] caching the to-be-recorded data into a write data cache.

[0033] Optionally, the identification information at least includes a processor core identification number, or an input / output device identification number; and when the processor core identification number exists, the identification information further includes a thread identification number in the processor core.

[0034] Optionally, the access data source information further includes a priority of the access request and a type of the access request.

[0035] In a second aspect, an embodiment of the present application provides a memory data analysis method, comprising:

[0036] performing data analysis on memory data based on to-be-recorded data, wherein the to-be-recorded data is written into a preset address range of the memory based on the memory access information recording method in the first aspect.

[0037] In a third aspect, an embodiment of the present application provides a memory access information recording device, comprising:

[0038] an obtaining module, configured to obtain an access request, wherein the access request at least includes access address information and access data source information, and the access data source information at least includes identification information of a device sending the access request;

[0039] a generating module, configured to generate to-be-recorded data and a write command corresponding to the to-be-recorded data according to the access request, wherein the to-be-recorded data includes the access address information and the access data source information of the access request;

[0040] The write module is configured to write the to-be-recorded data into a preset address range of the memory based on a write command corresponding to the to-be-recorded data; the preset address range is a preset region for storing the to-be-recorded data, and the preset address is provided with an access permission.

[0041] In a fourth aspect, an embodiment of the present application provides a memory controller, which comprises the memory access information recording apparatus in the third aspect.

[0042] Optionally, the memory controller further comprises:

[0043] The command queue is configured to store an access request sent by an upstream device of the memory controller and the write command generated by the memory access information recording apparatus in the third aspect.

[0044] The write data buffer module is configured to buffer memory access write data corresponding to the access request and the to-be-recorded data corresponding to the write command generated by the memory access information recording apparatus in the third aspect.

[0045] The arbiter is configured to select an access request or a write command in the command queue as a target task; if the target task is the write command, the to-be-recorded data corresponding to the write command is written into the preset address range, so that the to-be-recorded data is recorded in the preset address range.

[0046] Optionally, the selecting an access request or a write command in the command queue as a target task comprises:

[0047] According to an access priority and / or an address access efficiency of the to-be-executed access request or the write command, an access request or a write command is selected as a target task from the to-be-executed access request or the write command stored in the command queue.

[0048] In a fifth aspect, an embodiment of the present application provides an electronic device, which comprises the memory controller in the fourth aspect.

[0049] In a sixth aspect, an embodiment of the present application provides a storage medium, which stores one or more computer executable instructions; when the one or more computer executable instructions are executed, the memory access information recording method in the first aspect or the memory data analysis method in the second aspect is implemented.

[0050] In a seventh aspect, an embodiment of the present application provides a computer program product, which comprises one or more computer executable instructions; when the one or more computer executable instructions are executed, the memory access information recording method in the first aspect or the memory data analysis method in the second aspect is implemented.

[0051] The embodiment of the present application provides a memory access information recording method, a memory data analysis method and related equipment, wherein the memory access information recording method comprises the following steps: obtaining an access request, wherein the access request comprises at least access address information and access data source information, and the access data source information comprises at least identification information of a device sending the access request; generating to-be-recorded data and a write command corresponding to the to-be-recorded data according to the access request, wherein the to-be-recorded data comprises the access address information and the access data source information of the access request; and writing the to-be-recorded data into a preset address range of a memory based on the write command corresponding to the to-be-recorded data; the preset address range is a preset region for storing the to-be-recorded data, and the preset address is provided with an access permission.

[0052] It can be seen that the memory access information recording method provided by the embodiment of the present application generates to-be-recorded data comprising the access address information and the access data source information of the access request and a write command corresponding to the to-be-recorded data, and writes the to-be-recorded data into a preset address range of a memory, so as to record the data source of the memory. BRIEF DESCRIPTION OF DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only the embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on the provided drawings.

[0054] Fig. 1 is an optional block diagram of a processor system;

[0055] Fig. 2 is an optional structure diagram of a memory controller and a memory for data interaction;

[0056] Fig. 3 is an optional flow diagram of a memory access information recording method provided by the embodiment of the present application;

[0057] Fig. 4 is another optional flow diagram of a memory access information recording method provided by the embodiment of the present application;

[0058] Fig. 5 is an optional flow diagram of generating to-be-recorded data and a write command corresponding to the to-be-recorded data provided by the embodiment of the present application;

[0059] Fig. 6 is a first diagram of to-be-recorded data provided by the embodiment of the present application;

[0060] Fig. 7 is a second diagram of to-be-recorded data provided by the embodiment of the present application;

[0061] Fig. 8 is an optional structure diagram of a memory access information recording device provided by the embodiment of the present application;

[0062] FIG. 9 is a schematic diagram of an optional structure of a generation module in the memory access information recording apparatus according to an embodiment of the present application;

[0063] FIG. 10 is a schematic diagram of an optional structure of a memory controller according to an embodiment of the present application. DETAILED DESCRIPTION

[0064] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0065] To facilitate understanding of the processor system, an optional block diagram of the processor system is shown in FIG. 1. As shown in FIG. 1, the processor system can include a plurality of processor cores, such as processor core 101, processor core 102, processor core 103, etc.; a plurality of levels of cache arranged outside the plurality of processor cores, such as a plurality of levels of cache 108 connected to the processor core 101, a plurality of levels of cache 109 connected to the processor core 102, and a plurality of levels of cache 110 connected to the processor core 103; a bus 105; a memory controller 106 and a memory 107; wherein the plurality of levels of cache interacts with the memory 107 through the memory controller 106. In an optional implementation, the bus 105 can also be connected to an IO (input / output) device 104, such as a PCIe device, for data interaction.

[0066] The processor core is the operation and control core of the processor system. The processor core can be, for example, a CPU (Central Processing Unit, central processor) core, a GPU (Graphics Processing Unit, graphics processor) core, a NPU (Neural-network Processing Unit, embedded neural network processor) core, a TPU (Tensor Processing Unit, tensor processing unit), an AI (Artificial Intelligence, artificial intelligence) core, etc.

[0067] Cache is a memory with extremely fast access speed between processor core and memory, used to map a relatively large amount of storage units in memory by a relatively small amount of storage units. Cache generally has a multi-level structure, in which a higher level cache can map a relatively large amount of storage units of a lower level cache by a relatively small amount of storage units, and a last level cache can map a relatively large amount of storage units of memory by a relatively small amount of storage units; and the upper level cache has a faster data access speed than the lower level cache, but the capacity of the upper level cache is smaller than that of the lower level cache. Therefore, the processor core can start from the uppermost cache with the fastest data access speed but the smallest capacity, and process the multi-level cache and memory to realize data processing. It should be noted that the upper level cache is closer to the processor core than the lower level cache.

[0068] In today's highly complex processor systems, the interaction between upstream devices such as processor cores and memory becomes increasingly frequent and intensive. As a key bridge connecting the two, the memory controller undertakes the important task of processing a large number of command operations and data accesses. However, with the continuous progress of technology, the performance requirements of processor systems are also increasing, the transmission speed of commands and data continues to rise, and the data throughput also shows an explosive growth trend.

[0069] It can be understood that, in order to improve system performance, it is necessary to analyze memory data to reflect the characteristics of memory data, and analyzing memory data from the perspective of data source can intuitively reflect the data characteristics of each device interacting with the memory.

[0070] Further, referring to FIG. 2, FIG. 2 is a schematic diagram of an optional structure of data interaction between a memory controller and a memory. As shown in FIG. 2, after receiving an access request sent by an upstream, the memory controller 106 parses the access address information of the access request and saves it to the command queue 201 together with the access priority information of the access request. The arbitrator 202 selects a target access request from the command queue 201 according to the access priority and / or address access efficiency of the access request, and sends the request to the memory to perform corresponding operations (such as data read or write operations).

[0071] Obviously, this memory access method cannot record the data source of the memory data.

[0072] Therefore, the embodiments of the present application provide a memory access information recording method, a memory data analysis method and related devices, wherein the memory access information recording method comprises: obtaining an access request, wherein the access request comprises at least access address information and access data source information, and the access data source information comprises at least identification information of a device sending the access request; generating to-be-recorded data and a write command corresponding to the to-be-recorded data according to the access request, wherein the to-be-recorded data comprises the access address information and the access data source information of the access request; and writing the to-be-recorded data into a preset address range of a memory based on the write command corresponding to the to-be-recorded data, wherein the preset address range is a preset region for storing the to-be-recorded data, and the preset address is provided with an access permission.

[0073] It can be seen that the memory access information recording method provided by the embodiments of the present application generates to-be-recorded data comprising the access address information and the access data source information of the access request and a write command corresponding to the to-be-recorded data, and writes the to-be-recorded data into a preset address range of a memory, thereby realizing recording of a memory data source.

[0074] Correspondingly, in memory data analysis, the memory data source provided based on the above scheme can be used as a data basis to intuitively reflect data characteristics of each device interacting with the memory, thereby being more conducive to proposing a feasible software and hardware optimization scheme based on corresponding data analysis.

[0075] Based on the above idea, FIG. 3 exemplarily shows an optional flowchart of a memory access information recording method provided by the embodiments of the present application, which can be implemented by a memory controller. As shown in FIG. 3, the flowchart of the method can comprise the following steps.

[0076] Step S100: obtaining an access request.

[0077] The access request refers to a request sent by an upstream device (such as a processor core, an IO (input / output) device, etc.) to a memory controller. The memory controller can perform a data reading or writing operation on a memory region requested to be accessed according to the access request.

[0078] In an optional implementation, the access request can comprise access address information and access data source information, wherein the access address information refers to a memory address specified by the upstream device when sending the access request and required to be accessed, so that the memory controller can perform data access on the memory region requested to be accessed based on the access address information; and the access data source information comprises at least identification information of a device sending the access request. In an optional implementation, the access data source information can further comprise a priority of the access request and a type of the access request, etc.

[0079] In an optional implementation, the identification information can include a processor core identification number, or an input / output device identification number; and when the processor core identification number exists, the identification information can further include a thread identification number within the processor core.

[0080] Step S200: generating, according to the access request, to-be-recorded data and a write command corresponding to the to-be-recorded data.

[0081] The to-be-recorded data can include access address information and access data source information of the access request. The access address information refers to a memory address specified by an upstream device when sending an access request, and is used to instruct the memory controller to perform a read or write operation on the specified memory location. In the memory, each memory location has a unique address identifier, so that the upstream device can access the data in the memory by sending an access request containing specific address information.

[0082] The access data source information at least includes identification information of a device sending the access request. In an optional implementation, the access data source information can further include a priority of the access request and a type of the access request, etc. The identification information of the device sending the access request can explicitly indicate which device sends the access request. In an optional implementation, the identification information can include a processor core identification number, or an input / output device identification number; and when the processor core identification number exists, the identification information can further include a thread identification number within the processor core.

[0083] The priority of the access request can represent the importance or urgency of the access request, and a request with a high priority will be processed first, while a request with a low priority needs to be queued and waited. For example, when multiple programs or processes simultaneously send access requests, the memory controller can determine which request to process first according to the priorities of these requests.

[0084] The type of the access request refers to the operation type performed by the access request, which can be read access or write access, for example.

[0085] The to-be-recorded data is generated according to the access request and contains data information corresponding to the access request, for subsequent recording, tracking or analysis. It can be understood that the to-be-recorded data contains specific information about which device accesses which memory address.

[0086] In an optional implementation, in order to reduce the occupation of the memory access bandwidth, the write command can be a new request generated by multiple original access requests. The aggregated write command can more efficiently utilize the memory bandwidth, because it reduces the number of new requests and avoids frequently performing small and scattered write operations.

[0087] Step S300: based on a write command corresponding to the to-be-recorded data, write the to-be-recorded data into a preset address range of the memory.

[0088] The preset address range is a preset region for storing the to-be-recorded data, and the preset address is provided with an access permission to ensure that only authorized systems or processes can access it, thereby ensuring the security and integrity of the data.

[0089] It can be seen that the memory access information recording method provided in the embodiments of the present application generates to-be-recorded data including access address information and access data source information of the access request and a write command corresponding to the to-be-recorded data, and writes the to-be-recorded data into a preset address range of the memory, thereby realizing recording of the memory data source.

[0090] Correspondingly, in memory data analysis, based on the memory data source provided in the above scheme as a data basis, the data characteristics of each device interacting with the memory can be intuitively reflected, thereby being more conducive to proposing feasible software and hardware optimization schemes based on corresponding data analysis.

[0091] For example, in the context of optimizing the design of a memory controller, the processing flow of the above access request is usually executed thousands or even billions of times in a preset period, and the processing information generated in the processing process is extracted as basic data to analyze the defects and problems of the memory controller. The memory data source recorded by the above scheme can realize detailed analysis of the memory data and provide a basis for optimizing the design of the memory controller.

[0092] In an optional example, referring to another optional flowchart of the memory access information recording method provided by the embodiments of the present application shown in FIG. 4, before the step of generating to-be-recorded data and a write command corresponding to the to-be-recorded data according to an access request, the method can further include:

[0093] Step S101: obtaining a to-be-recorded data trigger command or a to-be-recorded data prohibition command.

[0094] The to-be-recorded data trigger command is used to trigger the step of generating to-be-recorded data and a write command corresponding to the to-be-recorded data according to an access request; and the to-be-recorded data prohibition command is used to prohibit the step of generating to-be-recorded data and a write command corresponding to the to-be-recorded data according to an access request.

[0095] According to the to-be-recorded data trigger command or the to-be-recorded data prohibition command, the write flow of the to-be-recorded data can be opened or closed based on demand, thereby being opened when there is a design demand and being closed when there is no demand.

[0096] In an optional example, the optional flowchart of generating the to-be-recorded data and the write command corresponding to the to-be-recorded data according to the embodiments of the present application shown in FIG. 5 can include the following steps:

[0097] Step S201: decoding the access address information of the access request.

[0098] When the access address information provided by the upstream device is a logical address, it needs to be converted into a physical address to perform memory access (i.e., decoding the access address information), and the address conversion process ensures that the upstream device can access the memory through the logical address. The logical address refers to the relative address generated when the program is compiled or assembled, and the physical address refers to the actual address of each storage unit in the memory, which is used to uniquely identify a specific location in the memory.

[0099] In an optional implementation, the address conversion can be completed by one or more address decoders. The address decoder can parse the logical address into various components of the physical address, such as a chip select address, a bank address, a row address, and a column address, etc. These components correspond to the physical organization of the memory, so as to ensure that the memory controller can accurately locate a specific location in the memory.

[0100] Among them, the chip select address is used to select a specific chip or module in the memory. The bank address is used to select a specific bank in the memory with multiple banks. The row address and the column address are used to locate a specific storage unit in the selected chip or bank.

[0101] It should be noted that the specific address conversion method and memory organization method can be different due to different memory architectures and standards. Therefore, in actual applications, the access address information can be decoded accordingly according to the actual situation, and the embodiments of the present application are not limited thereto.

[0102] Step S202: generating the to-be-recorded data based on the decoded access address information and the access data source information of the access request.

[0103] In an optional implementation, the decoded access address information can be, for example, a chip select address, a bank address, a row address, and a column address, etc.

[0104] The access data source information at least includes identification information of the device that sends the access request. In an optional implementation, the access data source information can further include priority of the access request and type of the access request. The identification information of the device that sends the access request can explicitly indicate which device sends the access request. In an optional implementation, the identification information can include a processor core identification number or an input / output device identification number. When the processor core identification number exists, the identification information can further include a thread identification number in the processor core.

[0105] The priority of the access request can represent importance or urgency of the access request. The request with high priority can be processed first, and the request with low priority needs to be queued and waited. For example, when multiple programs or processes send access requests at the same time, the memory controller can determine which request to process first according to the priorities of the requests.

[0106] The type of the access request refers to the operation type of the access request, for example, can be read access or write access.

[0107] The to-be-recorded data is generated according to the access request, and contains data information corresponding to the access request, for subsequent recording, tracking or analysis. The to-be-recorded data can be customized and combined according to the configuration of the software. The software administrator or developer can pre-set or configure the content and format of each item of data to generate to-be-recorded data that meets specific requirements.

[0108] In an optional example, a first schematic diagram of the to-be-recorded data provided by the embodiment of the application is shown in FIG. 6. As shown in FIG. 6, the to-be-recorded data can include row address, column address, bank address, chip select address, request type, processor core identification number (i.e., processor core ID in the figure), thread identification number in the processor core (i.e., thread ID in the figure) and priority.

[0109] In another optional example, a second schematic diagram of the to-be-recorded data provided by the embodiment of the application is shown in FIG. 7. As shown in FIG. 7, the to-be-recorded data can include row address, column address, bank address, request type, input / output device identification number (i.e., IO device number in the figure) and priority.

[0110] In an optional implementation, after the step of generating the to-be-recorded data and the write command corresponding to the to-be-recorded data according to the access request, before the step of writing the to-be-recorded data into the preset address range of the memory based on the write command corresponding to the to-be-recorded data, the method can further include: caching the to-be-recorded data into a write data cache.

[0111] Due to the delay of network transmission or internal data transmission, especially when processing a large amount of data or high concurrency requests, the generated to-be-recorded data is cached to the write data cache. Through the cache mechanism, the to-be-recorded data can be temporarily stored in the write data cache, and then sent at an appropriate time, thereby reducing the delay caused by waiting for transmission.

[0112] With reference back to FIG. 5, step S203 is performed: a write command corresponding to the to-be-recorded data is generated.

[0113] In an optional implementation, the access address of the write command can point to a preset address range, the preset address range being a preset region for storing the to-be-recorded data, and the preset address being provided with access permission to ensure that only authorized systems or processes can access it, thereby ensuring the security and integrity of the data.

[0114] In a specific example, the preset address range can be configured by software, for example, it can be {BasePhysical Addr, LimitPhysical Addr}. And the preset address is provided with access permission, for example, the preset address can not be open to unauthorized operating systems or application software, to ensure that only authorized systems or processes can access it, thereby ensuring the security and integrity of the data.

[0115] Wherein, BasePhysical Addr and LimitPhysical Addr are two parameters used to define the preset address range. The parameters allow software administrators or developers to flexibly configure and specify a specific physical memory region for storing to-be-recorded data. Specifically, BasePhysical Addr is the start address of the preset address range, used to specify the starting position of the memory region for storing to-be-recorded data. LimitPhysical Addr is the end address of the preset address range, used to specify the end position of the memory region for storing to-be-recorded data.

[0116] In an optional implementation, in order to ensure that the access addresses of all write commands point to the preset address range, and the access addresses of each write command do not conflict with each other, the access address of the write command can be set to increase by a preset value within the preset address range, for example, the access address of each write command increases by 64 bytes. By updating the access address of the write command by 64 bytes each time, it can be ensured that each write operation is performed within a fixed, predefined block size.

[0117] Meanwhile, the data amount of the to-be-recorded data can be controlled to be less than or equal to the preset value, for example, 64 bytes, so as to ensure that the to-be-recorded data does not cross multiple blocks, thereby avoiding the risk of address conflict and data confusion. In an optional implementation, if the data amount of the to-be-recorded data is less than the preset value, for example, 64 bytes, zero padding can be used to make the data amount of the to-be-recorded data equal to the preset value, so as to ensure that a complete block is used in each write operation.

[0118] When the access address of the write command reaches the upper limit of the preset address range, for example, LimitPhysical Addr, it means that the preset area for storing the to-be-recorded data is full. At this time, the generation of the write command should be stopped to ensure that the access address of the write command does not exceed the preset address range. In an optional implementation, after the step of stopping the generation of the write command, the step of stopping the generation of the to-be-recorded data can also be included to avoid data conflict or loss.

[0119] It should be noted that 64 bytes is only an example of the preset value, and the preset value can also be adjusted according to specific application scenarios and memory characteristics, and the embodiments of the present application are not limited thereto.

[0120] In an optional example, the step of writing the to-be-recorded data into the preset address range of the memory based on the write command corresponding to the to-be-recorded data can include: sending the write command to a command queue for arbitration, and if the write command is selected, writing the to-be-recorded data into the preset address range, so that the to-be-recorded data is recorded in the preset address range.

[0121] The command queue is used to cache the write command, temporarily store the write command, and wait for arbitration. The arbitration can be implemented by an arbitrator, which selects a target command from the command queue according to the priority of the write command and / or address access efficiency, and sends the command to the memory to perform the corresponding operation.

[0122] It can be understood that when the write command is selected by the arbitrator, it is the time to write the to-be-recorded data corresponding to the selected write command. The to-be-recorded data corresponding to the write command is written into the preset address range, so that the to-be-recorded data is recorded in the preset address range.

[0123] In a further example, the embodiments of the present application also provide a memory data analysis method, which performs data analysis on memory data based on to-be-recorded data, wherein the to-be-recorded data is written into a preset address range of the memory based on the memory access information recording method provided in the above scheme. In the memory data analysis, the memory data source provided in the above scheme is used as a data basis, which can intuitively reflect the data characteristics of each device interacting with the memory, thereby being more conducive to proposing feasible software and hardware optimization schemes based on corresponding data analysis.

[0124] In the following, the memory access information recording apparatus provided by the embodiments of the present application is introduced. The memory access information recording apparatus described below can be considered as a software functional module or a hardware functional module required to be set to implement the memory access information recording method provided by the embodiments of the present application. The content of the memory access information recording apparatus described below can be mutually correspondingly referred to the method content described above.

[0125] In an optional implementation, FIG. 8 exemplarily shows an optional structure schematic diagram of the memory access information recording apparatus provided by the embodiments of the present application, which is used to implement the memory access information recording method provided by the embodiments of the present application. As shown in FIG. 8, the memory access information recording apparatus 3 can include:

[0126] The obtaining module 30 is configured to obtain an access request, wherein the access request at least includes access address information and access data source information, and the access data source information at least includes identification information of a device sending the access request;

[0127] The generating module 31 is configured to generate to-be-recorded data and a write command corresponding to the to-be-recorded data according to the access request, wherein the to-be-recorded data includes the access address information and the access data source information of the access request;

[0128] The writing module 32 is configured to write the to-be-recorded data into a preset address range of the memory based on the write command corresponding to the to-be-recorded data; the preset address range is a preset region for storing the to-be-recorded data, and the preset address is provided with an access permission.

[0129] Optionally, before the generating module 31 is configured to generate the to-be-recorded data and the write command corresponding to the to-be-recorded data according to the access request, the generating module 31 can further include:

[0130] obtaining a to-be-recorded data trigger command, wherein the to-be-recorded data trigger command is used to trigger the step of generating the to-be-recorded data and the write command corresponding to the to-be-recorded data according to the access request;

[0131] Or,

[0132] An acquisition of a to-be-recorded data prohibition command, the to-be-recorded data prohibition command being used for prohibiting execution of the step of generating the to-be-recorded data and the write command corresponding to the to-be-recorded data according to the access request.

[0133] Optionally, the write module 32 is configured to write the to-be-recorded data into a preset address range of the memory based on the write command corresponding to the to-be-recorded data, and can include the following steps:

[0134] The write command is sent to a command queue for arbitration, and if the write command is selected, the to-be-recorded data is written into the preset address range, so that the to-be-recorded data is recorded in the preset address range.

[0135] Optionally, the generation module 31 is configured to generate the to-be-recorded data and the write command corresponding to the to-be-recorded data according to the access request, and specifically includes the following steps:

[0136] Decoding the access address information of the access request;

[0137] Generating the to-be-recorded data based on the decoded access address information and access data source information of the access request;

[0138] Generating the write command corresponding to the to-be-recorded data.

[0139] In an optional implementation, the optional structure of the generation module in the memory access information recording apparatus provided by the embodiment of the application is shown in FIG. 9. As shown in FIG. 9, the address decoder 311 in FIG. 9 can be used to decode the access address information, and then the to-be-recorded data generation module 312 can generate the to-be-recorded data based on the decoded access address information and access data source information of the access request. The write command generation module 313 in FIG. 9 can generate the write command corresponding to the to-be-recorded data, so that the to-be-recorded data can be written into a preset address range of the memory based on the write command corresponding to the to-be-recorded data.

[0140] The address decoder 311 can parse a logical address into various components such as a chip select address, a bank address, a row address, and a column address. These components correspond to the physical organization of the memory, so that the memory controller can accurately locate a specific position in the memory.

[0141] The chip select address is used to select a specific chip or module in the memory. The bank address is used to select a specific bank in the memory with multiple banks. The row address and the column address are used to locate a specific storage unit in the selected chip or bank.

[0142] It should be noted that the specific address conversion mode and memory organization mode can be different due to different memory architectures and standards. Therefore, in actual application, the access address information can be decoded according to the actual situation, and the embodiments of the application are not limited thereto.

[0143] Optionally, the access address of the write command is incremented by a preset value within a preset address range.

[0144] Optionally, if the access address of the write command reaches the upper limit of the preset address range, the generation of the write command is stopped.

[0145] Optionally, after the generation of the write command is stopped, the generation of the to-be-recorded data can also be stopped.

[0146] In an optional implementation, when the access address of the write command reaches the upper limit of the preset address range, the write command generation module 313 stops generating the write command and sends a signal to the to-be-recorded data generation module 312 to inform the to-be-recorded data generation module 312 to stop generating the to-be-recorded data according to the access request, so as to avoid data conflict or loss.

[0147] Optionally, the data amount of the to-be-recorded data is less than or equal to the preset value.

[0148] Optionally, when the data amount of the to-be-recorded data is less than the preset value, a zero padding method is used to make the data amount of the to-be-recorded data equal to the preset value.

[0149] Optionally, after the to-be-recorded data and the write command corresponding to the to-be-recorded data are generated according to the access request, before the to-be-recorded data is written into the preset address range of the memory based on the write command corresponding to the to-be-recorded data, the to-be-recorded data can also be cached into a write data cache.

[0150] Optionally, the identification information at least includes a processor core identification number, or an input / output device identification number; wherein, when the processor core identification number exists, the identification information can further include a thread identification number in the processor core.

[0151] Optionally, the access data source information can further include a priority of the access request and a type of the access request.

[0152] In an optional implementation, the memory access information recording apparatus provided by the embodiments of the application can be placed at different positions of a processor system to record the to-be-recorded data containing the data information corresponding to the access request. For example, it can be placed at an upstream of a multi-level cache, a bus or different observation points to record the to-be-recorded data.

[0153] The following takes the memory access information recording device placed inside the memory controller as an example for description. It can be understood that in actual application, the memory access information recording device can also be placed outside the memory controller to record the to-be-recorded data containing the data information corresponding to the access request. The embodiment of the present application does not limit the position of the memory access information recording device.

[0154] In an optional implementation, FIG. 10 exemplarily shows an optional structural schematic diagram of the memory controller provided by the embodiment of the present application, wherein the memory controller is provided with a memory access information recording device for implementing the memory access information recording method provided by the embodiment of the present application. As shown in FIG. 10, the memory controller 2 can include a command queue 21, an arbitrator 22, a write data cache module 23 and the memory access information recording device 3. In an optional implementation, the memory controller 2 can perform data interaction with the memory 4 by executing the access request sent by the bus 1. When the bus 1 sends the access request, the memory access write data corresponding to the access request is sent to the write data cache module 23 for caching, and is sent at an appropriate time to reduce the delay caused by waiting for transmission.

[0155] The command queue 21 is configured to store the access request sent by the upstream device of the memory controller 2 and the write command generated by the memory access information recording device 3.

[0156] The write data cache module 23 is configured to cache the memory access write data corresponding to the access request and the to-be-recorded data generated by the memory access information recording device 3. Caching the memory access write data corresponding to the access request and the to-be-recorded data generated by the memory access information recording device into the write data cache module 23 can improve the speed and efficiency of data access. When data needs to be written, the data is first written into the write data cache module 23. Then, at an appropriate time, the memory controller 2 takes out the data from the write data cache module 23 and writes it into the memory.

[0157] The arbitrator 22 is configured to select an access request or a write command in the command queue 21 as a target task. If the obtained target task is a write command, the to-be-recorded data corresponding to the write command is written into a preset address range, so that the to-be-recorded data is recorded in the preset address range. In an optional implementation, the selecting an access request or a write command in the command queue as a target task is specifically: selecting an access request or a write command as a target task from the to-be-executed access requests or write commands stored in the command queue according to the access priority and / or address access efficiency of the to-be-executed access requests or write commands.

[0158] In a specific implementation, after receiving the upstream transmitted access request, the memory controller 2 saves the access address information corresponding to the access request and the access priority information of the access request into the command queue 21. Meanwhile, the memory controller 2 sends the access request including the access address information and the access data source information to the memory access information recording device 3 to generate the to-be-recorded data and the write command corresponding to the to-be-recorded data, so that the to-be-recorded data can be written into the preset address range of the memory based on the write command corresponding to the to-be-recorded data, thereby realizing the recording of the memory data source.

[0159] Correspondingly, in the memory data analysis, the memory data source provided by the above scheme can be used as a data basis to intuitively reflect the data characteristics of each device interacting with the memory, thereby being more conducive to proposing a feasible software and hardware optimization scheme based on corresponding data analysis.

[0160] The access address information refers to the memory address specified by the upstream device when sending the access request, which needs to be accessed, so that the memory controller can realize data access to the requested memory region based on the access address information. The access data source information at least includes the identification information of the device issuing the access request. In an optional implementation, the access data source information can further include the priority of the access request and the type of the access request.

[0161] In an optional implementation, the identification information can include a processor core identification number or an input / output device identification number. When the processor core identification number exists, the identification information can further include a thread identification number in the processor core.

[0162] In an optional implementation, when the recording of the to-be-recorded data is completed, the function of the memory access information recording device 3 can be closed through a control register. The to-be-recorded data stored in the memory 4 and containing each item of data corresponding to the access request can be obtained by reading the data in the specified address range of the memory 4.

[0163] As can be seen, the memory controller provided by the embodiment of the present application and provided with the memory access information recording device for implementing the memory access information recording method provided by the embodiment of the present application generates the to-be-recorded data and the write command corresponding to the to-be-recorded data to write the to-be-recorded data into the preset address range of the memory, thereby realizing the recording of the memory data source.

[0164] Correspondingly, in the memory data analysis, the memory data source provided by the above scheme can be used as a data basis to intuitively reflect the data characteristics of each device interacting with the memory, thereby being more conducive to proposing a feasible software and hardware optimization scheme based on corresponding data analysis.

[0165] The embodiment of the present application further provides an electronic device, which can comprise the memory controller as described above.

[0166] The embodiment of the present application further provides a storage medium, which stores one or more computer executable instructions, and the one or more computer executable instructions, when executed, implement the memory access information recording method as described above, or implement the memory data analysis method as described above.

[0167] The embodiment of the present application further provides a computer program product, which can comprise one or more computer executable instructions, and the one or more computer executable instructions, when executed, implement the memory access information recording method as described above, or implement the memory data analysis method as described above.

[0168] The above describes the multiple embodiment schemes provided by the embodiment of the present application, and each optional mode introduced by each embodiment scheme can be combined, cross-referenced in the case of no conflict, thereby extending multiple possible embodiment schemes, which can be considered as the embodiment schemes disclosed and published by the embodiment of the present application.

[0169] Although the embodiment of the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, and therefore the protection scope of the present application should be subject to the range defined by the claims.

Claims

1. A memory access information recording method characterized by comprising: The method comprises the following steps: acquiring an access request, the access request comprising at least access address information and access data source information, the access data source information comprising at least identification information of a device sending the access request; generating, according to the access request, to-be-recorded data and a write command corresponding to the to-be-recorded data, the to-be-recorded data comprising the access address information and the access data source information of the access request; writing, based on the write command corresponding to the to-be-recorded data, the to-be-recorded data into a preset address range of a memory; the preset address range is a preset region for storing the to-be-recorded data, and the preset address is provided with an access permission.

2. The memory access information recording method of claim 1, wherein, Before the step of generating, according to the access request, to-be-recorded data and a write command corresponding to the to-be-recorded data, the method further comprises the following steps: acquiring a to-be-recorded data trigger command, the to-be-recorded data trigger command being used to trigger the execution of the step of generating, according to the access request, to-be-recorded data and a write command corresponding to the to-be-recorded data; or acquiring a to-be-recorded data prohibition command, the to-be-recorded data prohibition command being used to prohibit the execution of the step of generating, according to the access request, to-be-recorded data and a write command corresponding to the to-be-recorded data. The step of writing, based on the write command corresponding to the to-be-recorded data, the to-be-recorded data into a preset address range of a memory comprises the following steps:

3. The memory access information recording method according to claim 1 or 2, characterized by, sending the write command to a command queue for arbitration, and if the write command is selected, writing the to-be-recorded data into the preset address range, so that the to-be-recorded data is recorded in the preset address range. The step of generating, according to the access request, to-be-recorded data and a write command corresponding to the to-be-recorded data specifically comprises the following steps:

4. The memory access information recording method according to any one of claims 1 to 3, characterized by, decoding the access address information of the access request; generating to-be-recorded data based on the decoded access address information and the access data source information of the access request; generating a write command corresponding to the to-be-recorded data. In the step of generating, according to the access request, to-be-recorded data and a write command corresponding to the to-be-recorded data, the access address of the write command is incremented by a preset value within the preset address range.

5. The memory access information recording method according to any one of claims 1 to 4, characterized by, The step of generating, according to the access request, to-be-recorded data and a write command corresponding to the to-be-recorded data further comprises the following step:

6. The memory access information recording method of claim 5, wherein, if the access address of the write command reaches an upper limit of the preset address range, stopping the generation of the write command. After the step of stopping the generation of the write command, the method further comprises the following step:

7. The memory access information recording method of claim 6, wherein, stopping the generation of the to-be-recorded data. In the step of writing, based on the write command corresponding to the to-be-recorded data, the to-be-recorded data into a preset address range of a memory, the data amount of the to-be-recorded data is less than or equal to the preset value.

8. The memory access information recording method of claim 5, wherein, When the data amount of the to-be-recorded data is less than the preset value, a zero-filling method is adopted to make the data amount of the to-be-recorded data equal to the preset value.

9. The memory access information recording method of claim 8, wherein, After the step of generating, according to the access request, to-be-recorded data and a write command corresponding to the to-be-recorded data, and before the step of writing, based on the write command corresponding to the to-be-recorded data, the to-be-recorded data into a preset address range of a memory, the method further comprises the following steps:

10. The memory access information recording method according to any one of claims 1 to 9, characterized by, ​ buffer the to-be-recorded data into a write data buffer.

11. The memory access information recording method according to any one of claims 1 to 10, characterized by, The identification information at least includes a processor core identification number or an input / output device identification number; and when the processor core identification number exists, the identification information further includes a thread identification number in the processor core.

12. The memory access information recording method according to any one of claims 1 to 11, characterized by, The access data source information further includes a priority of the access request and a type of the access request.

13. A method of analyzing memory data, the method comprising: The method comprises: Based on the to-be-recorded data, performing data analysis on the memory data, wherein the to-be-recorded data is written into a preset address range of the memory based on the memory access information recording method in any one of claims 1-12.

14. A memory access information recording apparatus, characterized by comprising: The method comprises: An acquisition module is configured to acquire an access request, the access request at least including access address information and access data source information, the access data source information at least including identification information of a device sending the access request; A generation module is configured to generate, according to the access request, to-be-recorded data and a write command corresponding to the to-be-recorded data, the to-be-recorded data including the access address information and the access data source information of the access request; A write module is configured to write the to-be-recorded data into a preset address range of the memory based on the write command corresponding to the to-be-recorded data; the preset address range is a preset region for storing the to-be-recorded data, and the preset address is provided with an access permission.

15. A memory controller, comprising: The memory access information recording device of claim 14 is included.

16. The memory controller of claim 15, wherein, The method further comprises: A command queue is configured to store an access request sent by an upstream device of a memory controller and a write command generated by the memory access information recording device of claim 14; A write data buffer module is configured to buffer memory access write data corresponding to the access request and the to-be-recorded data generated by the memory access information recording device of claim 14; An arbiter is configured to select an access request or a write command in the command queue as a target task; wherein, if the target task acquired is a write command, the to-be-recorded data corresponding to the write command is written into the preset address range, so that the to-be-recorded data is recorded in the preset address range.

17. The memory controller of claim 16, wherein, The selecting an access request or a write command in the command queue as a target task specifically comprises: According to an access priority and / or an address access efficiency of an access request or a write command to be executed, selecting an access request or a write command from the access requests or write commands to be executed stored in the command queue as a target task.

18. An electronic device, comprising: The memory controller of any one of claims 15-17 is included.

19. A storage medium, characterized by The storage medium stores one or more computer executable instructions, which are executed to implement the memory access information recording method of any one of claims 1-12 or the memory data analysis method of claim 13.

20. A computer program product, characterised in that, The storage medium stores one or more computer executable instructions, which are executed to implement the memory access information recording method of any one of claims 1-12 or the memory data analysis method of claim 13.

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