Semiconductor device and method for producing semiconductor device

Abstract

Provided is a semiconductor device that has high field-effect mobility. This semiconductor device includes: a transistor having an oxide semiconductor layer; an insulating layer; and an oxide layer. In the insulating layer, the widths of mutually opposing first and second lateral surfaces are less than the widths of mutually opposing third and fourth lateral surfaces. Also, the heights of the first and second lateral surfaces are greater than the widths of the first and second lateral surfaces, respectively. A source electrode and a drain electrode are provided along the first and second lateral surfaces, respectively. The oxide layer is located on the insulating layer. The oxide semiconductor layer covers the source electrode, the drain electrode, the insulating layer, and the oxide layer. A gate insulating layer is provided so as to cover the oxide semiconductor layer in a cross-sectional view in a channel width direction. A gate electrode is provided on the gate insulating layer. In the oxide semiconductor layer, the crystal orientations of crystal grains are aligned or substantially aligned with each other in any of a region in contact with the third lateral surface, a region in contact with the fourth lateral surface, and a region in contact with the upper surface of the oxide layer.

Description

Semiconductor device and method for manufacturing the same

[0001] One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device each including an oxide semiconductor layer. Another embodiment of the present invention relates to a method for manufacturing the semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic units, and memory devices are all embodiments of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0004] In recent years, semiconductor devices have been developed, and semiconductor devices mainly use LSIs (Large Scale Integration), CPUs (Central Processing Units), memories, etc. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] 2. Description of the Related Art Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components of various electronic devices.

[0006] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0007] Furthermore, it is known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor having a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor having a small leakage current.

[0008] Examples of oxide semiconductors that can be used for the active layer of a transistor include indium oxide, indium gallium zinc oxide, etc. Non-Patent Document 1 discloses a thin-film transistor that uses hydrogenated polycrystalline indium oxide formed by low-temperature solid-phase crystallization for the active layer.

[0009] JP 2012-257187 A JP 2011-151383 A

[0010] Y. Magari et al., "High-mobility hydrogenated polycrystalline InO(InO:H) thin-film transistors", Nature Communications, 13, 1078 (2022) Takashi Koida, "High-mobility transparent conductive film", National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0011] An object of one embodiment of the present invention is to provide a semiconductor device with high field-effect mobility. Another object of one embodiment of the present invention is to provide a semiconductor device with high operating speed. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device which can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with little variation in electrical characteristics of transistors. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device.

[0012] Another object of one embodiment of the present invention is to provide a memory device that can be miniaturized or highly integrated.Another object of one embodiment of the present invention is to provide a memory device with a large storage capacity.Another object of one embodiment of the present invention is to provide a memory device with high operation speed.Another object of one embodiment of the present invention is to provide a memory device with low power consumption.Another object of one embodiment of the present invention is to provide a novel memory device.

[0013] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

[0014] One embodiment of the present invention includes a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, an oxide layer, and an oxide semiconductor layer. The oxide semiconductor layer has a channel formation region. The first conductive layer has a region in contact with a first side surface of the first insulating layer. The second conductive layer has a region in contact with a second side surface of the first insulating layer. The second side surface faces the first side surface. The oxide layer is located over the first insulating layer, the first conductive layer, and the second conductive layer. The oxide semiconductor layer covers the first conductive layer, the second conductive layer, the first insulating layer, and the oxide layer. a third conductive layer provided on the oxide semiconductor layer, the third conductive layer provided to cover the oxide semiconductor layer via the second insulating layer in a cross-sectional view in the channel width direction, the height of the first insulating layer being greater than the width of the first insulating layer in a cross-sectional view in the channel width direction, the oxide semiconductor layer containing indium and having crystals with a cubic crystal structure, the oxide semiconductor layer having a first region in contact with a third side surface of the first insulating layer, a second region in contact with a fourth side surface of the first insulating layer, and a third region in contact with an upper surface of the oxide layer, the fourth side surface facing the third side surface.

[0015] Alternatively, in the above aspect, the first insulating layer may be hexahedral.

[0016] Alternatively, in the above aspect, the crystal orientation of the crystal grains in the first region, the crystal orientation of the crystal grains in the second region, and the crystal orientation of the crystal grains in the third region may be identical or approximately identical to each other.

[0017] Alternatively, in the above embodiment, the oxide semiconductor layer may be located over a substrate, and the crystal orientations of the crystal grains in the first region, the second region, and the third region may be <111> with respect to a direction perpendicular or approximately perpendicular to a surface of the substrate.

[0018] Alternatively, in the above aspect, the first conductive layer, the second conductive layer, and the first insulating layer may be located on a substrate, and the height of the first conductive layer from the surface of the substrate and the height of the second conductive layer from the surface of the substrate may each be equal to or less than the height of the first insulating layer from the surface of the substrate.

[0019] Alternatively, in the above aspect, the top surface of the first conductive layer, the top surface of the second conductive layer, and the top surface of the first insulating layer may coincide or approximately coincide with one another.

[0020] Alternatively, in the above aspect, the semiconductor device may have a fourth conductive layer, a fifth conductive layer, and a third insulating layer, the first conductive layer having a region in contact with an upper surface of the fourth conductive layer, the second conductive layer having a region in contact with an upper surface of the fifth conductive layer, the third insulating layer having a region in contact with a side surface of the first conductive layer, a region in contact with a side surface of the second conductive layer, a region in contact with an upper surface of the fourth conductive layer, and a region in contact with an upper surface of the fifth conductive layer, and the first insulating layer may be provided on the third insulating layer.

[0021] Alternatively, one embodiment of the present invention includes a first step of forming an insulating film, a second step of forming a first opening and a second opening in the insulating film, a third step of forming a first conductive layer inside the first opening and a second conductive layer inside the second opening, a fourth step of forming an oxide layer so as to be in contact with a top surface of the first conductive layer, a top surface of the second conductive layer, and a top surface of the insulating film in a region between the first conductive layer and the second conductive layer, and a fourth step of forming the first insulating layer by removing a region of the insulating film that does not overlap with the oxide layer. a fifth step of forming an oxide semiconductor layer so as to cover the first conductive layer, the second conductive layer, the first insulating layer, and the oxide layer; a seventh step of forming a second insulating layer over the oxide semiconductor layer; an eighth step of forming a third opening in the second insulating layer so as to reach the oxide semiconductor layer; a ninth step of forming a third insulating layer so as to cover the inside of the third opening; and a tenth step of forming a third conductive layer over the third insulating layer so as to fill the third opening.

[0022] Alternatively, in the above aspect, before the first step, an eleventh step of forming a fourth conductive layer and a fifth conductive layer and a twelfth step of forming a fourth insulating layer on the fourth conductive layer and the fifth conductive layer may be performed, and in the first step, an insulating film may be formed on the fourth insulating layer, and in the second step, a first opening reaching the fourth conductive layer and a second opening reaching the fifth conductive layer may be formed in the fourth insulating layer.

[0023] Alternatively, in the above embodiment, in the sixth step, the oxide semiconductor layer may be formed to have a region in contact with the top surface of the fourth insulating layer.

[0024] Alternatively, in the above embodiment, in the sixth step, the oxide semiconductor layer may be formed to contain indium and have crystals with a cubic crystal structure.

[0025] According to one embodiment of the present invention, a semiconductor device with high field-effect mobility can be provided. According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device which can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with little variation in electrical characteristics of transistors can be provided. According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a method for manufacturing a novel semiconductor device can be provided.

[0026] According to one embodiment of the present invention, a memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a memory device with a large storage capacity can be provided. According to one embodiment of the present invention, a memory device with a high operating speed can be provided. According to one embodiment of the present invention, a memory device with low power consumption can be provided. According to one embodiment of the present invention, a novel memory device can be provided.

[0027] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0028] FIG. 1A is a plan view showing a structural example of a semiconductor device. FIGS. 1B, 1C, and 1D are cross-sectional views showing a structural example of a semiconductor device. FIG. 1E is a perspective view showing a structural example of a semiconductor device. FIGS. 2A and 2B are perspective views showing a structural example of a semiconductor device. FIG. 3 is a perspective view showing a structural example of a semiconductor device. FIGS. 4A and 4B are cross-sectional views showing a structural example of a semiconductor device. FIG. 4C is a perspective view showing a structural example of a semiconductor device. FIG. 5A is a plan view showing a structural example of a semiconductor device. FIGS. 5B, 5C, and 5D are cross-sectional views showing a structural example of a semiconductor device. FIG. 5E is a perspective view showing a structural example of a semiconductor device. FIG. 6 is a cross-sectional view showing a structural example of a semiconductor device. FIGS. 7A and 7B are cross-sectional views showing a structural example of a semiconductor device. FIG. 8A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 8B, 8C, and 8D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 8E is a perspective view showing an example of a method for manufacturing a semiconductor device. FIG. 9A is a plan view showing an example of a method for manufacturing a semiconductor device. FIGS. 9B, 9C, and 9D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. FIG. 9E is a perspective view illustrating an example of a method for manufacturing a semiconductor device. FIG. 10A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 10B, 10C, and 10D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 10E is a perspective view illustrating an example of a method for manufacturing a semiconductor device. FIG. 11A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 11B, 11C, and 11D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 11E is a perspective view illustrating an example of a method for manufacturing a semiconductor device. FIG. 12A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 12B, 12C, and 12D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 12E is a perspective view illustrating an example of a method for manufacturing a semiconductor device. FIG. 13A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 13B, 13C, and 13D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 13E is a perspective view illustrating an example of a method for manufacturing a semiconductor device. FIG. 14A is a plan view illustrating an example of a method for manufacturing a semiconductor device. 14B, 14C, and 14D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device, and Fig. 14E is a perspective view illustrating an example of a method for manufacturing a semiconductor device.FIG. 15A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 15B, 15C, and 15D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 15E is a perspective view illustrating an example of a method for manufacturing a semiconductor device. FIG. 16A is a plan view illustrating an example of a method for manufacturing a semiconductor device. FIGS. 16B, 16C, and 16D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. FIG. 16E is a perspective view illustrating an example of a method for manufacturing a semiconductor device. FIG. 17 is a cross-sectional view illustrating a structural example of a semiconductor device. FIG. 18 is a cross-sectional view illustrating a structural example of a semiconductor device. FIG. 19 is a cross-sectional view illustrating a structural example of a memory device. FIGS. 20A and 20B are diagrams illustrating carrier concentration dependence of Hall mobility. FIG. 20C is a cross-sectional view illustrating an indium oxide film. FIG. 21A is an equivalent circuit diagram of a logic circuit. FIG. 21B is a diagram illustrating a circuit symbol of the logic circuit. FIG. 21C is a timing chart illustrating the operation of the logic circuit. FIGS. 22A and 22D are equivalent circuit diagrams of the logic circuit. FIGS. 22B, 22C, 22E, and 22F are diagrams illustrating circuit symbols of logic circuits. FIG. 23A is a diagram illustrating the circuit symbol of a buffer circuit. FIG. 23B is a diagram illustrating a configuration example of a buffer circuit. FIG. 23C is a timing chart illustrating the operation of the buffer circuit. FIG. 23D is a diagram illustrating a configuration example of a ring oscillator. FIG. 23E is a diagram illustrating oscillation of the ring oscillator. FIG. 24A is an equivalent circuit diagram of a DFF circuit. FIG. 24B is a diagram illustrating the circuit symbol of a DFF circuit. FIG. 25A is a diagram illustrating a configuration example of a shift register circuit. FIG. 25B is a timing chart illustrating the operation of the shift register circuit. FIGS. 26A and 26B are diagrams illustrating configuration examples of a selector. FIG. 26C is a diagram illustrating a configuration example of an analog switch. FIG. 27A is a circuit diagram illustrating a configuration example of a logic circuit including a semiconductor device of one embodiment of the present invention, and FIG. 27B is a timing chart. FIGS. 28A and 28B are circuit diagrams illustrating a configuration example of a logic circuit including a semiconductor device of one embodiment of the present invention. Fig. 29 is a block diagram showing a configuration example of a semiconductor device. Fig. 30A, Fig. 30B, Fig. 30C, Fig. 30D, Fig. 30E, Fig. 30F, Fig. 30G, and Fig. 30H are diagrams showing circuit configuration examples of memory cells.Fig. 31A and Fig. 31B are diagrams showing an example of an electronic component. Fig. 32A, Fig. 32B, and Fig. 32C are diagrams showing an example of a mainframe computer. Fig. 32D is a diagram showing an example of space equipment. Fig. 32E is a diagram showing an example of a storage system applicable to a data center.

[0029] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0030] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0031] Furthermore, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0032] In order to make the invention easier to understand, particularly in plan views or perspective views, some components may be omitted from the drawings, and some hidden lines may be omitted.

[0033] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes, stacking order, or arrangement order. Furthermore, even if a term is not accompanied by an ordinal number in this specification, ordinal numbers may be accompanied in the claims to avoid confusion between components. Furthermore, even if a term is accompanied by an ordinal number in this specification, ordinal numbers may be accompanied by a different ordinal number in the claims. Furthermore, even if a term is accompanied by an ordinal number in this specification, ordinal numbers may be omitted in the claims.

[0034] It should be noted that the terms "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0035] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0036] In this specification and the like, the opening also includes, for example, a groove, a slit, and the like.

[0037] Although the drawings used in this embodiment mode show the case where the side surface of the opening of the insulating layer is perpendicular or approximately perpendicular to the substrate surface or the surface where the insulating layer is formed, the side surface may have a tapered shape.

[0038] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface on which the structure is to be formed. For example, it is preferable to have a region in which the angle between the inclined side surface and the substrate surface or the surface on which the structure is to be formed (hereinafter, sometimes referred to as the taper angle) is less than 90°. The side surface of the structure and the substrate surface do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0039] In this specification, "having the same or approximately the same height" refers to a configuration in which the heights from a reference plane (e.g., a flat surface such as a substrate surface) are equal in cross-sectional view. For example, in a manufacturing process of a memory device, a planarization process (typically a process using chemical mechanical polishing (CMP)) may expose the surface of a single layer or multiple layers. In this case, the surfaces processed by the CMP process have a configuration in which the heights from the reference plane are equal. However, the heights of multiple layers may differ depending on the processing equipment, processing method, or material of the processed surface during the CMP process. In this specification, this case is also treated as "having the same or approximately the same height." For example, in the case of a structure having two layers (here, a first layer and a second layer) with different heights relative to the reference plane, the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less is also referred to as "having the same or approximately the same height."

[0040] In this specification, "side edges that coincide or approximately coincide" means that, in a plan view, at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the term "side edges that coincide or approximately coincide" is also used.

[0041] In this specification, the phrase "the planar shapes are identical or approximately identical" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be disposed inside the lower layer, or the upper layer may be disposed outside the lower layer. In these cases, the phrase "the planar shapes are identical or approximately identical" may also be used. Furthermore, when the planar shapes are identical or approximately identical, it can also be said that the edges are aligned or approximately aligned, or that the side edges are aligned or approximately aligned.

[0042] In this specification and the like, a cubic crystal structure may be referred to as a cubic crystal, a cubic crystal structure, etc. The same applies to other crystal systems (hexagonal, trigonal, tetragonal, orthorhombic, monoclinic, and triclinic).

[0043] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements. Note that A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0044] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0045] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0046] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0047] Embodiment 1 In this embodiment, a semiconductor device including an oxide semiconductor layer and a method for manufacturing the semiconductor device will be described with reference to drawings.

[0048] One embodiment of the present invention is a semiconductor device including a transistor having an oxide semiconductor layer, an insulating layer covered with the oxide semiconductor layer, and an oxide layer. The insulating layer may be hexahedral and have a first side surface, a second side surface, a third side surface, and a fourth side surface. The second side surface faces the first side surface, and the fourth side surface faces the third side surface. The third side surface shares one side with each of the first side surface and the second side surface. Similarly, the fourth side surface shares one side with each of the first side surface and the second side surface.

[0049] The length (width) of the first side surface in a direction parallel to the surface on which the insulating layer is formed is smaller than the widths of the third side surface and the fourth side surface. Similarly, the width of the second side surface is smaller than the widths of the third side surface and the fourth side surface. Furthermore, the length (height) of the insulating layer in a direction perpendicular to the surface on which the insulating layer is formed is greater than the widths of the first side surface and the second side surface.

[0050] The source electrode of the transistor is provided along a first side surface of the insulating layer and has, for example, a region in contact with the first side surface, and the drain electrode of the transistor is provided along a second side surface of the insulating layer and has, for example, a region in contact with the second side surface.

[0051] The height of the source electrode of the transistor is greater than the width of the source electrode. Similarly, the height of the drain electrode of the transistor is greater than the width of the drain electrode. The source electrode and the drain electrode of the transistor may be cylindrical, for example. In this case, the diameter may be the width of the source electrode and the width of the drain electrode of the transistor.

[0052] The oxide layer is located over the insulating layer, the source electrode of the transistor, and the drain electrode of the transistor. The oxide semiconductor layer is provided so as to cover the source electrode, the drain electrode, the insulating layer, and the oxide layer. The oxide layer and the oxide semiconductor layer contain, for example, indium. For example, indium oxide can be used as the oxide semiconductor layer. By using indium oxide as the oxide semiconductor layer, a transistor with high on-state current, a transistor with high field-effect mobility, and a transistor with high frequency characteristics (also referred to as f characteristics) can be realized. Here, when indium oxide is used as the oxide semiconductor layer, the indium oxide can have a crystal structure with a cubic crystal structure.

[0053] In a cross-sectional view of the transistor in the channel width direction, a side surface of the oxide layer coincides or substantially coincides with a side surface of the insulating layer. In addition, in a cross-sectional view of the transistor in the channel width direction, the oxide semiconductor layer has a first region in contact with the third side surface of the insulating layer, a second region in contact with the fourth side surface, and a third region in contact with the top surface of the oxide layer. Here, in a cross-sectional view of the transistor in the channel width direction, the height of the insulating layer is greater than its width (corresponding to the widths of the first and second side surfaces).

[0054] The oxide layer functions as a seed or a nucleus when treatment for increasing the crystallinity of the oxide semiconductor layer is performed. By providing the oxide layer in the semiconductor device of one embodiment of the present invention, the oxide semiconductor layer can be formed so that the crystal orientations of the crystal grains in the first region, the second region, and the third region of the oxide semiconductor layer are aligned or substantially aligned with each other.

[0055] A gate insulating layer of the transistor is provided to cover the oxide semiconductor layer in a cross-sectional view in the channel width direction. A gate electrode of the transistor is provided on the gate insulating layer. The gate electrode of the transistor is provided to cover the oxide semiconductor layer via the gate insulating layer in a cross-sectional view in the channel width direction. The gate electrode of the transistor has a region overlapping with a top surface of the insulating layer with the gate insulating layer and the oxide semiconductor layer therebetween, and also has a region facing a third side surface of the insulating layer and a region facing a fourth side surface of the insulating layer with the gate insulating layer and the oxide semiconductor layer therebetween in a cross-sectional view in the channel width direction.

[0056] As described above, in the semiconductor device of one embodiment of the present invention, not only the region over the insulating layer in the oxide semiconductor layer but also the region facing the first region and the region facing the second region function as a channel formation region of the transistor. Therefore, compared to a case where the insulating layer is not provided, the channel width of the transistor is increased by the region facing the first region and the region facing the second region in the oxide semiconductor layer. In particular, the channel width of the transistor can be increased as the height of the insulating layer is greater than the width in a cross-sectional view of the transistor in the channel width direction. As described above, a transistor with high on-state current, high field-effect mobility, and high frequency characteristics can be realized.

[0057] <Configuration Example 1 of Semiconductor Device> FIGS. 1A to 4C are diagrams showing configuration examples of a semiconductor device having a transistor 10 on a substrate (not shown).

[0058] 1A is a plan view of the semiconductor device. Note that some elements are omitted in FIG. 1A for clarity. Some elements may also be omitted in the subsequent plan views.

[0059] Figure 1B is a cross-sectional view of the portion indicated by dashed-dotted line A-B in Figure 1A, and is also a cross-sectional view of the transistor 10 in the channel length direction. Figure 1C is a cross-sectional view of the portion indicated by dashed-dotted line C-D in Figure 1A, and is also a cross-sectional view of the transistor 10 in the channel width direction. Figure 1D is a cross-sectional view of the portion indicated by dashed-dotted line E-F in Figure 1A, and is also a cross-sectional view of the transistor 10 in the channel width direction. Here, dashed-dotted line A-B is perpendicular to dashed-dotted line C-D and dashed-dotted line E-F. In addition, dashed-dotted line C-D and dashed-dotted line E-F are parallel to each other.

[0060] In this specification and the like, a cross section in the channel width direction does not necessarily include the channel formation region of the transistor. The cross section in the channel width direction may also include a cross section parallel to the cross section in the channel width direction including the channel formation region. For example, the cross section of the portion indicated by the dashed dotted line E-F in FIG. 1D can be considered a cross section in the channel width direction, although it does not include the channel formation region of the transistor 10.

[0061] 1E to 3 are perspective views of the semiconductor device. FIG. 2A is a view in which some elements are omitted from FIG. 1E. FIG. 2B is a view in which some elements are further omitted from FIG. 2A. FIG. 3 is a view in which some elements are omitted from FIG. 1E, showing a channel formation region 21C of the transistor 10. Note that some elements are shown transparently in FIGS. 1E to 2B. In the subsequent perspective views, some elements may also be shown transparently.

[0062] Fig. 4A is an enlarged view of Fig. 1B. Fig. 4A includes an example of a cross-sectional configuration of the transistor 10 in the channel length direction. Fig. 4B is an enlarged view of some elements shown in Fig. 1C. Fig. 4C is a view in which some elements are further omitted from Fig. 2B.

[0063] A semiconductor device of one embodiment of the present invention includes an insulating layer 11 over a substrate (not shown), conductive layers 24a, 24b, and 43 over the insulating layer 11, an insulating layer 44 over the conductive layer 24a, the conductive layer 24b, and the insulating layer 43, a conductive layer 25a having a region in contact with a top surface of the conductive layer 24a, a conductive layer 25b having a region in contact with a top surface of the conductive layer 24b, and an insulating layer 41 over the insulating layer 44. Here, the insulating layer 41 is provided between the conductive layer 25a and the conductive layer 25b.

[0064] The semiconductor device of one embodiment of the present invention also includes an oxide layer 21S over the insulating layer 41, the conductive layer 25a, and the conductive layer 25b, an oxide semiconductor layer 21 over the oxide layer 21S, the conductive layer 25a, the conductive layer 25b, and the insulating layer 44, an insulating layer 22 over the oxide semiconductor layer 21, and a conductive layer 23 over the insulating layer 22.

[0065] Furthermore, the semiconductor device of one embodiment of the present invention includes an insulating layer 42 over the oxide semiconductor layer 21 and the insulating layer 44. An opening 20 is provided in the insulating layer 42. The side surface of the insulating layer 42 functions as a sidewall of the opening 20. The insulating layer 22 and the conductive layer 23 are provided inside the opening 20 so as to have a region overlapping with the oxide semiconductor layer 21. The opening 20 reaches the oxide semiconductor layer 21 and the insulating layer 44, and the insulating layer 22 is in contact with the oxide semiconductor layer 21, the insulating layer 42, and the insulating layer 44 inside the opening 20. The top surface of the conductive layer 23 is provided so as to be flush or substantially flush with the uppermost part of the insulating layer 22 and the top surface of the insulating layer 42. Note that the sidewall of the opening 20 may be perpendicular or substantially perpendicular to the top surface of the oxide semiconductor layer 21 or may have a tapered shape. The tapered sidewall improves coverage with the insulating layer 22 and the like and reduces defects such as voids.

[0066] In this specification and the like, the sidewall of an opening refers to the side surface within the opening of the layer in which the opening is formed.

[0067] Fig. 1E shows the insulating layer 42 in a see-through manner. Fig. 2A shows the oxide semiconductor layer 21 from Fig. 1E in a see-through manner, and the insulating layer 44 in a see-through manner. Fig. 2B shows the conductive layer 23 and the insulating layer 22 from Fig. 2A in a see-through manner. Fig. 3 shows the conductive layer 23, the insulating layer 22, and the insulating layer 42 from Fig. 1E in a see-through manner.

[0068] The insulating layer 11, the insulating layer 43, and the insulating layer 42 function as interlayer insulating layers. Note that the insulating layer 44 may also function as an interlayer insulating layer.

[0069] 3, the oxide semiconductor layer 21 has a channel formation region 21C. The conductive layer 23 has a region that functions as a gate electrode of the transistor 10. The insulating layer 22 has a region that functions as a gate insulating layer of the transistor 10. A region of the oxide semiconductor layer 21 that overlaps with the conductive layer 23 can be defined as the channel formation region 21C.

[0070] The conductive layer 25a has a region functioning as one of the source electrode and drain electrode of the transistor 10. The conductive layer 24a functions as a wiring connected to the conductive layer 25a. The conductive layer 25b has a region functioning as the other of the source electrode and drain electrode of the transistor 10. The conductive layer 24b functions as a wiring connected to the conductive layer 25b. Note that at least a part of the conductive layer 24a may function as one of the source electrode and drain electrode of the transistor 10. Furthermore, at least a part of the conductive layer 24b may function as the other of the source electrode and drain electrode of the transistor 10.

[0071] The upper surface of the insulating layer 43 coincides or substantially coincides with the upper surface of the conductive layer 24a and the upper surface of the conductive layer 24b, thereby allowing the insulating layer 44 to be provided on a flat surface.

[0072] The insulating layer 44 has an opening 28a that reaches the conductive layer 24a and an opening 28b that reaches the conductive layer 24b. The conductive layer 25a has a region located inside the opening 28a. Similarly, the conductive layer 25b has a region located inside the opening 28b. The side surface of the insulating layer 44 at the opening 28a can contact the side surface of the conductive layer 25a. Similarly, the side surface of the insulating layer 44 at the opening 28b can contact the side surface of the conductive layer 25b. Furthermore, the insulating layer 44 can have a region that contacts the top surface of the conductive layer 24a, a region that contacts the top surface of the conductive layer 24b, and a region that contacts the top surface of the insulating layer 43.

[0073] In FIG. 4B , insulating layer 11, insulating layer 43, insulating layer 22, and conductive layer 23 are omitted. FIG. 4C shows insulating layer 11, insulating layer 43, insulating layer 44, insulating layer 41, conductive layer 24a, and conductive layer 24b. As shown in FIG. 4C , insulating layer 41 may be a hexahedron. In this case, insulating layer 41 has side surfaces 31a, 31b, 31c, and 31d, as shown in FIGS. 1B to 1D and 4A to 4C . Side surface 31b faces side surface 31a. Side surface 31d faces side surface 31c. Side surface 31c shares one side with side surface 31a and side surface 31b, respectively. Similarly, side surface 31d shares one side with side surface 31a and side surface 31b, respectively.

[0074] In FIGS. 4A to 4C , the distance between the side surface 31a and the side surface 31b is referred to as width Ww1. The distance between the side surface 31c and the side surface 31d is referred to as width Ww2. Width Ww1 may be the width of the side surface 31c and the width of the side surface 31d, and may be the width of the insulating layer 41 in a cross-sectional view of the transistor 10 in the channel length direction. Width Ww2 may be the width of the side surface 31a and the width of the side surface 31b, and may be the width of the insulating layer 41 in a cross-sectional view of the transistor 10 in the channel width direction. In FIGS. 4A to 4C , the height of the insulating layer 41 is referred to as height Hw. Height Hw may be the difference between the height of the upper surface of the insulating layer 41 from a reference plane and the height of the lower surface of the insulating layer 41 from the reference plane. The reference plane may be the surface of the substrate, the upper surface of the insulating layer 11, the upper surface of the insulating layer 43, or the upper surface of the insulating layer 44.

[0075] The width Ww2 is smaller than the width Ww1. The height Hw is at least greater than the width Ww2. That is, in a cross-sectional view of the transistor 10 in the channel width direction, the height of the insulating layer 41 is greater than the width of the insulating layer 41. The width Ww1 may be greater than or equal to the height Hw. Here, the value obtained by dividing the height Hw by the width Ww2 is referred to as the aspect ratio of the insulating layer 41 in a cross-sectional view of the transistor 10 in the channel width direction. The aspect ratio of the insulating layer 41 is preferably as large as possible without causing the insulating layer 41 to collapse during the manufacturing process of the transistor 10. For example, the height Hw can be 1 to 20 times, preferably 1.3 to 15 times, and more preferably 1.5 to 10 times the width Ww2. For example, the width L can be 5 nm to 100 nm, preferably 5 nm to 50 nm, and more preferably 8 nm to 30 nm. For example, the height Hw can be set to 30 nm or more and 300 nm or less, and preferably 50 nm or more and 150 nm or less.

[0076] 4B , in a cross-sectional view in the channel width direction, the angle θ between the side surface of the insulating layer 41 and the top surface of the insulating layer 44 is preferably perpendicular or approximately perpendicular. For example, the angle θ is preferably 80° to 100°, more preferably 85° to 95°.

[0077] The upper portion of the insulating layer 41 may have a curved shape. Such a curved shape can prevent defects such as voids from being formed in the oxide layer 21S near the upper portion of the insulating layer 41.

[0078] The conductive layer 25a is provided along the side surface 31a of the insulating layer 41 and has, for example, a region in contact with the side surface 31a. The conductive layer 25b is provided along the side surface 31b of the insulating layer 41 and has, for example, a region in contact with the side surface 31b. The conductive layers 25a and 25b may be columnar, for example, cylindrical. In FIG. 4A , the width of the conductive layer 25a is represented as width Wp, and the height of the conductive layer 25a is represented as height Hp.

[0079] For example, if the conductive layer 25a is cylindrical, the diameter can be set to the width Wp. Note that the shape of the conductive layer 25a is not limited to a cylinder, and it may be, for example, a square prism, a triangular prism, or a polygonal prism with pentagonal or higher sides. The same applies to the shape of the conductive layer 25b.

[0080] The height Hp can be the difference between the height of the upper surface of the conductive layer 25a from the reference plane and the height of the lower surface of the conductive layer 25a from the reference plane. The reference plane may be the surface of the substrate, the upper surface of the insulating layer 11, or the upper surface of the conductive layer 24a. Here, the width of the conductive layer 25b can also be the width Wp, and the height of the conductive layer 25b can also be the height Hp.

[0081] The upper surfaces of the conductive layers 25a, 25b, and 41 are flush or substantially flush with one another. This allows the oxide layer 21S to be formed on a flat surface. Furthermore, the heights of the lower surfaces of the conductive layers 25a and 25b from the reference plane can be reduced by the thickness of the insulating layer 44 compared to the height of the lower surface of the insulating layer 41 from the reference plane. The upper surface of the conductive layer 25a is flush or substantially flush with the upper surface of the insulating layer 41, and the height of the lower surface of the conductive layer 25a from the reference plane is equal to or less than the height of the lower surface of the insulating layer 41 from the reference plane, so that the height Hp is equal to or greater than the height Hw. The same is true for the conductive layer 25b.

[0082] In the insulating layer 41, the side surface 31a in contact with the side surface of the conductive layer 25a and the side surface 31b in contact with the side surface of the conductive layer 25b may have a curved portion. Specifically, the side surface 31a may have a shape corresponding to the shape of the side surface of the conductive layer 25a. Similarly, the side surface 31b may have a shape corresponding to the shape of the side surface of the conductive layer 25b.

[0083] The oxide semiconductor layer 21 is provided so as to cover the conductive layer 25 a, the conductive layer 25 b, the insulating layer 41, and the oxide layer 21S. The oxide semiconductor layer 21 is provided so as to cover, for example, the entire conductive layer 25 a, the conductive layer 25 b, the insulating layer 41, and the oxide layer 21S. The oxide semiconductor layer 21 can have, for example, a region in contact with a side surface of the conductive layer 25 a, a region in contact with an upper surface of the conductive layer 25 a, a region in contact with a side surface of the conductive layer 25 b, a region in contact with an upper surface of the conductive layer 25 b, a region in contact with a side surface 31 c of the insulating layer 41, a region in contact with a side surface 31 d, a region in contact with a side surface of the oxide layer 21S, a region in contact with an upper surface of the oxide layer 21S, and a region in contact with an upper surface of the insulating layer 44.

[0084] In a cross-sectional view of the transistor 10 in the channel width direction, a side surface of the oxide layer 21S coincides or substantially coincides with a side surface of the insulating layer 41. Specifically, as shown in FIG. 4B , a side surface 31c and a side surface 31d of the insulating layer 41 coincide or substantially coincides with a side surface of the oxide layer 21S. In a cross-sectional view of the transistor 10 in the channel width direction, the oxide semiconductor layer 21 is provided so as to be folded in half with the insulating layer 41 and the oxide layer 21S sandwiched therebetween. As shown in FIG. 3 , a channel formation region 21C is formed in part of the folded region of the oxide semiconductor layer 21. Furthermore, as shown in FIG. 4B , the oxide semiconductor layer 21 has a region 33a in contact with the side surface 31c, a region 33b in contact with the side surface 31d, and a region 33c in contact with the top surface of the oxide layer 21S.

[0085] In the oxide semiconductor layer 21, the region in contact with the conductive layer 25a and the region nearby it function as one of the source region and the drain region. The region in contact with the conductive layer 25b and the region nearby it function as the other of the source region and the drain region. Here, since the height Hp is equal to or greater than the height Hw as described above, the greater the height Hw, the greater the height Hp. Furthermore, the greater the height Hp, for example, the greater the area of ​​the side surface of the conductive layer 25a. Therefore, the contact area between the oxide semiconductor layer 21 and the conductive layer 25a increases without increasing the area occupied by the transistor 10. Similarly, the greater the height Hp, the greater the contact area between the oxide semiconductor layer 21 and the conductive layer 25b increases without increasing the area occupied by the transistor 10.

[0086] As described above, the larger the height Hw, the larger the contact area between the oxide semiconductor layer 21 and the conductive layer 25a and the contact area between the oxide semiconductor layer 21 and the conductive layer 25b can be without increasing the occupied area of ​​the transistor 10. Therefore, the on-state current of the transistor 10 can be increased. Furthermore, the field-effect mobility and frequency characteristics of the transistor 10 can be improved. Therefore, a semiconductor device with high operating speed can be provided. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. Furthermore, since the contact area between the oxide semiconductor layer 21 and the conductive layer 25a and the contact area between the oxide semiconductor layer 21 and the conductive layer 25b can be increased without increasing the occupied area of ​​the transistor 10, the on-state current of the transistor 10 can be ensured even when the semiconductor device is miniaturized. Furthermore, the semiconductor device can be highly integrated, thereby increasing the storage capacity of a memory device using the semiconductor device.

[0087] The oxide layer 21S and the oxide semiconductor layer 21 contain, for example, indium. For example, indium oxide can be used as the oxide semiconductor layer 21. By using indium oxide as the oxide semiconductor layer 21, the transistor 10 with a large on-state current, a high field-effect mobility, and high frequency characteristics can be realized. Here, when indium oxide is used as the oxide semiconductor layer 21, the indium oxide can have crystals with a cubic crystal structure.

[0088] The oxide layer 21S functions as a seed or a nucleus when treatment is performed to increase the crystallinity of the oxide semiconductor layer 21. By providing the oxide layer 21S in the semiconductor device of one embodiment of the present invention, the oxide semiconductor layer 21 can be formed so that the crystal orientation of the crystal grains in the region 33a, the crystal orientation of the crystal grains in the region 33b, and the crystal orientation of the crystal grains in the region 33c are aligned or substantially aligned with each other.

[0089] The insulating layer 22 is provided so as to cover the oxide semiconductor layer 21 in a cross-sectional view in the channel width direction. The conductive layer 23 is provided on the insulating layer 22 as described above. In a cross-sectional view in the channel width direction, the conductive layer 23 is provided so as to cover the oxide semiconductor layer 21 via the insulating layer 22. In addition to a region overlapping the top surface of the insulating layer 41 with the insulating layer 22 and the oxide semiconductor layer 21 sandwiched therebetween, the conductive layer 23 also has a region facing a side surface 31 c and a region facing a side surface 31 d of the insulating layer 41 with the insulating layer 22 and the oxide semiconductor layer 21 sandwiched therebetween, as shown in FIG. 1C .

[0090] As described above, in the semiconductor device of one embodiment of the present invention, not only the region over the insulating layer 41 in the oxide semiconductor layer 21 but also the region facing the side surface 31c and the region facing the side surface 31d function as a channel formation region of the transistor 10. Therefore, compared to when the insulating layer 41 is not provided, the channel width of the transistor 10 is increased by the region facing the side surface 31c and the region facing the side surface 31d in the oxide semiconductor layer 21.

[0091] In particular, when viewed in a cross section of the transistor 10 in the channel width direction, the greater the height Hw of the insulating layer 41 compared to the width Ww2, i.e., the higher the aspect ratio of the insulating layer 41, the longer the length of the region 33a in the cross section of the channel width direction and the length of the region 33b in the cross section of the channel width direction can be compared to the length of the region 33c in the cross section of the channel width direction. Thus, when viewed in a cross section of the transistor 10 in the channel width direction, the higher the aspect ratio of the insulating layer 41, the larger the channel width of the transistor 10 can be without changing the area occupied by the oxide semiconductor layer 21. Here, the lengths of the regions 33a and 33b in the cross section of the channel width direction correspond to the height Hw. The length of the region 33c in the cross section of the channel width direction corresponds to the width Ww2.

[0092] As described above, the increase in the channel width can increase the on-state current of the transistor 10. Furthermore, the field-effect mobility and frequency characteristics of the transistor 10 can be improved. As a result, a semiconductor device with high operating speed can be provided. Furthermore, the operating speed of a memory device using the semiconductor device can be increased. In the above structure, the oxide semiconductor layer 21 is provided to cover the insulating layer 41, thereby increasing the channel width without increasing the area occupied by the transistor 10. This enables miniaturization or high integration of the semiconductor device. Furthermore, the memory capacity of a memory device using the semiconductor device can be increased. Furthermore, the above structure increases the area where the side surfaces of the conductive layer 23 and the oxide semiconductor layer 21 face each other, so that the transistor 10 can be normally off by controlling the threshold voltage.

[0093] The transistor 10 includes a metal oxide functioning as a semiconductor in the oxide semiconductor layer 21 including a channel formation region. Hereinafter, a transistor whose channel is formed in an oxide semiconductor, such as the transistor 10, may be referred to as an OS transistor. Note that in this specification and the like, the oxide semiconductor layer 21 includes a metal oxide, and therefore the oxide semiconductor layer 21 can be referred to as a metal oxide layer.

[0094] An OS transistor has an oxygen vacancy (V Ｏ The presence of oxygen vacancies and impurities may cause fluctuations in electrical characteristics and reduce reliability. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region of the oxide semiconductor. In other words, it is preferable that the carrier concentration of the channel formation region of the oxide semiconductor is reduced and the channel formation region is made i-type (intrinsic) or substantially i-type.

[0095] Furthermore, when an excessive amount of oxygen is supplied to the oxide semiconductor layer 21, electron traps due to the excess oxygen are formed in the insulating layer 22. This makes the OS transistor more susceptible to positive drift degradation in a +GBT (gate bias-temperature) stress test. In other words, the amount of positive drift degradation in the +GBT stress test increases.

[0096] Therefore, in the semiconductor device of one embodiment of the present invention, the impurity concentration in the oxide semiconductor layer 21 is preferably low. Furthermore, an appropriate amount of oxygen is preferably supplied to the oxide semiconductor layer 21. Furthermore, it is preferable to reduce the amount of excess oxygen in the oxide semiconductor layer 21.

[0097] Indium oxide is preferably used for the oxide semiconductor layer 21. Examples of metal oxides that can be used for the oxide semiconductor layer 21 include oxides containing gallium (Ga) and oxides containing zinc (Zn). The metal oxide preferably contains at least In or Zn. The metal oxide preferably contains two or three elements selected from In, element M, and Zn. The element M is a metal element or a metalloid element having a high bond energy with oxygen, such as a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M contained in the metal oxide is preferably one or more of the above elements, particularly preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred. Hereinafter, a metal oxide containing In, M, and Zn may be referred to as an In-M-Zn oxide. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0098] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. For example, the atomic ratios of metal elements in such an In-M-Zn oxide may be In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, or compositions in the vicinity thereof. Note that the term "composition in the vicinity" refers to a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current, field-effect mobility, or the like of the transistor can be increased.

[0099] Furthermore, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M. For example, the atomic ratio of metal elements in such an In-M-Zn oxide may be In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or a composition close to these. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0100] The oxide semiconductor layer 21 can be made of, for example, In—Zn oxide, In—Ga oxide, In—Sn oxide, In—Ti oxide, In—Ga—Al oxide, In—Ga—Sn oxide, In—Ga—Zn oxide, In—Sn—Zn oxide, In—Al—Zn oxide, In—Ti—Zn oxide, In—Ga—Sn—Zn oxide, In—Ga—Al—Zn oxide, etc. Ga—Zn oxide may also be used. On the other hand, a material containing Zn is preferred because it is easy to increase crystallinity.

[0101] Note that the metal oxide may contain one or more metal elements with a higher period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of the metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element with a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements with a higher period number include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

[0102] The metal oxide may contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0103] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). In particular, it is preferable to form the metal oxide film by the ALD method, which has excellent coverage. When forming the metal oxide by sputtering, the composition of the metal oxide film may differ from the composition of the target. In particular, the zinc content in the metal oxide film may decrease to about 50% compared to the target.

[0104] In this specification, the content of a metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if a metal oxide contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide is A, then Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +AＺ ) In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide (atomic number ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ When the metal oxide contains two or four or more kinds of metal elements, the content can be expressed in the same manner.

[0105] For example, in the case of a metal oxide containing In, a transistor with a large on-current can be realized by increasing the In content.

[0106] By using a metal oxide that does not contain Ga or has a Ga content as low as possible in the oxide semiconductor layer 21, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of variation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test can be obtained. Furthermore, when a metal oxide containing Ga is used, it is preferable to make the Ga content lower than the In content. This makes it possible to realize a transistor with high mobility and high reliability.

[0107] On the other hand, by increasing the Ga content, a transistor with high reliability against light can be obtained. That is, a transistor with a small amount of variation in threshold voltage in a Negative Bias Temperature Illumination Stress (NBTIS) test can be obtained. Specifically, a metal oxide in which the atomic ratio of Ga is equal to or greater than the atomic ratio of In has a larger band gap, and the amount of variation in threshold voltage of the transistor in the NBTIS test can be reduced.

[0108] Furthermore, by increasing the zinc content, the metal oxide becomes highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0109] The oxide semiconductor layer 21 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the oxide semiconductor layer 21 may have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. A stacked structure in which two or more oxide semiconductor layers with different compositions are stacked may also be used. Furthermore, by using the ALD method, it is possible to form a metal oxide layer whose composition varies continuously in the thickness direction. This not only broadens the range of design options compared to using a film with a fixed composition, but also prevents the generation of interface states between two layers with different compositions, thereby improving electrical characteristics and reliability. Furthermore, a metal oxide layer having a stacked structure may be formed using both the sputtering method and the ALD method.

[0110] When the oxide semiconductor layer 21 has a two-layer structure, it is preferable to use a material with higher mobility (higher conductivity) for the second layer, i.e., the side closer to the gate electrode, than for the first layer. This allows for a normally-off transistor with a large on-state current. Therefore, low power consumption and high performance can be achieved at the same time. Alternatively, a material with higher mobility than for the second layer may be used for the first layer, i.e., the side in contact with the source electrode and drain electrode. This reduces the contact resistance between the oxide semiconductor layer 21 and the source electrode or drain electrode, thereby reducing parasitic resistance and enabling a transistor with a large on-state current.

[0111] When the oxide semiconductor layer 21 has a three-layer structure, it is preferable to use a material for the second layer that has higher mobility than the first and third layers, thereby realizing a transistor with high on-state current and high reliability.

[0112] The difference in the mobility and conductivity described above can be expressed, for example, by the indium content. In addition, whether or not an element other than indium that contributes to improving conductivity is contained, and the content of that element, also affect the mobility and conductivity. Examples of high-mobility materials include In:Ga:Zn = 4:2:3, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 4:1, In:Sn:Zn = 40:X:10 (where X is 0.1 or more and 5 or less, typically X = 1), or materials with compositions similar to these. On the other hand, materials with lower mobility or conductivity than the above-mentioned materials include In:Ga:Zn = 1:3:2, In:Ga:Zn = 1:3:4, In:Ga:Zn = 2:2:1, In:Ga:Zn = 1:1:1, In:Ga:Zn = 1:1:2, or materials with compositions similar to these.

[0113] It is preferable to use a crystalline metal oxide layer for the oxide semiconductor layer 21. For example, a metal oxide layer having a single crystal structure, a CAAC structure, a polycrystalline structure, a nano-crystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the oxide semiconductor layer 21, the density of defect states in the oxide semiconductor layer 21 can be reduced, and a highly reliable semiconductor device can be realized.

[0114] The higher the crystallinity of the metal oxide layer used for the oxide semiconductor layer 21, the more the density of defect states in the oxide semiconductor layer 21 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0115] In particular, indium oxide is preferably used for the oxide semiconductor layer 21. In particular, a single-crystal indium oxide film is preferably used. Note that a crystalline film is preferably used for the oxide semiconductor layer 21, and indium oxide having a single-crystal structure is particularly preferable. However, indium oxide having a polycrystalline structure or a microcrystalline structure can also be used. By using indium oxide having a single-crystal structure, carrier scattering at crystal grain boundaries can be suppressed, and a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized. When indium oxide having a polycrystalline structure is used, it is preferable that crystal grain boundaries are not observed at least in the channel formation region (a region overlapping with the conductive layer 23). As a result, even indium oxide having a polycrystalline structure can achieve the same effects as indium oxide having a single-crystal structure.

[0116] The thickness of the oxide semiconductor layer 21 is preferably 2 nm to 50 nm, more preferably 2.5 nm to 30 nm, more preferably 2.5 nm to 20 nm, more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. By setting the thickness of the oxide semiconductor layer 21 within the above range, the crystallinity of the oxide semiconductor layer 21 can be improved.

[0117] Among oxide semiconductors with high crystallinity, indium oxide is a film through which one or both of hydrogen and oxygen move more easily than, for example, an IGZO (In—Ga—Zn—O-based oxide) film. Therefore, it can be said that indium oxide is a film through which one or both of hydrogen and oxygen are more easily supplied and discharged than, for example, an IGZO film. As a result, it can be said that excess oxygen or excess hydrogen, which can become carriers or fixed charges, is less likely to accumulate in the oxide semiconductor layer 21, and therefore a transistor with good electrical characteristics and reliability can be obtained.

[0118] The oxide semiconductor layer 21 preferably has a reduced concentration of elements that reduce crystallinity. For example, the concentration of elements such as boron and aluminum is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

[0119] Furthermore, when indium oxide is used for the oxide semiconductor layer 21, unintentionally mixed gallium has a tendency to easily bond with excess oxygen atoms, which may result in a large amount of fluctuation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test. Therefore, when indium oxide is used for the oxide semiconductor layer 21, the gallium concentration in the oxide semiconductor layer 21 is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

[0120] An OS transistor has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as off-state current), and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0121] The semiconductor device according to one embodiment of the present invention can be applied to, for example, a processor, a memory device, or various ICs. The transistor according to one embodiment of the present invention is capable of passing a large current and has an extremely low off-state current, and therefore, high-speed operation of a circuit and low power consumption can be achieved at the same time.

[0122] A semiconductor device according to one embodiment of the present invention can also be applied to a display device, for example. To increase the emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher withstand voltage between the source and drain than a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the emission luminance of the light-emitting device.

[0123] When the transistor operates in the saturation region, the OS transistor can reduce the change in source-drain current with respect to the change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the amount of current flowing through the light-emitting device can be precisely controlled. This allows for a larger number of gray levels in the pixel circuit. Furthermore, even if the electrical characteristics (e.g., resistance) of the light-emitting device fluctuate or vary, a stable current can flow.

[0124] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," "suppression of the influence of manufacturing variations in light-emitting devices," and the like.

[0125] OS transistors exhibit smaller variations in electrical characteristics due to radiation exposure than Si transistors, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0126] The oxide layer 21S has crystals. The oxide layer 21S functions as a seed or a nucleus when a process for increasing the crystallinity of the oxide semiconductor layer 21 is performed. In other words, the oxide layer 21S functions as a seed or a nucleus when the oxide semiconductor layer 21 grows crystals. In this specification and the like, the crystals of the oxide layer 21S can be referred to as seed crystals or crystal nuclei. Furthermore, since the oxide layer 21S has crystals, the oxide layer 21S can be referred to as a crystalline portion.

[0127] Indium oxide crystals have a cubic crystal structure (bixbyite type). When indium oxide is used for the oxide semiconductor layer 21, the oxide layer 21S preferably has, for example, the same cubic crystal structure as indium oxide.

[0128] Alternatively, the oxide layer 21S preferably has crystals with a hexagonal or trigonal structure. In this case, the oxide layer 21S has crystals with a <001> crystal orientation relative to the surface or the surface on which the oxide layer 21S is formed, thereby forming the oxide semiconductor layer 21 having crystals with a <111> crystal orientation. Note that a crystal with a layered crystal structure can be used as the crystal with a hexagonal or trigonal structure. In this case, the oxide semiconductor layer 21 having crystals with a cubic crystal structure is formed on the oxide layer 21S having crystals with a layered structure. That is, the oxide semiconductor layer 21 can be considered as a stacked structure fabricated using a technique such as heteroepitaxial growth, heteroepitaxial growth, or axial growth. Note that axial growth here refers to a state in which at least one of the crystal axes or crystal orientations of the oxide layer 21S coincides or substantially coincides with one of the crystal axes or crystal orientations of the oxide semiconductor layer 21.

[0129] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, in this specification, due to formatting restrictions, numbers may be expressed by adding a minus sign (-) before them instead of adding a bar above them. Individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0130] 4B , it is preferable that the crystal orientations of the crystal grains in the oxide semiconductor layer 21 are the same or substantially the same in all regions. For example, as shown in FIG. 4B , it is preferable that the crystal orientations of the crystal grains included in regions 33a to 33c in the oxide semiconductor layer 21 are <111>. Here, the <111> crystal orientation of the oxide semiconductor layer 21 is perpendicular or substantially perpendicular to the surface of the substrate (which can also be referred to as the surface of the insulating layer 44) in all regions. It can also be said that the <111> crystal orientation of the oxide semiconductor layer 21 is parallel or substantially parallel to the side surface of the insulating layer 41 and perpendicular or substantially perpendicular to the top surface of the insulating layer 41.

[0131] As described above, not only the region on the insulating layer 41 in the oxide semiconductor layer 21 but also the region facing the side surface 31c and the region facing the side surface 31d function as a channel formation region of the transistor 10. Therefore, the crystal structure of the oxide semiconductor layer 21 in the region on the insulating layer 41, the region facing the side surface 31c, and the region facing the side surface 31d is made uniform, which can stabilize the electrical characteristics of the transistor 10. This makes it possible to realize a transistor 10 with a large on-state current, a high field-effect mobility, and high frequency characteristics.

[0132] The oxide layer 21S is preferably made of a material that has a crystal structure with a small degree of lattice mismatch with the crystal structure of the material that constitutes the oxide semiconductor layer 21. This makes it easier for heteroepitaxial growth or axial growth to occur when the oxide semiconductor layer 21 is formed on the oxide layer 21S, and makes it easier to crystallize a part of the oxide semiconductor layer 21.

[0133] One method for evaluating the degree of lattice mismatch is the lattice mismatch ratio. The lattice mismatch ratio Δa [%] of the crystals of the formed film to the crystals of the film to be formed is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２is the length of the unit lattice vector or the lattice constant of the crystal of the film to be formed.

[0134] The smaller the absolute value of the lattice mismatch Δa between the oxide layer 21S and the oxide semiconductor layer 21, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0135] The oxide layer 21S preferably contains, for example, a metal oxide containing the same metal element as the oxide semiconductor layer 21. In particular, both the oxide layer 21S and the oxide semiconductor layer 21 preferably contain one or more of indium, tin, and zinc. In particular, it is more preferable that both the oxide layer 21S and the oxide semiconductor layer 21 contain indium.

[0136] The oxide layer 21S may be a metal oxide film having a cubic crystal structure, such as indium oxide or indium-tin oxide. Alternatively, a metal oxide film having a hexagonal crystal structure, such as zinc oxide, In—Ga oxide, gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), In—Al—Zn oxide, In—Ga—Zn oxide, or In—Sn—Zn oxide, may be used. Alternatively, a metal oxide film having a tetragonal crystal structure, such as tin oxide or titanium oxide, may be used.

[0137] It is preferable to use In—Ga—Zn oxide as the oxide layer 21S. In this case, the oxide layer 21S contains indium, gallium, zinc, and oxygen. Specifically, it is preferable to use a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto, or a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition close thereto. Metal oxides with these compositions are suitable for the oxide layer 21S because they easily form a layered structure. Note that a composition close thereto includes a range of ±30% of the desired atomic ratio.

[0138] In—Ga—Zn oxide and In—Sn—Zn oxide, for example, tend to have a c-axis aligned crystal (CAAC) structure. When an oxide having a CAAC structure is used for the oxide layer 21S, the c-axis of the crystal nuclei is perpendicular or approximately perpendicular to the surface of the oxide layer 21S or the surface on which it is formed. In other words, by using an oxide that tends to have a CAAC structure for the oxide layer 21S, it is possible to improve the controllability of the crystal orientation of the crystal nuclei. That is, indium oxide formed on the oxide layer 21S having a CAAC structure tends to become crystals in which the crystal orientation <111> is oriented perpendicular to the surface on which it is formed.

[0139] The oxide layer 21S may have a tapered shape in a cross-sectional view. For example, the angle formed between the top surface of the conductive layer 25a or the conductive layer 25b and the side surface of the oxide layer 21S may be less than 90°, preferably 30° or more and less than 90°. By forming the oxide layer 21S in a tapered shape, the coverage of the oxide semiconductor layer 21 can be improved and defects such as voids can be reduced. Furthermore, crystal growth of the oxide semiconductor layer 21 can be promoted.

[0140] The oxide layer 21S preferably has a thin film thickness. For example, the oxide layer 21S is preferably thinner than the oxide semiconductor layer 21. Specifically, the oxide layer 21S preferably has a region with a film thickness of 0.1 nm or more and less than 2 nm, and more preferably has a region with a film thickness of 0.5 nm or more and less than 2 nm. By reducing the film thickness of the oxide layer 21S, the steps generated between the oxide layer 21S and the conductive layer 25a, the conductive layer 25b, and the insulating layer 41 are reduced. This improves the coverage of the oxide semiconductor layer 21 and reduces defects such as voids. Furthermore, it is possible to promote crystal growth of the oxide semiconductor layer 21. The oxide layer 21S may be layered or granular.

[0141] In an OS transistor, impurities, oxygen vacancies, and V Ｏ In view of this, an insulating layer containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor layer, and heat treatment is performed to supply oxygen from the insulating layer to the oxide semiconductor layer, thereby eliminating oxygen vacancies and VＯ H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, the on-state current or the field-effect mobility of the transistor 10 may decrease. Furthermore, variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface may cause variations in the characteristics of a semiconductor device including the transistor. Furthermore, if oxygen supplied from the insulating layer to the oxide semiconductor layer diffuses into a conductive layer such as a gate electrode, a source electrode, or a drain electrode, the conductive layer may be oxidized, resulting in a loss of conductivity, which may adversely affect the electrical characteristics and reliability of the transistor.

[0142] In the transistor, it is preferable to prevent an excessive amount of hydrogen from being contained in the channel formation region, to prevent oxidation of the conductive layer 25 a, the conductive layer 25 b, and the conductive layer 23, and to prevent a decrease in the hydrogen concentration in the source region and the drain region.

[0143] The insulating layer 22 in contact with the channel formation region of the oxide semiconductor layer 21 preferably has a function of capturing or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the oxide semiconductor layer 21. Ｏ By reducing H, the channel forming region can be made i-type or substantially i-type.

[0144] 4A , the insulating layer 22 preferably has a stacked structure of an insulating layer 22a in contact with the oxide semiconductor layer 21, an insulating layer 22b on the insulating layer 22a, an insulating layer 22c on the insulating layer 22b, and an insulating layer 22d on the insulating layer 22c. In this case, the insulating layer 22a and the insulating layer 22c preferably have a function of capturing or fixing hydrogen.

[0145] Examples of insulators capable of capturing or fixing hydrogen include metal oxides having an amorphous structure. For the insulating layer 22a and the insulating layer 22c, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium. In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, metal oxides having an amorphous structure can be said to have a high ability to capture or fix hydrogen.

[0146] Furthermore, it is preferable to use a high-dielectric constant (high-k) material for the insulating layer 22a and the insulating layer 22c. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. By using a high-k material for the insulating layer 22a and the insulating layer 22c, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulating layer. Furthermore, it is possible to reduce the equivalent oxide thickness (EOT) of the gate insulating layer.

[0147] For the insulating layer 22a and the insulating layer 22c, it is preferable to use an oxide containing one or both of aluminum and hafnium, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium.

[0148] In this embodiment, an aluminum oxide film is used as the insulating layer 22 a. The aluminum oxide preferably has an amorphous structure. By providing the insulating layer 22 a in contact with the oxide semiconductor layer 21, hydrogen contained in the oxide semiconductor layer 21 and the like can be more effectively captured and fixed.

[0149] In this embodiment, hafnium oxide is used as the insulating layer 22c. By providing the insulating layer 22c between the insulating layer 22b and the insulating layer 22d, hydrogen contained in the insulating layer 22b and the like can be more effectively captured and fixed.

[0150] It is preferable to use a thermally stable insulator such as silicon oxide or silicon oxynitride as the insulating layer 22b. Note that in this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0151] The silicon oxide film used as the insulating layer 22b is preferably formed by the ALD method, and more specifically, by the PEALD (Plasma Enhanced ALD) method.

[0152] In order to suppress oxidation of the conductive layer 23, it is preferable to provide a barrier insulating layer against oxygen near the conductive layer 23. In the semiconductor device described in this embodiment, the insulating layer is, for example, the insulating layer 22d.

[0153] In this specification and the like, a barrier insulating layer refers to an insulating layer having barrier properties. In this specification and the like, having barrier properties refers to having a property of preventing the permeation of a corresponding substance (also referred to as low permeability). For example, an insulating layer having barrier properties has a property that makes it difficult for a corresponding substance to diffuse into the insulating layer. Furthermore, for example, an insulating layer having barrier properties has a function of capturing or fixing (also referred to as gettering) a corresponding substance inside the insulating layer.

[0154] Examples of materials that can be used for the oxygen barrier insulating layer include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, the insulating layer 22 a, the insulating layer 22 c, and the insulating layer 22 d each preferably have a single-layer structure or a multilayer structure of the oxygen barrier insulating layer.

[0155] The insulating layer 22a is provided in contact with the upper surface and side surfaces of the oxide semiconductor layer 21 and the upper surface of the insulating layer 44. The insulating layer 22a has a barrier property against oxygen, and thus can suppress oxygen from being desorbed from the channel formation region of the oxide semiconductor layer 21 when heat treatment or the like is performed. Therefore, the formation of oxygen vacancies in the oxide semiconductor layer 21 can be reduced.

[0156] An oxide containing one or both of aluminum and hafnium has a barrier property against oxygen, and therefore can be suitably used as the insulating layer 22a.

[0157] The insulating layer 22d is provided between the channel formation region of the oxide semiconductor layer 21 and the conductive layer 23, and between the insulating layer 42 and the conductive layer 23. Therefore, the insulating layer 22d has a barrier property against oxygen, which can prevent oxygen contained in the channel formation region of the oxide semiconductor layer 21 from diffusing into the conductive layer 23 and forming oxygen vacancies in the channel formation region of the oxide semiconductor layer 21. Furthermore, the insulating layer 22d can prevent oxygen contained in the oxide semiconductor layer 21 and oxygen contained in the insulating layer 42 from diffusing into the conductive layer 23 and oxidizing the conductive layer 23. The insulating layer 22d is preferably at least less permeable to oxygen than the insulating layer 42. For example, a silicon nitride film is preferably used as the insulating layer 22d. In this case, the insulating layer 22d is an insulating layer containing at least nitrogen and silicon.

[0158] Furthermore, the insulating layer 22d preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductive layer 23 from diffusing into the oxide semiconductor layer 21. Examples of materials that can be used for the barrier insulating layer against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride.

[0159] With the above structure, the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made n-type, thereby providing a semiconductor device with good electrical characteristics. Furthermore, with the above structure, the semiconductor device can have good electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 10 can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0160] The insulating layers 22a to 22d function as part of the gate insulating layer. The insulating layers 22a to 22d, together with the conductive layer 23, are provided in the opening 20 formed in the insulating layer 42. To miniaturize the transistor 10, the insulating layers 22a to 22d preferably have a small thickness. The insulating layers 22a to 22d each have a thickness of preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, still more preferably 1.0 nm to less than 5.0 nm, and still more preferably 1.0 nm to 3.0 nm. It is preferable that at least a portion of each of the insulating layers 22a to 22d has a region having the above-described thickness.

[0161] The thickness of the silicon oxide film used as the insulating layer 22b is preferably 0.7 nm or more and 3 nm or less.

[0162] In order to thin the insulating layers 22a to 22d as described above, it is preferable to form the insulating layers 22a to 22d by using the ALD method. Furthermore, in order to provide the insulating layers 22a to 22d inside the opening 20, it is preferable to form the insulating layers by using the ALD method. Examples of the ALD method include thermal ALD and PEALD. The PEALD method may be preferable because it uses plasma, which allows film formation at a lower temperature.

[0163] The ALD method can deposit atoms layer by layer, and therefore has the following advantages: it is possible to form an extremely thin film, it is possible to form a film on a structure with a high aspect ratio, it is possible to form a film with few defects such as pinholes, it is possible to form a film with excellent coverage, it is possible to form a film at a low temperature, etc. Therefore, the insulating layer 22 can be formed with good coverage on the side surfaces of the openings formed in the insulating layer 42 and the side edges of the conductive layers 25 a and 25 b, etc., with a thin film thickness as described above.

[0164] Note that some precursors used in the ALD method contain carbon and the like. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the quantity of impurities can be determined using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0165] Although the insulating layer 22 has been described above as having a four-layer structure of insulating layers 22a to 22d, the present invention is not limited to this. The insulating layer 22 may have a structure including at least one of the insulating layers 22a to 22d. By configuring the insulating layer 22 as one, two, or three of the insulating layers 22a to 22d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0166] It is preferable to use the ALD process two or more times in forming the insulating layer 22. For example, the insulating layer 22 preferably has a stacked structure of a plurality of insulating films, and it is preferable that two or more of the plurality of insulating films are formed using the ALD process. By forming at least two or more insulating films using the ALD process, it is possible to improve the coverage and film thickness uniformity of the insulating layer 22. Furthermore, it is possible to increase productivity by successively forming two or more different films, for example, two or more insulating films, using the ALD process.

[0167] It is preferable that the insulating layer 11, the insulating layer 43, the insulating layer 41, and the insulating layer 42 each have a lower dielectric constant than the insulating layer 22. By using a material with a low dielectric constant for these insulating layers, the parasitic capacitance generated between wirings can be reduced.

[0168] It is preferable that the insulating layer 11, the insulating layer 43, the insulating layer 41, and the insulating layer 42 each contain one or more of, for example, silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies.

[0169] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0170] The concentration of impurities such as water and hydrogen in the insulating layer 42 is preferably reduced. For example, the insulating layer 42 preferably contains an oxide containing silicon, such as silicon oxide or silicon oxynitride. The reduced impurity concentration in the insulating layer 42 can suppress diffusion of impurities into the oxide semiconductor layer 21. Therefore, the reliability of the transistor 10 can be improved.

[0171] The insulating layer 44 is made of a material having a high etching selectivity with respect to the insulating layer 41. This prevents a portion of the insulating layer 44 from being removed when the insulating layer 41 is etched. For example, when silicon oxide is used for the insulating layer 42, one or more of silicon nitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used for the insulating layer 44. Silicon nitride and silicon nitride oxide, in particular, are characterized by low release of impurities (e.g., water and hydrogen) from themselves and are less permeable to oxygen and hydrogen. Therefore, these materials are preferable because they can prevent hydrogen from diffusing from the structure located below the insulating layer 44 to the oxide semiconductor layer 21 and prevent oxygen from the oxide semiconductor layer 21 from diffusing below the insulating layer 44.

[0172] The insulating layer 44 may have a stacked structure of two or more layers. For example, the above-described hydrogen barrier insulating layer may be used as a layer in contact with the oxide semiconductor layer 21, and a silicon oxide film may be provided on the hydrogen barrier insulating layer. This can suppress diffusion of hydrogen into the oxide semiconductor layer 21 and improve the reliability of the transistor 10.

[0173] The conductive layer 23, the conductive layer 24a, the conductive layer 24b, the conductive layer 25a, and the conductive layer 25b are preferably made of a material having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. With the above structure, the electrical resistivity of the conductive layer 23, the conductive layer 24a, the conductive layer 24b, the conductive layer 25a, and the conductive layer 25b can be reduced. This can increase the on-state current of the transistor 10 and improve the operating speed of the semiconductor device of one embodiment of the present invention.

[0174] 4A shows the conductive layer 23 as having a two-layer structure. Here, the conductive layer 23 preferably includes a conductive layer 23a and a conductive layer 23b provided on the conductive layer 23a. For example, the conductive layer 23a is preferably provided so as to surround the bottom and side surfaces of the conductive layer 23b. In this case, the conductive layer 23a is preferably made of a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion.

[0175] The conductive layer 23a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0176] Furthermore, since the conductive layer 23a has a function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductive layer 23b caused by oxygen contained in the insulating layer 42, etc. As the conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0177] Furthermore, it is preferable that the conductive layer 23b be made of a conductor having high conductivity. For example, the conductive layer 23b may be made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductive layer 23b may also have a layered structure, for example, a layered structure of titanium or titanium nitride and the above conductive material.

[0178] 5A, 5B, 5C, 5D, and 5E illustrate examples in which the structures of the source electrode and drain electrode of the transistor 10 are different from those in FIGS. 1A, 1B, 1C, 1D, and 1E, respectively. In the examples illustrated in FIGS. 5A and 5B, one of the source electrode and drain electrode of the transistor 10 includes a conductive layer 27a, a conductive layer 26a over the conductive layer 27a, and a conductive layer 25a over the conductive layer 26a. The other of the source electrode and drain electrode of the transistor 10 includes a conductive layer 27b, a conductive layer 26b over the conductive layer 27b, and a conductive layer 25b over the conductive layer 26b. Note that FIG. 5A illustrates the oxide semiconductor layer 21 in a see-through manner.

[0179] In the example shown in Figures 5A to 5E, the conductive layer 26a is provided so as to surround the bottom and side surfaces of the conductive layer 25a. The conductive layer 27a is provided so as to surround the bottom and side surfaces of the conductive layer 26a. Similarly, the conductive layer 26b is provided so as to surround the bottom and side surfaces of the conductive layer 25b. Furthermore, the conductive layer 27b is provided so as to surround the bottom and side surfaces of the conductive layer 26b. Here, the top surface of the conductive layer 25a, the top end of the conductive layer 26a, the top end of the conductive layer 27a, the top surface of the conductive layer 25b, the top end of the conductive layer 26b, and the top end of the conductive layer 27b coincide or substantially coincide with the top surface of the insulating layer 41. Furthermore, the conductive layers 25a, 26a, and 27a may be provided in this order from the inside, for example, concentrically. Similarly, the conductive layers 25b, 26b, and 27b may be provided in this order from the inside, for example, concentrically.

[0180] The conductive layer 27a has a region in contact with the top surface of the conductive layer 24a, a region in contact with the side surface of the oxide semiconductor layer 21, a region in contact with the side surface of the insulating layer 44, and a region in contact with the side surface of the insulating layer 41. The conductive layer 27b has a region in contact with the top surface of the conductive layer 24b, a region in contact with the side surface of the oxide semiconductor layer 21, a region in contact with the side surface of the insulating layer 44, and a region in contact with the side surface of the insulating layer 41. A conductive material containing oxygen can be used for the conductive layer 27a and the conductive layer 27b. This can reduce the contact resistance between the source electrode and the drain electrode of the transistor 10 and the oxide semiconductor layer 21. Examples of the conductive material containing oxygen include indium oxide containing tungsten, indium oxide containing titanium, ITO, indium tin oxide containing titanium, ITSO, indium zinc oxide, and indium zinc oxide containing tungsten. In this specification and the like, a conductive layer using a conductive material containing oxygen may be referred to as an oxide conductive layer.

[0181] The conductive layers 26a and 26b are preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. This can prevent the conductive layers 25a and 25b from being excessively oxidized by, for example, oxygen contained in the oxide semiconductor layer 21. This can prevent the conductivity of the conductive layers 25a and 25b from decreasing due to oxidation.

[0182] For the conductive layer 26a and the conductive layer 26b, it is preferable to use a metal nitride, such as a nitride containing titanium, a nitride containing tantalum, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing titanium and aluminum, or a nitride containing tantalum and aluminum. In one embodiment of the present invention, it is particularly preferable to use a nitride containing titanium. Alternatively, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when absorbing oxygen.

[0183] For example, tungsten can be used for the conductive layers 25a and 25b, titanium nitride can be used for the conductive layers 26a and 26b, and ITO can be used for the conductive layers 27a and 27b.

[0184] Fig. 6 is a diagram showing an example in which layers 37a and 37b are provided on the oxide semiconductor layer 21. Fig. 7A is an enlarged view of some elements shown in Fig. 6, showing the insulating layer 41, the oxide layer 21S, the oxide semiconductor layer 21, the layers 37a and 37b, the insulating layer 22, the conductive layer 23, and the insulating layer 42.

[0185] As shown in FIG. 6 , a portion of the side surface of the layer 37a and a portion of the side surface of the layer 37b can coincide or substantially coincide with a side surface of the oxide semiconductor layer 21. Furthermore, as shown in FIGS. 6 and 7A , the layers 37a and 37b are provided to face each other across the opening 20. The layers 37a and 37b have lower electrical resistivity than the oxide semiconductor layer 21. The layers 37a and 37b can be, for example, conductive layers or low-resistance semiconductor layers. Therefore, the region of the oxide semiconductor layer 21 in contact with the layer 37a and the region nearby functions as one of the source region and the drain region. The region of the oxide semiconductor layer 21 in contact with the layer 37b and the region nearby functions as the other of the source region and the drain region.

[0186] When the layers 37a and 37b are conductive layers, the layers 37a and 37b can be formed using the same material as that used for the conductive layers 25a, 25b, 26a, 26b, 27a, and 27b. Metal nitrides can be used for the layers 37a and 37b, and examples of such nitrides include titanium nitrides, tantalum nitrides, molybdenum nitrides, tungsten nitrides, titanium and aluminum nitrides, and tantalum and aluminum nitrides. In one embodiment of the present invention, titanium nitrides or tantalum nitrides are particularly preferred. Furthermore, for example, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel may also be used. Furthermore, for the layers 37 a and 37 b, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, and the like, or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements, etc. can be used.

[0187] When the layers 37a and 37b are semiconductor layers with reduced resistance, the layers 37a and 37b can be made of an oxide semiconductor doped with impurities. For example, the layers 37a and 37b can be made of a material that can be used for the oxide layer 21S. For example, indium oxide, tin oxide, indium tin oxide, or the like can be used for the layers 37a and 37b. For example, a metal element can be used as the impurity. For example, titanium, aluminum, tantalum, tungsten, tin, silicon, germanium, zirconium, hafnium, antimony, or magnesium can be used as the impurity. Hydrogen, carbon, boron, arsenic, or the like can also be used as the impurity.

[0188] As shown in FIG. 7A , the layer 37 a and the layer 37 b have regions overlapping with the conductive layer 23. This allows the oxide semiconductor layer 21 to have a structure that is neither a source region nor a drain region and does not have a region that does not overlap with the conductive layer 23 in a plan view. That is, the oxide semiconductor layer 21 can have no offset region. Furthermore, the channel length of the transistor 10 can be shortened. As described above, a transistor 10 with a large on-state current, a high field-effect mobility, and high frequency characteristics can be realized. Here, the channel length of the transistor 10 shown in FIGS. 6 and 7A can be, for example, 2 nm to 6 nm.

[0189] In the example shown in Figure 7A, the thickness of at least a portion of the layer 37a and layer 37b in the region overlapping with the conductive layer 23 is thinner than the thickness of the region not overlapping with the conductive layer 23. In Figure 7A, the thickness of the region of layer 37a with the thinner thickness is defined as thickness T1. The thickness of layer 37a in the region not overlapping with the conductive layer 23 is defined as thickness T2. Here, the region of layer 37a with thickness T1 is defined as region 47a, and the region with thickness T2 is defined as region 48a. Similarly, layer 37b can have a region 47b with thickness T1 and a region 47b with thickness T2.

[0190] The region 47a is closer to the conductive layer 23 than the region 48a. Similarly, the region 47b is closer to the conductive layer 23 than the region 48b. The regions 47a and 47b overlap with the conductive layer 23. The regions 48a and 48b do not overlap with the conductive layer 23. Here, the layer 37a includes the region 47a and the layer 37b includes the region 47b, which prevents the insulating layer 22 from being thicker in the region between the layers 37a and 37b than in other regions due to a step between the layer 37a and the oxide semiconductor layer 21 and a step between the layer 37b and the oxide semiconductor layer 21. This makes it easier to apply a gate electric field to the channel formation region of the oxide semiconductor layer 21. As described above, the transistor 10 having a large on-state current, a high field-effect mobility, and high frequency characteristics can be realized.

[0191] The thickness T1 is preferably 0.1 nm to 5 nm, more preferably 0.2 nm to 2 nm, and even more preferably 0.3 nm to 1 nm. The thickness T2 is preferably 1 nm to 20 nm, more preferably 1.5 nm to 10 nm, and even more preferably 2 nm to 5 nm.

[0192] 7B is a diagram showing an example in which the oxide semiconductor layer 21 shown in FIG. 7A has a recess 39. The recess 39 is formed in a region between the region 47a and the region 47b. When the opening 20 is formed, the recess 39 may be formed in the oxide semiconductor layer 21. Specifically, when the layers 37a and 37b are processed to form a region with a film thickness T1 in the layers 37a and 37b, the oxide semiconductor layer 21 may be processed to form the recess 39.

[0193] Here, when impurities are supplied to the layer 37a and the layer 37b, heat treatment is preferably performed. As a result, the impurities can be supplied to the oxide semiconductor layer 21, and the source and drain regions can be expanded. As a result, the distance between the source and drain regions of the oxide semiconductor layer 21 can be reduced. As a result, the transistor 10 can have a large on-state current, a high field-effect mobility, and high frequency characteristics.

[0194] <Constituent Materials of Semiconductor Device> Constituent materials that can be used for the semiconductor device will be described below. Each layer that constitutes the semiconductor device may have a single layer structure or a multilayer structure.

[0195] <<Substrate>> Examples of substrates for forming transistors include insulating substrates, semiconductor substrates, and conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Examples of substrates include substrates having a metal nitride, substrates having a metal oxide, substrates having a conductive layer or semiconductor layer on an insulating substrate, substrates having a conductive layer or insulating layer on a semiconductor substrate, and substrates having a semiconductor layer or insulating layer on a conductive substrate. Alternatively, one or more types of elements may be provided on the substrate, such as a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0196] <<Insulating Layer>> Examples of insulators that can be used for at least one of the insulating layer 11, the insulating layer 22, the insulating layer 41, the insulating layer 42, the insulating layer 43, and the insulating layer 44 include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, which have insulating properties.

[0197] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-k material for the gate insulating layer makes it possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the insulating layer that functions as an interlayer insulating layer can reduce the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select materials according to the function of the insulating layer.

[0198] Examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0199] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, and resin.

[0200] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulating layers that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include, for example, insulating layers containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, which can be used in a single layer or stacked layers. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0201] The gate insulating layer is preferably an insulating layer having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide semiconductor layer 21, oxygen vacancies in the oxide semiconductor layer 21 can be compensated for.

[0202] <<Conductive Layer>> The conductor that can be used for at least one of the conductive layers 23, 24a, 24b, 25a, 25b, 26a, 26b, 27a, and 27b is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element or an alloy combining the above-mentioned metal elements. Examples of the conductor include tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferable because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Also, semiconductors with high conductivity, typified by polycrystalline silicon containing impurities such as phosphorus, or silicides such as nickel silicide may be used.

[0203] When a conductive layer having a stacked structure is used, for example, a stacked structure combining the material containing the metal element described above and a conductive material containing oxygen, a stacked structure combining the material containing the metal element described above and a conductive material containing nitrogen, or a stacked structure combining the material containing the metal element described above and a conductive material containing oxygen and a conductive material containing nitrogen may be applied.

[0204] When an oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0205] In particular, for the conductive layer functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which a channel is formed. Alternatively, the conductive material containing the above-mentioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten, indium zinc oxide containing tungsten, indium oxide containing titanium, indium tin oxide containing titanium, indium zinc oxide, and indium tin oxide with added silicon may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the metal oxide in which a channel is formed may be captured. Alternatively, hydrogen introduced from an outer insulating layer may be captured.

[0206] 8A to 16E, an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Here, the case of manufacturing the semiconductor device illustrated in FIGS. 1A to 1E will be described as an example.

[0207] (A) in each figure shows a plan view. Furthermore, (B) in each figure shows a cross-sectional view of the portion indicated by the dashed-dotted line A-B in (A) of each figure. Furthermore, (C) in each figure shows a cross-sectional view of the portion indicated by the dashed-dotted line C-D in (A) of each figure. Furthermore, (D) in each figure shows a cross-sectional view of the portion indicated by the dashed-dotted line E-F in (A) of each figure. Furthermore, (E) in each figure shows a perspective view.

[0208] In the following, an insulating material for forming an insulating layer, a conductive material for forming a conductive layer, or a semiconductor material for forming a semiconductor layer can be formed by appropriately using a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0209] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source; DC (Direct Current) sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is preferably used for film formation using an insulating target. DC sputtering is mainly used when forming films using conductive targets. In addition to forming conductive films, DC sputtering can also form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when forming films of compounds such as oxides, nitrides, and carbides by reactive sputtering.

[0210] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (photo-CVD), which uses light. They can also be further classified into metal CVD (MCVD) and MOCVD, depending on the source gas used.

[0211] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, the thermal CVD method is a film formation method that can reduce plasma damage to the workpiece because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, the thermal CVD method does not cause plasma damage during film formation, so films with fewer defects can be obtained.

[0212] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0213] The CVD and ALD methods differ from sputtering methods in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as the CVD method, which have a faster film formation rate.

[0214] Furthermore, the CVD method allows deposition of a film of any composition by adjusting the flow rate ratio of the source gases. For example, the CVD method allows deposition of a film with a continuously changing composition by changing the flow rate ratio of the source gases during deposition. When deposition is performed while changing the flow rate ratio of the source gases, the time required for deposition can be shortened compared to deposition using multiple deposition chambers because no time is required for transport or pressure adjustment. Therefore, the productivity of semiconductor devices can be improved in some cases.

[0215] First, in the steps shown in FIGS. 8A to 8E, a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate.

[0216] The substrate may be a substrate having heat resistance sufficient to withstand at least the subsequent heat treatment.

[0217] An inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used as the insulating layer 11. The insulating layer 11 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. If the surface on which the insulating layer 11 is to be formed is not flat, a planarization process may be performed after the insulating layer 11 is formed so that the upper surface of the insulating layer 11 becomes flat.

[0218] 8A to 8E, an insulating layer 43 and conductive layers 24a and 24b embedded in the insulating layer 43 are formed on the insulating layer 11. Then, in the steps shown in FIG.

[0219] For example, a conductive film that will become the conductive layers 24 a and 24 b is first formed, and unnecessary regions are removed by etching using photolithography to form the conductive layers 24 a and 24 b. Subsequently, an insulating film that will become the insulating layer 43 is formed, and then planarization treatment is performed using a CMP method or the like so that the top surfaces of the conductive layers 24 a and 24 b are exposed, thereby forming the insulating layer 43.

[0220] The conductive layers 24a and 24b may be formed by depositing an insulating layer 43 on the insulating layer 11, forming openings in the insulating layer 43 at positions where the conductive layers 24a and 24b are provided, depositing a conductive film that will become the conductive layers 24a and 24b, and performing a planarization process so that the top surface of the insulating layer 43 is exposed.

[0221] 8A to 8E, an insulating layer 44 is formed on the conductive layer 24a, the conductive layer 24b, and the insulating layer 43. The insulating layer 44 is formed using an insulating material different from that of the insulating layer 41 to be formed later. The insulating layer 44 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0222] Subsequently, in the steps shown in FIGS. 8A to 8E, an insulating film 41A, which will later become the insulating layer 41, is formed on the insulating layer 44.

[0223] The insulating film 41A is preferably formed by a deposition method such as a sputtering method or a plasma CVD method. Since the insulating layer 41 is in contact with the oxide semiconductor layer 21 formed in a later step, the use of a sputtering method in particular eliminates the need for hydrogen in the deposition gas, and therefore the insulating layer 41 can have an extremely low hydrogen content. Therefore, supply of hydrogen to the oxide semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 10 can be stabilized.

[0224] Furthermore, since the insulating layer 41 is in contact with the channel formation region of the oxide semiconductor layer 21, it is preferable to use an oxide insulating film for the insulating film 41A. In particular, it is preferable to use an oxide insulating film that releases oxygen when heated. It is preferable to use an oxide insulating film such as silicon oxide or silicon oxynitride as the insulating film 41A.

[0225] Subsequently, heat treatment may be performed. The heat treatment is preferably performed at a temperature of 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, and then in an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher to compensate for desorbed oxygen. By performing the above heat treatment, impurities such as water and hydrogen contained in the insulating film 41A or the like can be reduced before the formation of an oxide semiconductor film to be a semiconductor layer.

[0226] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is set to 1 ppb (0.001 ppm) or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the insulating layer 41 and the like as much as possible.

[0227] After the insulating film 41A is formed, a process of supplying oxygen may be performed, which allows oxygen to be supplied from the insulating layer 41A to the oxide semiconductor film 21f by heat or the like applied after the oxide semiconductor film 21f is formed.

[0228] Examples of the treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma) in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the insulating layer by forming an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere by sputtering. The formed oxide film may be removed immediately or may be left as it is. Note that the oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３ ), nitrous oxide (N ２ The atmosphere may include a gas containing an oxygen-containing compound such as oxygen (O).

[0229] Note that one or both of the heat treatment and the oxygen supply treatment may be performed after the insulating film 41A is processed into the insulating layer 41 and before the oxide semiconductor film 21f is formed.

[0230] 9A to 9E, openings 28a reaching the conductive layer 24a and openings 28b reaching the conductive layer 24b are formed in the insulating film 41A and the insulating layer 44. The openings 28a and 28b are preferably formed using anisotropic dry etching. This allows the openings 28a and 28b to have a high aspect ratio. The openings 28a and 28b can also be formed using an etching mask. For example, a resist mask can be used as the etching mask. Alternatively, a hard mask may be formed as the etching mask. A material having a high etching rate selectivity relative to the insulating film 41A can be used as the hard mask, and an insulating film, conductive film, or semiconductor film can be used.

[0231] 10A to 10E, a conductive film is formed to have regions located inside the openings 28a and 28b, and a planarization process is performed to expose the top surface of the insulating film 41A, thereby forming the conductive layer 25a inside the openings 28a and the conductive layer 25b inside the openings 28b.

[0232] 5A to 5E, after the openings 28a and 28b are formed, a first conductive film to become conductive layers 27a and 27b and a second conductive film to become conductive layers 26a and 26b are sequentially formed along the upper surface of the insulating film 41A, the side surfaces of the insulating film 41A and the insulating layer 44 at the opening 28a, the side surfaces of the insulating film 41A and the insulating layer 44 at the opening 28b, the upper surface of the conductive layer 24a, and the upper surface of the conductive layer 24b. Subsequently, a third conductive film to become conductive layers 25a and 25b is formed on the second conductive film so as to fill the openings 28a and 28b. Thereafter, the first to third conductive films are planarized until the upper surface of the insulating film 41A is exposed. As a result, conductive layer 27a and conductive layer 26a on conductive layer 27a are formed along the side surfaces of opening 28a in insulating film 41A and insulating layer 44, and the upper surface of conductive layer 24a. Furthermore, conductive layer 27b and conductive layer 26b on conductive layer 27b are formed along the side surfaces of opening 28b in insulating film 41A and insulating layer 44, and the upper surface of conductive layer 24b. Furthermore, conductive layer 25a is formed on conductive layer 26a to fill opening 28a, and conductive layer 25b is formed on conductive layer 26b to fill opening 28b.

[0233] 11A to 11E, an oxide layer 21S having an elongated shape (also referred to as a strip shape) in a plan view is formed on the conductive layer 25a, the conductive layer 25b, and the insulating film 41A. The oxide layer 21S is formed by depositing a film to become the oxide layer 21S and then removing unnecessary regions by photolithography. The oxide layer 21S is formed so as to be in contact with the top surfaces of the conductive layer 25a, the conductive layer 25b, and the top surface of the insulating film 41A in the regions therebetween. Here, the resist mask 35 used in processing the oxide layer 21S is preferably left unremoved because it is also used as an etching mask for the insulating film 41A later.

[0234] The oxide layer 21S has crystals and functions as a seed or nucleus for the crystal growth of the oxide semiconductor film 21f that becomes the oxide semiconductor layer 21.

[0235] 12A to 12E, the insulating film 41A is etched away from the resist mask 35 and the oxide layer 21S, forming the insulating layer 41. The resist mask 35 is then removed. The insulating film 41A is etched using an anisotropic dry etching method, which allows the side surfaces of the insulating layer 41 to be processed substantially perpendicular to the surface on which the insulating layer 41 is to be formed. This is preferable because it allows the insulating layer 41 to have a high aspect ratio. Here, using a material with a high etching selectivity to the insulating film 41A for the insulating layer 44 is preferable because it prevents a portion of the insulating layer 44 from being removed during the formation of the insulating layer 41.

[0236] 13A to 13E , an oxide semiconductor film 21f is formed to cover the conductive layer 25a, the conductive layer 25b, the insulating layer 41, and the oxide layer 21S. The oxide semiconductor film 21f can be formed by an ALD method or a sputtering method, but the ALD method is preferable because it has higher coverage than the sputtering method and can satisfactorily cover the side surfaces of the insulating layer 41, the conductive layer 25a, and the conductive layer 25b.

[0237] By performing heat treatment during or after the formation of the oxide semiconductor film 21f, or both, crystal growth can proceed using the crystals contained in the oxide layer 21S as crystal nuclei, thereby forming the oxide semiconductor film 21f with high crystallinity. Note that the above description can be referred to for the method of heat treatment.

[0238] When the oxide semiconductor film 21f is formed by the ALD method, a first precursor and a first oxidizing agent can be used. The first precursor preferably contains indium. In this case, an indium oxide film is formed as the oxide semiconductor film 21f. That is, an oxide film containing a single element other than oxygen is formed. Note that it is preferable to use a thermal ALD method as the ALD method.

[0239] Examples of precursors that can be used that contain indium include trimethylindium, triethylindium, ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, and dimethyl(2-propanolato)indium.

[0240] Alternatively, an inorganic precursor containing no hydrocarbon may be used as the indium-containing precursor. Examples of the inorganic precursor containing indium include halogen-based indium compounds such as trifluoroindium (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide). Indium trichloride has a decomposition temperature of approximately 500°C to 700°C. Therefore, by using indium trichloride, film formation can be performed by the ALD method while heating the substrate at approximately 400°C to 600°C, for example, at 500°C.

[0241] In the method for forming the oxide semiconductor film 21f, it is preferable to use a precursor having a low impurity concentration, i.e., a high purity. For example, by using a precursor having a purity of 3N (99.9%) or more, preferably 4N (99.99%) or more, more preferably 5N (99.999%) or more, and even more preferably 6N (99.9999%) or more, the impurities in the oxide semiconductor film 21f can be sufficiently reduced.

[0242] The gallium content and aluminum content of the indium-containing precursor are each preferably 1000 ppm or less, more preferably 500 ppm or less, even more preferably 100 ppm or less, still more preferably 50 ppm or less, still more preferably 10 ppm or less, and still more preferably 1 ppm or less. By using a precursor with a low gallium content, the gallium concentration in the oxide semiconductor film 21f can be reduced, thereby improving the reliability of the transistor. Furthermore, by using a precursor with a low aluminum content, the aluminum concentration in the oxide semiconductor film 21f can be reduced, thereby improving the crystallinity of the oxide semiconductor film 21f.

[0243] As the first oxidant, ozone (O ３ ), oxygen (O ２ ), water (H ２ O), hydrogen peroxide (H ２ O ２ ) or the like can be used. The first oxidant preferably contains at least one of ozone and oxygen. By using ozone, oxygen, or the like that does not contain hydrogen as the first oxidant, the amount of hydrogen mixed into the insulating layer 41 can be reduced. Note that the first oxidant can contain at least one of water and hydrogen peroxide. In this way, the oxide semiconductor film 21f with low crystallinity can be formed.

[0244] After forming the oxide semiconductor film 21f with low crystallinity, the oxide layer 21S is used as a crystal nucleus and crystallized by heat treatment, whereby the oxide semiconductor film 21f having a polycrystalline structure with large crystal grains or a single-crystalline structure can be formed.

[0245] It is particularly preferable to use indium oxide as the oxide semiconductor film 21f.

[0246] In the oxide semiconductor film 21f formed to cover the oxide layer 21S, crystal growth starts from the region in contact with the oxide layer 21S and proceeds downward along the side surface of the insulating layer 41. The crystal growth can occur during the formation of the oxide semiconductor film 21f, during a heat treatment after the formation of the oxide semiconductor film 21f, or both. This allows the oxide semiconductor film 21f to be formed so that the crystal orientations of the crystal grains are aligned or approximately aligned in any region.

[0247] The oxide semiconductor film 21f formed in this manner can have a polycrystalline structure with large crystal grains or a single-crystalline structure. This reduces the number of crystal grain boundaries located on the current path in the channel formation region, thereby realizing a transistor 10 capable of passing a larger current. In particular, since the oxide semiconductor film 21f has larger crystal grains than a film not using the oxide layer 21S, the channel formation region can be formed with a single crystal grain, and the oxide semiconductor film 21f can be considered to be substantially single-crystalline in the channel formation region. A single-crystalline oxide semiconductor film 21f is more preferable because no crystal grain boundaries exist on the current path in the channel formation region.

[0248] Note that the oxide semiconductor film 21f may be formed using a metal oxide film other than indium oxide, as described above. Even in this case, the oxide semiconductor film 21f can be formed with high crystallinity.

[0249] The oxide semiconductor film 21f can also be formed by a sputtering method. The oxide semiconductor film 21f can be formed by a sputtering method using a metal oxide target. In this case, it is preferable to form the film under conditions that make crystallization as difficult as possible. For example, the substrate temperature during film formation is set to a temperature between room temperature and 100°C, preferably between room temperature and 80°C, and more preferably between room temperature and 50°C, so that an amorphous oxide semiconductor film 21f can be formed. In particular, it is preferable to form the film without heating the substrate. Furthermore, conditions that make crystallization difficult can also be achieved by reducing the oxygen content in the film formation gas. For example, the ratio of oxygen gas (O ２ The ratio of the flow rate of the gas) can be set to 0% or more and 10% or less, preferably 0% or more and 5% or less.

[0250] Immediately after the oxide semiconductor film 21f with low crystallinity is formed, a crystalline region reflecting the crystal orientation of the oxide layer 21S can be formed in the region in contact with the oxide layer 21S. By subsequently performing heat treatment, crystal growth progresses, and the oxide semiconductor film 21f with high crystallinity can be formed.

[0251] 14A to 14E , a portion of the oxide semiconductor film 21f is removed by photolithography. Specifically, after forming a resist mask, a portion of a region of the oxide semiconductor film 21f that is in contact with the top surface of the insulating layer 44 is removed by etching. This forms the oxide semiconductor layer 21 that covers the conductive layer 25a, the conductive layer 25b, the insulating layer 41, and the oxide layer 21S. The oxide semiconductor layer 21 can be formed to have a region that is in contact with the top surface of the insulating layer 44. After the oxide semiconductor layer 21 is formed, the resist mask is removed.

[0252] 15A to 15E, an insulating layer 42 is formed on the oxide semiconductor layer 21 and the insulating layer 44. The insulating layer 42 can be formed using a method that can be used to form the insulating film 41A. After the insulating layer 42 is formed, it is preferable to planarize the upper surface of the insulating layer 42.

[0253] 16A to 16E , a portion of the insulating layer 42 is removed by etching to form an opening 20 that reaches the oxide semiconductor layer 21 and the insulating layer 44. The opening 20 is preferably formed by an anisotropic dry etching method.

[0254] 1A to 1E, an insulating layer 22 is formed so as to cover the inside of the opening 20 and the upper surface of the insulating layer 42. The insulating layer 22 is preferably formed by the ALD method, which has high coverage.

[0255] Subsequently, a conductive film is formed so as to fill the opening 20, and then a planarization process is performed until the upper surface of the insulating layer 42 is exposed. As a result, a conductive layer 23 is formed on the insulating layer 22 so as to fill the opening 20.

[0256] Through the above steps, the transistor 10 shown in FIGS. 1A to 1E can be manufactured.

[0257] <Configuration Example 2 of Semiconductor Device> A semiconductor device including the above-described transistor 10 can realize various circuits by combining it with a Si transistor. A configuration including a Si transistor and the transistor 10 will be described below.

[0258] 17 and 18 illustrate examples of the structure of a semiconductor device in which a transistor 90, which is a Si transistor, and a transistor 10, which is an OS transistor, are stacked. Fig. 17 illustrates an example of a cross-sectional structure of the transistor 90 and the transistor 10 in the channel length direction. Fig. 18 illustrates an example of a cross-sectional structure of the transistor 90 and the transistor 10 in the channel width direction.

[0259] 17 and 18 includes a functional layer 16 in which a transistor 90 is provided and a functional layer 15 in which a transistor 10 is provided. The functional layer 15 can be provided on the functional layer 16.

[0260] The transistor 90 is provided on a substrate 91 and includes a conductive layer 94 functioning as a gate electrode, an insulating layer 93 functioning as a gate insulating layer, a semiconductor region 92 formed of a part of the substrate 91, a low-resistance region 95a functioning as one of a source region and a drain region, and a low-resistance region 95b functioning as the other of the source region and the drain region. The transistor 90 may be either a P-type or an N-type.

[0261] 18, a transistor 90 has a semiconductor region 92 (part of a substrate 91) in which a channel is formed, which has a convex shape (fin shape). A conductive layer 94 is provided to cover the side and top surfaces of the semiconductor region 92 with an insulating layer 93 interposed therebetween. Such a transistor 90 is also called a FIN-type transistor because it utilizes the convex portions of the semiconductor substrate. An example having three convex portions is shown here.

[0262] It is preferable to have a wiring layer 98 in which interlayer insulating layers and wiring layers are alternately stacked between the functional layer 16 in which the transistor 90 is provided and the functional layer 15 in which the transistor 10 is provided. Fig. 17 shows an example in which the low-resistance region 95b of the transistor 90 is connected to the conductive layer 24a provided in the functional layer 15 via a wiring and a plug.

[0263] 17 illustrates the transistor illustrated in FIG. 5B as an example of the transistor 10. In the example illustrated in FIG. 17, an insulating layer 32 is provided between the insulating layer 44 and the insulating layer 42. An insulating layer 45 is provided on the transistor 10, and an insulating layer 46 is provided on the insulating layer 45. The insulating layer 45 functions as a protective layer and prevents impurities such as hydrogen from diffusing from outside the transistor 10. The insulating layer 46 functions as an interlayer insulating layer.

[0264] 19 shows an example in which a memory device is further stacked above the transistor 10. The memory device has a plurality of memory cells 40 arranged in a matrix.

[0265] 19 includes a functional layer 16 having a transistor 90, a functional layer 15 having a transistor 10, and a functional layer 17 having a memory cell 40. The functional layer 15 can be provided on the functional layer 16. The functional layer 17 can be provided on the functional layer 15.

[0266] The memory cell 40 has a configuration in which a capacitor element 60 and a transistor 50 are stacked. The memory cell 40 functions as a memory cell of, for example, a DRAM (Dynamic Random Access Memory).

[0267] The capacitor 60 includes a conductive layer 61, a conductive layer 63, and an insulating layer 62 sandwiched between them. The conductive layer 61 has a region that functions as one electrode of the capacitor 60. The conductive layer 63 has a region that functions as the other electrode of the capacitor 60. The insulating layer 62 has a region that functions as a dielectric of the capacitor 60. The insulating layer 62 can also be an insulating layer that exhibits ferroelectricity.

[0268] An insulating layer 71 and a conductive layer 64 embedded in the insulating layer 71 are provided on the insulating layer 46. The conductive layer 64 functions as wiring. An insulating layer 72 having an opening reaching the conductive layer 64 is provided on the conductive layer 64. Inside the opening of the insulating layer 72, the conductive layer 61, the insulating layer 62, and the conductive layer 63 are stacked. The conductive layer 61 is provided in contact with the conductive layer 64 inside the opening of the insulating layer 72, and the conductive layer 63 is provided to fill the opening. The conductive layer 61 and the insulating layer 62 have regions located on the insulating layer 72 and are provided in common to the multiple capacitor elements 60. The conductive layer 63 has a region embedded in the insulating layer 73 located on the insulating layer 62.

[0269] In the transistor 50, the source electrode and the drain electrode are located at different heights, and a current flows in the height direction of the semiconductor layer. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, one embodiment of the present invention can be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0270] The transistor 50 includes a semiconductor layer 51, a conductive layer 54, a conductive layer 55, an insulating layer 52, and a conductive layer 53. The conductive layer 54 has a region that functions as one of the source electrode and the drain electrode of the transistor 50. The conductive layer 55 has a region that functions as the other of the source electrode and the drain electrode of the transistor 50. The insulating layer 52 has a region that functions as a gate insulating layer of the transistor 50. The conductive layer 53 has a region that functions as a gate electrode of the transistor 50.

[0271] The semiconductor layer 51 of the transistor 50 is preferably made of a metal oxide (oxide semiconductor) that exhibits semiconductor characteristics. For example, silicon, a typical semiconductor material, needs to be doped with impurities that function as donors or acceptors to form source and drain regions. However, in the vertical transistor of one embodiment of the present invention, it may be difficult to dope impurities into the semiconductor layer with high precision because the source and drain regions are different in height and the channel formation region is located vertically relative to the substrate surface. On the other hand, an oxide semiconductor can form a low-resistance region without doping with such impurities and can provide good connection with the source and drain electrodes. Therefore, a transistor having a three-dimensional structure as in one embodiment of the present invention can be manufactured with high yield.

[0272] The conductive layer 54 is provided in contact with the upper surface of the conductive layer 63. An insulating layer 74 is provided on the conductive layer 54, and a conductive layer 55 is provided on the insulating layer 74. The conductive layer 55 and the insulating layer 74 have openings that reach the conductive layer 55. The semiconductor layer 51 has a region in contact with the conductive layer 55, a region in contact with the side surface of the insulating layer 74 inside the opening of the insulating layer 74, and a region in contact with the conductive layer 54. The insulating layer 52 is provided to cover the semiconductor layer 51. The conductive layer 53 is provided on the insulating layer 52. The semiconductor layer 51 and the insulating layer 52 have regions located on the insulating layer 74 and are provided in common to multiple transistors 10. The conductive layer 53 has a region embedded in the insulating layer 75 on the insulating layer 52. In addition, a conductive layer 56 in contact with the conductive layer 53 is provided on the insulating layer 75. The conductive layer 56 is connected to the conductive layers 53 of the multiple transistors 10 arranged in the depth direction.

[0273] An insulating layer 76 can be provided on the conductive layer 56 and the insulating layer 75. An insulating layer 77 can be provided on the insulating layer 76. The insulating layer 76 functions as an interlayer insulating layer, and the insulating layer 77 functions as a protective layer. The stacking order of the insulating layer 76 and the insulating layer 77 may be changed.

[0274] For example, a driver circuit, an arithmetic circuit, a control circuit, or the like can be configured using the transistors 10 and 90, and a memory device having memory cells 40 can be stacked above the driver circuit, and the memory device can be configured to operate at high speed because the wiring length can be significantly shortened.

[0275] The memory cells 40 may be stacked. For example, two, four, eight, or sixteen or more layers may be stacked. The greater the number of stacked memory cells 40, the greater the storage capacity.

[0276] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0277] Embodiment 2 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0278] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0279] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0280] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 20A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 20B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0281] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 20B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 20A (see Non-Patent Document 2). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 20A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 20A.

[0282] 20A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0283] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0284] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0285] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0286] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 20A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0287] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0288] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 20B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei finally occurs, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and there is a possibility that the transistor will no longer function. On the other hand, in indium oxide, as shown in FIG. 20A, the lower the carrier concentration, the larger the hole mobility. When Ef = Ei finally occurs, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0289] Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. The normally-off state can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to the state in which the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of the transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0290] In addition, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef = Ei can be obtained.

[0291] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0292] The above film configuration can also be considered as a stacked structure of a film (e.g., a silicon oxide film) capable of supplying oxygen to the indium oxide film from the indium oxide film side, a film (e.g., a hafnium oxide film) capable of gettering hydrogen, and a film (e.g., a silicon nitride film) that suppresses the penetration of oxygen and hydrogen. With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Furthermore, hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0293] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0294] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0295] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0296] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0297] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0298] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can cause a decrease in field-effect mobility. These impurities can also inhibit the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and the like are elements that can be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0299] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0300] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0301] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 20C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film.Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0302] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0303] Furthermore, as shown in FIG. 20C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with the oxygen contained in the film and is released as water molecules.

[0304] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0305] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0306]

[0307] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0308] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit lattice vector or the lattice constant of the crystal of the seed layer.

[0309] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0310] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0311] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a crystalline structure is IGZO. It should be noted that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystal. However, when comparing indium oxide and silicon in terms of whether they can be formed as single crystals on an insulating film, they have different properties.

[0312] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0313] Embodiment 3 In this embodiment, an example of a CMOS circuit configuration using a Si transistor and an OS transistor according to one embodiment of the present invention will be described.

[0314] Si transistors have higher field-effect mobility and faster operation speed than OS transistors. Furthermore, OS transistors have significantly lower off-state current than Si transistors. In particular, OS transistors that use indium oxide for the semiconductor layer in which a channel is formed have significantly lower off-state current and higher field-effect mobility comparable to that of Si transistors. A CMOS circuit that consumes less power and operates at high speed can be realized by using an OS transistor and a Si transistor in combination.

[0315] In this embodiment, examples of circuits using Si transistors and OS transistors will be described, including a NOT circuit, a NOR circuit, and a NAND circuit, which are logic circuits. Also, examples of circuits using Si transistors and OS transistors will be described, including a buffer circuit, a ring oscillator, a delay flip-flop (DFF) circuit, a shift register circuit using a DFF circuit, a selector, and an analog switch.

[0316] [NOT Circuit] Fig. 21A is a circuit diagram showing an example of the configuration of a NOT circuit (NOT). A NOT circuit is also called an inversion circuit, an inverter circuit, etc. Fig. 21B shows the circuit symbol of a NOT circuit. Fig. 21C is a timing chart explaining the operation of the NOT circuit.

[0317] The NOT circuit shown in FIG. 21A includes a transistor Tr11 and a transistor Tr12. The transistor Tr11 is a Si transistor functioning as a p-channel transistor, and the transistor Tr12 is an OS transistor functioning as an n-channel transistor. A potential H (e.g., a high power supply potential VDD) is supplied to one of the source and the drain of the transistor Tr11. The other of the source and the drain of the transistor Tr11 is connected to one of the source and the drain of the transistor Tr12 and to a terminal Y. A potential L (e.g., a low power supply potential VSS) is supplied to the other of the source and the drain of the transistor Tr12. The gates of the transistors Tr11 and Tr12 are connected to a terminal A.

[0318] In this specification and the like, a high power supply potential VDD (hereinafter simply referred to as "VDD") refers to a power supply potential that is higher than a low power supply potential VSS (hereinafter simply referred to as "VSS"). Also, the low power supply potential VSS refers to a power supply potential that is lower than the high power supply potential VDD.

[0319] The potential H is a potential that turns on an n-channel transistor and turns off a p-channel transistor. The potential L is a potential that turns off an n-channel transistor and turns on a p-channel transistor. Therefore, the potential H is higher than the potential L. The potential H may be equal to VDD, and the potential L may be equal to VSS.

[0320] 21A, terminal A functions as an input terminal, and terminal Y functions as an output terminal. When a potential H is input to terminal A of the NOT circuit, a potential L is output from terminal Y, and when a potential L is input to terminal A, a potential H is output from terminal Y (see FIG. 21C).

[0321] As shown in FIG. 21C , the NOT circuit has a function of correcting an input signal distorted by wiring resistance, parasitic capacitance, noise, etc., to a signal that is distorted or has reduced distortion, and outputting the corrected signal (also referred to as a "waveform shaping function"). The NOT circuit also has a function of amplifying the voltage amplitude of the input signal and outputting the signal. The output of the NOT circuit is supplied to a load such as a capacitance element Cx and a transistor Trx. Since power is supplied to the output of the NOT circuit via transistor Tr11 or transistor Tr12, the ability to drive a load connected to the output can be improved. The NOT circuit has a function of improving the ability to drive a load (also referred to as a "driving force improvement function").

[0322] [NOR Circuit] Fig. 22A is a circuit diagram showing a configuration example of a two-input, one-output NOR circuit (NOR). Fig. 22B shows a circuit symbol of the NOR circuit. The NOR circuit shown in Fig. 22A includes transistors Tr21, Tr22, Tr23, and Tr24. Si transistors functioning as p-channel transistors are used as the transistors Tr21 and Tr22, and OS transistors functioning as n-channel transistors are used as the transistors Tr23 and Tr24.

[0323] 22A , a potential H is supplied to one of the source and drain of transistor Tr21. The other of the source and drain of transistor Tr21 is connected to one of the source and drain of transistor Tr22. The other of the source and drain of transistor Tr22 is connected to one of the source and drain of transistor Tr23, one of the source and drain of transistor Tr24, and terminal Y. A potential L is supplied to the other of the source and drain of transistor Tr23 and the other of the source and drain of transistor Tr24.

[0324] The gate of the transistor Tr21 is connected to the gate of the transistor Tr23 and the terminal A. The gate of the transistor Tr22 is connected to the gate of the transistor Tr24 and the terminal B.

[0325] 22A and 22B has a function of outputting a potential H from a terminal Y when a potential L is input to both a terminal A and a terminal B. In addition, the NOR circuit has a function of outputting a potential L from a terminal Y when a potential H is input to one or both of the terminals A and B.

[0326] Furthermore, as shown in FIG. 22C, an OR circuit can be realized by connecting the input of a NOT circuit to the output of a NOR circuit.

[0327] [NAND Circuit] Fig. 22D is a circuit diagram showing a configuration example of a two-input, one-output NAND circuit (NAND). Fig. 22E shows a circuit symbol of the NAND circuit. The NAND circuit shown in Fig. 22D includes transistors Tr31, Tr32, Tr33, and Tr34. Si transistors functioning as p-channel transistors are used as the transistors Tr31 and Tr32, and OS transistors functioning as n-channel transistors are used as the transistors Tr33 and Tr34.

[0328] 22D , a potential H is supplied to one of the source and drain of transistor Tr31 and one of the source and drain of transistor Tr32. The other of the source and drain of transistor Tr31 and the other of the source and drain of transistor Tr32 are connected to one of the source and drain of transistor Tr33 and terminal Y. The other of the source and drain of transistor Tr33 is connected to one of the source and drain of transistor Tr34. A potential L is supplied to the other of the source and drain of transistor Tr34.

[0329] The gate of the transistor Tr31 is connected to the gate of the transistor Tr34 and the terminal B. The gate of the transistor Tr32 is connected to the gate of the transistor Tr33 and the terminal A.

[0330] 22D and 22E has a function of outputting a potential L from a terminal Y when a potential H is input to both a terminal A and a terminal B. In addition, the NAND circuit has a function of outputting a potential H from a terminal Y when a potential L is input to one or both of the terminals A and B.

[0331] Furthermore, as shown in FIG. 22F, an AND circuit can be realized by combining a NAND circuit with a NOT circuit.

[0332] [Buffer Circuit] Figure 23A shows the circuit symbol for a buffer circuit. A buffer circuit (BF) can be realized by connecting an even number of NOT circuits in series. Figure 23B shows an example configuration of a buffer circuit made up of two NOT circuits. Figure 23C is a timing chart explaining the operation of the buffer circuit.

[0333] The buffer circuit does not perform a logical operation, but outputs the same value as the input logical value. Specifically, when a potential H is input, a potential H is output, and when a potential L is input, a potential L is output. Similarly to the NOT circuit, the buffer circuit has a waveform shaping function (see FIG. 23C ) and a driving force improving function. By using the buffer circuit, it is possible to correct a distorted signal and improve the driving force for a load without inverting the signal.

[0334] [Ring Oscillator] A ring oscillator (also called an "oscillating circuit") can be realized by connecting an odd number of NOT circuits in a ring. FIG. 23D shows an example of the configuration of a ring oscillator (RO) made up of NOT circuits. FIG. 23D shows a ring oscillator made up of five NOT circuits. A ring oscillator has the function of generating (oscillating) an AC signal when power is supplied. FIG. 23E is a diagram illustrating the oscillation of a ring oscillator.

[0335] Generally, the first of n NOT circuits (n is an odd number equal to or greater than 3) that make up a ring oscillator is sometimes called the "first stage." The nth circuit is sometimes called the "nth stage." A ring oscillator made up of NOT circuits has a configuration in which the output of each NOT circuit is connected to the input of the NOT circuit in the next stage. The output of the nth NOT circuit is connected to the input of the first NOT circuit.

[0336] Furthermore, in a NOT circuit, a certain delay time occurs before the inverted signal of the input signal is output. Since n is an odd number, the signal output from the first stage is delayed by n stages before being input to the first stage. This causes the ring oscillator to oscillate. That is, an AC signal is supplied to terminal Y shown in FIG. 23C. By using a ring oscillator, for example, a clock signal can be generated within the circuit. Furthermore, the delay time of the NOT circuit can be determined by measuring the oscillation frequency of the ring oscillator.

[0337] [DFF Circuit] Fig. 24A is a circuit diagram showing an example of the configuration of a D flip-flop circuit (DFF). Fig. 24B shows the circuit symbol of the D flip-flop circuit. The DFF has a clock signal input terminal CK, an input terminal D, and an output terminal Q.

[0338] 24A includes transistors Tr41 to Tr49, transistors Tr51 to Tr59, transistor Tr61, transistor Tr62, transistor Tr71, and transistor Tr72. Si transistors functioning as p-channel transistors are used as the transistors Tr41 to Tr49, transistors Tr61, and transistor Tr62, and OS transistors functioning as n-channel transistors are used as the transistors Tr51 to Tr59, transistors Tr71, and transistor Tr72.

[0339] A potential H is supplied to one of the source and drain of transistor Tr41, one of the source and drain of transistor Tr42, one of the source and drain of transistor Tr44, one of the source and drain of transistor Tr46, one of the source and drain of transistor Tr48, one of the source and drain of transistor Tr61, and one of the source and drain of transistor Tr62.

[0340] The other of the source and drain of transistor Tr41 is connected to one of the source and drain of transistor Tr51, the gate of transistor Tr44, the gate of transistor Tr46, the gate of transistor Tr53, and the gate of transistor Tr59. The gate of transistor Tr41 is connected to clock signal input terminal CK, the gate of transistor Tr51, the gate of transistor Tr42, the gate of transistor Tr48, the gate of transistor Tr55, and the gate of transistor Tr57.

[0341] The other of the source and drain of transistor Tr42 is connected to one of the source and drain of transistor Tr43. The other of the source and drain of transistor Tr44 is connected to one of the source and drain of transistor Tr45. The other of the source and drain of transistor Tr43 is connected to the other of the source and drain of transistor Tr45, one of the source and drain of transistor Tr52, one of the source and drain of transistor Tr54, the gate of transistor Tr61, and the gate of transistor Tr71. The gate of transistor Tr43 is connected to the gate of transistor Tr52 and input terminal D.

[0342] The other of the source and drain of transistor Tr52 is connected to one of the source and drain of transistor Tr53. The other of the source and drain of transistor Tr54 is connected to one of the source and drain of transistor Tr55. The gate of transistor Tr45 is connected to the gate of transistor Tr54, the other of the source and drain of transistor Tr61, one of the source and drain of transistor Tr71, the gate of transistor Tr47, and the gate of transistor Tr56. The other of the source and drain of transistor Tr46 is connected to one of the source and drain of transistor Tr47. The other of the source and drain of transistor Tr48 is connected to one of the source and drain of transistor Tr49.

[0343] The other of the source and drain of the transistor Tr47 is connected to one of the source and drain of the transistor Tr56, the other of the source and drain of the transistor Tr49, one of the source and drain of the transistor Tr58, the gate of the transistor Tr62, and the gate of the transistor Tr72. The other of the source and drain of the transistor Tr62 is connected to one of the source and drain of the transistor Tr72, the gate of the transistor Tr49, the gate of the transistor Tr58, and the output terminal Q.

[0344] The other of the source and drain of transistor Tr56 is connected to one of the source and drain of transistor Tr57. The other of the source and drain of transistor Tr58 is connected to one of the source and drain of transistor Tr59. A potential L is supplied to the other of the source and drain of transistor Tr51, the other of the source and drain of transistor Tr53, the other of the source and drain of transistor Tr55, the other of the source and drain of transistor Tr71, the other of the source and drain of transistor Tr57, the other of the source and drain of transistor Tr59, and the other of the source and drain of transistor Tr72.

[0345] 24A and 24B has a function in which information (potential) supplied to input terminal D is written to DFF at the timing when the signal input to clock signal input terminal CK changes from potential L to potential H, and the information is held until the next timing when the signal input to clock signal input terminal CK changes from potential L to potential H. In addition, a signal (potential H or potential L) based on the information held by DFF is always output from output terminal Q.

[0346] FIG. 25A is a block diagram showing an example configuration of a shift register circuit (SR). The SR includes multiple DFFs. In this specification, the first-stage (first) DFF is referred to as "DFF[1]," and the potential (data) output from the output terminal Q of DFF[1] is referred to as "DATA OUT[1]." FIG. 25A shows a block diagram of an SR including four stages (four) of DFFs (DFF[1] to DFF[4]). In FIG. 25A, the data output from the output terminals Q of DFF[1] to DFF[4] are referred to as DATA OUT[1] to DATA OUT[4].

[0347] 25B is a timing chart illustrating the operation of the SR. The clock signal CLK1 is input to the clock signal input terminal CK of the odd-numbered DFF. The inverted signal of the clock signal CLK1 is input to the clock signal input terminal CK of the even-numbered DFF.

[0348] A pulse signal SPL is input to the input terminal D of DFF[1]. DFF[1] holds a signal corresponding to the input signal SPL in synchronization with the clock signal CLK1 and outputs it as data OUT[1]. Note that data OUT[1] has a value corresponding to the data held by DFF[1].

[0349] Furthermore, data OUT[1] is input to input terminal D of DFF[2]. DFF[2] holds a signal corresponding to the input data OUT[1] in synchronization with clock signal CLK1 and outputs it as data OUT[2]. Similarly, data OUT[2] is input to input terminal D of DFF[3], and data OUT[3] is input to input terminal D of DFF[4].

[0350] In this way, the SR has the function of sequentially transferring the input signal SPL to the subsequent DFF in synchronization with the clock signal CLK1. The SR also has the function of sequentially switching the potential of the data OUT output from the multiple DFFs in synchronization with the clock signal CLK1.

[0351] Furthermore, it is preferable to provide an overlapping structure between a Si transistor and an OS transistor. By providing an overlapping structure between a Si transistor and an OS transistor, a circuit with a small occupancy area can be realized. Furthermore, an OS transistor operates stably even in a high-temperature environment and exhibits little fluctuation in characteristics. Therefore, the OS transistor is less susceptible to the heat generated by the Si transistor and can operate stably. Furthermore, by providing an overlapping structure between a Si transistor and an OS transistor, the connection distance between them can be made extremely short. As a result, wiring resistance and parasitic capacitance are reduced, enabling the circuit to operate at high speed. Furthermore, the power consumption of the circuit is reduced.

[0352] [Selector] A selector (also referred to as a "selection circuit") can be realized by using a plurality of transistors. Figures 26A and 26B are circuit diagrams showing configuration examples of a selector (SEL).

[0353] 26A shows an example in which selectors are provided between a power supply PW and a circuit 1001, a circuit 1002, and a circuit 1003. The selectors shown in Fig. 26A include a transistor Tr81, a transistor Tr82, and a transistor Tr83. The transistors Tr81, Tr82, and Tr83 each function as a switch.

[0354] 26A , one of the source and drain of the transistor Tr81, one of the source and drain of the transistor Tr82, and one of the source and drain of the transistor Tr83 are connected to a power supply PW via a wiring PL. The other of the source and drain of the transistor Tr81 is connected to a circuit 1001. The other of the source and drain of the transistor Tr82 is connected to a circuit 1002. The other of the source and drain of the transistor Tr83 is connected to a circuit 1003.

[0355] That is, the circuit 1001 is connected to the power supply PW via a transistor Tr81, the circuit 1002 is connected to the power supply PW via a transistor Tr82, and the circuit 1003 is connected to the power supply PW via a transistor Tr83. The transistors Tr81 to Tr83 function as power transistors that control the power supply to the circuits 1001 to 1003. OS transistors are suitable as power transistors because they have a higher withstand voltage between the source and drain than Si transistors.

[0356] Furthermore, by providing a selector between the circuit 1001, the circuit 1002, and the circuit 1003 and the power supply PW, power gating can be performed to supply power to circuits that are operating and stop the power supply to circuits that are not operating.

[0357] FIG. 26B shows an example in which selectors are provided between the circuit 1001, the circuit 1002, and the circuit 1003 and the circuit 1100.

[0358] 26B , one of the source and drain of the transistor Tr81, one of the source and drain of the transistor Tr82, and one of the source and drain of the transistor Tr83 are connected to the circuit 1100 through a wiring SL. By using a selector, for example, the supply destination of the output signal of the circuit 1100 can be selected from the circuit 1001, the circuit 1002, and the circuit 1003. Alternatively, it can be selected which of the circuits 1001, 1002, and 1003 the output signal of which is to be supplied to the circuit 1100.

[0359] Furthermore, for example, when a clock signal is supplied from circuit 1100 to circuit 1001, circuit 1002, and circuit 1003, clock gating can be performed to supply a clock signal to a circuit that is operating and stop supplying the clock signal to a circuit that is not operating.

[0360] Furthermore, when transmitting and receiving signals of different polarities between multiple circuits, it is preferable to use analog switches (ASW) as switches provided between the multiple circuits. Fig. 26C is a circuit diagram showing an example of the configuration of an analog switch. The analog switch shown in Fig. 26C has a transistor Tr84 which is a p-channel transistor and a transistor Tr85 which is an n-channel transistor.

[0361] One of the source and drain of transistor Tr84 is connected to one of the source and drain of transistor Tr85 and functions as one of the input terminal and output terminal of the analog switch. The other of the source and drain of transistor Tr84 is connected to the other of the source and drain of transistor Tr85 and functions as the other of the input terminal and output terminal of the analog switch. The gate of transistor Tr84 is connected to terminal A, and the gate of transistor Tr85 is connected to terminal AB.

[0362] 26C shows an example in which one of the input terminal or output terminal of the analog switch is connected to the circuit 1100, and the other of the input terminal or output terminal of the analog switch is connected to the circuit 1001. Furthermore, potentials that are always inverted to each other are supplied to the terminal A and the terminal AB. For example, when the analog switch is turned on, a potential L is supplied to the terminal A, and a potential H is supplied to the terminal AB. Furthermore, when the analog switch is turned off, a potential H is supplied to the terminal A, and a potential L is supplied to the terminal AB.

[0363] By using analog switches as switches, signals with different polarities can be transmitted more reliably. Analog switches can be used in the selectors shown in Figures 26A and 26B.

[0364] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0365] Embodiment 4 In this embodiment, a structural example of a logic circuit including a semiconductor device which is one embodiment of the present invention will be described.

[0366] 27A is a circuit diagram illustrating an example of a logic circuit including a semiconductor device of one embodiment of the present invention, which includes a logic circuit RC1, a logic circuit RC2, a transistor SW1, a transistor SW2, and a transistor SW3.

[0367] The logic circuits RC1 and RC2 have Si transistors fabricated using a CMOS (Complementary MOS) process. The logic circuits RC1 and RC2 are basic logic gates such as NOT, NAND, NOR, AND, and OR. Alternatively, the logic circuits RC1 and RC2 may be circuits such as flip-flops, registers, and shift registers that are combinations of these logic gates. Alternatively, the logic circuits RC1 and RC2 may be large-scale arithmetic circuits that are combinations of multiple of the above circuits.

[0368] For example, in the case of a NOT gate, the logic circuit RC1 outputs, from its output terminal (OUT), the inverted logic of the input data SIN input to its input terminal (IN). Depending on the type of logic gate, there may be multiple input terminals and output terminals. In FIG. 27A, the wiring connected to the output terminal of the logic circuit RC1 is designated as node NodeA.

[0369] In the case of a NOT gate, for example, the logic circuit RC2 outputs, from its output terminal (OUT), the inverted logic of the signal held at node NodeB that is input to its input terminal (IN) as an output signal SOUT. In Fig. 27A, the wiring connected to the input terminal of the logic circuit RC2 is referred to as node NodeB.

[0370] The logic circuits RC1 and RC2 are each connected to a wiring line supplied with a high power supply potential VDD. The logic circuit RC1 is connected to a power supply line supplied with a low power supply potential VSS via a transistor SW1. The logic circuit RC2 is connected to a power supply line supplied with a low power supply potential VSS via a transistor SW2. The output terminal of the logic circuit RC1 is connected to the input terminal of the logic circuit RC2 via a transistor SW3.

[0371] The transistors SW1 to SW3 are the transistors described in the above embodiment, each including indium in an oxide semiconductor layer that serves as a channel formation region. The transistors SW1 to SW2 function as power gating switches. The transistor SW3 functions as a switch that controls conduction between the logic circuits RC1 and RC2. The transistors SW1 to SW3 are turned on or off by control signals SPG1 to SPG3, respectively.

[0372] As described above, a transistor, which is one embodiment of a semiconductor device, has extremely high field-effect mobility comparable to that of polycrystalline silicon and extremely low off-state current. Therefore, when the transistors SW1 and SW2 are used as switches for power gating of the logic circuits, power gating can be achieved for each logic circuit without impairing high-speed operation of the logic circuits. Furthermore, when the transistor SW3 is used as a switch for controlling conduction between the logic circuits, a potential corresponding to data input / output between the logic circuits can be held.

[0373] In the configuration of Figure 27A, partial power gating can be performed without stopping the output signal by performing power gating for each logic circuit and maintaining a potential according to the data input and output between the logic circuits.

[0374] Fig. 27B is a timing chart illustrating the power gating operation of the logic circuits RC1 and RC2 shown in Fig. 27A, showing periods P01 to P06 that illustrate the on / off timing of the transistors SW1 to SW3.

[0375] A period P01 is a period for explaining normal operation. In this operation, all of the transistors SW1 to SW3 are turned on. The logic circuits RC1 and RC2 can obtain output data according to input data.

[0376] Period P02 is a period for cutting off the current path between nodes NodeA and NodeB. During this period, transistor SW3 is switched off. By turning off transistor SW3, the current path between nodes NodeA and NodeB between logic circuits RC1 and RC2 can be cut off. As a result, node NodeB between transistor SW3 and logic circuit RC2 can hold a charge according to the logic of the output terminal of logic circuit RC1.

[0377] Period P03 is a period during which the logic circuit RC1 is power-gated. During this period, the transistor SW1 is switched off. By turning off the transistor SW1, the current path between the power supply lines that provide the power supply potential to the logic circuit RC1 can be cut off. As a result, the logic circuit RC1 is power-gated, and power consumption is reduced. In the logic circuit RC2, a charge corresponding to the signal logic is held at node NodeB, and an output signal SOUT corresponding to that logic can be output.

[0378] FIG. 28A is a circuit diagram showing a schematic representation of period P03. In FIG. 28A, crosses are drawn over the off-state transistors SW1 and SW3, and the potential VDATA corresponding to the charge held at node NodeB is shown. Also in FIG. 28A, the power gating of logic circuit RC1 is shown by a dashed line. As shown in FIG. 28A, the configuration of FIG. 27A enables fine-grained power gating at the logic circuit level. This configuration allows partial power gating of logic circuit RC1 without stopping the output signal SOUT.

[0379] Although the configuration of Figure 27A is illustrated with one logic circuit RC1, multiple logic circuits RC1 may be used. Figure 28B is a schematic diagram of partial power gating when logic circuits RC1A and RC1B corresponding to the logic circuit RC1 of Figure 27A are included. Figure 28B illustrates transistor SW1A, which controls the power gating of logic circuit RC1A, and transistor SW3A, which is located between logic circuit RC2. Figure 28B also illustrates transistor SW1B, which controls the power gating of logic circuit RC1B, and transistor SW3B, which is located between logic circuit RC2.

[0380] 28B, crosses are drawn over the transistors SW1A and SW3A that are turned off, and the signal paths between the logic circuits RC1B and RC2 are indicated by bold arrows. Also, in FIG. 28B, the power gating of the logic circuit RC1A is indicated by dashed lines. As shown in FIG. 28B, it is also possible to use the transistors SW3A and SW3B as switching switches to selectively power gate the logic circuits RC1A and RC1B.

[0381] Period P04 is a period during which the logic circuit RC2 is power-gated. During this period, the transistor SW2 is switched off. By turning off the transistor SW2, the current path between the power supply lines that provide the power supply potential to the logic circuit RC2 can be cut off. As a result, both the logic circuits RC1 and RC2 are power-gated, reducing power consumption.

[0382] Period P05 is a period for opening a current path between node NodeA and node NodeB. During this period, transistor SW3 is turned on. By turning on transistor SW3, a signal path between node NodeA and node NodeB can be opened when logic circuits RC1 and RC2 are operating.

[0383] The period P06, like the period P01, is a period for explaining normal operation. In this operation, all of the transistors SW1 to SW3 are turned on. The logic circuits RC1 and RC2 can obtain output data according to the input data.

[0384] As described above, power gating for each logic circuit can be performed by selectively turning off transistors functioning as switches provided for each logic circuit. This allows for extremely small leakage current between power supply lines without impairing the high-speed operation of the logic circuits. Furthermore, by selectively turning off transistors functioning as switches provided between logic circuits, the current path between the logic circuits can be blocked. As a result, charge can be retained according to the signal logic, signal paths can be switched, and the impact of operational delays caused by power gating can be reduced.

[0385] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0386] Embodiment 5 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0387] Fig. 29 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 29 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 29 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0388] The transistor described as an example in Embodiment 1 can be applied to the memory cell 950. By using the transistor, the operation speed of the memory device can be improved. Furthermore, miniaturization and high integration of the memory device can be achieved. Furthermore, the capacitance per area of ​​the memory device can be increased.

[0389] The driver circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generating circuit 928.

[0390] In the semiconductor device 900, the circuits, signals, and voltages can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, clock signal CLK2, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside.

[0391] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0392] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0393] The voltage generation circuit 928 has a function of generating a voltage. The signal WAKE has a function of controlling the input of the clock signal CLK2 to the voltage generation circuit 928. For example, when an H-level signal is given as the signal WAKE, the clock signal CLK2 is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a voltage.

[0394] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0395] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0396] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0397] The PSW 931 has a function of controlling the supply of VDD to the peripheral circuit 915. The PSW 932 has a function of controlling the supply of VHM to the row driver 923. In this embodiment, the high power supply potential of the semiconductor device 900 is VDD, and the low power supply potential is GND (ground potential). Also, VHM is a high power supply potential used to set the word line to a high level, and is higher than VDD. The on / off of the PSW 931 is controlled by a signal PON1, and the on / off of the PSW 932 is controlled by a signal PON2. In FIG. 29, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it may be set to a plurality of power domains. In this case, a power switch can be provided for each power domain.

[0398] 30A to 30H, other examples of memory cell configurations that can be applied to the memory cell 950 will be described.

[0399] 30A shows an example of a circuit configuration of a DRAM memory cell. In this specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). A memory cell 951 includes a transistor M1 and a capacitor CA.

[0400] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring to which a constant potential or a signal is applied, or the front gate and the back gate may be connected to each other.

[0401] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0402] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0403] Data is written and read by applying a high-level potential to the wiring WOL to turn on the transistor M1 and connect the wiring BIL to the first terminal of the capacitor CA.

[0404] Furthermore, the memory cell that can be used for the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 952 shown in FIG. 30B may have a configuration. The memory cell 952 is an example in which the memory cell 952 does not include a capacitor CA and a wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0405] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0406] Note that the OS transistor described in Embodiment 1 is preferably used as the transistor M1. For example, the transistor 10 or the transistor 50 having the structure described in Embodiment 1 can be used as the transistor M1 of the memory cell 951. By using the OS transistor described in Embodiment 1 as the transistor M1, the operation speed of the memory device can be improved. Furthermore, the area occupied by the memory cell can be reduced. Furthermore, the off-state current of an OS transistor is extremely low. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be significantly reduced. That is, written data can be held by the transistor M1 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, the extremely low leakage current allows the memory cells 951 and 952 to hold multilevel data or analog data.

[0407] 30C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a memory device having a gain cell type memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0408] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0409] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0410] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and connecting the wiring WBL to the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0411] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0412] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 30D. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0413] 30E is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 953. Also, the memory cell 956 shown in Fig. 30F is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 954. With such a configuration, the integration degree of the memory cells can be increased.

[0414] Note that at least the transistor M2 is preferably the OS transistor described in Embodiment 1. For example, the transistor 10 and the transistor 90 described in Embodiment 1 can be used as the transistors M2 and M3 in the memory cells 953 and 954, respectively. Note that the transistor 10 described in Embodiment 1 may also be used as the transistor M3. By using the OS transistor described in Embodiment 1 as at least one of the transistors included in the memory cells 953 to 956, the operation speed of the storage device can be improved. Furthermore, the area occupied by the memory cell can be reduced.

[0415] Since the OS transistor has an extremely low off-state current, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956.

[0416] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956, each of which uses an OS transistor as the transistor M2, are one embodiment of an NOSRAM.

[0417] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0418] When an OS transistor is used as the transistor M3, the memory cell can be configured as a unipolar circuit.

[0419] 30G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 has transistors M4 to M6 and a capacitor CC.

[0420] The first terminal of the transistor M4 is connected to the first terminal of the capacitor CC, the second terminal of the transistor M4 is connected to the wiring BIL, and the gate of the transistor M4 is connected to the wiring WOL. The second terminal of the capacitor CC is electrically connected to the first terminal of the transistor M5 and the wiring GNDL. The second terminal of the transistor M5 is connected to the first terminal of the transistor M6, and the gate of the transistor M5 is connected to the first terminal of the capacitor CC. The second terminal of the transistor M6 is connected to the wiring BIL, and the gate of the transistor M6 is connected to the wiring RWL.

[0421] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0422] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and connecting the wiring BIL to the first terminal of the capacitor CC. Specifically, when the transistor M4 is turned on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby holding the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0423] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0424] Note that at least the transistor M4 is preferably the OS transistor described in Embodiment 1. By using the OS transistor described in Embodiment 1, the area occupied by the memory cell can be reduced.

[0425] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0426] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured as a unipolar circuit.

[0427] [OS-SRAM] FIG. 30H shows an example of an SRAM (Static Random Access Memory) using OS transistors. In this specification and the like, an SRAM using OS transistors is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in FIG. 30H is a memory cell of an SRAM capable of backing up data.

[0428] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0429] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0430] A second terminal of the transistor MS1 is electrically connected to the wiring VDL. A second terminal of the transistor MS2 is electrically connected to the wiring VDL. A second terminal of the transistor MS3 is electrically connected to the wiring GNDL. A second terminal of the transistor MS4 is electrically connected to the wiring GNDL.

[0431] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0432] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0433] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the conductive state and non-conductive state of the transistors M9 and M10.

[0434] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0435] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is in a conductive state, a potential corresponding to information to be recorded is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0436] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is conductive, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Because the transistors M9 and M10 are conductive, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. After that, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0437] Data is read by precharging the wirings BIL and BILB to a predetermined potential in advance, and then applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. The potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. The potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. The potentials of the wirings BIL and BILB change from the precharged potentials to the potentials of the first terminal of the capacitor CD2 and the first terminal of the capacitor CD1, respectively. Therefore, the potential held in the memory cell can be read from the potential of the wiring BIL or BILB.

[0438] Note that OS transistors are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, thereby reducing the frequency of refreshing the memory cells. Alternatively, refreshing the memory cells can be eliminated. Furthermore, by using the OS transistors described in Embodiment 1 as the transistors M7 to M10, the operating speed of the memory device can be improved. Furthermore, the area occupied by the memory cells can be reduced.

[0439] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0440] Embodiment 6 In this embodiment, application examples of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 31A to 32E.

[0441] The semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframes, space equipment, data centers (also referred to as DCs), and various electronic devices. By using the semiconductor device of one embodiment of the present invention, low power consumption and high performance can be achieved for the electronic components, mainframes, space equipment, data centers, and various electronic devices.

[0442] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0443] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0444] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, and a function to read out programs or data recorded on a recording medium.

[0445] [Electronic Component] FIG. 31A shows a perspective view of a substrate (mounting substrate 989) on which an electronic component 980 is mounted. The electronic component 980 shown in FIG. 31A has a semiconductor device 981 inside a mold 984. FIG. 31A omits some details in order to show the interior of the electronic component 980. The electronic component 980 has lands 985 on the outside of the mold 984. The lands 985 are electrically connected to electrode pads 986, and the electrode pads 986 are electrically connected to the semiconductor device 981 via wires 987. The electronic component 980 is mounted on, for example, a printed circuit board 988. A plurality of such electronic components are combined and electrically connected on the printed circuit board 988 to complete the mounting substrate 989.

[0446] The semiconductor device 981 also includes a drive circuit layer 982 and a memory layer 983. The memory layer 983 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 982 and the memory layer 983 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 982 and the memory layer 983, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0447] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0448] Furthermore, it is preferable that the memory cell arrays included in the memory layer 983 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve one or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 983, it is more difficult to form a monolithic stacked configuration than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked configuration.

[0449] Alternatively, an OS transistor can be used for the driver circuit layer 982. The OS transistor described in the above embodiment can pass a large current, which enables the semiconductor device 994 to operate at high speed.

[0450] The semiconductor device 981 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0451] Although the above example shows the semiconductor device 981 functioning as a memory device, the present invention is not limited to this. For example, the semiconductor device 981 can also function as a processor such as a CPU, a GPU, or a field programmable gate array (FPGA). In this case, an OS transistor is preferably used for the semiconductor device 981. The OS transistor described in the above embodiment can pass a large current. This enables the semiconductor device 981 to operate at high speed.

[0452] 31B shows a perspective view of an electronic component 990. The electronic component 990 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 990 has an interposer 991 provided on a package substrate 992 (printed circuit board), and a semiconductor device 994 and a plurality of semiconductor devices 981 provided on the interposer 991.

[0453] In the electronic component 990, the semiconductor device 981 is used as a high bandwidth memory (HBM), and the semiconductor device 994 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA.

[0454] In addition, an OS transistor is preferably used for the semiconductor device 994. The OS transistor described in the above embodiment can pass a large current, which enables the semiconductor device 994 to operate at high speed.

[0455] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 992. For example, a silicon interposer or a resin interposer can be used as the interposer 991.

[0456] The interposer 991 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 991 also functions to connect the integrated circuits provided on the interposer 991 to electrodes provided on the package substrate 992. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 991, and the integrated circuits and the package substrate 992 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0457] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0458] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0459] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, TSVs, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 990, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs with a monolithic stacked memory cell array.

[0460] A heat sink (heat dissipation plate) may be provided over the electronic component 990. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 991. For example, in the electronic component 990 shown in this embodiment, it is preferable to align the height of the semiconductor device 981 and the height of the semiconductor device 994.

[0461] Electrodes 993 may be provided on the bottom of the package substrate 992 in order to mount the electronic component 990 on another substrate. FIG. 31B shows an example in which the electrodes 993 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 992, BGA (Ball Grid Array) mounting can be achieved. The electrodes 993 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 992, PGA (Pin Grid Array) mounting can be achieved.

[0462] The electronic component 990 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0463] [Mainframe] Next, Fig. 32A shows a perspective view of a mainframe 5600. The mainframe 5600 shown in Fig. 32A has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe 5600 may also be called a supercomputer.

[0464] The computer 5620 can have the configuration shown in the perspective view in Fig. 32B, for example. In Fig. 32B, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0465] PC card 5621 shown in Figure 32C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that although Figure 32C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 can be referenced for information on these semiconductor devices.

[0466] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0467] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the standards for each include HDMI (registered trademark).

[0468] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0469] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 990 can be used as the semiconductor device 5627.

[0470] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 990 can be used as the semiconductor device 5628.

[0471] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0472] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0473] A semiconductor device according to one embodiment of the present invention includes an OS transistor. Compared to a Si transistor, an OS transistor exhibits smaller variations in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and is therefore highly reliable and suitable for use in environments where radiation may be incident. For example, an OS transistor can be suitably used in outer space. Specifically, an OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutrons. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification can include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0474] Fig. 32D shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 32D illustrates a planet 6804 in space.

[0475] 32D , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it has low power consumption and high reliability even in space.

[0476] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0477] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 in the satellite 6800. Note that the solar panel may be called a solar cell module.

[0478] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0479] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 6807 is preferably a semiconductor device including an OS transistor which is one embodiment of the present invention.

[0480] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0481] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0482] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0483] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. Managing long-term data requires the construction of a large-scale building, such as installing storage and servers for storing a huge amount of data, ensuring a stable power supply for data retention, or ensuring cooling equipment required for data retention.

[0484] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of cooling equipment, etc. Therefore, it is possible to reduce the space required for the data center.

[0485] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0486] Fig. 32E shows a storage system applicable to a data center. The storage system 7010 shown in Fig. 32E has a plurality of servers 7001sb as hosts 7001. It also has a plurality of storage devices 7003md as storage 7003. The host 7001 and storage 7003 are connected via a storage area network 7004 and a storage control circuit 7002.

[0487] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0488] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0489] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0490] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0491] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0492] 10: transistor, 11: insulating layer, 15: functional layer, 16: functional layer, 17: functional layer, 20: opening, 21: oxide semiconductor layer, 21C: channel formation region, 21f: oxide semiconductor film, 21S: oxide layer, 22: insulating layer, 22a: insulating layer, 22b: insulating layer, 22c: insulating layer, 22d: insulating layer, 23: conductive layer, 23a: conductive layer, 23b: conductive layer, 24a: conductive layer, 24b: conductive layer, 25a: conductive layer, 25b: conductive layer, 26a: conductive layer, 26b: conductive layer, 27a: conductive layer, 27b: conductive layer, 28a: opening, 28b: opening, 31a: side surface, 31b: side surface, 31c : side surface, 31d: side surface, 32: insulating layer, 33a: region, 33b: region, 33c: region, 35: resist mask, 37a: layer, 37b: layer, 39: recess, 40: memory cell, 41: insulating layer, 41A: insulating film, 42: insulating layer, 43: insulating layer, 44: insulating layer, 45: insulating layer, 46: insulating layer, 47a: region, 47b: region, 48a: region, 48b: region, 50: transistor, 51: semiconductor layer, 52: insulating layer, 53: conductive layer, 54: conductive layer, 55: conductive layer, 56: conductive layer, 60: capacitor element, 61: conductive layer, 62: insulating layer, 63: conductive layer, 64: conductive layer, 71: insulating layer, 72: insulating layer, 73: insulating layer, 74: insulating layer, 75: insulating layer, 76: insulating layer, 77: insulating layer, 90: transistor, 91: substrate, 92: semiconductor region, 93: insulating layer, 94: conductive layer, 95a: low resistance region, 95b: low resistance region, 98: wiring layer, 900: semiconductor device, 910: driver circuit, 911: peripheral circuit, 912: control circuit, 915: peripheral circuit, 920: memory array, 923: row driver, 924: column driver, 925: input circuit, 926: output circuit, 927: sense amplifier, 928: voltage generation circuit, 931: PSW, 932: PSW, 94 1: row decoder, 942: column decoder, 950: memory cell, 951: memory cell, 952: memory cell, 953: memory cell, 954: memory cell, 955: memory cell, 956: memory cell, 957: memory cell, 958: memory cell, 980: electronic component, 981: semiconductor device, 982: drive circuit layer, 983: memory layer, 984: mold, 985: land, 986: electrode pad, 987: wire, 988: printed circuit board, 989: mounting board, 990: electronic component, 991: interposer, 992: package board, 993: electrode, 994: semiconductor device,1001: circuit, 1002: circuit, 1003: circuit, 1100: circuit, 5600: mainframe, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device, 7010: storage system,

Claims

a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, an oxide layer, and an oxide semiconductor layer; the oxide semiconductor layer has a channel formation region, the first conductive layer has a region in contact with a first side surface of the first insulating layer; the second conductive layer has a region in contact with a second side surface of the first insulating layer; the second side surface faces the first side surface, the oxide layer is located on the first insulating layer, on the first conductive layer, and on the second conductive layer; the oxide semiconductor layer covers the first conductive layer, the second conductive layer, the first insulating layer, and the oxide layer; the second insulating layer is provided on the oxide semiconductor layer; the third conductive layer is provided to cover the oxide semiconductor layer via the second insulating layer in a cross-sectional view in a channel width direction; In a cross-sectional view in the channel width direction, a height of the first insulating layer is greater than a width of the first insulating layer; the oxide semiconductor layer contains indium and has crystals with a cubic crystal structure; the oxide semiconductor layer has a first region in contact with a third side surface of the first insulating layer, a second region in contact with a fourth side surface of the first insulating layer, and a third region in contact with a top surface of the oxide layer; The fourth side surface faces the third side surface. 　 In claim 1, The semiconductor device wherein the first insulating layer is hexahedral. 　 In claim 1, A semiconductor device in which the crystal orientation of the crystal grains in the first region, the crystal orientation of the crystal grains in the second region, and the crystal orientation of the crystal grains in the third region are the same or approximately the same. 　 In claim 3, the oxide semiconductor layer is located on a substrate; A semiconductor device in which the crystal orientation of the crystal grains in the first region, the crystal orientation of the crystal grains in the second region, and the crystal orientation of the crystal grains in the third region are <111> with respect to a direction perpendicular or approximately perpendicular to the surface of the substrate. 　 In any one of claims 1 to 3, the first conductive layer, the second conductive layer, and the first insulating layer are located on a substrate; A semiconductor device in which the height of the first conductive layer from the surface of the substrate and the height of the second conductive layer from the surface of the substrate are each equal to or less than the height of the first insulating layer from the surface of the substrate. 　 In any one of claims 1 to 4, A semiconductor device in which the top surface of the first conductive layer, the top surface of the second conductive layer, and the top surface of the first insulating layer are aligned or substantially aligned with one another. 　 In claim 6, a fourth conductive layer, a fifth conductive layer, and a third insulating layer; the first conductive layer has a region in contact with an upper surface of the fourth conductive layer; the second conductive layer has a region in contact with an upper surface of the fifth conductive layer, the third insulating layer has a region in contact with a side surface of the first conductive layer, a region in contact with a side surface of the second conductive layer, a region in contact with a top surface of the fourth conductive layer, and a region in contact with a top surface of the fifth conductive layer; The semiconductor device, wherein the first insulating layer is provided on the third insulating layer. 　 a first step of forming an insulating film; a second step of forming a first opening and a second opening in the insulating film; a third step of forming a first conductive layer within the first opening and a second conductive layer within the second opening; a fourth step of forming an oxide layer so as to be in contact with an upper surface of the first conductive layer, an upper surface of the second conductive layer, and an upper surface of the insulating film in a region between the first conductive layer and the second conductive layer; a fifth step of forming a first insulating layer by removing a region of the insulating film that does not overlap with the oxide layer; a sixth step of forming an oxide semiconductor layer so as to cover the first conductive layer, the second conductive layer, the first insulating layer, and the oxide layer; a seventh step of forming a second insulating layer on the oxide semiconductor layer; an eighth step of forming a third opening in the second insulating layer, the third opening reaching the oxide semiconductor layer; a ninth step of forming a third insulating layer so as to cover the inside of the third opening; and a tenth step of forming a third conductive layer on the third insulating layer so as to fill the third opening. 　 In claim 8, before the first step, an eleventh step of forming a fourth conductive layer and a fifth conductive layer, and a twelfth step of forming a fourth insulating layer on the fourth conductive layer and the fifth conductive layer are performed; In the first step, the insulating film is formed on the fourth insulating layer; the second step forming the first opening, which reaches the fourth conductive layer, and the second opening, which reaches the fifth conductive layer, in the fourth insulating layer. 　 In claim 9, In the sixth step, the oxide semiconductor layer is formed to have a region in contact with an upper surface of the fourth insulating layer. 　 In any one of claims 8 to 10, In the sixth step, the oxide semiconductor layer is formed to contain indium and have crystals with a cubic crystal structure.

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