Semiconductor device and method for producing semiconductor device

Abstract

The present invention provides a transistor that can cause a large current to flow. This semiconductor device has a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a first insulating layer, and a second insulating layer. The first conductive layer and the second conductive layer each have a columnar shape and are spaced apart from each other. The first insulating layer has an elongated shape in a plan view, and is in contact with the first conductive layer and the second conductive layer at ends in the long-side direction thereof. The semiconductor layer surrounds the first insulating layer, the first conductive layer, and the second conductive layer in a plan view, and is in contact with a pair of side surfaces parallel to the long-side direction of the first insulating layer, the side surface of the first conductive layer, and the side surface of the second conductive layer. The second insulating layer is provided between the first conductive layer and the second conductive layer to cover the semiconductor layer, and the third conductive layer is provided to cover the second insulating layer.

Description

Semiconductor device and method for manufacturing the same

[0001] 1. Field of the Invention One embodiment of the present invention relates to a semiconductor device, a transistor, or a memory device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] In recent years, the development of semiconductor devices has progressed, and CPUs, memories, and other large-scale integrated circuits (LSIs) are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed into chips by processing a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0004] 2. Description of the Related Art A CPU, a memory, or other LSI semiconductor circuit (IC chip) is mounted on a circuit board, such as a printed wiring board, and is used as one of the components of various electronic devices.

[0005] Furthermore, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0006] Furthermore, it is known that a transistor including an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the property of a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time.

[0007] JP 2012-257187 A JP 2011-151383 A

[0008] Takashi Koida, "High-mobility transparent conductive film," National Institute of Advanced Industrial Science and Technology (AIST), AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf> C. Chen, S. P. Ong, "A universal graph deep learning interatomic potential for the periodic table," Nat. Comput. Sci., 2, 2022, pp. 718-728

[0009] An object of one embodiment of the present invention is to provide a transistor capable of passing a large current. Another object is to provide a transistor with favorable electrical characteristics. Another object is to provide a transistor that can be miniaturized. Another object is to provide a transistor that occupies a small area. Another object is to provide a transistor that combines miniaturization with high reliability. Another object is to provide a semiconductor device in which transistors can be arranged at high density.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device, a memory device, or an electronic device having a novel structure. An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0012] One embodiment of the present invention is a semiconductor device including a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a first insulating layer, and a second insulating layer. The first conductive layer and the second conductive layer each have a columnar shape and are spaced apart from each other. The first insulating layer has an elongated shape in a plan view, and one of a pair of ends in a long side direction of the first insulating layer is in contact with the first conductive layer, and the other is in contact with the second conductive layer. The semiconductor layer surrounds the first insulating layer, the first conductive layer, and the second conductive layer in a plan view and is in contact with a pair of side surfaces of the first insulating layer parallel to the long side direction, a side surface of the first conductive layer, and a side surface of the second conductive layer. The second insulating layer is provided between the first conductive layer and the second conductive layer to cover the semiconductor layer, and the third conductive layer is provided to cover the second insulating layer.

[0013] Another embodiment of the present invention is a semiconductor device including a first functional layer and a second functional layer below the first functional layer. The first functional layer includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a first insulating layer, and a second insulating layer. The first conductive layer and the second conductive layer each have a columnar shape and are spaced apart from each other. The first insulating layer has an elongated shape in a plan view, and one of a pair of ends in the long side direction of the first insulating layer contacts the first conductive layer, and the other end contacts the second conductive layer. The semiconductor layer surrounds the first insulating layer, the first conductive layer, and the second conductive layer in a plan view and contacts a pair of side surfaces parallel to the long side direction of the first insulating layer, a side surface of the first conductive layer, and a side surface of the second conductive layer. The second insulating layer is provided between the first conductive layer and the second conductive layer to cover the semiconductor layer. The third conductive layer is provided to cover the second insulating layer. The second functional layer also has a first transistor having a channel formed in a portion of the semiconductor substrate. The first transistor has a semiconductor region, a first low-resistance region, and a second low-resistance region, each of which is a portion of the semiconductor substrate, as well as a gate insulating layer and a gate electrode. The semiconductor region, the first low-resistance region, and the second low-resistance region each contain silicon.

[0014] In the above, it is preferable that a wiring layer be provided between the first functional layer and the second functional layer.

[0015] In the above, the semiconductor region preferably has a fin-like shape.

[0016] In the above, it is preferable that a third functional layer having a plurality of memory cells is further provided above the first functional layer. In this case, it is preferable that the memory cell includes a second transistor and a capacitor. Furthermore, it is preferable that the second transistor is a vertical transistor.

[0017] Another embodiment of the present invention is a semiconductor device including a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a semiconductor layer, a first insulating layer, a second insulating layer, and a dielectric layer. The first conductive layer and the second conductive layer each have a columnar shape and are provided separately. The first insulating layer has an elongated shape in a plan view, and one of a pair of ends in a long side direction of the first insulating layer is in contact with the first conductive layer, and the other is in contact with the second conductive layer. The semiconductor layer surrounds the first insulating layer, the first conductive layer, and the second conductive layer in a plan view and is in contact with a pair of side surfaces parallel to the long side direction of the first insulating layer, a side surface of the first conductive layer, and a side surface of the second conductive layer. The second insulating layer is provided to cover the semiconductor layer in a first region between the first conductive layer and the second conductive layer. The third conductive layer is provided to cover the second insulating layer. A dielectric layer is disposed over the semiconductor layer in a second region between the first and second conductive layers, and a fourth conductive layer is disposed over the dielectric layer.

[0018] In the above, the dielectric layer preferably contains aluminum oxide.

[0019] In the above, the dielectric layer preferably contains an insulating material exhibiting ferroelectricity.

[0020] In the above, the dielectric layer preferably contains hafnium oxide, zirconium oxide, or hafnium zirconium oxide.

[0021] In any of the above, the height of the first insulating layer is preferably 1 to 50 times the width in the short side direction in a plan view.

[0022] In any of the above, it is preferable that the semiconductor device further includes a third insulating layer. The third insulating layer covers the first conductive layer, the second conductive layer, the semiconductor layer, and the first insulating layer, and has a groove that reaches the semiconductor layer and the first insulating layer. In this case, it is preferable that the second insulating layer is provided so as to cover the semiconductor layer inside the groove, and the third conductive layer is provided so as to fill the groove.

[0023] Alternatively, the third insulating layer is preferably provided to cover the first conductive layer, the second conductive layer, the semiconductor layer, and the first insulating layer, and in this case, the third insulating layer is preferably in contact with the top surface of the first insulating layer, the top surface of the first conductive layer, and the top surface of the second conductive layer.

[0024] In any of the above, the semiconductor layer preferably contains indium oxide.

[0025] In any of the above, the semiconductor layer preferably has a single crystal structure or a polycrystalline structure.

[0026] In any of the above, the first conductive layer and the second conductive layer preferably have a first layer and a second layer, respectively. In this case, the first layer and the second layer are preferably provided concentrically in this order, and the second layer is preferably in contact with the semiconductor layer. Furthermore, in this case, it is preferable that the semiconductor layer contains indium oxide, and the second layer contains an oxide containing indium.

[0027] Another embodiment of the present invention is a transistor including a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a first insulating layer, and a second insulating layer. The first conductive layer and the second conductive layer each have a columnar shape and are provided separately. The first insulating layer has an elongated shape in a plan view, and one of a pair of ends in a long side direction of the first insulating layer is in contact with the first conductive layer, and the other is in contact with the second conductive layer. The semiconductor layer surrounds the first insulating layer, the first conductive layer, and the second conductive layer in a plan view and is in contact with a pair of side surfaces of the first insulating layer parallel to the long side direction, a side surface of the first conductive layer, and a side surface of the second conductive layer. The second insulating layer is provided between the first conductive layer and the second conductive layer to cover the semiconductor layer. The third conductive layer is provided to cover the second insulating layer. The off-state current per 1 μm of the channel width of the transistor is 1 aA (1×10 −１８ A) The following.

[0028] Another embodiment of the present invention is a method for manufacturing a semiconductor device, the method including: forming a first conductive layer and a second conductive layer, each embedded in a first insulating layer, at a distance from each other; removing a part of the first insulating layer to form a wall shape in which an end portion of the first insulating layer in a long side direction in a plan view is in contact with the first conductive layer and the second conductive layer; forming a semiconductor film to cover the first conductive layer, the second conductive layer, and the first insulating layer; and anisotropically etching the semiconductor film to expose a top surface of the first conductive layer, a top surface of the second conductive layer, and a top surface of the first insulating layer, and forming a semiconductor layer surrounding each side surface of the first conductive layer, the second conductive layer, and the first insulating layer.

[0029] Another embodiment of the present invention is a method for manufacturing a semiconductor device, the method including: forming a first conductive layer and a second conductive layer, each of which is embedded in a first insulating layer, at a distance from each other; forming a first layer containing crystals in contact with top surfaces of the first insulating layer, the first conductive layer, and the second conductive layer; removing a part of the first insulating layer that is not covered by the first layer to process the first insulating layer into a wall shape whose end portion in a long side direction in a plan view is in contact with the first conductive layer and the second conductive layer; forming a semiconductor film having a single crystal structure or a polycrystalline structure to cover the first conductive layer, the second conductive layer, the first insulating layer, and the first layer; and anisotropically etching the semiconductor film to expose a top surface of the first conductive layer, a top surface of the second conductive layer, and a top surface of the first insulating layer, and forming a semiconductor layer surrounding each side surface of the first conductive layer, the second conductive layer, and the first insulating layer.

[0030] In addition, in the above, it is preferable to have, after forming the semiconductor layer, a step of forming a second insulating layer to cover a part of the semiconductor layer and a part of the first insulating layer, and a step of forming a third conductive layer to cover the second insulating layer.

[0031] Furthermore, in the above, it is preferable to have the following steps after forming the semiconductor layer: forming a third insulating layer that covers the first conductive layer, the second conductive layer, the first insulating layer, and the semiconductor layer; forming a groove in the third insulating layer that reaches the semiconductor layer and the first insulating layer; forming a second insulating layer inside the groove that covers the semiconductor layer and the first insulating layer; and forming a third conductive layer inside the groove that covers the second insulating layer.

[0032] a step of forming a semiconductor film covering the first conductive layer, the second conductive layer, and the first insulating layer; a step of anisotropically etching the semiconductor film to expose a top surface of the first conductive layer, a top surface of the second conductive layer, and a top surface of the first insulating layer, and forming a semiconductor film surrounding side surfaces of the first conductive layer, the second conductive layer, and the first insulating layer; a step of forming a sacrificial layer between the first conductive layer and the second conductive layer to cover the semiconductor layer; a step of supplying a first element to a region of the semiconductor layer that is not covered by the sacrificial layer; and a step of removing the sacrificial layer.

[0033] Another aspect of the present invention is a method for manufacturing a semiconductor device, comprising the steps of: forming a first conductive layer and a second conductive layer, each of which is embedded in a first insulating layer, at a distance from each other; forming a first layer containing crystals in contact with top surfaces of the first insulating layer, the first conductive layer, and the second conductive layer; removing a portion of the first insulating layer that is not covered by the first layer to process the first insulating layer into a wall shape whose end portion in the long side direction in plan view is in contact with the first conductive layer and the second conductive layer; and forming a single-crystal structure or a polycrystalline structure covering the first conductive layer, the second conductive layer, the first insulating layer, and the first layer. a step of forming a semiconductor film having a structure; a step of anisotropically etching the semiconductor film to expose a top surface of a first conductive layer, a top surface of a second conductive layer, and a top surface of a first insulating layer, and forming a semiconductor layer surrounding each of side surfaces of the first conductive layer, the second conductive layer, and the first insulating layer; a step of forming a sacrificial layer that covers the semiconductor layer between the first conductive layer and the second conductive layer; a step of supplying a first element to a region of the semiconductor layer that is not covered by the sacrificial layer; and a step of removing the sacrificial layer.

[0034] In any of the above, the first element is preferably one or more selected from titanium, aluminum, tantalum, tungsten, tin, silicon, germanium, zirconium, hafnium, antimony, magnesium, hydrogen, boron, phosphorus, and noble gases.

[0035] In any of the above, it is preferable to further include the steps of: after supplying the first element, forming a third insulating layer to cover the sacrificial layer; planarizing the upper part of the third insulating layer so that the upper surface of the sacrificial layer is exposed; removing the sacrificial layer to expose the semiconductor layer and the first insulating layer; forming a second insulating layer in contact with the semiconductor layer and the first insulating layer; and forming a third conductive layer to cover the second insulating layer.

[0036] In any of the above, the semiconductor layer is preferably formed using an indium oxide film.Furthermore, the first layer is preferably formed using an indium oxide film, an indium tin oxide film, a zinc oxide film, an indium gallium oxide film, a gallium zinc oxide film, an aluminum zinc oxide film, an indium aluminum zinc oxide film, an indium gallium zinc oxide film, or an indium tin zinc oxide film.

[0037] In any of the above methods, it is preferable to perform heat treatment after the formation of the semiconductor film. The heat treatment is preferably performed at a temperature of 250° C. or higher and 650° C.

[0038] According to one embodiment of the present invention, a transistor capable of passing a large current can be provided. Alternatively, a transistor with favorable electrical characteristics can be provided. Alternatively, a transistor that can be miniaturized can be provided. Alternatively, a transistor that occupies a small area can be provided. Alternatively, a transistor that can be miniaturized and has high reliability can be provided. Alternatively, a semiconductor device in which transistors can be arranged at high density can be provided.

[0039] According to one aspect of the present invention, it is possible to provide a semiconductor device, a memory device, or an electronic device having a novel configuration. According to one aspect of the present invention, it is possible to at least alleviate at least one of the problems of the prior art.

[0040] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0041] FIGS. 1A, 1B, 1C, 1D, and 1E are structural examples of semiconductor devices. FIG. 2 is a structural example of a semiconductor device. FIGS. 3A, 3B, 3C, 3D, and 3E are structural examples of semiconductor devices. FIGS. 4A, 4B, 4C, 4D, and 4E are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 5A, 5B, 5C, 5D, and 5E are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 6A, 6B, 6C, 6D, and 6E are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 7A, 7B, 7C, 7D, and 7E are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 8A, 8B, 8C, 8D, and 8E are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 9A, 9B, 9C, 9D, and 9E are diagrams illustrating a manufacturing method of a semiconductor device. FIGS. 10A, 10B, 10C, 10D, and 10E are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 11A, 11B, 11C, and 11D are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIGS. 12A, 12B, 12C, and 12D are diagrams illustrating an example of a method for manufacturing a semiconductor device. FIG. 13 is a structural example of a semiconductor device. FIGS. 14A and 14B are structural examples of a semiconductor device. FIG. 15 is a structural example of a semiconductor device. FIG. 16 is a structural example of a semiconductor device. FIG. 17 is a structural example of a semiconductor device. FIGS. 18A and 18B are diagrams illustrating carrier concentration dependence of Hall mobility. FIG. 18C is a cross-sectional view illustrating an indium oxide film. FIG. 19A is an equivalent circuit diagram of a logic circuit. FIG. 19B is a diagram showing circuit symbols for the logic circuit. FIG. 19C is a timing chart illustrating the operation of the logic circuit. FIGS. 20A and 20D are equivalent circuit diagrams of a logic circuit. 20B, 20C, 20E, and 20F are diagrams showing circuit symbols for logic circuits. FIG. 21A is a diagram showing the circuit symbol for a buffer circuit. FIG. 21B is a diagram showing an example configuration of a buffer circuit. FIG. 21C is a timing chart explaining the operation of the buffer circuit. FIG. 21D is a diagram showing an example configuration of a ring oscillator. FIG. 21E is a diagram illustrating oscillation of a ring oscillator. FIG. 22A is an equivalent circuit diagram of a DFF circuit. FIG. 22B is a diagram showing the circuit symbol for a DFF circuit. FIG. 23A is a diagram explaining an example configuration of a shift register circuit.FIG. 23B is a timing chart illustrating the operation of a shift register circuit. FIGS. 24A and 24B are diagrams illustrating a configuration example of a selector. FIG. 24C is a diagram illustrating a configuration example of an analog switch. FIG. 25A is a circuit diagram illustrating a configuration example of a logic circuit including a semiconductor device of one embodiment of the present invention, and FIG. 25B is a timing chart. FIGS. 26A and 26B are circuit diagrams illustrating a configuration example of a logic circuit including a semiconductor device of one embodiment of the present invention. FIG. 27 is a block diagram illustrating a configuration example of a semiconductor device. FIGS. 28A, 28B, 28C, 28D, 28E, 28F, 28G, and 28H are diagrams illustrating circuit configuration examples of memory cells. FIGS. 29A and 29B are diagrams illustrating examples of electronic components. FIGS. 30A, 30B, and 30C are diagrams illustrating an example of a mainframe computer. FIG. 30D is a diagram illustrating an example of space equipment. FIG. 30E is a diagram illustrating an example of a storage system applicable to a data center. FIGS. 31A and 31B are cross-sectional images according to Example 1. FIG. 32 is a diagram showing a transistor structure, various parameters, and field-effect mobility according to Example 3. FIGS. 33A, 33B, and 33C are graphs showing Id-Vg characteristics and field-effect mobility according to Example 3. FIGS. 34A, 34B, and 34C are graphs showing cutoff frequencies (fT) according to Example 3. FIG. 35 is a graph showing the relationship between channel length and mobility according to Example 3. FIG. 36 is a diagram showing a transistor structure and various parameters according to Example 4. FIG. 37 is a graph of an ID-VG curve according to Example 4. FIG. 38 is a diagram showing a transistor according to Example 5. FIG. 39 is a graph showing the temperature dependence of off-current according to Example 5.

[0042] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0043] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0044] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0045] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0046] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0047] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0048] In this specification and the like, either the source or the drain of a transistor may be referred to as a “first electrode,” and the other of the source or the drain may be referred to as a “second electrode.” The gate may also be referred to as a “gate” or a “gate electrode.”

[0049] Furthermore, in this specification, "electrically connected" includes connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0050] In this specification, the phrase "top surface shapes generally match" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0051] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0052] In the following, expressions indicating directions such as "up" and "down" will basically be used in accordance with the directions in the drawings. However, for purposes such as facilitating explanation, the directions indicated by "up" or "down" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided (such as a forming surface, a support surface, an adhesive surface, or a flat surface) is located above the laminate in the drawings, the forming surface side may be expressed as "down" and the direction opposite to the forming surface as "up."

[0053] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in an on-state. The channel width direction refers to a direction perpendicular to the channel length direction. Depending on the structure or shape of the transistor, the channel length direction and the channel width direction may not be defined as a single direction.

[0054] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0055] Unless otherwise specified, in this specification and the like, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state refers to a state in which the gate-source voltage Vgs is lower than the threshold voltage Vth for an n-channel transistor (higher than Vth for a p-channel transistor).

[0056] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, due to formatting restrictions, in this specification, instead of adding a bar above the numbers, they may be expressed by adding a minus sign (-) before the numbers. Furthermore, individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0057] In this specification, "two lines parallel" refers to a state in which the two lines are arranged at an angle of -10 degrees or more and 10 degrees or less. "Two lines approximately parallel" refers to a state in which the two lines are arranged at an angle of -30 degrees or more and 30 degrees or less (including parallel). "Two lines perpendicular" refers to a state in which the two lines are arranged at an angle of 80 degrees or more and 100 degrees or less. "Two lines approximately perpendicular" refers to a state in which the two lines are arranged at an angle of 60 degrees or more and 120 degrees or less (including perpendicular).

[0058] In this specification, "two surfaces are parallel" refers to a state in which their interior angle is between -10 degrees and 10 degrees. "Two surfaces are approximately parallel" refers to a state in which their interior angle is between -30 degrees and 30 degrees (including parallel). "Two surfaces are perpendicular" refers to a state in which their interior angle is between 80 degrees and 100 degrees (including perpendicular). "Two surfaces are approximately perpendicular" refers to a state in which their interior angle is between 60 degrees and 120 degrees (including perpendicular).

[0059] Embodiment 1 In this embodiment, a structure example of a semiconductor device according to one embodiment of the present invention and an example of a manufacturing method thereof will be described. Hereinafter, a transistor will be described as a specific example of a semiconductor device.

[0060] One embodiment of the present invention includes a pair of columnar electrodes, a fin-shaped (or wall-shaped) insulating layer provided between the electrodes, and a semiconductor layer provided to cover side surfaces of the pair of electrodes and the insulating layer. The semiconductor layer further includes a gate insulating layer provided to cover part of the semiconductor layer in contact with the side surface of the insulating layer, and a gate electrode overlapping with the semiconductor layer with the gate insulating layer interposed therebetween. The pair of columnar electrodes function as a source electrode and a drain electrode, respectively.

[0061] The semiconductor layer located on the side of the insulating layer overlaps with the gate electrode via the gate insulating layer, and functions as a channel formation region. In addition, the semiconductor layer contacts the side surfaces of the pair of pillar-shaped electrodes, so that the contact area between them can be increased, and the contact resistance between the semiconductor layer and the electrodes can be reduced.

[0062] The height of the fin-shaped insulating layer is greater than its width in a plan view. For example, the height of the insulating layer is preferably 5 to 50 times the width of the insulating layer. This allows the channel width to be increased without increasing the area occupied by the transistor in a plan view, thereby increasing the source-drain current (also referred to as on-current) when the transistor is turned on.

[0063] As the semiconductor material used for the semiconductor layer, it is preferable to use a metal oxide (oxide semiconductor) that exhibits semiconductor properties. In this case, it is also preferable to use a metal oxide for the portions of the pair of electrodes that contact the semiconductor layer. This is preferable because it can reduce the contact resistance between the semiconductor layer and the pair of electrodes.

[0064] Here, it is preferable to use a metal oxide with high crystallinity for the semiconductor layer. For example, it is preferable to use a metal oxide having a single crystal structure or a polycrystalline structure. In particular, a metal oxide with a single crystal structure is preferable. In this case, a crystalline metal oxide film that functions as a seed crystal is formed in advance on the fin-shaped insulating layer, and a metal oxide film that will become the semiconductor layer is formed in contact with this, thereby making it possible to form a semiconductor layer with high crystallinity.

[0065] In this case, the crystalline structure of the semiconductor layer may be affected by the crystalline structure of the crystalline metal oxide film in contact with the underside of the semiconductor layer. More specifically, the crystalline structure of the semiconductor layer may be such that the crystalline orientation of the crystalline regions of the crystalline metal oxide film is aligned in a specific direction. For example, when a metal oxide having a hexagonal crystalline structure, such as In—Ga—Zn oxide, is used for the crystalline metal oxide film and a metal oxide having a cubic crystalline structure, such as indium oxide, is used for the semiconductor layer, if the

[001] orientation of the crystalline regions of the crystalline metal oxide film is oriented perpendicular to the surface on which the semiconductor layer is formed, the semiconductor layer may have a single-crystal structure or a polycrystalline structure in which the

[111] orientation of the crystalline regions is oriented perpendicular to the surface on which the semiconductor layer is formed. Thus, by using a metal oxide having uniaxially oriented crystalline regions for the crystalline metal oxide film, a semiconductor layer with high crystallinity can be obtained. This allows for the realization of a transistor with high on-state current and high reliability.

[0066] A more specific example will be described below with reference to the drawings.

[0067] [Configuration Example] Fig. 1A shows a schematic top view of a transistor 10. Figs. 1B, 1C, and 1D show schematic cross-sectional views taken along the cutting lines C-D, A-B, and E-F in Fig. 1A, respectively. Fig. 1E shows a schematic perspective view of the transistor 10. Fig. 1C shows a cross-section of the transistor 10 in the channel length direction, and Fig. 1B shows a cross-section in the channel width direction. Note that Fig. 1A omits some components (insulating layer 42, insulating layer 43, insulating layer 44, etc.). Fig. 1E shows only the outline of the insulating layer 42.

[0068] The transistor 10 includes a semiconductor layer 21, a conductive layer 25a, a conductive layer 25b, an insulating layer 22, and a conductive layer 23. The conductive layer 25a and the conductive layer 25b are spaced apart from each other and function as a source electrode and a drain electrode, respectively. A part of the conductive layer 23 functions as a gate electrode. A part of the insulating layer 22 functions as a gate insulating layer. A conductive layer 24a connected to the conductive layer 25a and functioning as a wiring is provided below the conductive layer 25a, and a conductive layer 24b connected to the conductive layer 25b and functioning as a wiring is provided below the conductive layer 25b. In addition, insulating layers such as an insulating layer 43, an insulating layer 44, an insulating layer 41, and an insulating layer 42 are provided over the insulating layer 11.

[0069] The transistor 10 is provided over an insulating layer 11 that is provided over a substrate (not shown). The insulating layer 11 functions as a base insulating layer.

[0070] An insulating layer 43, a conductive layer 24a, and a conductive layer 24b are provided on the insulating layer 11. The conductive layers 24a and 24b are provided so as to be embedded in the insulating layer 43. It is preferable that the upper surfaces of the insulating layer 43, the conductive layers 24a, and the conductive layers 24b are flattened and the heights of these upper surfaces are approximately the same.

[0071] An insulating layer 44 is provided to cover the insulating layer 43, the conductive layer 24a, and the conductive layer 24b. The insulating layer 44 functions as an etching stop film when processing the insulating layer 41, the insulating layer 42, the semiconductor layer 21, etc. The insulating layer 44 preferably contains an insulating material different from that of the insulating layer 41 and the insulating layer 42.

[0072] A columnar conductive layer 25a is provided on the conductive layer 24a, and a columnar conductive layer 25b is provided on the conductive layer 24b. The conductive layer 25a and the conductive layer 25b are in contact with the upper surface of the conductive layer 24a or the conductive layer 24b, respectively, through openings provided in the insulating layer 44.

[0073] The conductive layers 25a and 25b preferably have a cylindrical shape. However, the horizontal cross-sectional shape is not limited to this and may be an ellipse, a rectangle with rounded corners, or the like. They may also be regular polygons such as an equilateral triangle, a square, or a regular pentagon, or other polygons other than regular polygons. They may also be concave polygons, such as star polygons, with at least one interior angle exceeding 180 degrees. They may also be closed curves that combine straight lines and curves.

[0074] The height of the conductive layers 25a and 25b is preferably 5 to 50 times the diameter of the upper surface (the maximum diameter if the conductive layers 25a and 25b are not circular).

[0075] A fin-shaped (or wall-shaped) insulating layer 41 is provided on the insulating layer 44. The insulating layer 41 has an island-like shape. The insulating layer 41 is provided so as to contact and connect the side surfaces of the conductive layer 25a and the conductive layer 25b. The insulating layer 41 has an elongated shape (having a long side direction and a short side direction) in a planar view. The long side direction of the insulating layer 41 is approximately parallel to the line connecting the center of the conductive layer 25a and the center of the conductive layer 25b. Furthermore, the thickness (also referred to as width) in the direction perpendicular to the line (short side direction) is preferably as thin as possible. For example, it can be 0.01 to 1 times, preferably 0.01 to 0.8 times, more preferably 0.01 to 0.6 times the diameter of the conductive layer 25a or 25b. The height of the insulating layer 41 is equal to or smaller than the height of the conductive layer 25a or 25b. For example, the height of the insulating layer 41 can be 5 to 50 times its width. The height of the insulating layer 41 can be, for example, 10 to 200 nm, preferably 10 to 100 nm, and more preferably 10 to less than 60 nm. By making the height of the insulating layer 41 less than 60 nm, the semiconductor layer 21 can easily be formed of a single crystal grain from the upper end to the lower end of the insulating layer 41.

[0076] The insulating layer 41 is provided in contact with the conductive layer 25a and the conductive layer 25b. Specifically, a pair of ends of the insulating layer 41 in the long side direction in a plan view are in contact with the conductive layer 25a or the conductive layer 25b, respectively. This increases the mechanical strength of the insulating layer 41 compared to a case where the conductive layer 25a and the conductive layer 25b are not provided. Therefore, even if the width of the short side of the insulating layer 41 is extremely narrow, for example, between 5 nm and 20 nm, the insulating layer 41 can be manufactured with a high yield without collapsing during processing. This allows for the realization of a miniaturized transistor 10.

[0077] The semiconductor layer 21 is provided in contact with (covers) a pair of side surfaces of the insulating layer 41, a side surface of the conductive layer 25 a, and a side surface of the conductive layer 25 b. As shown in Figures 1A and 1E, in plan view, the semiconductor layer 21 is provided so as to surround the insulating layer 41, the conductive layer 25 a, and the conductive layer 25 b.

[0078] An insulating layer 42 is provided to cover the insulating layer 44, the semiconductor layer 21, the insulating layer 41, the conductive layer 25a, and the conductive layer 25b. The insulating layer 42 functions as an interlayer insulating layer. The upper surface of the insulating layer 42 is preferably flattened.

[0079] The insulating layer 42 is provided with a slit (groove) that reaches the semiconductor layer 21 and the insulating layer 41, and the insulating layer 22 and the conductive layer 23 are provided so as to fill the slit.

[0080] 1B , in a cross section of the transistor 10 in the channel width direction, a pair of portions of the semiconductor layer 21 are provided to sandwich an insulating layer 41. An insulating layer 22 is provided in contact with the pair of portions of the semiconductor layer 21 and an upper surface of the insulating layer 41, and a conductive layer 23 is provided to cover the insulating layer 22. The portion of the semiconductor layer 21 that covers the upper surface of the insulating layer 41 has been removed. Therefore, it can be said that the transistor 10 has two channel formation regions with the insulating layer 41 sandwiched between them.

[0081] 2 is a perspective schematic view in which the insulating layer 42, the insulating layer 22, and the conductive layer 23 in FIG. 1E are omitted. In FIG. 2, a region 21C of the semiconductor layer 21 that functions as a channel formation region is indicated by a hatching pattern different from that of the other portions. More specifically, the region 21C is a region of the semiconductor layer 21 that overlaps with the conductive layer 23 with the insulating layer 22 interposed therebetween.

[0082] The width of the region 21C in a direction parallel to the substrate surface corresponds to the channel length L. A smaller channel length is preferable because the on-state current of the transistor 10 can be increased. The channel length can be set to 1 nm or more and less than 70 nm, preferably 1 nm or more and 60 nm or less, more preferably 1 nm or more and 30 nm or less, further preferably 1 nm or more and 12 nm or less, further preferably 2 nm or more and 10 nm or less, and further preferably 3 nm or more and 8 nm or less. A transistor using the metal oxide film of one embodiment of the present invention for the semiconductor layer 21 can have good switching characteristics even when the channel length is 3 nm or less. For example, it is difficult to shorten the channel length to this extent in a transistor using silicon for the channel formation region.

[0083] The channel length of the transistor does not necessarily need to be as small as described above, and may be set to an appropriate channel length depending on the application, such as greater than 70 nm and equal to or less than 1 μm, 70 nm or more and 500 nm or less, 70 nm or more and 300 nm or less, or 70 nm or more and 100 nm or less.

[0084] 1B, the conductive layer 23 is provided so as to surround the semiconductor layer 21 and the insulating layer 41, so that a gate electric field can be efficiently applied to the semiconductor layer 21. This improves the switching characteristics of the transistor, not only increasing the on-current but also reducing the subthreshold value (S value). It also reduces the leakage current in the off state.

[0085] Here, a metal oxide (oxide semiconductor) exhibiting semiconductor properties is preferably used for the semiconductor layer 21. In this case, a conductive metal oxide (oxide conductor) is preferably used for at least the portions of the conductive layers 25 a and 25 b that are in contact with the semiconductor layer 21. By using a metal oxide for the conductive film that is in contact with the metal oxide-containing semiconductor layer 21, the contact resistance therebetween can be reduced, the load on the wiring can be reduced, and the on-current of the transistor 10 can be increased.

[0086] The conductive layer 25a and the conductive layer 25b preferably contain a metal oxide containing the same metal element as the semiconductor layer 21. In particular, it is preferable that both the conductive layer 25a and the conductive layer 25b and the semiconductor layer 21 contain a metal oxide containing indium. This can reduce the contact resistance between the semiconductor layer 21 and the conductive layer 25a or the conductive layer 25b. It is preferable to use a metal oxide containing indium and tin for the conductive layer 25a and the conductive layer 25b, because this can increase the conductivity.

[0087] 3A to 3E show examples in which the conductive layer 25a and the conductive layer 25b each have a three-layer structure. The conductive layer 25a includes a conductive layer 26a, a conductive layer 27a, and a conductive layer 28a arranged concentrically from the center, while the conductive layer 25b includes a conductive layer 26b, a conductive layer 27b, and a conductive layer 28b arranged concentrically from the center. The outermost conductive layers 28a and 28b are in contact with the semiconductor layer 21.

[0088] The conductive layers 26a and 26b are preferably made of a low-resistance conductive material. The conductive layers 27a and 27b are preferably made of a conductive material having oxygen barrier properties, such as a metal nitride or a metal oxide. The conductive layers 28a and 28b are preferably made of a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material. Metal oxides, which are conductive oxide materials, are particularly preferred.

[0089] With this structure, first, the conductive layers 28a and 28b can reduce the contact resistance with the semiconductor layer 21. Furthermore, the low-resistance conductive layers 26a and 26b can reduce the electrical resistance. By providing the conductive layers 27a and 27b between these layers, oxidation of the conductive layers 26a and 26b can be prevented, thereby improving reliability.

[0090] The above is a description of the configuration example.

[0091] [Regarding Components] <Substrate> The substrate on which a transistor is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides may also be used. Further, there are substrates in which a conductive layer or a semiconductor layer is provided on an insulating substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive substrate. Alternatively, any of these substrates may be provided with elements. The elements provided on the substrate include capacitor elements, resistor elements, switch elements (including transistors), light-emitting elements, memory elements, and the like.

[0092] <Semiconductor Layer> The semiconductor layer 21 preferably contains a metal oxide (oxide semiconductor).

[0093] The semiconductor layer 21 is preferably made of indium oxide.

[0094] Examples of metal oxides that can be used for the semiconductor layer 21 include Ga oxide and Zn oxide. The metal oxide preferably contains at least In or Zn. The metal oxide preferably contains two or three elements selected from In, element M, and Zn. The element M is a metal element or semimetal element with a high bond energy with oxygen, such as a metal element or semimetal element with a bond energy with oxygen higher than that of indium. Specific examples of the element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M contained in the metal oxide is preferably one or more of the above elements, and is particularly preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred. Hereinafter, a metal oxide having In, M, and Zn may be referred to as an In-M-Zn oxide. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0095] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. For example, the atomic ratios of metal elements in such an In-M-Zn oxide may be In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, or compositions in the vicinity thereof. Note that the term "composition in the vicinity" refers to a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current, field-effect mobility, and the like of a transistor can be increased.

[0096] Furthermore, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M. For example, the atomic ratio of metal elements in such an In-M-Zn oxide may be In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or a composition close to these. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0097] The semiconductor layer 21 can be made of, for example, In—Zn oxide, In—Ga oxide, In—Sn oxide, In—Ti oxide, In—Ga—Al oxide, In—Ga—Sn oxide, In—Ga—Zn oxide, In—Sn—Zn oxide, In—Al—Zn oxide, In—Ti—Zn oxide, In—Ga—Sn—Zn oxide, or In—Ga—Al—Zn oxide. Ga—Zn oxide may also be used. On the other hand, a material containing Zn is preferred because it is easy to increase crystallinity.

[0098] Note that the metal oxide may contain one or more metal elements with higher period numbers in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element with a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements with higher period numbers include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

[0099] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0100] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). In particular, it is preferable to form the metal oxide by the ALD method, which has excellent coating properties. When forming the metal oxide by sputtering, the composition of the metal oxide after film formation may differ from the composition of the target. In particular, the zinc content in the metal oxide after film formation may be reduced to about 50% compared to the target. Furthermore, the sputtering method and the ALD method can be combined as a method for forming the metal oxide. For example, a method in which a metal oxide is formed by sputtering and then formed by ALD, or a method in which a metal oxide is formed by ALD and then formed by sputtering, can be used.

[0101] In this specification, the content of a metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if a metal oxide contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide is A, then Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ ) In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide (atomic number ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0102] For example, in the case of a metal oxide containing In, a transistor with a large on-current can be realized by increasing the In content.

[0103] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 21, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of threshold voltage fluctuation in a PBTS (Positive Bias Temperature Stress) test can be obtained. Furthermore, when using a metal oxide that contains Ga, it is preferable to make the Ga content lower than the In content. This makes it possible to realize a transistor with high mobility and high reliability.

[0104] On the other hand, by increasing the Ga content, a transistor with high reliability against light can be obtained. That is, a transistor with a small amount of variation in threshold voltage in a Negative Bias Temperature Illumination Stress (NBTIS) test can be obtained. Specifically, a metal oxide in which the atomic ratio of Ga is equal to or greater than the atomic ratio of In has a larger band gap, and the amount of variation in threshold voltage of the transistor in the NBTIS test can be reduced.

[0105] Furthermore, by increasing the zinc content, the metal oxide becomes highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0106] The semiconductor layer 21 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 21 may have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. A stacked structure in which two or more oxide semiconductor layers with different compositions are stacked may also be used. Furthermore, by using the ALD method, it is possible to form a metal oxide layer whose composition varies continuously in the thickness direction. This not only broadens the range of design options compared to using a film with a fixed composition, but also prevents the generation of interface states between two layers with different compositions, thereby improving electrical characteristics and reliability. Furthermore, a metal oxide layer having a stacked structure may be formed using both the sputtering method and the ALD method.

[0107] When the semiconductor layer 21 has a two-layer structure, it is preferable to use a material with higher mobility (higher conductivity) in the second layer, i.e., the side closer to the gate electrode, than in the first layer. This allows for a transistor that is normally off and has a large on-current. This makes it possible to achieve both low power consumption and high performance. Alternatively, a material with higher mobility than in the second layer may be used in the first layer, i.e., the side in contact with the source electrode and drain electrode. This reduces the contact resistance between the semiconductor layer 21 and the source electrode or drain electrode, thereby reducing parasitic resistance and enabling a transistor with a large on-current.

[0108] Furthermore, when the semiconductor layer 21 has a three-layer structure, it is preferable to use a material for the second layer that has a higher mobility than the first and third layers, thereby realizing a transistor with a high on-current and high reliability.

[0109] The difference in the mobility and conductivity described above can be expressed, for example, by the indium content. In addition, whether or not an element other than indium that contributes to improving conductivity is included, and the content of that element, also affect the mobility and conductivity. Examples of high-mobility materials include In:Ga:Zn = 4:3:2, In:Zn = 1:1, In:Zn = 2:1, In:Zn = 4:1, In:Sn:Zn = 40:X:10 (where X is 0.1 or more and 5 or less, typically X = 1), or materials with compositions similar to these. On the other hand, materials with lower mobility or conductivity than the above-mentioned materials include In:Ga:Zn = 1:3:2, In:Ga:Zn = 1:3:4, In:Ga:Zn = 2:2:1, In:Ga:Zn = 1:1:1, In:Ga:Zn = 1:1:2, or materials with compositions similar to these.

[0110] It is preferable to use a crystalline metal oxide layer for the semiconductor layer 21. For example, a metal oxide layer having a single crystal structure, a CAAC structure, a polycrystalline structure, a nano-crystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 21, the density of defect states in the semiconductor layer 21 can be reduced, and a highly reliable semiconductor device can be realized.

[0111] When an IGZO (In—Ga—Zn—O-based oxide) film is used as the metal oxide layer applied to the semiconductor layer 21, the higher the crystallinity of the metal oxide layer, the more the defect level density in the semiconductor layer 21 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, the carrier concentration can be increased, and a transistor capable of passing a large current can be realized in some cases.

[0112] In particular, it is preferable to use indium oxide for the semiconductor layer 21. In particular, it is preferable to use a single-crystal indium oxide film. Note that it is preferable to use a crystalline film for the semiconductor layer 21, and it is particularly preferable to use indium oxide with a single-crystal structure. However, indium oxide with a polycrystalline structure or a microcrystalline structure can also be used. By using indium oxide with a single-crystal structure, carrier scattering at crystal grain boundaries can be suppressed, and a transistor with high field-effect mobility can be realized. Furthermore, a highly reliable transistor can be realized. When indium oxide with a polycrystalline structure is used, it is preferable that crystal grain boundaries are not observed at least in the channel formation region (the region overlapping with the conductive layer 23). As a result, even indium oxide with a polycrystalline structure can achieve the same effects as indium oxide with a single-crystal structure.

[0113] The thickness of the semiconductor layer 21 is preferably 2 nm to 50 nm, more preferably 2.5 nm to 30 nm, more preferably 2.5 nm to 20 nm, more preferably 5 nm to 20 nm, and even more preferably 5 nm to 10 nm. By setting the thickness of the semiconductor layer 21 within the above range, the crystallinity of the semiconductor layer 21 can be improved.

[0114] Among oxide semiconductors with high crystallinity, indium oxide is a film through which one or both of hydrogen and oxygen move more easily than, for example, an IGZO (In—Ga—Zn—O-based oxide) film. Therefore, indium oxide is a film through which one or both of hydrogen and oxygen are more easily supplied and discharged than, for example, an IGZO film. This means that excess oxygen or excess hydrogen, which can become carriers or fixed charges, is less likely to accumulate in the semiconductor layer 21, thereby making it possible to provide a transistor with good electrical characteristics and reliability.

[0115] The semiconductor layer 21 preferably has a reduced concentration of elements that reduce crystallinity. For example, the concentration of elements such as boron and aluminum is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

[0116] Furthermore, when indium oxide is used for the semiconductor layer 21, unintentionally mixed gallium has a tendency to easily bond with excess oxygen atoms, which may result in a large amount of fluctuation in threshold voltage in a PBTS (Positive Bias Temperature Stress) test. Therefore, when indium oxide is used for the semiconductor layer 21, the gallium concentration in the semiconductor layer 21 is preferably 1 atomic % or less, more preferably 0.1 atomic % or less, and even more preferably 0.01 atomic % (100 ppm) or less.

[0117] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as an off-state current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0118] The semiconductor device according to one embodiment of the present invention can be applied to, for example, a processor, a memory device, or various ICs. The transistor according to one embodiment of the present invention is capable of passing a large current and has an extremely low off-state current, and therefore, high-speed operation of a circuit and low power consumption can be achieved at the same time.

[0119] A semiconductor device according to one embodiment of the present invention can also be applied to a display device, for example. To increase the emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Since an OS transistor has a higher withstand voltage between the source and drain than a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the emission luminance of the light-emitting device.

[0120] When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the amount of current flowing through the light-emitting device can be precisely controlled. This allows for a larger number of gray levels in the pixel circuit. Furthermore, even if the electrical characteristics (e.g., resistance) of the light-emitting device fluctuate or vary, a stable current can flow.

[0121] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," "suppression of the influence of manufacturing variations in light-emitting devices," and the like.

[0122] OS transistors exhibit smaller variations in electrical characteristics due to radiation exposure than Si transistors, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0123] The semiconductor material that can be used for the semiconductor layer 21 is not limited to oxide semiconductors. For example, semiconductors made of simple elements or compound semiconductors can be used. Examples of semiconductors made of simple elements include silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. These semiconductor materials may contain impurities as dopants.

[0124] Alternatively, the semiconductor layer 21 may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0125] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0126] The crystallinity of the semiconductor material used for the semiconductor layer 21 is not particularly limited, and any of an amorphous semiconductor, a single-crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0127] <Gate Insulating Layer> The insulating layer 22 functions as a gate insulating layer of a transistor. When an oxide semiconductor is used for the semiconductor layer 21, it is preferable to use an oxide insulating film for at least the film of the insulating layer 22 that is in contact with the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide can be used. Alternatively, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can also be used for the insulating layer 22. Furthermore, the insulating layer 22 may have a stacked structure, for example, a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0128] Furthermore, the insulating layer 22 is preferably formed by laminating insulating materials made of high-k materials with a high dielectric constant, and preferably by using a laminate structure of a high-k material and a material with a higher dielectric strength than the high-k material. For example, the insulating layer 22 can be formed by laminating an insulating film (also referred to as ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order. Alternatively, the insulating layer 22 can be formed by laminating an insulating film (also referred to as ZAZA) in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in this order. Alternatively, the insulating film can be formed by laminating hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By using a laminate of an insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved and electrostatic breakdown can be suppressed.

[0129] Furthermore, a material exhibiting ferroelectricity may be used for the insulating layer 22. Examples of the material exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ (X is a real number greater than 0).

[0130] When the insulating layer 22 has a two-layer structure, it is preferable to use an insulating film having a function of capturing or fixing hydrogen as the film in contact with the semiconductor layer 21, and to use an insulating film having a barrier property against hydrogen as the film located on the conductive layer 23 side that functions as the gate electrode. This makes it possible to suppress diffusion of hydrogen from the conductive layer 23 side to the semiconductor layer 21, thereby realizing a highly reliable transistor.

[0131] As an insulating film that captures or fixes hydrogen, it is preferable to use a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, etc. Furthermore, as an insulating film having a barrier property against hydrogen, it is preferable to use a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, etc.

[0132] Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 21, and an insulating film having a barrier property against hydrogen may be used as a film located on the conductive layer 23 side. Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 21, and an insulating film that has a function of capturing or fixing hydrogen may be used as a film located on the conductive layer 23 side.

[0133] When the insulating layer 22 has a three-layer structure, it is preferable to use an insulating film made of a material through which oxygen easily diffuses as the film in contact with the semiconductor layer 21, an insulating film having barrier properties against hydrogen and oxygen as the film located on the conductive layer 23 side, and an insulating film having the function of capturing or fixing hydrogen as the film located between them. Silicon oxide or silicon oxynitride can be used as the material through which oxygen easily diffuses. With this structure, oxygen can be supplied to the semiconductor layer 21 from the film in contact with the semiconductor layer 21. Furthermore, the film located on the conductive layer 23 side prevents oxygen from diffusing toward the conductive layer 23, thereby suppressing oxidation of the conductive layer 23.

[0134] As the insulating film having a barrier property against oxygen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, a hafnium silicate film, etc. As the insulating film having a barrier property against oxygen and hydrogen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, etc.

[0135] When the insulating layer 22 has a four-layer structure, it is preferable to use an insulating film having a barrier property against oxygen as the film in contact with the semiconductor layer 21, followed by an insulating film made of a material through which oxygen easily diffuses, an insulating film having a function of capturing or fixing hydrogen, and an insulating film having a barrier property against hydrogen and oxygen, from the side closer to the semiconductor layer 21. That is, in addition to the above-mentioned three-layer structure, a configuration can be obtained in which a film in contact with the semiconductor layer 21 is added. By using an insulating film having a barrier property against oxygen as the film in contact with the semiconductor layer 21, oxygen can be prevented from being desorbed from the semiconductor layer 21. In this case, it is preferable to use an aluminum oxide film as the film in contact with the semiconductor layer 21. Aluminum oxide not only has a barrier property against oxygen but also has a function of capturing or fixing hydrogen, and therefore has the effect of preventing hydrogen from diffusing into the semiconductor layer 21.

[0136] When the insulating layer 22 has a stacked structure, each insulating film is preferably a thin film. For example, the thickness of the insulating layer 22 is 1 nm to 20 nm, preferably 3 nm to 10 nm, to reduce the subthreshold swing (also referred to as the S value) of the transistor. The thickness of each insulating film is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, still more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm.

[0137] As a specific example, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 21 side, and to set the thicknesses of these films to 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 21 side.

[0138] In this specification and the like, the barrier property refers to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that when hydrogen is described as a corresponding substance, it can refer to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0139] Here, a transistor using a metal oxide film can have stable electrical characteristics by being surrounded by an insulating film that has a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. Examples of insulating films that have a function of suppressing the permeation of impurities and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can also be used.

[0140] Examples of insulating film materials capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with an amorphous structure have dangling bonds in some oxygen atoms, which enhance their ability to capture or adhering hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Metal oxides may have crystalline regions and / or grain boundaries in some regions.

[0141] <Conductive Layer> The conductive layer 25a and the conductive layer 25b (hereinafter also collectively referred to as the conductive layer 25) are in contact with the semiconductor layer 21. When an oxide semiconductor is used as the semiconductor layer 21, if an easily oxidized metal such as aluminum is used in the portion of the conductive layer 25 in contact with the semiconductor layer 21, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 25 and the semiconductor layer 21, preventing electrical conduction therebetween. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material in at least the portion of the conductive layer 25 in contact with the semiconductor layer 21.

[0142] For the conductive layer 25 in contact with the semiconductor layer 21, it is preferable to use, for example, titanium, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. These are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when oxidized.

[0143] Alternatively, conductive oxides such as indium oxide, zinc oxide, In—Sn oxide, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide, and Ga—Zn oxide can be used. Conductive oxides containing indium are particularly preferred because of their high conductivity. Alternatively, oxide materials such as In—Ga—Zn oxide that can be used for the semiconductor layer 21 can also be used as a conductive layer by increasing the carrier concentration.

[0144] For example, the conductive layer 25 can be a single-layer structure of the above-mentioned conductive oxide film, a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are stacked in this order, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on tungsten, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on the above-mentioned conductive oxide film, or a two-layer structure in which the above-mentioned conductive oxide film is stacked on a ruthenium film or a ruthenium oxide film.

[0145] Note that the conductive layers 28a and 28b are preferably made of a conductive oxide that can be used for the conductive layer 25. The conductive layers 27a and 27b are preferably made of the conductive material that is not easily oxidized or a material that maintains its conductivity even when oxidized.

[0146] The conductive layer 23, as well as the conductive layers 24a and 24b (hereinafter collectively referred to as the conductive layer 24) preferably uses a low-resistance conductive material. For the conductive layer 23 and the conductive layer 24, it is preferable to use a metal element selected from the group consisting of aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing such a metal element. Nitrides of the above metals or alloys, or oxides of the above metals or alloys, may also be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferably used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may also be used.

[0147] The conductive layers 23 and 24 may be made of the nitrides and oxides that can be used for the conductive layer 25 .

[0148] <Insulating Layer> The insulating layer 41, the insulating layer 42, and the insulating layer 43 can be used as interlayer insulating films. For example, they are preferably formed by a film formation method such as a sputtering method or a plasma CVD method. In particular, when a sputtering method is used, hydrogen gas is not used as a film formation gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 10 can be stabilized.

[0149] The insulating layers 41, 42, and 43 preferably have a low dielectric constant. By using a material with a low dielectric constant as the interlayer insulating film, the parasitic capacitance generated between wirings can be reduced. For example, it is preferable to have one or more of silicon oxide, silicon oxynitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide having vacancies. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.

[0150] Since the insulating layers 41, 42, and 43 function as interlayer insulating layers, it is preferable to use a film formation method that allows film formation at a high film formation rate compared to other insulating layers. For example, the insulating layers 41, 42, and 43 may be formed using TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC ２ H ５ ) ４ Alternatively, a silicon oxide film formed by plasma CVD using a silicon dioxide film containing SiO 2 may be used. This can improve productivity.

[0151] The insulating layer 11, which functions as a base insulating layer, also functions as an interlayer insulating layer. The insulating layer 11 can be made of the same insulating material as can be used for the insulating layers 41, 42, and 43.

[0152] It is preferable that the insulating layer 44 is made of a material different from that of the insulating layer 41. This allows the insulating layer 44 to be used as an etching stop film when processing the insulating layer 41. For example, when silicon oxide or silicon oxynitride is used for the insulating layer 41, it is preferable that the insulating layer 44 is made of a nitride or oxide containing an element different from that of the insulating layer 41, such as silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, or hafnium oxide.

[0153] This concludes the description of the components.

[0154] [Manufacturing Method Example 1] An example of a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described below, taking the transistor 10 exemplified in the above structure example as an example.

[0155] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0156] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0157] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0158] CVD methods can be classified into plasma-enhanced chemical vapor deposition (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (photo-CVD), which uses light. CVD methods can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0159] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, since the thermal CVD method does not use plasma, it is possible to minimize plasma damage to the workpiece. Furthermore, since the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0160] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0161] Unlike sputtering, CVD and ALD are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which have a faster film formation rate.

[0162] In the CVD method, a film of any composition can be formed by adjusting the flow rate ratio of the source gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0163] In the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors. Alternatively, when multiple different precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor. Furthermore, as with the CVD method, a film with a continuously changing composition can be formed.

[0164] The thin film constituting the semiconductor device can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Alternatively, the island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0165] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0166] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0167] Thin film etching can be performed using methods such as dry etching, wet etching, and sandblasting. Dry etching can be performed isotropically or anisotropically by controlling the etching conditions. Wet etching can be performed isotropically.

[0168] 4 to 10 (FIGS. 4A to 10E) will be used to describe an example of a method for manufacturing the transistor 10. For example, FIG. 4A corresponds to FIG. 1A and is a schematic top view of a manufacturing process of the transistor 10, FIGS. 4B, 4C, and 4D are schematic cross-sectional views corresponding to FIGS. 1B, 1C, and 1D, respectively, and FIG. 4E is a schematic perspective view corresponding to FIG. 1E.

[0169] First, a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate.

[0170] The substrate may be a substrate having heat resistance sufficient to withstand at least the subsequent heat treatment.

[0171] An inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used as the insulating layer 11. The insulating layer 11 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. If the surface on which the insulating layer 11 is to be formed is not flat, a planarization process may be performed after the insulating layer 11 is formed so that the upper surface of the insulating layer 11 becomes flat.

[0172] Subsequently, an insulating layer 43 is formed on the insulating layer 11, and the conductive layers 24a and 24b are embedded in the insulating layer 43.

[0173] For example, a conductive film that will become the conductive layers 24 a and 24 b is first formed, and unnecessary portions are removed by etching using photolithography to form the conductive layers 24 a and 24 b. Subsequently, an insulating film that will become the insulating layer 43 is formed, and then planarization treatment is performed using a chemical mechanical polishing (CMP) method or the like so that the top surfaces of the conductive layers 24 a and 24 b are exposed, thereby forming the insulating layer 43.

[0174] The conductive layers 24a and 24b may be formed by depositing an insulating layer 43 on the insulating layer 11, forming openings in the insulating layer 43 at positions where the conductive layers 24a and 24b will be provided, depositing a conductive film that will become the conductive layers 24a and 24b, and performing a planarization treatment so that the top surface of the insulating layer 43 is exposed.

[0175] Next, an insulating layer 44 is formed to cover the insulating layer 43 and the conductive layers 24a and 24b. The insulating layer 44 is formed using an insulating material different from that of the insulating layer 41 to be formed later. The insulating layer 44 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method. For example, the insulating layer 44 can be formed using one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate. Silicon nitride and silicon nitride oxide, in particular, have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being impermeable to oxygen and hydrogen. Therefore, they are preferable because they can prevent hydrogen from diffusing into the semiconductor layer 21 from the structure located below the insulating layer 44 and prevent oxygen from the semiconductor layer 21 from diffusing below the insulating layer 44.

[0176] Subsequently, an insulating film 41A, which will later become the insulating layer 41, is formed on the insulating layer 44.

[0177] The insulating film 41A is preferably formed by a deposition method such as a sputtering method or a plasma CVD method. Since the insulating layer 41 is in contact with the semiconductor layer 21, the use of a sputtering method in particular eliminates the need for hydrogen in the deposition gas, and therefore the film can have an extremely low hydrogen content. This can suppress the supply of hydrogen to the semiconductor layer 21, thereby stabilizing the electrical characteristics of the transistor 10.

[0178] Furthermore, since the insulating layer 41 is in contact with the channel formation region of the semiconductor layer 21, it is preferable to use an oxide insulating film for the insulating film 41A. In particular, it is preferable to use an oxide insulating film that releases oxygen when heated. It is preferable to use an oxide insulating film such as silicon oxide or silicon oxynitride as the insulating film 41A.

[0179] Subsequently, heat treatment may be performed. The heat treatment is preferably performed at a temperature of 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration is preferably about 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher to compensate for desorbed oxygen after the heat treatment in the nitrogen gas or inert gas atmosphere. By performing the above heat treatment, impurities such as water and hydrogen contained in the insulating film 41A or the like can be reduced before the formation of an oxide semiconductor film to be a semiconductor layer.

[0180] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is set to 1 ppb (0.001 ppm) or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being introduced into the insulating layer 41 and the like as much as possible.

[0181] After the insulating film 41A is formed, a process of supplying oxygen may be performed, whereby oxygen can be supplied from the insulating layer 41A to the semiconductor film 21f by heat or the like applied after the semiconductor film 21f is formed.

[0182] Examples of the treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma) in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the insulating layer by forming an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere by sputtering. The formed oxide film may be removed immediately or may be left as it is. Note that the oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３ ), nitrous oxide (N ２ The atmosphere may include a gas containing an oxygen-containing compound such as oxygen (O).

[0183] Note that one or both of the heat treatment and the oxygen supply treatment may be performed after processing the insulating film 41A into the insulating layer 41 and before forming the semiconductor film 21f.

[0184] Next, a pair of openings are formed in the insulating film 41A and the insulating layer 44, reaching the conductive layer 24a and the conductive layer 24b, respectively. The openings are preferably formed using anisotropic dry etching. This allows for the formation of openings with a high aspect ratio. Alternatively, a hard mask may be used as an etching mask for processing. The hard mask may be made of a material that has a high etching rate selectivity relative to the insulating film 41A, and may be an insulating film, a conductive film, or a semiconductor film.

[0185] Subsequently, a conductive film is formed to fill the openings, and planarization treatment is performed to expose the upper surface of the insulating film 41A, thereby forming conductive layers 25a and 25b (FIGS. 4A to 4E).

[0186] Next, a layer 21S having an elongated shape (also referred to as a strip shape) in a plan view is formed in contact with the top surfaces of the insulating film 41A, the conductive layer 25a, and the conductive layer 25b ( FIGS. 5A to 5E ). The layer 21S is formed by depositing a film to become the layer 21S and then removing unnecessary portions by photolithography. The layer 21S is provided so as to be in contact with the top surfaces of the conductive layers 25a and 25b and with a part of the insulating film 41A therebetween. Here, the resist mask 35 used in processing the layer 21S is preferably left unremoved because it is also used as an etching mask for the insulating film 41A later.

[0187] The layer 21S has crystals. The layer 21S functions as a seed or nucleus when crystals of the semiconductor film 21f that becomes the semiconductor layer 21 grow. In this specification and the like, the layer 21S or the crystals of the layer 21S can be referred to as a seed crystal or a crystal nucleus. Furthermore, since the layer 21S has crystals, the layer 21S can be referred to as a crystal portion.

[0188] Next, the portions of the insulating film 41A that are not covered by the resist mask 35 and the layer 21S are removed by etching, thereby forming the fin-shaped insulating layer 41. The resist mask 35 is then removed (FIGS. 6A to 6E). When an anisotropic dry etching method is used to etch the insulating film 41A, the side surfaces of the fin-shaped insulating layer 41 can be processed to be approximately perpendicular to the surface on which the insulating film 41 is formed, which is preferable because it allows the insulating layer 41 to have a high aspect ratio.

[0189] Next, a semiconductor film 21f is formed to cover the insulating layer 44, the conductive layer 25a, the conductive layer 25b, the insulating layer 41, and the layer 21S (FIGS. 7A to 7E). The semiconductor film 21f can be formed by ALD or sputtering, but the ALD method is preferable because it has higher coverage than the sputtering method and can satisfactorily cover the side surfaces of the insulating layer 41, the conductive layer 25a, and the conductive layer 25b.

[0190] By performing a heat treatment during or after the formation of the semiconductor film 21f, or both, crystal growth can proceed using the crystals contained in the layer 21S as crystal nuclei, thereby forming the semiconductor film 21f with high crystallinity. Note that the above description can be referred to for the method of the heat treatment.

[0191] When the semiconductor film 21f is formed by the ALD method, a first precursor and a first oxidizing agent can be used. The first precursor preferably contains indium. In this case, an indium oxide film is formed as the semiconductor film 21f. That is, an oxide film containing a single element other than oxygen is formed. Note that it is preferable to use a thermal ALD method as the ALD method.

[0192] Examples of precursors that can be used that contain indium include trimethylindium, triethylindium, ethyldimethylindium, tris(1-methylethyl)indium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) acetylacetonate, (3-(dimethylamino)propyl)dimethylindium, (diethylphosphino)dimethylindium, chlorodimethylindium, bromodimethylindium, and dimethyl(2-propanolato)indium.

[0193] Alternatively, an inorganic precursor containing no hydrocarbon may be used as the indium-containing precursor. Examples of the inorganic precursor containing indium include halogen-based indium compounds such as trifluoroindium (indium(III) fluoride), indium trichloride (indium(III) chloride), indium tribromide (indium(III) bromide), and indium triiodide (indium(III) iodide). Indium trichloride has a decomposition temperature of approximately 500°C to 700°C. Therefore, by using indium trichloride, film formation can be performed by the ALD method while heating the substrate at approximately 400°C to 600°C, for example, at 500°C.

[0194] To form the semiconductor film 21f, it is preferable to use a material with a low impurity concentration, i.e., a high-purity precursor. For example, the purity is preferably 3N (99.9%) or higher, more preferably 4N (99.99%) or higher, even more preferably 5N (99.999%) or higher, and even more preferably 6N (99.9999%) or higher. By using a high-purity material, it is possible to reduce the impurities in the semiconductor film 21f.

[0195] The gallium content and aluminum content of the indium-containing precursor are preferably 1000 ppm or less, more preferably 500 ppm or less, even more preferably 100 ppm or less, still more preferably 50 ppm or less, even more preferably 10 ppm or less, and still more preferably 1 ppm or less. By using a precursor with a low gallium content, the gallium concentration in the semiconductor film 21f can be reduced, thereby improving the reliability of the transistor. Furthermore, by using a precursor with a low aluminum content, the aluminum concentration in the semiconductor film 21f can be reduced, thereby improving the crystallinity of the semiconductor film 21f.

[0196] As the first oxidant, ozone (O ３ ), oxygen (O ２ ), water (H ２ O), hydrogen peroxide (H ２ O ２ ) or the like can be used. The first oxidizing agent preferably contains at least one of ozone and oxygen. By using ozone, oxygen, or the like that does not contain hydrogen as the first oxidizing agent, the amount of hydrogen mixed into the insulating layer 41 can be reduced. Note that the first oxidizing agent can contain at least one of water and hydrogen peroxide. This allows the semiconductor film 21f to have low crystallinity.

[0197] After forming the semiconductor film 21f with low crystallinity, the layer 21S is used as a crystal nucleus and then crystallized by heat treatment, thereby forming the semiconductor film 21f having a polycrystalline structure with large crystal grains or a single-crystalline structure.

[0198] It is particularly preferable to use indium oxide as the semiconductor film 21f.

[0199] Indium oxide crystals have a cubic crystal structure (bixbyite type). When indium oxide is used for the semiconductor film 21f, the layer 21S preferably has, for example, the same cubic crystal structure as indium oxide.

[0200] Alternatively, the layer 21S preferably has crystals with a hexagonal or trigonal structure. In this case, by having crystals in the layer 21S with a <001> crystal orientation relative to the surface or the surface on which the layer 21S is formed, the semiconductor film 21f can be formed with crystals with a <111> crystal orientation. Note that crystals with a layered crystal structure can be used as the crystals with a hexagonal or trigonal structure. In this case, the semiconductor film 21f with crystals with a cubic crystal structure can be formed on the layer 21S with crystals with a layered structure. That is, it can also be considered as a stacked structure fabricated using a technique such as heteroepitaxial growth, heteroepitaxial growth, or axial growth. Note that axial growth here refers to a state in which at least one of the crystal axes or crystal orientations of the layer 21S coincides or approximately coincides with one of the crystal axes or crystal orientations of the semiconductor film 21f.

[0201] It is preferable to use a material for the layer 21S that has a crystal structure with a small degree of lattice mismatch with the crystal structure of the material constituting the semiconductor film 21f, which makes it easier for heteroepitaxial growth or axial growth to occur when the semiconductor film 21f is formed on the layer 21S, facilitating the crystallization of a portion of the semiconductor film 21f.

[0202] One method for evaluating the degree of lattice mismatch is the lattice mismatch ratio. The lattice mismatch ratio Δa [%] of the crystals of the formed film to the crystals of the film to be formed is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit lattice vector or the lattice constant of the crystal of the film to be formed.

[0203] The smaller the absolute value of the lattice mismatch Δa between the layer 21S and the semiconductor film 21f, the more preferable, and it is most preferable that the lattice mismatch Δa be 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0204] The layer 21S preferably contains, for example, a metal oxide containing the same metal element as the semiconductor film 21f. In particular, both the layer 21S and the semiconductor film 21f preferably contain one or more of indium, tin, and zinc. In particular, it is more preferable that both the layer 21S and the semiconductor film 21f contain indium.

[0205] The layer 21S may be a metal oxide film having a cubic crystal structure, such as indium oxide or indium-tin oxide. Alternatively, a metal oxide film having a hexagonal crystal structure, such as zinc oxide, In—Ga oxide, gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), In—Al—Zn oxide, In—Ga—Zn oxide, or In—Sn—Zn oxide, may be used. Alternatively, a metal oxide film having a tetragonal crystal structure, such as tin oxide or titanium oxide, may be used.

[0206] It is preferable to use In—Ga—Zn oxide as the layer 21S. In this case, the layer 21S contains indium, gallium, zinc, and oxygen. Specifically, it is preferable to use a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto, or a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition close thereto. Metal oxides of these compositions are suitable for the layer 21S because they easily form a layered structure. Note that a composition close thereto includes a range of ±30% of the desired atomic ratio.

[0207] In—Ga—Zn oxide and In—Sn—Zn oxide, for example, tend to have a c-axis aligned crystal (CAAC) structure. When an oxide having a CAAC structure is used for the layer 21S, the c-axis of the crystal nuclei is perpendicular or approximately perpendicular to the surface of the layer 21S or the surface on which it is formed. In other words, by using an oxide that tends to have a CAAC structure for the layer 21S, it is possible to improve the controllability of the crystal orientation of the crystal nuclei. That is, indium oxide formed on the layer 21S having a CAAC structure tends to become crystals in which the crystal orientation <111> is oriented perpendicular to the surface on which it is formed.

[0208] In the semiconductor film 21f formed to cover the layer 21S, crystal growth begins at the portion in contact with the layer 21S and proceeds downward along the side surface of the insulating layer 41. The crystal growth can occur during the formation of the semiconductor film 21f, during a heat treatment after the formation of the semiconductor film 21f, or both. This allows the formation of the semiconductor film 21f having a single crystal grain from the portion in contact with the upper end to the portion in contact with the lower end of the side surface of the insulating layer 41.

[0209] The semiconductor film 21f formed in this manner can have a polycrystalline structure with large crystal grains or a single-crystal structure. This reduces the number of crystal grain boundaries located on the current path in the channel formation region, resulting in a transistor 10 capable of passing a larger current. In particular, since the semiconductor film 21f has larger crystal grains than when the layer 21S is not used, it is possible to form the channel formation region with a single crystal grain, and the semiconductor film 21f can be considered substantially single-crystal in the channel formation region. A single-crystal semiconductor film 21f is more preferable because no crystal grain boundaries exist on the current path in the channel formation region.

[0210] The semiconductor film 21f may be made of a metal oxide other than indium oxide, as described above. Even in this case, the semiconductor film 21f can have high crystallinity.

[0211] The semiconductor film 21f can also be formed by sputtering. The semiconductor film 21f can be formed by sputtering using a metal oxide target. In this case, it is preferable to form the film under conditions that make crystallization as difficult as possible. For example, an amorphous semiconductor film 21f can be formed by forming the film under conditions in which the substrate temperature during film formation is from room temperature to 100°C, preferably from room temperature to 80°C, and more preferably from room temperature to 50°C. In particular, it is preferable to form the film without heating the substrate. Furthermore, conditions that make crystallization difficult can also be achieved by lowering the oxygen content in the film formation gas. For example, the ratio of oxygen gas (O ２ The ratio of the flow rate of the gas) can be set to 0% or more and 10% or less, preferably 0% or more and 5% or less.

[0212] Immediately after the semiconductor film 21f with low crystallinity is formed, a crystalline region that reflects the crystal orientation of the layer 21S can be formed in the region in contact with the layer 21S. By subsequently performing a heat treatment, crystal growth progresses, and the semiconductor film 21f with high crystallinity can be formed.

[0213] Next, anisotropic dry etching is performed on the semiconductor film 21f to remove the insulating layer 41, the conductive layer 25a, and the conductive layer 25b, leaving only the portions located on their respective side surfaces, thereby forming the semiconductor layer 21 (FIGS. 8A to 8E). At this time, the layer 21S is also removed. Note that if the etching rate selectivity of the layer 21S relative to the semiconductor film 21f is high, the layer 21S may remain. By etching the semiconductor film 21f, the upper surfaces of the insulating layer 41, the conductive layer 25a, and the conductive layer 25b are exposed.

[0214] Subsequently, an insulating layer 42 is formed to cover the insulating layer 44, the semiconductor layer 21, the insulating layer 41, the conductive layer 25a, the conductive layer 25b, etc. (FIGS. 9A to 9E). Thereafter, it is preferable to planarize the upper surface of the insulating layer 42.

[0215] Next, a portion of the insulating layer 42 is removed by etching to form the insulating layer 44, the semiconductor layer 21, and the slit 20 that reaches the insulating layer 41 (FIGS. 10A to 10E). The insulating layer 42 is preferably formed using an anisotropic dry etching method.

[0216] Subsequently, an insulating layer 22 is formed to cover the insulating layer 42, the insulating layer 44, the semiconductor layer 21, and the insulating layer 41, and to cover the inside of the slit 20 and the upper surface of the insulating layer 42. The insulating layer 22 is preferably formed by the ALD method, which has high coverage.

[0217] Subsequently, a conductive film is formed so as to fill the slits 20, and then a planarization process is performed until the upper surface of the insulating layer 42 is exposed, thereby forming the conductive layer 23 buried in the slits 20.

[0218] Through the above steps, the transistor 10 illustrated in FIGS. 1A to 1E can be manufactured.

[0219] This concludes the description of the first manufacturing method example.

[0220] [Manufacturing Method Example 2] Hereinafter, a manufacturing method example of a semiconductor device will be described, which is partly different from Manufacturing Method Example 1. Note that description of parts that overlap with Manufacturing Method Example 1 will be omitted.

[0221] The following describes a configuration in which low-resistance regions are provided between the channel formation region of the semiconductor layer 21 and the conductive layer 25 a, and between the channel formation region and the conductive layer 25 b, which can reduce the parasitic resistance between the source and drain, and further increase the on-current.

[0222] 11A to 11D are schematic perspective views illustrating the steps of the following exemplary fabrication method.

[0223] First, similarly to Manufacturing Method Example 1, an insulating layer 43, conductive layers 24a, 24b, an insulating layer 44, conductive layers 25a, 25b, an insulating layer 41, and a semiconductor layer 21 are formed over an insulating layer 11.

[0224] Next, a sacrificial layer 31 is formed to cover the insulating layer 44, the semiconductor layer 21, and a part of the insulating layer 41 ( FIG. 11A ). The sacrificial layer 31 is provided to cover a region that will become a channel formation region of the semiconductor layer 21. The sacrificial layer 31 can also be formed at a position where the insulating layer 22 and the conductive layer 23 will be provided later.

[0225] The sacrificial layer 31 is preferably made of a material having a high etching selectivity with respect to the semiconductor layer 21, the insulating layer 44, the insulating layer 42, and the insulating layer 41 so that the semiconductor layer 21, the insulating layer 44, the insulating layer 42, and the insulating layer 41 are not etched when the sacrificial layer 31 is subsequently removed. For example, the sacrificial layer 31 can be made of an organic or inorganic material formed by a coating method. More specifically, a coating-type insulating film such as an SOC (spin on carbon) film or an SOG (spin on glass) film can be used. Alternatively, the sacrificial layer 31 can be formed by a film formation method such as a sputtering method or a CVD method. The material used for the sacrificial layer 31 preferably satisfies the following conditions: it can be formed thick, it can be formed or processed vertically, and it is easy to remove (leaving no residue and causing minimal damage to the surface on which it is formed).

[0226] The sacrificial layer 31 can be formed by forming a film to be the sacrificial layer 31, forming a resist mask thereon, and then etching away the areas not covered by the resist mask. In this process, the width of the sacrificial layer 31 corresponds to the width of the slits 20 to be formed later. Therefore, the narrower the width of the sacrificial layer 31, the shorter the channel length of the transistor 10 that can be fabricated. To finely process the sacrificial layer 31, it is preferable to use a stacked film of an SOC film and an inorganic film that will serve as a hard mask as the film to be the sacrificial layer 31. The inorganic film can be the SOG film or an inorganic film formed by sputtering, CVD, or the like.

[0227] The width of the sacrificial layer 31 (i.e., the width of the slit 20) is preferably 3 nm to 30 nm, more preferably 4 nm to 25 nm, and even more preferably 5 nm to 20 nm. This allows a transistor with an extremely short channel length to be realized. Note that if miniaturization of the channel length is not required, the width can be greater than 30 nm.

[0228] Subsequently, a process of supplying impurities to the exposed region of the semiconductor layer 21 is performed to form a low-resistance region 21N in part of the semiconductor layer 21 (FIG. 11B).

[0229] The impurity may be an element that increases the carrier concentration of the metal oxide contained in the semiconductor layer 21. Examples of such elements include titanium, aluminum, tantalum, tungsten, tin, silicon, germanium, zirconium, hafnium, antimony, and magnesium. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0230] Alternatively, one or more of hydrogen, boron, phosphorus, and noble gases (helium, neon, argon, krypton, xenon, etc.) can be used as impurities. For example, BH ３ , P.H. ４ By using a gas such as the above and supplying it to the semiconductor layer 21 without mass separation, boron or phosphorus and hydrogen can be supplied into the semiconductor layer 21 at the same time.

[0231] In this manner, the region with a low carrier concentration in the semiconductor layer 21 can be used as the channel formation region (region 21C) of the transistor, and the region with a high carrier concentration in the semiconductor layer 21 can be used as the source and drain regions of the transistor, thereby realizing a transistor 10 that has high mobility, a low off-state current, and is capable of being normally off.

[0232] For example, in the channel formation region (region 21C) of the transistor, the carrier concentration is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ When indium oxide is used for the semiconductor layer 21, the carrier concentration can be sufficiently reduced to achieve a hole mobility value of 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0233] The region 21N functions as a source region and a drain region of the transistor. In the region 21N, the carrier concentration is 1×10 ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By making the carrier concentration sufficiently high, the sheet resistance can be set to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0234] For example, ion implantation can be used as a supply process for impurity elements. Ion implantation can control the concentration profile in the depth direction with high precision by adjusting the acceleration energy and dose of ions. Furthermore, by using an ion implantation method in which a source gas is ionized and the ions are mass-separated before supply, ions of a specific mass can be supplied, thereby increasing the purity of the supplied element. Alternatively, by using an ion implantation method in which ions are supplied without mass separation, productivity can be increased. Unless otherwise specified in this specification, the presence or absence of mass separation is not limited. Note that a method in which ions are mass-separated before supplying them is sometimes called an ion implantation method, and a method in which ions are supplied without mass separation is sometimes called an ion doping method.

[0235] After the impurity element supplying treatment, heat treatment may be performed. The heat treatment method can be as described above.

[0236] Next, an insulating layer 42 is formed to cover the insulating layer 44, the semiconductor layer 21, the conductive layer 25a, the conductive layer 25b, the insulating layer 41, the sacrificial layer 31, etc., and then a planarization process is performed to expose the upper surface (upper portion) of the sacrificial layer 31. Thereafter, the sacrificial layer 31 is removed to form a slit 20 in the insulating layer 42 ( FIG. 11C ).

[0237] At this time, as shown in FIG. 11C, the region of the semiconductor layer 21 located inside the slit 20 becomes a high-resistance region 21C, and the region covered with the insulating layer 42 becomes a low-resistance region 21N.

[0238] Thereafter, an insulating layer 22 and a conductive layer 23 are formed in the same manner as in the above-described Manufacturing Method Example 1, thereby completing the manufacturing of a transistor (FIG. 11D).

[0239] By using such a method, a transistor with high on-state current can be manufactured.

[0240] [Modification of Manufacturing Method Example] Hereinafter, a manufacturing method example of a semiconductor device that is partly different from the above Manufacturing Method Example 2 will be described.

[0241] First, the process is carried out in the same manner as in the above-described Example 2 of the manufacturing method, up to the formation of the sacrificial layer 31 (FIG. 12A).

[0242] Subsequently, an insulating layer 32 is formed to cover the insulating layer 44, the semiconductor layer 21, the conductive layer 25a, the conductive layer 25b, the insulating layer 41, the sacrificial layer 31, etc. ( FIG. 12B ). The insulating layer 32 may be made of the same material as the insulating layer 44. The insulating layer 32 has a portion provided along the side surface of the sacrificial layer 31.

[0243] Next, an impurity element is supplied to the region of the semiconductor layer 21 that is not covered by the sacrificial layer 31 via the insulating layer 32. At this time, the impurity element is not supplied to the region of the semiconductor layer 21 that is covered by the portion of the insulating layer 32 that is in contact with the side surface of the sacrificial layer 31. Furthermore, supplying the impurity element via the insulating layer 32 has the advantages of preventing the impurity element from being released again and reducing damage to the semiconductor layer 21.

[0244] Next, an insulating layer 42 is formed in the same manner as in the second manufacturing method, and then planarization is performed to expose the upper surface of the sacrificial layer 31. The sacrificial layer 31 is then removed (FIG. 12C). In FIG. 12C, only the outline of the insulating layer 32 is shown.

[0245] At this time, a low-resistance region 21N is formed in the region of the semiconductor layer 21 that overlaps with the insulating layer 42. On the other hand, a region 21L that does not overlap with the insulating layer 42 but overlaps with the insulating layer 32 becomes a region with a low carrier concentration and high resistance, similar to the region 21C that becomes the channel formation region. By providing such a region 21L, it is possible to suppress the diffusion of impurity elements from the region 21N to the region 21C, and it is possible to realize a transistor that has good switching characteristics and high reliability even when the channel length is extremely short.

[0246] Thereafter, an insulating layer 22 and a conductive layer 23 are formed in the same manner as in the above-described Manufacturing Method Example 2, thereby completing the transistor (FIG. 12D).

[0247] 12D has a configuration in which an insulating layer 32 is provided between the semiconductor layer 21, the conductive layer 25a, the conductive layer 25b, the insulating layer 41, and the insulating layer 22 and the insulating layer 42. By using a film having a barrier property against hydrogen for the insulating layer 32, the insulating layer 32 functions as a protective layer and can prevent hydrogen from diffusing from the outside into the semiconductor layer 21, thereby realizing a highly reliable transistor.

[0248] The above is a description of the modified example of the manufacturing method.

[0249] [Application Examples] Application examples of the transistor 10 illustrated in the above configuration example will be described below.

[0250] 13 shows an example of a configuration having a plurality of insulating layers 41. The plurality of insulating layers 41 are arranged at equal intervals in the direction of the short sides of the insulating layers 41 in a plan view. Although Fig. 13 shows an example of an arrangement of three insulating layers 41, two or four or more insulating layers may also be arranged.

[0251] The conductive layers 25a and 25b each have a rectangular shape with rounded corners in a plan view so as to contact all of the insulating layers 41. The conductive layers 25a and 25b are provided so that their longitudinal directions intersect (preferably perpendicular to) the longitudinal direction of the insulating layers 41. The conductive layer 25a is connected to the conductive layer 24b (not shown), and the conductive layer 25b is connected to the conductive layer 24b.

[0252] This configuration makes it possible to realize a transistor with a large channel width. That is, when n insulating layers 41 are provided (n is a natural number of 2 or more), the channel width can be n times larger than that of a configuration having one insulating layer 41. This allows a large current to flow, thereby achieving high-speed circuit operation.

[0253] 13 may be able to suppress the occurrence of structural defects (structural defects in the semiconductor layer 21 due to a defective shape of the insulating layer 41, stress in the insulating layer 42, or the transistor manufacturing process) that may occur in the semiconductor layer 21. This is expected to have the same effect as the technology of providing dummy gates at both ends of a fin-type semiconductor region in a silicon transistor to suppress the occurrence of structural defects in the semiconductor region.

[0254] Although an example in which the shapes of the conductive layers 25a and 25b are different from those described above has been shown, a configuration in which cylindrical conductive layers 25a and 25b as exemplified in the above configuration example are provided in the same number as the number of insulating layers 41. In that case, a configuration in which the conductive layers 24a and 24b are connected to each conductive layer 25a or each conductive layer 25b can be used.

[0255] {Application Example 2} The configuration shown in FIG. 14A is an example in which a transistor 10 and a transistor 10FE are connected in series between a conductive layer 25a and a conductive layer 25b.

[0256] The transistor 10FE has a configuration in which the insulating layer 22 functioning as the gate insulating layer of the transistor 10 is replaced with an insulating layer 22FE.

[0257] The insulating layer 22FE can be made of an insulating material exhibiting ferroelectricity. This allows the transistor 10FE to be used as a ferroelectric transistor (FeFET: Ferroelectric Field Effect Transistor). Another configuration of a ferroelectric transistor is one in which a ferroelectric capacitor is connected to the gate of the transistor. The threshold voltage of a ferroelectric transistor can be changed by applying a voltage above a certain level to the gate. This allows data to be retained, allowing the ferroelectric transistor to function as a nonvolatile memory element. In this case, the insulating layer 22FE can also be said to function as a dielectric layer of the ferroelectric transistor.

[0258] Ferroelectric materials suitable for the insulating layer 22FE include oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. It is also preferable to use materials containing Group 3 (IIIa) elements added to these oxides. For example, it is preferable to include one or more elements selected from the group consisting of scandium, yttrium, and lanthanides. Adding such elements can stably exhibit ferroelectricity, suppress characteristic degradation during repeated rewriting, improve reliability, and increase the breakdown voltage of the insulating layer 22FE. In addition to ferroelectric materials, antiferroelectric materials can also be used for the insulating layer 22FE.

[0259] Oxides containing one or both of hafnium and zirconium easily exhibit ferroelectricity even in extremely thin films prepared using thin film deposition methods such as sputtering and ALD, and therefore have high compatibility with semiconductor manufacturing processes, allowing for reduced manufacturing costs.

[0260] Alternatively, the insulating layer 22FE may be made of piezoelectric ceramics having a perovskite structure, such as barium titanate, lead titanate, strontium titanate, barium strontium titanate (BST), lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), etc. Alternatively, the insulating layer 22FE may be made of an organic ferroelectric material, such as polyvinylidene fluoride (PVDF) or a copolymer of vinylidene fluoride (VDF) and trifluoroethylene (TrFE).

[0261] Among these, hafnium oxide, a material containing hafnium oxide and zirconium oxide (HZO), and a material containing yttrium in addition to HZO (HZYO) are preferred as materials exhibiting ferroelectricity because they exhibit ferroelectricity even in thin films of only a few nanometers. By using a film containing hafnium oxide, HZO, or HZYO, the film thickness of the insulating layer 22FE can be set to 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 3 nm or more and 20 nm or less, and even more preferably 4 nm or more and 10 nm or less.

[0262] Although an example in which an insulating layer exhibiting ferroelectricity is used as insulating layer 22FE of transistor 10FE has been shown here, it may also have the same configuration as insulating layer 22. In that case, two transistors connected in series may be provided between conductive layer 25a and conductive layer 25b.

[0263] 14B is an example in which a transistor 10 and a capacitor 80 are provided between a conductive layer 25 a and a conductive layer 25 b. Since the capacitor is connected to one of the source and the drain of the transistor 10, the structure shown in FIG. 14B can be used as a memory cell of a dynamic random access memory (DRAM).

[0264] The capacitor 80 includes a part of the semiconductor layer 21, a conductive layer 82, and an insulating layer 81 located therebetween. The part of the semiconductor layer 21 functions as one electrode of the capacitor 80. The insulating layer 81 functions as a dielectric layer of the capacitor 80.

[0265] The insulating layer 81 is provided to cover the insulating layer 44, the semiconductor layer 21, and the insulating layer 41. The conductive layer 82 is provided to cover the insulating layer 81. The insulating layer 42 is provided to cover the capacitor element 80.

[0266] The insulating layer 81 preferably contains a material with a higher dielectric constant than silicon oxide. For example, silicon nitride, zirconium oxide, aluminum oxide, etc. By stacking and using an insulator with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved and electrostatic breakdown can be suppressed.

[0267] Although an example in which a part of the semiconductor layer 21 is used as one electrode of the capacitor 80 has been shown here, a conductive layer in contact with the semiconductor layer 21 may be provided between the insulating layer 81 and the semiconductor layer 21, and the conductive layer may be used as one electrode of the capacitor 80. This can reduce the resistance of the electrode that constitutes the capacitor 80, enabling faster charge and discharge operations.

[0268] The transistor including a metal oxide according to one embodiment of the present invention can be combined with a transistor having a channel formed in silicon (hereinafter also referred to as a Si transistor) to realize various circuits. Hereinafter, a structure including a Si transistor and a transistor 10 will be described.

[0269] 15 and 16 show an example in which a transistor 90, which is a Si transistor, and a transistor 10 are stacked. Fig. 15 shows a cross section of the transistor 90 and the transistor 10 in the channel length direction, and Fig. 16 shows a cross section of the transistors 90 and 10 in the channel width direction.

[0270] 15 and 16, it can also be said that the functional layer 16 has the transistor 90 and the functional layer 15 has the transistor 10 on the functional layer 16.

[0271] The transistor 90 is provided on a substrate 91 and includes a conductive layer 94 functioning as a gate, an insulating layer 93 functioning as a gate insulating layer, a semiconductor region 92 formed of a part of the substrate 91, and low-resistance regions 95 a and 95 b functioning as source and drain regions. The transistor 90 may be either a P-type or an N-type.

[0272] 16, a transistor 90 has a semiconductor region 92 (part of a substrate 91) in which a channel is formed, which has a convex shape (fin shape). A conductive layer 94 is provided to cover the side and top surfaces of the semiconductor region 92 with an insulating layer 93 interposed therebetween. Such a transistor 90 is also called a FIN-type transistor because it utilizes the convex portions of the semiconductor substrate. An example having three convex portions is shown here.

[0273] 15, a pair of dummy gates 94d are provided so as to cover both ends of the convex portion of the substrate 91. Since the convex portion is thin and therefore susceptible to damage, defects, and the like during processing, the dummy gates 94d suppress deformation of the convex portion, crystal defects, and the like, thereby suppressing deterioration of the transistor characteristics and a drop in reliability.

[0274] It is preferable to provide a wiring layer 98 in which interlayer insulating layers and wiring layers are alternately stacked between the functional layer 16 in which the transistor 90 is provided and the functional layer 15 in which the transistor 10 is provided. Fig. 15 shows an example in which the low-resistance region 95b of the transistor 90 is connected to the conductive layer 24a of the transistor 10 via a wiring and a plug.

[0275] 15 uses the transistor illustrated in FIG. 3 as an example of the transistor 10. In addition, in FIG. 15, an insulating layer 32 is provided between the transistor 10 and an insulating layer 42. An insulating layer 45 is provided to cover the transistor 10, and an insulating layer 46 is provided on the insulating layer 45. The insulating layer 45 functions as a protective layer and has a function of preventing impurities such as hydrogen from diffusing from the outside. The insulating layer 46 functions as an interlayer insulating layer.

[0276] 17 shows an example in which a memory device is further stacked above the transistor 10. The memory device has a plurality of memory cells 40 arranged in a matrix.

[0277] 17, it can also be said that there are functional layers 16 having transistors 90, functional layers 15 having transistors 10 on functional layer 16, and functional layers 17 having memory cells 40 on functional layer 15.

[0278] The memory cell 40 has a stacked configuration of a capacitor 60 and a transistor 50. The memory cell 40 functions as a memory cell of a DRAM, for example.

[0279] The capacitor 60 includes a conductive layer 61, a conductive layer 63, and an insulating layer 62 sandwiched between the conductive layers 61 and 63 and functioning as a dielectric. The insulating layer 62 may be an insulating layer exhibiting ferroelectricity.

[0280] An insulating layer 71 and a conductive layer 64 embedded in the insulating layer 71 are provided on the insulating layer 46. The conductive layer 64 functions as wiring. An insulating layer 72 having an opening reaching the conductive layer 64 is provided on the conductive layer 64. Inside the opening of the insulating layer 72, the conductive layer 61, the insulating layer 62, and the conductive layer 63 are stacked. The conductive layer 61 is provided in contact with the conductive layer 64 inside the opening of the insulating layer 72, and the conductive layer 63 is provided to fill the opening. The conductive layer 61 and the insulating layer 62 have portions located on the insulating layer 72 and are provided in common to a plurality of capacitor elements 60. The conductive layer 63 has a portion embedded in the insulating layer 73 that covers the insulating layer 62.

[0281] In the transistor 50, the source electrode and the drain electrode are located at different heights, and a current flows in the height direction of the semiconductor layer. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, one embodiment of the present invention can be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0282] The transistor 50 includes a semiconductor layer 51, a conductive layer 54 functioning as one of a source electrode and a drain electrode, a conductive layer 55 functioning as the other electrode, an insulating layer 52 functioning as a gate insulating layer, and a conductive layer 53 functioning as a gate electrode.

[0283] The semiconductor layer 51 of the transistor 50 is preferably made of a metal oxide (oxide semiconductor) that exhibits semiconductor characteristics. For example, silicon, a typical semiconductor material, needs to be doped with impurities that function as donors or acceptors to form source and drain regions. However, in the vertical transistor of one embodiment of the present invention, it may be difficult to dope impurities into the semiconductor layer with high precision because the source and drain regions are different in height and the channel formation region is located vertically relative to the substrate surface. On the other hand, an oxide semiconductor can be well connected to the source and drain electrodes without doping with such impurities, and therefore a transistor having a three-dimensional structure as in one embodiment of the present invention can be manufactured with high yield.

[0284] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as an off-state current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0285] The conductive layer 54 is provided in contact with the upper surface of the conductive layer 53. An insulating layer 74 is provided on the conductive layer 54, and a conductive layer 55 is provided on the insulating layer 74. The conductive layer 55 and the insulating layer 74 have openings that reach the conductive layer 55. The semiconductor layer 51 has a portion in contact with the conductive layer 55, a portion in contact with a side surface of the insulating layer 74 within the opening of the insulating layer 74, and a portion in contact with the conductive layer 54. The insulating layer 52 is provided to cover the semiconductor layer 51, and the conductive layer 53 is provided to cover the insulating layer 52. The semiconductor layer 51 and the insulating layer 52 have portions located on the insulating layer 74 and are provided in common to multiple transistors 10. The conductive layer 53 has a portion embedded in the insulating layer 75 on the insulating layer 52. In addition, a conductive layer 56 in contact with the conductive layer 53 is provided on the insulating layer 75. The conductive layer 56 is connected to the conductive layers 53 of the multiple transistors 10 arranged in the depth direction.

[0286] An insulating layer 76 may be provided to cover the transistor 10, and an insulating layer 77 may be provided over the insulating layer 76. The insulating layer 76 functions as an interlayer insulating layer, and the insulating layer 77 functions as a protective layer. Note that the stacking order of the insulating layer 76 and the insulating layer 77 may be changed.

[0287] For example, a driver circuit, an arithmetic circuit, a control circuit, or the like can be configured using the transistors 10 and 90, and a memory device having memory cells 40 can be stacked above the driver circuit, and the memory device can be configured to operate at high speed because the wiring length can be significantly shortened.

[0288] The memory cells 40 may be stacked. For example, two, four, eight, or 16 or more layers may be stacked. The greater the number of stacked memory cells 40, the greater the storage capacity.

[0289] The above is a description of the application example.

[0290] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0291] Embodiment 2 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0292] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0293] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0294] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 18A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 18B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0295] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 18B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 18A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 18A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 18A.

[0296] 18A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0297] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0298] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0299] In addition, in indium oxide, the region where the carrier concentration is in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconducting properties. Note that, as a method for supplying an element that increases the carrier concentration, a method of forming a film containing the element and diffusing it, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. Note that, unless otherwise specified in this specification, the presence or absence of mass separation is not limited. For example, in this specification, a method of supplying ions after mass separation is referred to as an ion implantation method, and a method of supplying ions without mass separation is referred to as an ion doping method.

[0300] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 18A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0301] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0302] In addition, a semiconductor being i-type can be rephrased as having the same Fermi level (Ef) and intrinsic Fermi level (Ei) (Ef = Ei). As shown in FIG. 18B, in IGZO, the lower the carrier concentration, the smaller the hole mobility. Therefore, when Ef = Ei finally occurs, the carriers disappear (in other words, the physical properties become similar to those of an insulator), and there is a possibility that the transistor will no longer function. On the other hand, in indium oxide, as shown in FIG. 18A, the lower the carrier concentration, the higher the hole mobility. When Ef = Ei finally occurs, the hole mobility is maximized. In other words, a transistor containing indium oxide can achieve high field-effect mobility by setting Ef = Ei. Note that a transistor containing indium oxide is likely to be normally-off due to its low carrier concentration. Therefore, a transistor containing indium oxide can be normally-off and achieve high field-effect mobility.

[0303] Note that normally-off refers to a state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0 V. Furthermore, normally-off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth is calculated by a constant current method. More specifically, Vth refers to a state in which the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristics of a transistor is 1 nA (1 × 10 −９ A). Vsh is the gate voltage (Vg) when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically and the tangent of the maximum slope is Id = 1 pA (1 × 10 −１２ The gate voltage (Vg) is the intersection point between the line of Id = 1 pA and the line extrapolated from two points where the slope of Id is maximum when Id is expressed logarithmically in the Id-Vg characteristics of the transistor. For example, if either or both of Vth and Vsh are zero or a positive value, the transistor can be considered to be normally-off.

[0304] In addition, in a transistor containing indium oxide, in order to make the semiconductor i-type, that is, to achieve Ef = Ei, the film structure in contact with the indium oxide film is important. For example, in a transistor containing indium oxide, a film structure in which a silicon oxide film in contact with the indium oxide film, a hafnium oxide film, and a silicon nitride film are stacked is exemplified. By using this film structure, a semiconductor device with high reliability and Ef = Ei can be obtained.

[0305] In the above film configuration, a film containing oxygen, such as a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, or a gallium oxide film, can be used instead of the silicon oxide film. Also, in the above film configuration, a silicon nitride oxide film, a silicon oxynitride film, or the like can be used instead of the silicon nitride film. The hafnium oxide film, which is located closer to the indium oxide film than the silicon nitride film, functions as a gettering site for hydrogen.

[0306] The above film configuration can also be considered as a stacked structure of a film (e.g., a silicon oxide film) capable of supplying oxygen to the indium oxide film from the indium oxide film side, a film (e.g., a hafnium oxide film) capable of gettering hydrogen, and a film (e.g., a silicon nitride film) that suppresses the penetration of oxygen and hydrogen. With this configuration, oxygen vacancies in the indium oxide film are filled with oxygen in the silicon oxide film. Hydrogen in the indium oxide film is captured by the hafnium oxide film by heat treatment or the like. Furthermore, the provision of the silicon nitride film results in a film configuration that reduces the penetration of oxygen and hydrogen from the outside. That is, with the above film configuration, the indium oxide film can be made closer to i-type. Therefore, a transistor having the above-described indium oxide film has high field-effect mobility and high reliability.

[0307] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0308] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0309] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0310] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0311] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0312] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0313] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0314] In addition, the indium oxide film in this specification and the like has a high film density. ２ O ３ The film densities of the films are shown in Table 1.

[0315]

[0316] As shown in Table 1, the film density of the indium oxide film was evaluated at six levels, Sample 1 to Sample 6. In Table 1, Condition 1 is the condition of the underlayer film for the indium oxide film, Samples 1 to 3 are glass, Sample 4 is a SiOx film formed by sputtering, and Samples 5 and 6 are yttria-stabilized zirconia (YSZ). Condition 2 is the film formation condition for the indium oxide film, Samples 1 to 3 are film formation by sputtering (SP), and Samples 4 to 6 are film formation by ALD. Condition 3 is the heat treatment condition after the formation of the indium oxide film, with Sample 1, Sample 4, and Sample 5 being no heat treatment (as-deposited), Sample 2 being baked at 350°C in a CDA atmosphere, Sample 3 being baked at 650°C in a CDA atmosphere, and Sample 6 being baked at 250°C in a vacuum atmosphere.

[0317] In Table 1, CDA stands for clean dry air. It is preferable that the atmosphere used in the heat treatment (condition 3) after the formation of the indium oxide film contains as little hydrogen and water as possible. It is preferable to use a high-purity gas with a dew point of −60° C. or lower, preferably −100° C. or lower, as the atmosphere.

[0318] As shown in Table 1, the indium oxide film tends to have a higher film density when subjected to heat treatment compared to when not subjected to heat treatment (Sample 1, Sample 4, or Sample 5). This is because the heat treatment removes impurity elements (e.g., carbon, nitrogen, hydrogen, argon, etc.) from the film, thereby increasing the purity of the indium oxide film. Furthermore, as shown in Samples 5 and 6, the indium oxide film on YSZ has a film density of 7.00 g / cm. ３ The theoretical film density of an indium oxide film is 7.18 g / cm ３ In this specification, the range of the film density of the indium oxide film is 6.70 g / cm ３ 7.18g / cm or more ３ Preferably, it is 6.90 g / cm or less. ３ 7.18g / cm or more ３ More preferably, it is 7.00 g / cm or less. ３ 7.18g / cm or more ３ The following is the result.

[0319] The film density can be evaluated by, for example, Rutherford backscattering spectroscopy (RBS) or X-ray reflectometry (XRR). Differences in film density can sometimes be evaluated by cross-sectional transmission electron microscope (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, whereas a low film density results in a faint (bright) transmission electron (TE) image.

[0320] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0321] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 18C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0322] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0323] Furthermore, as shown in FIG. 18C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0324] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0325] Table 2 shows the results of single crystal indium oxide (here, In ２ O ３) and single-crystal silicon (Si). As shown in Table 2, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 2, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0326]

[0327] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0328] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0329] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0330] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0331] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７An example of a crystal having a crystalline structure is IGZO. It should be noted that a single crystal film of indium oxide can be formed not only on a YSZ substrate but also on an insulating film. On the other hand, it is difficult to form a single crystal film of silicon on an insulating film. Silicon crystals have a diamond structure. As such, indium oxide and silicon have similar properties in terms of single crystal. However, when comparing indium oxide and silicon in terms of whether they can be formed as single crystals on an insulating film, they have different properties.

[0332] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0333] Embodiment 3 In this embodiment, an example of a CMOS circuit configuration using a Si transistor and an OS transistor according to one embodiment of the present invention will be described.

[0334] Si transistors have higher field-effect mobility and faster operation speed than OS transistors. Furthermore, OS transistors have significantly lower off-state current than Si transistors. In particular, OS transistors using indium oxide (also referred to as indium oxide) for a semiconductor layer in which a channel is formed have significantly lower off-state current and higher field-effect mobility comparable to that of Si transistors. A CMOS circuit with low power consumption and high-speed operation can be realized by using an OS transistor and a Si transistor in combination.

[0335] In this embodiment, examples of circuits using Si transistors and OS transistors will be described, including a NOT circuit, a NOR circuit, and a NAND circuit, which are logic circuits. Also, examples of circuits using Si transistors and OS transistors will be described, including a buffer circuit, a ring oscillator, a delay flip-flop (DFF) circuit, a shift register circuit using a DFF circuit, a selector, and an analog switch.

[0336] [NOT Circuit] Fig. 19A is a circuit diagram showing an example of the configuration of a NOT circuit (NOT). A NOT circuit is also called an inversion circuit, an inverter circuit, etc. Fig. 19B shows the circuit symbol of a NOT circuit. Fig. 19C is a timing chart explaining the operation of the NOT circuit.

[0337] The NOT circuit shown in FIG. 19A includes a transistor Tr11 and a transistor Tr12. The transistor Tr11 is a Si transistor functioning as a p-type transistor, and the transistor Tr12 is an OS transistor functioning as an n-type transistor. A potential H (e.g., a potential VDD that is a high power supply potential) is supplied to one of the source and the drain of the transistor Tr11. The other of the source and the drain of the transistor Tr11 is connected to one of the source and the drain of the transistor Tr12 and to a terminal Y. A potential L (e.g., a potential VSS that is a low power supply potential) is supplied to the other of the source and the drain of the transistor Tr12. The gates of the transistors Tr11 and Tr12 are connected to a terminal A.

[0338] 19A, the terminal A functions as an input terminal, and the terminal Y functions as an output terminal. When a potential H is input to the terminal A of the NOT circuit, the terminal Y outputs a potential L, and when a potential L is input to the terminal A, the terminal Y outputs a potential H (see FIG. 19C).

[0339] As shown in FIG. 19C , the NOT circuit has a function of correcting an input signal distorted by wiring resistance, parasitic capacitance, noise, etc., to a signal that is distorted or has reduced distortion, and outputting the corrected signal (also referred to as a "waveform shaping function"). The NOT circuit also has a function of amplifying the voltage amplitude of the input signal and outputting the signal. The output of the NOT circuit is supplied to a load such as a capacitance element Cx and a transistor Trx. Since power is supplied to the output of the NOT circuit via transistor Tr11 or transistor Tr12, the ability to drive a load connected to the output can be improved. The NOT circuit has a function of improving the ability to drive a load (also referred to as a "driving force improvement function").

[0340] [NOR Circuit] Fig. 20A is a circuit diagram showing an example of the configuration of a two-input, one-output NOR circuit (NOR). Fig. 20B shows a circuit symbol for the NOR circuit. The NOR circuit shown in Fig. 20A includes transistors Tr21, Tr22, Tr23, and Tr24. Si transistors functioning as p-channel transistors are used as the transistors Tr21 and Tr22, and OS transistors functioning as n-channel transistors are used as the transistors Tr23 and Tr24.

[0341] 20A , a potential H is supplied to one of the source or drain of transistor Tr21. The other of the source or drain of transistor Tr21 is connected to one of the source or drain of transistor Tr22. The other of the source or drain of transistor Tr22 is connected to one of the source or drain of transistor Tr23, one of the source or drain of transistor Tr24, and terminal Y. A potential L is supplied to the other of the source or drain of transistor Tr23 and the other of the source or drain of transistor Tr24.

[0342] The gate of the transistor Tr21 is connected to the gate of the transistor Tr23 and the terminal A. The gate of the transistor Tr22 is connected to the gate of the transistor Tr24 and the terminal B.

[0343] 20A and 20B has a function of outputting a potential H from a terminal Y when a potential L is input to both a terminal A and a terminal B. In addition, the NOR circuit has a function of outputting a potential L from a terminal Y when a potential H is input to one or both of the terminals A and B.

[0344] Furthermore, as shown in FIG. 20C, an OR circuit can be realized by connecting the input of a NOT circuit to the output of a NOR circuit.

[0345] [NAND Circuit] Fig. 20D is a circuit diagram showing a configuration example of a two-input, one-output NAND circuit (NAND). Fig. 20E shows a circuit symbol of the NAND circuit. The NAND circuit shown in Fig. 20D includes transistors Tr31, Tr32, Tr33, and Tr34. Si transistors functioning as p-channel transistors are used as the transistors Tr31 and Tr32, and OS transistors functioning as n-channel transistors are used as the transistors Tr33 and Tr34.

[0346] 20D , a potential H is supplied to one of the source or drain of transistor Tr31 and one of the source or drain of transistor Tr32. The other of the source or drain of transistor Tr31 and the other of the source or drain of transistor Tr32 are connected to one of the source or drain of transistor Tr33 and terminal Y. The other of the source or drain of transistor Tr33 is connected to one of the source or drain of transistor Tr34. A potential L is supplied to the other of the source or drain of transistor Tr34.

[0347] The gate of the transistor Tr31 is connected to the gate of the transistor Tr34 and the terminal B. The gate of the transistor Tr32 is connected to the gate of the transistor Tr33 and the terminal A.

[0348] 20D and 20E has a function of outputting a potential L from a terminal Y when a potential H is input to both the terminal A and the terminal B. In addition, the NAND circuit has a function of outputting a potential H from a terminal Y when a potential L is input to one or both of the terminal A and the terminal B.

[0349] Furthermore, as shown in FIG. 20F, an AND circuit can be realized by combining a NAND circuit with a NOT circuit.

[0350] [Buffer Circuit] Figure 21A shows the circuit symbol for a buffer circuit. A buffer circuit (BF) can be realized by connecting an even number of NOT circuits in series. Figure 21B shows an example configuration of a buffer circuit made up of two NOT circuits. Figure 21C is a timing chart explaining the operation of the buffer circuit.

[0351] The buffer circuit does not perform a logical operation, but outputs the same value as the input logical value. Specifically, when a potential H is input, a potential H is output, and when a potential L is input, a potential L is output. In addition, like a NOT circuit, the buffer circuit has a waveform shaping function (see FIG. 21C ) and a driving force improving function. By using a buffer circuit, it is possible to correct a distorted signal and improve the driving force for a load without inverting the signal.

[0352] [Ring Oscillator] A ring oscillator (also called an "oscillating circuit") can be realized by connecting an odd number of NOT circuits in a ring. FIG. 21D shows an example of the configuration of a ring oscillator (RO) made up of NOT circuits. FIG. 21D shows a ring oscillator made up of five NOT circuits. A ring oscillator has the function of generating (oscillating) an AC signal when power is supplied. FIG. 21E is a diagram illustrating the oscillation of a ring oscillator.

[0353] Generally, the first of n NOT circuits (n is an odd number equal to or greater than 3) that make up a ring oscillator is sometimes called the "first stage." The nth circuit is sometimes called the "nth stage." A ring oscillator made up of NOT circuits has a configuration in which the output of each NOT circuit is connected to the input of the NOT circuit in the next stage. The output of the nth NOT circuit is connected to the input of the first NOT circuit.

[0354] Furthermore, in a NOT circuit, a certain delay time occurs before the inverted signal of the input signal is output. Since n is an odd number, the signal output from the first stage is delayed by n stages before being input to the first stage. This causes the ring oscillator to oscillate. That is, an AC signal is supplied to terminal Y shown in FIG. 21C. By using a ring oscillator, for example, a clock signal can be generated within the circuit. Furthermore, the delay time of the NOT circuit can be determined by measuring the oscillation frequency of the ring oscillator.

[0355] [DFF Circuit] Fig. 22A is a circuit diagram showing an example of the configuration of a D flip-flop circuit (DFF). Fig. 22B shows the circuit symbol of the D flip-flop circuit. The DFF has a clock signal input terminal CK, an input terminal D, and an output terminal Q.

[0356] 22A includes transistors Tr41 to Tr49, transistors Tr51 to Tr59, transistor Tr61, transistor Tr62, transistor Tr71, and transistor Tr72. Si transistors functioning as p-channel transistors are used as the transistors Tr41 to Tr49, transistors Tr61, and transistor Tr62, and OS transistors functioning as n-channel transistors are used as the transistors Tr51 to Tr59, transistors Tr71, and transistor Tr72.

[0357] A potential H is supplied to one of the source or drain of transistor Tr41, one of the source or drain of transistor Tr42, one of the source or drain of transistor Tr44, one of the source or drain of transistor Tr46, one of the source or drain of transistor Tr48, one of the source or drain of transistor Tr61, and one of the source or drain of transistor Tr62.

[0358] The other of the source or drain of transistor Tr41 is connected to one of the source or drain of transistor Tr51, the gate of transistor Tr44, the gate of transistor Tr46, the gate of transistor Tr53, and the gate of transistor Tr59. The gate of transistor Tr41 is connected to clock signal input terminal CK, the gate of transistor Tr51, the gate of transistor Tr42, the gate of transistor Tr48, the gate of transistor Tr55, and the gate of transistor Tr57.

[0359] The other of the source or drain of transistor Tr42 is connected to one of the source or drain of transistor Tr43. The other of the source or drain of transistor Tr44 is connected to one of the source or drain of transistor Tr45. The other of the source or drain of transistor Tr43 is connected to the other of the source or drain of transistor Tr45, one of the source or drain of transistor Tr52, one of the source or drain of transistor Tr54, the gate of transistor Tr61, and the gate of transistor Tr71. The gate of transistor Tr43 is connected to the gate of transistor Tr52 and input terminal D.

[0360] The other of the source or drain of transistor Tr52 is connected to one of the source or drain of transistor Tr53. The other of the source or drain of transistor Tr54 is connected to one of the source or drain of transistor Tr55. The gate of transistor Tr45 is connected to the gate of transistor Tr54, the other of the source or drain of transistor Tr61, one of the source or drain of transistor Tr71, the gate of transistor Tr47, and the gate of transistor Tr56. The other of the source or drain of transistor Tr46 is connected to one of the source or drain of transistor Tr47. The other of the source or drain of transistor Tr48 is connected to one of the source or drain of transistor Tr49.

[0361] The other of the source or drain of transistor Tr47 is connected to one of the source or drain of transistor Tr56, the other of the source or drain of transistor Tr49, one of the source or drain of transistor Tr58, the gate of transistor Tr62, and the gate of transistor Tr72. The other of the source or drain of transistor Tr62 is connected to one of the source or drain of transistor Tr72, the gate of transistor Tr49, the gate of transistor Tr58, and output terminal Q.

[0362] The other of the source or the drain of transistor Tr56 is connected to one of the source or the drain of transistor Tr57. The other of the source or the drain of transistor Tr58 is connected to one of the source or the drain of transistor Tr59. A potential L is supplied to the other of the source or the drain of transistor Tr51, the other of the source or the drain of transistor Tr53, the other of the source or the drain of transistor Tr55, the other of the source or the drain of transistor Tr71, the other of the source or the drain of transistor Tr57, the other of the source or the drain of transistor Tr59, and the other of the source or the drain of transistor Tr72.

[0363] 22A and 22B has a function in which information (potential) supplied to input terminal D is written to DFF at the timing when the signal input to clock signal input terminal CK changes from potential L to potential H, and the information is held until the next timing when the signal input to clock signal input terminal CK changes from potential L to potential H. In addition, a signal (potential H or potential L) based on the information held by DFF is always output from output terminal Q.

[0364] FIG. 23A is a block diagram showing an example configuration of a shift register circuit (SR). The SR includes multiple DFFs. In this specification and elsewhere, the first-stage (first) DFF is referred to as "DFF[1]," and the potential (data) output from the output terminal Q of DFF[1] is referred to as "DATA OUT[1]." FIG. 23A shows a block diagram of an SR including four stages (four) of DFFs (DFF[1] to DFF[4]). In FIG. 23A, the data output from the output terminals Q of DFF[1] to DFF[4] are referred to as DATA OUT[1] to DATA OUT[4].

[0365] 23B is a timing chart illustrating the operation of the SR. A clock signal CLK is input to the clock signal input terminal CK of the odd-numbered DFF. An inverted version of the signal CLK is input to the clock signal input terminal CK of the even-numbered DFF.

[0366] A pulse signal SPL is input to the input terminal D of DFF[1]. DFF[1] holds a signal corresponding to the input signal SPL in synchronization with the signal CLK and outputs it as data OUT[1]. Note that data OUT[1] has a value corresponding to the data held by DFF[1].

[0367] Furthermore, data OUT[1] is input to input terminal D of DFF[2]. DFF[2] holds a signal corresponding to the input data OUT[1] in synchronization with signal CLK and outputs it as data OUT[2]. Similarly, data OUT[2] is input to input terminal D of DFF[3], and data OUT[3] is input to input terminal D of DFF[4].

[0368] In this way, the SR has the function of sequentially transferring the input signal SPL to the subsequent DFF in synchronization with the signal CLK, and also has the function of sequentially switching the potential of the data OUT output from the multiple DFFs in synchronization with the signal CLK.

[0369] Furthermore, it is preferable to provide an overlapping structure between a Si transistor and an OS transistor. By providing an overlapping structure between a Si transistor and an OS transistor, a circuit with a small occupancy area can be realized. Furthermore, an OS transistor operates stably even in a high-temperature environment and exhibits little fluctuation in characteristics. Therefore, the OS transistor is less susceptible to the heat generated by the Si transistor and can operate stably. Furthermore, by providing an overlapping structure between a Si transistor and an OS transistor, the connection distance between them can be made extremely short. As a result, wiring resistance and parasitic capacitance are reduced, enabling the circuit to operate at high speed. Furthermore, the power consumption of the circuit is reduced.

[0370] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0371] [Selector] A selector (also referred to as a "selection circuit") can be realized by using a plurality of transistors. Figures 24A and 24B are circuit diagrams showing configuration examples of a selector (SEL).

[0372] 24A shows an example in which a selector is provided between a power supply PW and a circuit 1001, a circuit 1002, or a circuit 1003. The selector shown in Fig. 24A includes a transistor Tr81, a transistor Tr82, and a transistor Tr83. The transistor Tr81, the transistor Tr82, and the transistor Tr83 each function as a switch.

[0373] 24A , one of the source or drain of the transistor Tr81, one of the source or drain of the transistor Tr82, and one of the source or drain of the transistor Tr83 are connected to a power supply PW via a wiring PL. The other of the source or drain of the transistor Tr81 is connected to a circuit 1001. The other of the source or drain of the transistor Tr82 is connected to a circuit 1002. The other of the source or drain of the transistor Tr83 is connected to a circuit 1003.

[0374] That is, the circuit 1001 is connected to the power supply PW via a transistor Tr81, the circuit 1002 is connected to the power supply PW via a transistor Tr82, and the circuit 1003 is connected to the power supply PW via a transistor Tr83. The transistors Tr81 to Tr83 function as power transistors that control the power supply to the circuits 1001 to 1003. OS transistors are suitable as power transistors because they have a higher withstand voltage between the source and drain than Si transistors.

[0375] Furthermore, by providing a selector between the circuit 1001, the circuit 1002, and the circuit 1003 and the power supply PW, power gating can be performed to supply power to circuits that are operating and stop the power supply to circuits that are not operating.

[0376] FIG. 24B shows an example in which selectors are provided between the circuit 1001, the circuit 1002, and the circuit 1003 and the circuit 1100.

[0377] 24B , one of the source or drain of the transistor Tr81, one of the source or drain of the transistor Tr82, and one of the source or drain of the transistor Tr83 are connected to the circuit 1100 through a wiring SL. By using a selector, for example, the supply destination of the output signal of the circuit 1100 can be selected from the circuit 1001, the circuit 1002, and the circuit 1003. Alternatively, it can be selected which of the circuits 1001, 1002, and 1003 the output signal of which is to be supplied to the circuit 1100.

[0378] Furthermore, for example, when a clock signal is supplied from circuit 1100 to circuit 1001, circuit 1002, and circuit 1003, clock gating can be performed to supply a clock signal to a circuit that is operating and stop supplying the clock signal to a circuit that is not operating.

[0379] Furthermore, when transmitting and receiving signals of different polarities between multiple circuits, it is preferable to use analog switches (ASW) as switches provided between the multiple circuits. Fig. 24C is a circuit diagram showing an example of the configuration of an analog switch. The analog switch shown in Fig. 24C has a transistor Tr84 which is a p-type transistor and a transistor Tr85 which is an n-type transistor.

[0380] One of the source or drain of transistor Tr84 is connected to one of the source or drain of transistor Tr85, and functions as one of the input terminal or output terminal of the analog switch. The other of the source or drain of transistor Tr84 is connected to the other of the source or drain of transistor Tr85, and functions as the other of the input terminal or output terminal of the analog switch. The gate of transistor Tr84 is connected to terminal A, and the gate of transistor Tr85 is connected to terminal AB.

[0381] 24C shows an example in which one of the input terminal or output terminal of the analog switch is connected to the circuit 1100, and the other of the input terminal or output terminal of the analog switch is connected to the circuit 1001. Furthermore, potentials that are always inverted to each other are supplied to the terminal A and the terminal AB. For example, when the analog switch is turned on, a potential L is supplied to the terminal A, and a potential H is supplied to the terminal AB. Furthermore, when the analog switch is turned off, a potential H is supplied to the terminal A, and a potential L is supplied to the terminal AB.

[0382] By using analog switches as switches, signals with different polarities can be transmitted more reliably. Analog switches can be used in the selectors shown in Figures 24A and 24B.

[0383] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0384] Embodiment 4 In this embodiment, a structural example of a logic circuit including a semiconductor device which is one embodiment of the present invention will be described.

[0385] 25A is a circuit diagram illustrating an example of a logic circuit including a semiconductor device of one embodiment of the present invention, which illustrates logic circuits RC1 and RC2 and transistors SW1, SW2, and SW3.

[0386] The logic circuits RC1 and RC2 have Si transistors fabricated using a CMOS (Complementary MOS) process. The logic circuits RC1 and RC2 are basic logic gates such as NOT, NAND, NOR, AND, and OR. Alternatively, the logic circuits RC1 and RC2 may be circuits such as flip-flops, registers, and shift registers that are combinations of these logic gates. Alternatively, the logic circuits RC1 and RC2 may be large-scale arithmetic circuits that are combinations of multiple of the above circuits.

[0387] In the case of a NOT gate, for example, the logic circuit RC1 receives input data S ＩＮ The logic circuit RC1 outputs the inverted logic to the output terminal (OUT). There may be multiple input terminals and output terminals depending on the type of logic gate. In addition, in Figure 25A, the wiring connected to the output terminal of the logic circuit RC1 is referred to as node NodeA.

[0388] In the case of a NOT gate, for example, the logic circuit RC2 outputs an inverted logic signal of a signal held at a node NodeB input to an input terminal (IN) as an output signal S from an output terminal (OUT). ＯＵＴ In Fig. 25A, the wiring connected to the input terminal of the logic circuit RC2 is designated as a node NodeB.

[0389] The logic circuits RC1 and RC2 are each connected to a wiring line to which a potential VDD is supplied. The logic circuit RC1 is connected to a power supply line to which a potential VSS is supplied via a transistor SW1. The logic circuit RC2 is connected to a power supply line to which a potential VSS is supplied via a transistor SW2. The potentials VDD and VSS are power supply potentials for operating the logic circuits RC1 and RC2. The output terminal of the logic circuit RC1 is connected to the input terminal of the logic circuit RC2 via a transistor SW3.

[0390] The transistors SW1 to SW3 are the transistors described in the above embodiment, each of which includes indium in an oxide semiconductor layer that serves as a channel formation region. The transistors SW1 and SW2 function as switches for power gating. The transistor SW3 functions as a switch that controls the conduction state between the logic circuits RC1 and RC2. The transistors SW1 to SW3 are each connected to a control signal S ＰＧ１ ~S ＰＧ３ is controlled to be on or off.

[0391] As described above, the transistor, which is one embodiment of a semiconductor device, has extremely high field-effect mobility and extremely low off-state current. Therefore, when the transistors SW1 and SW2 are used as switches for power gating of the logic circuits, power gating can be performed for each logic circuit without impairing high-speed operation of the logic circuits. Furthermore, when the transistor SW3 is used as a switch for controlling conduction between the logic circuits, a potential corresponding to data input / output between the logic circuits can be held.

[0392] In the configuration of Figure 25A, partial power gating can be performed without stopping the output signal by performing power gating for each logic circuit and maintaining a potential according to the data input and output between the logic circuits.

[0393] Fig. 25B is a timing chart illustrating the power gating operation of the logic circuits RC1 and RC2 illustrated in Fig. 25A. Fig. 25B illustrates periods P01 to P06 illustrating the on / off timing of the transistors SW1 to SW3.

[0394] A period P01 is a period for explaining normal operation. In this operation, all of the transistors SW1 to SW3 are turned on. The input data S ＩＮ Output data S according to ＯＵＴ can be obtained.

[0395] Period P02 is a period for cutting off the current path between nodes NodeA and NodeB. During this period, transistor SW3 is switched off. By turning off transistor SW3, the current path between nodes NodeA and NodeB between logic circuits RC1 and RC2 can be cut off. As a result, a charge corresponding to the logic of the output terminal of logic circuit RC1 can be held at node NodeB between transistor SW3 and logic circuit RC2.

[0396] A period P03 is a period during which the logic circuit RC1 is power-gated. During this period, the transistor SW1 is switched off. By turning off the transistor SW1, it is possible to cut off the current path between the power supply lines that provide the power supply potential to the logic circuit RC1. As a result, the logic circuit RC1 is power-gated, and power consumption is reduced. In the logic circuit RC2, a charge corresponding to the signal logic is held at the node NodeB, and an output signal S corresponding to that logic is generated. ＯＵＴ can be output.

[0397] 26A is a circuit diagram showing a schematic representation of the period P03. In FIG. 26A, crosses are drawn over the transistors SW1 and SW3 that are turned off, and a potential V ＤＡＴＡ 26A, the power gating of the logic circuit RC1 is indicated by a broken line. As shown in FIG. 26A, the configuration of FIG. 25A enables fine-grained power gating at the logic circuit level. With this configuration, the output signal S ＯＵＴ It is possible to perform partial power gating of the logic circuit RC1 without stopping the power supply.

[0398] Although the configuration of Figure 25A is illustrated with one logic circuit RC1, multiple logic circuits RC1 may be used. Figure 26B is a schematic diagram of partial power gating when logic circuits RC1A and RC1B corresponding to the logic circuit RC1 of Figure 25A are included. Figure 26B illustrates a transistor SW1A that controls the power gating of logic circuit RC1A and a transistor SW3A between logic circuit RC2. Figure 26B also illustrates a transistor SW1B that controls the power gating of logic circuit RC1B and a transistor SW3B between logic circuit RC2.

[0399] 26B, crosses are drawn over the transistors SW1A and SW3A that are turned off, and the signal paths between the logic circuits RC1B and RC2 are shown with bold arrows. Also, in FIG. 26B, the power gating of the logic circuit RC1A is shown with dashed lines. As shown in FIG. 26B, it is also possible to use the transistors SW3A and SW3B as switching switches to selectively power gate the logic circuits RC1A and RC1B.

[0400] Period P04 is a period during which the logic circuit RC2 is power-gated. During this period, the transistor SW2 is switched off. By turning off the transistor SW2, the current path between the power supply lines that provide the power supply potential to the logic circuit RC2 can be cut off. As a result, both the logic circuits RC1 and RC2 are power-gated, reducing power consumption.

[0401] Period P05 is a period for opening the current path between nodes NodeA and NodeB. During this period, transistor SW3 is turned on. By turning on transistor SW3, the signal path between nodes NodeA and NodeB can be opened when logic circuits RC1 and RC2 are operating.

[0402] The period P06 is a period for explaining normal operation, similar to the period P01. In this operation, all of the transistors SW1 to SW3 are turned on. The input data S ＩＮOutput data S according to ＯＵＴ can be obtained.

[0403] As described above, power gating for each logic circuit can be performed by selectively turning off the transistors functioning as switches provided for each logic circuit. This allows for extremely small leakage current between power supply lines without impairing the high-speed operation of the logic circuits. Furthermore, by selectively turning off the transistors functioning as switches provided between logic circuits, the current path between the logic circuits can be blocked. As a result, charge can be retained according to the signal logic, signal paths can be switched, and the impact of operational delays caused by power gating can be reduced.

[0404] Embodiment 5 In this embodiment, a semiconductor device 900 according to one embodiment of the present invention will be described. The semiconductor device 900 can function as a memory device.

[0405] Fig. 27 is a block diagram showing a configuration example of a semiconductor device 900. The semiconductor device 900 shown in Fig. 27 has a driver circuit 910 and a memory array 920. The memory array 920 has one or more memory cells 950. Fig. 27 shows an example in which the memory array 920 has a plurality of memory cells 950 arranged in a matrix.

[0406] The transistor described as an example in Embodiment 1 can be applied to the memory cell 950. By using the transistor, the operation speed of the memory device can be improved. Furthermore, miniaturization and high integration of the memory device can be achieved. Furthermore, the capacitance per area of ​​the memory device can be increased.

[0407] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0408] In the semiconductor device 900, each circuit, signal, and potential can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0409] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is a write data signal, and signal RDA is a read data signal. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 912.

[0410] The control circuit 912 is a logic circuit having a function of controlling the overall operation of the semiconductor device 900. For example, the control circuit 912 performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates a control signal for the peripheral circuit 911 so that this operation mode is executed.

[0411] The voltage generating circuit 928 has a function of generating a voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 928. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generating circuit 928, and the voltage generating circuit 928 generates a voltage.

[0412] The peripheral circuit 911 is a circuit for writing and reading data to and from the memory cells 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925, an output circuit 926, and a sense amplifier 927.

[0413] The row decoder 941 and the column decoder 942 have the function of decoding the signal ADDR. The row decoder 941 is a circuit for specifying a row to be accessed, and the column decoder 942 is a circuit for specifying a column to be accessed. The row driver 923 has the function of selecting the row specified by the row decoder 941. The column driver 924 has the function of writing data to the memory cells 950, reading data from the memory cells 950, and retaining the read data.

[0414] The input circuit 925 has a function of holding a signal WDA. The data held by the input circuit 925 is output to the column driver 924. The output data of the input circuit 925 is data (Din) to be written to the memory cell 950. The data (Dout) read from the memory cell 950 by the column driver 924 is output to the output circuit 926. The output circuit 926 has a function of holding Dout. In addition, the output circuit 926 has a function of outputting Dout to the outside of the semiconductor device 900. The data output from the output circuit 926 is a signal RDA.

[0415] The PSW 931 is a V ＤＤ The PSW 932 has the function of controlling the supply of V to the row driver 923. ＨＭ Here, the high power supply potential of the semiconductor device 900 is V ＤＤ and the low power supply potential is GND (ground potential). ＨＭ is the high power supply potential used to drive the word line high, and V ＤＤ27, in the peripheral circuit 915, V ＤＤ Although the number of power domains to which power is supplied is set to one, it is also possible to set it to a plurality of power domains. In this case, a power switch may be provided for each power domain.

[0416] 28A to 28H, examples of other memory cell configurations that can be applied to the memory cell 950 will be described.

[0417] 28A shows an example of a circuit configuration of a DRAM memory cell. In this specification and the like, a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). A memory cell 951 includes a transistor M1 and a capacitor CA.

[0418] The transistor M1 may have a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring that supplies a constant potential or a signal, or the front gate and the back gate may be connected to each other.

[0419] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, and a gate of the transistor M1 is connected to the wiring WOL. The second terminal of the capacitance element CA is connected to the wiring CAL.

[0420] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0421] Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and connecting the wiring BIL and the first terminal of the capacitor CA.

[0422] Furthermore, the memory cell that can be used for the memory cell 950 is not limited to the memory cell 951, and the circuit configuration can be changed. For example, the memory cell 950 may have the configuration of a memory cell 952 as shown in FIG. 28B. The memory cell 952 is an example in which the memory cell 952 does not include a capacitor CA and a wiring CAL. The first terminal of the transistor M1 is in an electrically floating state.

[0423] In the memory cell 952, the potential written through the transistor M1 is held in a capacitance (also referred to as a parasitic capacitance) between the first terminal and the gate, which is indicated by a dashed line. With this configuration, the configuration of the memory cell can be significantly simplified.

[0424] Note that the OS transistor described in Embodiment 1 is preferably used as the transistor M1. For example, the transistor 10 described in Embodiment 1 can be used as the transistor M1 of the memory cell 951. By using the OS transistor described in Embodiment 1, the operation speed of the memory device can be improved. Furthermore, the area occupied by the memory cell can be reduced. Furthermore, the OS transistor has a characteristic of extremely low off-state current. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be significantly reduced. That is, written data can be held by the transistor M1 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, because the leakage current is extremely low, multilevel data or analog data can be held in the memory cells 951 and 952.

[0425] 28C shows an example circuit configuration of a gain cell type memory cell having two transistors and one capacitor. The memory cell 953 includes a transistor M2, a transistor M3, and a capacitor CB. In this specification and the like, a memory device having a gain cell type memory cell in which the transistor M2 is an OS transistor is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).

[0426] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL. The second terminal of capacitance element CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.

[0427] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data, while retaining data, and when reading data, it is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CAL.

[0428] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and connecting the wiring WBL to the first terminal of the capacitance element CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitance element CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitance element CB and the potential of the gate of the transistor M3.

[0429] Data is read by applying a predetermined potential to the wiring SL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read by reading the potential of the wiring RBL connected to the first terminal of the transistor M3. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0430] Alternatively, for example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example circuit configuration of such a memory cell is shown in FIG. 28D. The memory cell 954 is configured such that the wiring WBL and the wiring RBL of the memory cell 953 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 954 is configured to operate as a write bit line and a read bit line using a single wiring BIL.

[0431] 28E is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 953. Also, a memory cell 956 shown in Fig. 28F is an example in which the capacitor element CB and the wiring CAL are omitted from the memory cell 954. With such a configuration, the integration degree of the memory cells can be increased.

[0432] Note that at least the transistor M2 is preferably the OS transistor described in Embodiment 1. For example, the transistor 10 or the like exemplified in Embodiment 1 is preferably used for one or both of the transistors M2 and M3 in the memory cells 953 and 954. By using the OS transistor described in Embodiment 1, the operation speed of the memory device can be improved. In addition, the area occupied by the memory cell can be reduced.

[0433] Since the OS transistor has an extremely low off-state current, written data can be held by the transistor M2 for a long time, which reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. Furthermore, since the leakage current is extremely low, multilevel data or analog data can be held in the memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956.

[0434] The memory cell 953, the memory cell 954, the memory cell 955, and the memory cell 956, in which an OS transistor is used as the transistor M2, are one embodiment of an NOSRAM.

[0435] Note that a Si transistor may be used as the transistor M3. The Si transistor can increase the field effect mobility and can also be used as a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0436] When an OS transistor is used as the transistor M3, the memory cell can be configured using only n-channel transistors.

[0437] 28G shows a three-transistor, one-capacitor gain cell type memory cell 957. The memory cell 957 has transistors M4 to M6 and a capacitative element CC.

[0438] The first terminal of the transistor M4 is connected to the first terminal of the capacitor CC, the second terminal of the transistor M4 is connected to the wiring BIL, and the gate of the transistor M4 is connected to the wiring WOL. The second terminal of the capacitor CC is electrically connected to the first terminal of the transistor M5 and the wiring GNDL. The second terminal of the transistor M5 is connected to the first terminal of the transistor M6, and the gate of the transistor M5 is connected to the first terminal of the capacitor CC. The second terminal of the transistor M6 is connected to the wiring BIL, and the gate of the transistor M6 is connected to the wiring RWL.

[0439] The wiring BIL functions as a bit line, the wiring WOL functions as a write word line, and the wiring RWL functions as a read word line. The wiring GNDL is a wiring that applies a low-level potential.

[0440] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and connecting the wiring BIL to the first terminal of the capacitor CC. Specifically, when the transistor M4 is turned on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitor CC and the gate of the transistor M5. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby maintaining the potential of the first terminal of the capacitor CC and the potential of the gate of the transistor M5.

[0441] Data is read by precharging the wiring BIL to a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Because the wiring RWL is at a high-level potential, the transistor M6 is turned on, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5. The potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5). By reading the potential of the wiring BIL, the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CC (or the gate of the transistor M5).

[0442] Note that at least the transistor M4 is preferably the OS transistor described in Embodiment 1. By using the OS transistor described in Embodiment 1, the area occupied by the memory cell can be reduced.

[0443] Note that Si transistors may be used as the transistors M5 and M6. As described above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystalline state of silicon used in the semiconductor layer.

[0444] When OS transistors are used as the transistors M5 and M6, the memory cell can be configured using only N-channel transistors.

[0445] 28H shows an example of an SRAM (Static Random Access Memory) using an OS transistor. In this specification and the like, an SRAM using an OS transistor is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Note that a memory cell 958 shown in FIG. 28H is a memory cell of an SRAM capable of backing up data.

[0446] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, and capacitors CD1 and CD2. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

[0447] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to a first terminal of transistor MS1, a first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and a first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to a first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and a first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0448] A second terminal of the transistor MS1 is electrically connected to the wiring VDL. A second terminal of the transistor MS2 is electrically connected to the wiring VDL. A second terminal of the transistor MS3 is electrically connected to the wiring GNDL. A second terminal of the transistor MS4 is electrically connected to the wiring GNDL.

[0449] A second terminal of the transistor M9 is connected to a first terminal of the capacitor CD1, and a gate of the transistor M9 is connected to the wiring BRL. A second terminal of the transistor M10 is connected to a first terminal of the capacitor CD2, and a gate of the transistor M10 is connected to the wiring BRL.

[0450] A second terminal of the capacitance element CD1 is connected to the wiring GNDL, and a second terminal of the capacitance element CD2 is connected to the wiring GNDL.

[0451] The wirings BIL and BILB function as bit lines, the wiring WOL functions as a word line, and the wiring BRL is a wiring that controls the conductive state and non-conductive state of the transistors M9 and M10.

[0452] The wiring VDL is a wiring that applies a high-level potential, and the wiring GNDL is a wiring that applies a low-level potential.

[0453] Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is in a conductive state, a potential corresponding to information to be recorded is applied to the wiring BIL, and the potential is written to the second terminal of the transistor M10.

[0454] Since the memory cell 958 includes an inverter loop formed by the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Because the transistor M8 is conductive, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Furthermore, because the transistors M9 and M10 are conductive, the potentials of the second terminals of the transistors M7 and M8 are held in the first terminals of the capacitors CD2 and CD1, respectively. Subsequently, a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to turn off the transistors M7 to M10, thereby holding the potentials of the first terminals of the capacitors CD1 and CD2.

[0455] Data reading will now be described. First, the wirings BIL and BILB are precharged to a predetermined potential. Next, a high-level potential is applied to the wiring WOL, and a high-level potential is applied to the wiring BRL. At this time, the potential of the first terminal of the capacitor CD1 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BILB. The potential of the first terminal of the capacitor CD2 is refreshed by the inverter loop of the memory cell 958 and output to the wiring BIL. The potentials of the wirings BIL and BILB change from the precharged potentials to the potentials of the first terminals of the capacitor CD2 and the first terminals of the capacitor CD1, respectively, so that the potential held in the memory cell can be read from the potential of the wiring BIL or the wiring BILB.

[0456] Note that the OS transistors described in Embodiment 1 are preferably used as the transistors M7 to M10. This allows written data to be held by the transistors M7 to M10 for a long time, thereby reducing the frequency of refreshing the memory cells. Alternatively, the refresh operation of the memory cells can be eliminated. Furthermore, the operating speed of the memory device can be improved. Furthermore, the area occupied by the memory cells can be reduced.

[0457] Note that Si transistors may be used as the transistors MS1 to MS4.

[0458] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0459] Embodiment 6 In this embodiment, application examples of a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 29A to 30E.

[0460] The semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframes, space equipment, data centers (also referred to as DCs), and various electronic devices. By using the semiconductor device of one embodiment of the present invention, low power consumption and high performance can be achieved for the electronic components, mainframes, space equipment, data centers, and various electronic devices.

[0461] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproduction devices.

[0462] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0463] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, and a function to read out programs or data recorded on a recording medium.

[0464] [Electronic Component] FIG. 29A shows a perspective view of a substrate (mounting substrate 989) on which an electronic component 980 is mounted. The electronic component 980 shown in FIG. 29A has a semiconductor device 981 inside a mold 984. FIG. 29A omits some parts to show the interior of the electronic component 980. The electronic component 980 has lands 985 on the outside of the mold 984. The lands 985 are electrically connected to electrode pads 986, and the electrode pads 986 are electrically connected to the semiconductor device 981 via wires 987. The electronic component 980 is mounted on, for example, a printed circuit board 988. A plurality of such electronic components are combined and electrically connected on the printed circuit board 988 to complete the mounting substrate 989.

[0465] The semiconductor device 981 also includes a drive circuit layer 982 and a memory layer 983. The memory layer 983 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 982 and the memory layer 983 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 982 and the memory layer 983, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0466] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0467] Furthermore, it is preferable that the memory cell arrays included in the memory layer 983 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve one or both of the memory bandwidth and the memory access latency. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 983, it is more difficult to form a monolithic stacked configuration than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked configuration.

[0468] Alternatively, an OS transistor can be used for the driver circuit layer 982. The OS transistor described in the above embodiment can pass a large current, which enables the semiconductor device 994 to operate at high speed.

[0469] The semiconductor device 981 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0470] Although the above example shows the semiconductor device 981 functioning as a memory device, the present invention is not limited to this. For example, the semiconductor device 981 can also function as a processor such as a CPU, a GPU, or a field programmable gate array (FPGA). In this case, an OS transistor is preferably used for the semiconductor device 981. The OS transistor described in the above embodiment can pass a large current. This enables the semiconductor device 981 to operate at high speed.

[0471] 29B shows a perspective view of an electronic component 990. The electronic component 990 is an example of a SiP (System in Package) or an MCM (Multi-Chip Module). The electronic component 990 has an interposer 991 provided on a package substrate 992 (printed circuit board), and a semiconductor device 994 and a plurality of semiconductor devices 981 provided on the interposer 991.

[0472] The electronic component 990 shows an example in which the semiconductor device 981 is used as a high bandwidth memory (HBM). The semiconductor device 994 can be used in an integrated circuit such as a CPU, a GPU, or an FPGA.

[0473] In addition, an OS transistor is preferably used for the semiconductor device 994. The OS transistor described in the above embodiment can pass a large current, which enables the semiconductor device 994 to operate at high speed.

[0474] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 992. For example, a silicon interposer or a resin interposer can be used as the interposer 991.

[0475] The interposer 991 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 991 also functions to connect the integrated circuits provided on the interposer 991 to electrodes provided on the package substrate 992. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 991, and the integrated circuits and the package substrate 992 are connected using the through electrodes. In addition, in a silicon interposer, TSVs can also be used as through electrodes.

[0476] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0477] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0478] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 990, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array.

[0479] A heat sink (heat dissipation plate) may be provided over the electronic component 990. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 991. For example, in the electronic component 990 shown in this embodiment, it is preferable to align the height of the semiconductor device 981 and the height of the semiconductor device 994.

[0480] Electrodes 993 may be provided on the bottom of the package substrate 992 in order to mount the electronic component 990 on another substrate. FIG. 29B shows an example in which the electrodes 993 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 992, BGA (Ball Grid Array) mounting can be achieved. The electrodes 993 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 992, PGA (Pin Grid Array) mounting can be achieved.

[0481] The electronic component 990 can be mounted on other substrates using various mounting methods, not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0482] [Mainframe] Next, Fig. 30A shows a perspective view of a mainframe 5600. The mainframe 5600 shown in Fig. 30A has a rack 5610 housing a plurality of rack-mounted computers 5620. The mainframe 5600 may also be called a supercomputer.

[0483] The computer 5620 can have the configuration shown in the perspective view in Fig. 30B, for example. In Fig. 30B, the computer 5620 has a motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. A PC card 5621 is inserted into the slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0484] PC card 5621 shown in Figure 30C is an example of a processing board equipped with a CPU, a GPU, a storage device, etc. PC card 5621 has board 5622. Board 5622 also has connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that Figure 30C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 can be referred to.

[0485] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0486] The connection terminals 5623, 5624, and 5625 can be, for example, interfaces for supplying power to the PC card 5621, inputting signals, etc. Furthermore, they can be, for example, interfaces for outputting signals calculated by the PC card 5621. Examples of standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when a video signal is output from the connection terminals 5623, 5624, and 5625, examples of the respective standards include HDMI (registered trademark).

[0487] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 can be connected to the board 5622 by inserting the terminal into a socket (not shown) provided on the board 5622.

[0488] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 990 can be used as the semiconductor device 5627.

[0489] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 990 can be used as the semiconductor device 5628.

[0490] The mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0491] [Space Equipment] The semiconductor device of one embodiment of the present invention can be suitably used in space equipment.

[0492] A semiconductor device according to one embodiment of the present invention includes an OS transistor. Compared to a Si transistor, an OS transistor exhibits smaller variations in electrical characteristics due to radiation exposure. That is, the OS transistor has high radiation resistance and is therefore highly reliable and suitable for use in environments where radiation may be incident. For example, an OS transistor can be suitably used in outer space. Specifically, an OS transistor can be used as a transistor for a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutrons. Note that outer space refers to an altitude of 100 km or higher, and the outer space described in this specification can include one or more of the thermosphere, the mesosphere, and the stratosphere.

[0493] Fig. 30D shows an artificial satellite 6800 as an example of space equipment. The artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Note that Fig. 30D also shows a planet 6804 in space.

[0494] 30D , a battery management system (also referred to as a BMS) or a battery control circuit may be provided for the secondary battery 6805. The use of an OS transistor in the battery management system or the battery control circuit is preferable because it consumes low power and has high reliability even in space.

[0495] Furthermore, outer space is an environment with radiation levels 100 times higher than on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0496] When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where sunlight is not irradiated onto the solar panel or where the amount of sunlight irradiating the solar panel is small, the generated power is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is preferable to provide a secondary battery 6805 on the satellite 6800. Note that the solar panel may be called a solar cell module.

[0497] The satellite 6800 can generate a signal. The signal is transmitted via an antenna 6803, and can be received by, for example, a receiver installed on the ground or another satellite. By receiving the signal transmitted by the satellite 6800, the position of the receiver that received the signal can be determined. As described above, the satellite 6800 can constitute a satellite positioning system.

[0498] The control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device. Note that the control device 6807 is preferably a semiconductor device including an OS transistor which is one embodiment of the present invention.

[0499] The artificial satellite 6800 can also be configured to include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 can have the function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. As described above, the artificial satellite 6800 can function as, for example, an earth observation satellite.

[0500] Although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.

[0501] As described above, OS transistors have excellent advantages over Si transistors, such as the ability to achieve a wide memory bandwidth and high radiation resistance.

[0502] [Data Center] The semiconductor device of one embodiment of the present invention can be suitably used in a storage system applied to, for example, a data center. The data center is required to perform long-term management of data, such as ensuring data immutability. To manage long-term data, the building must be large enough to accommodate the installation of storage and servers for storing a huge amount of data, a stable power source for storing the data, or cooling equipment required for storing the data.

[0503] By using the semiconductor device of one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and the size of the semiconductor device that stores data. Therefore, it is possible to reduce the size of the storage system, the size of the power supply for storing data, the scale of the cooling equipment, and the like. Therefore, it is possible to reduce the space required for the data center.

[0504] Furthermore, the semiconductor device of one embodiment of the present invention has low power consumption, which allows heat generation from the circuit to be reduced. Therefore, adverse effects of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0505] Fig. 30E shows a storage system applicable to a data center. The storage system 7010 shown in Fig. 30E has multiple servers 7001sb as hosts 7001 (illustrated as Host Computers). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).

[0506] The host 7001 corresponds to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0507] Although the storage 7003 uses flash memory to reduce the data access speed, i.e., the time required to store and output data, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In order to solve the problem of the long access speed of the storage 7003, a storage system typically provides cache memory within the storage to reduce the time required to store and output data.

[0508] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.

[0509] By using OS transistors as transistors for storing data in the cache memory and holding a potential corresponding to the data, the frequency of refresh operations can be reduced, and power consumption can be reduced.

[0510] Note that the semiconductor device of one embodiment of the present invention can reduce power consumption by applying it to any one or more of electronic components, mainframe computers, space equipment, data centers, and electronic devices. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can reduce carbon dioxide (CO ２ Furthermore, the semiconductor device of one embodiment of the present invention is effective as a countermeasure against global warming because it consumes low power.

[0511] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0512] In this example, a crystalline indium oxide film was formed and the results of observing its cross section will be described.

[0513] First, the sample will be described. A single-crystal YSZ substrate was used as the substrate on which the indium oxide film was formed. The single-crystal YSZ substrate used had a (111) crystal plane on its surface. Next, a silicon oxynitride film with a thickness of approximately 1000 nm was formed on the YSZ substrate by plasma CVD. A portion of the silicon oxynitride film was then removed by etching to expose a portion of the surface of the YSZ substrate. Specifically, by immersing a portion of the substrate in an etching solution, the silicon oxynitride film was etched only in the portion that came into contact with the etching solution. At this time, the surface on which the silicon oxynitride film was formed was facing downward, and the substrate was tilted and immersed in the etching solution to form a tapered edge of the silicon oxynitride film.

[0514] Subsequently, an indium oxide film having a thickness of about 10 nm was formed by ALD using triethylindium as a precursor and ozone as an oxidizing agent at a substrate temperature of 200°C.

[0515] The prepared samples were subjected to cross-sectional observation using a transmission electron microscope.

[0516] 31A shows a cross-sectional image of the vicinity of the edge of the silicon oxynitride film. A silicon oxynitride film (SiON) having a thickness of about 2 nm is provided on a YSZ substrate. A polycrystalline indium oxide film (In ２ O ３ 31A ) is provided. On the right side of the cross-sectional image shown in FIG. 31A , there is a region where a part of the silicon oxynitride film has disappeared, and in this region, the YSZ substrate and the indium oxide film are in contact. Furthermore, even in the portion where the silicon oxynitride film appears extremely thin, it is presumed that there is a portion in the vicinity in the depth direction where a part of the silicon oxynitride film has disappeared and the YSZ substrate and the indium oxide film are in contact.

[0517] Figure 31B shows an enlarged view of the area enclosed by the white frame in Figure 31A. Observation of the crystal grains of the indium oxide film on the silicon oxynitride film revealed that, first, the

[111] crystal orientation was oriented approximately perpendicular to the surface where the film was formed, similar to YSZ, in the area in contact with the YSZ substrate. Furthermore, over a range of approximately 60 nm from the area on the silicon oxynitride film, the

[111] crystal orientation was oriented approximately perpendicular to the surface where the film was formed, revealing a region that could be considered a single crystal grain. From these results, it was confirmed that, even on an amorphous film, crystal growth occurred in the lateral direction (perpendicular to the film thickness direction) over a range of approximately 60 nm from the area in contact with the crystal nucleus layer, and that this region could be considered a single crystal.

[0518] The above results suggest that when an indium oxide film is formed in contact with a layer that serves as a crystal nucleus, it is possible to form an indium oxide film having a single crystal region over a range of approximately 60 nm, centered on the portion that serves as the crystal nucleus.

[0519] In this example, the mechanism of crystal growth of indium oxide will be described using interfacial energy.

[0520] The interfacial energy refers to the energy loss due to the formation of an interface between a crystalline structure and an amorphous structure, and can be calculated using the following formula:

[0521]

[0522] Here, Eｉｎｔｅｒｆａｃｅ is the interfacial energy, and E ａｍｏ is the total energy of the amorphous structure model, and E ｃｒｙ is the total energy of the single crystal structure model, and E ａ／ｃ is the total energy of the model in which the amorphous structure and the single crystal structure are bonded. S is the bond cross-sectional area, which is the contact area between the amorphous structure and the single crystal structure in the model in which the amorphous structure and the single crystal structure are bonded.

[0523] The smaller the interfacial energy, the smaller the energy loss due to crystallization. Therefore, crystals grow to maximize the surface area of ​​the crystal plane with low interfacial energy. In other words, the rate of crystal growth is fast in the direction along the crystal plane with low interfacial energy, and slow in the direction perpendicular to the crystal plane with low interfacial energy.

[0524] First, a model including a single crystal structure is prepared as a model in which an amorphous structure and a single crystal structure are bonded. Next, half of the model is melted at 3000 K and rapidly cooled to 300 K. In this calculation, a molecular dynamics calculation is performed using the NVT ensemble. Next, the structure of the rapidly cooled model is optimized using first-principles calculations. From the above steps, a model in which an amorphous structure and a single crystal structure are bonded can be created.

[0525] The total energy of each of the amorphous structure model, single crystal structure model, and model in which an amorphous structure and a single crystal structure are joined can be calculated using first-principles calculations.

[0526] The molecular dynamics calculation was performed using LAMMPS, which is an open source software. In this example, M3GNet (see Non-Patent Document 2) was used as the molecular force field.

[0527] The free software Quantum Espresso was used for the above first-principles calculations. In this example, GGA / PBE (Generalized-Gradient-Approximation / Perdew-Burke-Ernzerhof) was used as the exchange-correlation functional, and an ultrasoft pseudopotential was used. The cutoff energy of the wave function was set to 100 Ry, and the cutoff energy of the electron density was set to 900 Ry. Spin polarization was not used.

[0528] Table 3 shows the interfacial energies of the (110), (001), and (111) planes of an indium oxide crystal.

[0529]

[0530] From Table 3, it can be seen that indium oxide has a tendency for the interfacial energy of the (111) plane to be small, the interfacial energy of the (001) plane to be next small, and the interfacial energy of the (110) plane to be large. From this, it is presumed that, since the interfacial energy of the (111) plane is small in indium oxide, crystal growth occurs while maximizing the surface area of ​​the (111) plane.

[0531] The above results suggest that, taking into account the interfacial energy, indium oxide preferentially orients in the (111) plane. This agrees well with the results shown in Example 1 and FIG. 25. That is, it was confirmed that when an indium oxide film formed on an amorphous film undergoes lateral crystal growth, the crystal orientation

[111] grows so as to be oriented approximately perpendicular to the surface on which it is formed, minimizing the increase in interfacial energy.

[0532] In this example, a comparison of the field-effect mobility between a fin-type transistor using indium oxide as a semiconductor (IO FinFET) and a fin-type transistor using silicon as a semiconductor (Si FinFET) is performed by device simulation. The results are described below.

[0533] Figure 32 shows the structure and various parameters assumed in the device simulation. In this example, two types of IO FinFETs and one type of Si FinFET were assumed. As shown in Figure 32, the device structure is as follows: gate length (Lg) is 15 nm, Fin width is 5 nm, Fin height is 55 nm, and the gate insulating film (GI) structure is SiO ２ and 1.5 nm thick HfO ２ The thickness of the GI was 1.0 nm in terms of equivalent oxide thickness (EOT). It was assumed that there was no external resistance connected to the transistor.

[0534] For comparison, the channel length, channel width, channel thickness (Fin height), material and thickness of the gate insulating layer (GI), and drain voltage were set to be the same for the three types of FETs. No external resistance was set.

[0535] The electron mobility (material inherent mobility) of the IO FinFET (A) is 80 cm ２ / Vs, and the IO FinFET (B) is 20 cm ２ In both cases, a model in which the electron mobility does not depend on the electric field in the device (a model in which the electron mobility is constant) was adopted.

[0536] The electron mobility of the Si FinFET is 1413 cm ２ / Vs. A model was adopted in which the electron mobility changes depending on the electric field, due to factors such as interface scattering and saturation of the drift velocity. Therefore, the electron mobility decreases significantly depending on the applied voltage in the device.

[0537] 33A to 33C show the Id-Vg characteristics and field-effect mobility (μ ＦＥ (Sat): saturated mobility). ＦＥThe channel width W when calculating (Sat) was set to "fin height × 2 + fin width" (the distance the gate surrounds the fin). The Id-Vg characteristics and field-effect mobility in FIGS. 33A to 33C were measured at a drain voltage (Vd) of 0.7 V. FIG. 33A shows the results for the IO FinFET(A), FIG. 33B shows the results for the IO FinFET(B), and FIG. 33C shows the results for the Si FinFET. From these results, as shown in FIG. 32, the μ of the IO FinFET(A) was ＦＥ (Sat) is 19.8 cm ２ / Vs, μ of IO FinFET (B) ＦＥ (Sat) is 4.9 cm ２ / Vs, μ of Si FinFET ＦＥ (Sat) is 17.7 cm ２ / Vs was obtained.

[0538] 34A to 34C show the cutoff frequencies (fT) of the three transistors. As shown in FIG. 34A, the fT of the IO FinFET (A) was 581 GHz. As shown in FIG. 34B, the fT of the IO FinFET (B) was 141 GHz. As shown in FIG. 34C, the fT of the Si FinFET was 404 GHz. Thus, an IO FinFET with a gate length (Lg) of 15 nm is expected to have a cutoff frequency (fT) of 300 GHz or higher, preferably 400 GHz or higher, and more preferably 500 GHz or higher.

[0539] FIG. 35 shows the μ ＦＥ (Sat) is plotted on a graph showing the relationship between channel length and mobility.

[0540] In FIG. 35, the open triangles indicate the results for the IO FinFET (A), the black triangles indicate the results for the IO FinFET (B), and the black circles indicate the results for the Si FinFET.

[0541] Furthermore, in FIG. 35, the white circles represent the simulation data of the Si FET (μ ｄｒｉｆｔ ), and the white squares represent the theoretical values ​​of the CAAC-IGZO FET (μ ｄｒｉｆｔ), the black squares represent the measured values ​​(μ ＦＥ ) where μ ｄｒｉｆｔ is the drift mobility derived from the calculation of the electron velocity.

[0542] From FIG. 35, the μ ＦＥ It can be seen that (Sat) does not deviate significantly from the straight line of the simulation data of the Si FET. ＦＥ It can be seen that (Sat) is close to the straight line of the simulation data of the Si FET. ＦＥ It can be seen that (Sat) is close to the straight line of the simulation data for the IGZO FET. As described above, by shortening the channel length, specifically, by making the channel length less than 11 nm, preferably 1 nm or more and 8 nm or less, the IO FinFET is expected to have a field-effect mobility equivalent to or higher than that of a Si FET.

[0543] In this example, the results of evaluating the electrical characteristics of a fin-type transistor (IO FinFET) using indium oxide as a semiconductor by device simulation will be described.

[0544] The structure and parameters assumed in the device simulation are shown in Fig. 36. As shown in Fig. 36, the device structure is such that the gate length (Lg) is 3 nm to 10 nm, the Fin width is 5 nm, the Fin height is 55 nm, and the gate insulating film (GI) structure is SiO ２ and 1.5 nm thick HfO ２ The film thickness of the GI was 0.5 nm in terms of equivalent oxide thickness (EOT). There was no external resistor connected to the transistor, and the field effect mobility (μe) was 100 cm ２ / Vs was assumed as a constant model. Figure 37 shows the ID-VG curve of the IO FinFET of this example. Even when the gate length Lg was 3 nm, a good on / off ratio (subthreshold value (S value) was approximately 80 mV / dec) was obtained. On the other hand, the on-current tended to saturate.

[0545] In this example, a vertical OS transistor whose channel length direction includes a component in the height direction (vertical direction) was fabricated, and the results of evaluating its electrical characteristics will be described.

[0546] A cross-sectional view of an OS transistor manufactured in this example is shown in FIG. 38 . The OS transistor shown in FIG. 38 includes conductive layers 220_1 and 220_2, conductive layers 240_1 and 240_2, a semiconductor layer 230, an insulating layer 250, and a conductive layer 260 (conductive layers 260_1 and 260_2). The semiconductor layer 230 has a two-layer structure. The insulating layer 280 has a three-layer structure. The length L280 in FIG. 38 is 95 nm, and the width of the opening 290 is 60 nm.

[0547] The semiconductor layer 230 was formed by depositing a 10-nm-thick indium oxide film by ALD and then depositing a 5-nm-thick IGZO film by sputtering. The indium oxide film was deposited using triethylindium as a precursor and ozone as an oxidant, with the oxidant introduction time set to 9 seconds per cycle and the substrate temperature set to 200°C. The IGZO film was deposited using an oxide target with an atomic ratio of In:Ga:Zn = 1:1:1.2.

[0548] The off-state current of the fabricated transistor was evaluated. Because the off-state current of an OS transistor is extremely small, in this example, 20,000 transistors connected in parallel (hereinafter referred to as DUT (Device Under Test)) were prepared.

[0549] Here, we will explain a method for quantitatively evaluating the extremely small off-state current of a transistor. First, −2.0 V was applied to the gate terminal of a transistor serving as a DUT, 0 V was applied to the source terminal, and 0.8 V was applied to the drain terminal. Next, the drain terminal was floated, and the change in potential of the drain terminal over time was observed via a source follower circuit. The off-state current Ioff of the transistor serving as a DUT was calculated using the pre-measured parasitic capacitance Cfn of the drain terminal and the potential change ΔVfn over measurement time T by the formula: off-state current Ioff = parasitic capacitance Cfn × potential change ΔVfn / measurement time T.

[0550] As a comparative example, a reference sample was prepared, which included a silicon transistor (Si-FET) with a channel width (W) / length (L) of 120 nm / 60 nm as a DUT. To evaluate the off-state current of the transistor included in the reference sample, 0 V was applied to the gate and source terminals of the transistor as the DUT, and 1.2 V was applied to the drain terminal.

[0551] 39 shows an Arrhenius plot of the calculated off-state current. In FIG. 39 , the horizontal axis represents the reciprocal of temperature T (1000 / T) [1 / K], and the vertical axis represents off-state current Ioff [A / μm] per μm of channel width. The circles represent the calculated off-state current of the OS transistor, the squares represent the calculated off-state current of the comparative example, and the solid line represents a regression line obtained from the calculated values.

[0552] 39, the off-state current per μm of the channel width of the OS transistor of this example was 68.4 zA / μm (6.84×10) at 85° C. −２０ A / μm), and in an environment of 27°C (extrapolated), it is 0.28 aA / μm (0.28×10 −１８The results showed that the off-current per 1 μm of channel width was 1 aA (1×10) in an environment of 85° C. This was nine orders of magnitude smaller than the off-current of a silicon transistor, which was 0.23 nA / μm, at 27° C. This confirmed that the off-current of an OS transistor was small and had little temperature dependence. As described above, by using an indium oxide film as an OS transistor, the off-current per 1 μm of channel width was 1 aA (1×10) in an environment of 85° C. −１８ A) or less, preferably 1zA (1 x 10 −２１ A) It is expected that the following will be achieved.

[0553] 10: transistor, 10FE: transistor, 11: insulating layer, 15: functional layer, 16: functional layer, 17: functional layer, 20: slit, 21: semiconductor layer, 21C: region, 21f: semiconductor film, 21L: region, 21N: region, 21S: layer, 22: insulating layer, 22FE: insulating layer, 23: conductive layer, 24: conductive layer, 24a: conductive layer, 24b: conductive layer, 25: conductive layer, 25a: conductive layer, 25b: conductive layer, 26a: conductive layer, 26b: conductive layer, 27a: conductive layer, 27b: conductive layer, 28a: conductive layer, 28b: conductive layer, 31: sacrificial layer, 32: insulating layer, 35: resist mask, 40: Memory cell, 41: insulating layer, 41A: insulating film, 42: insulating layer, 43: insulating layer, 44: insulating layer, 45: insulating layer, 46: insulating layer, 50: transistor, 51: semiconductor layer, 52: insulating layer, 53: conductive layer, 54: conductive layer, 55: conductive layer, 56: conductive layer, 60: capacitance element, 61: conductive layer, 62: insulating layer, 63: conductive layer, 64: conductive layer, 71: insulating layer, 72: insulating layer, 73: insulating layer, 74: insulating layer, 75: insulating layer, 76: insulating layer, 77: insulating layer, 80: capacitance element, 81: insulating layer, 82: conductive layer, 90: transistor, 91: substrate, 92: semiconductor region, 93: insulating layer, 94: Conductive layer, 95a: Low resistance region, 95b: Low resistance region, 98: Wiring layer, 220_1: Conductive layer, 220_2: Conductive layer, 230: Semiconductor layer, 240_1: Conductive layer, 240_2: Conductive layer, 250: Insulating layer, 260: Conductive layer, 260_1: Conductive layer, 260_2: Conductive layer, 280: Insulating layer, 290: Opening, 900: Semiconductor device, 910: Driver circuit, 911: Peripheral circuit, 912: Control circuit, 915: Peripheral circuit, 920: Memory array, 923: Row driver, 924: Column driver, 925: Input circuit, 926: Output circuit, 927: Sense amplifier, 92 8: voltage generating circuit, 931: PSW, 932: PSW, 941: row decoder, 942: column decoder, 950: memory cell, 951: memory cell, 952: memory cell, 953: memory cell, 954: memory cell, 955: memory cell, 956: memory cell, 957: memory cell, 958: memory cell, 980: electronic component, 981: semiconductor device, 982: drive circuit layer, 983: memory layer, 984: mold, 985: land, 986: electrode pad, 987: wire, 988: printed circuit board, 989: mounting board, 990: electronic component, 991: interposer,992: package substrate, 993: electrode, 994: semiconductor device, 1001: circuit, 1002: circuit, 1003: circuit, 1100: circuit, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: PC card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 6800: artificial satellite, 6801: aircraft, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device, 7010: storage system,

Claims

a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a first insulating layer, and a second insulating layer; the first conductive layer and the second conductive layer each have a columnar shape and are provided apart from each other; the first insulating layer has an elongated shape in a plan view, and one of a pair of ends in a long side direction is in contact with the first conductive layer, and the other is in contact with the second conductive layer, the semiconductor layer surrounds the first insulating layer, the first conductive layer, and the second conductive layer in a plan view, and is in contact with a pair of side surfaces of the first insulating layer parallel to a long side direction, a side surface of the first conductive layer, and a side surface of the second conductive layer; the second insulating layer is provided between the first conductive layer and the second conductive layer to cover the semiconductor layer; the third conductive layer is provided over the second insulating layer; Semiconductor device. 　 A first functional layer and a second functional layer below the first functional layer, the first functional layer includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a first insulating layer, and a second insulating layer; the first conductive layer and the second conductive layer each have a columnar shape and are provided apart from each other; the first insulating layer has an elongated shape in a plan view, and one of a pair of ends in a long side direction is in contact with the first conductive layer, and the other is in contact with the second conductive layer, the semiconductor layer surrounds the first insulating layer, the first conductive layer, and the second conductive layer in a plan view, and is in contact with a pair of side surfaces of the first insulating layer parallel to a long side direction, a side surface of the first conductive layer, and a side surface of the second conductive layer; the second insulating layer is provided between the first conductive layer and the second conductive layer to cover the semiconductor layer; the third conductive layer is provided over the second insulating layer; the second functional layer has a first transistor having a channel formed in a part of a semiconductor substrate; the first transistor has a semiconductor region, a first low resistance region, a second low resistance region, a gate insulating layer, and a gate electrode; the semiconductor region, the first low resistance region, and the second low resistance region are each part of the semiconductor substrate; the semiconductor substrate comprises silicon; Semiconductor device. 　 In claim 2, a wiring layer between the first functional layer and the second functional layer; Semiconductor device. 　 In claim 2, The semiconductor region has a fin-like shape. Semiconductor device. 　 In claim 2, a third functional layer having a plurality of memory cells above the first functional layer; the memory cell includes a second transistor and a capacitance element; the second transistor is a vertical transistor. Semiconductor device. 　 a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a semiconductor layer, a first insulating layer, a second insulating layer, and a dielectric layer; the first conductive layer and the second conductive layer each have a columnar shape and are provided apart from each other; the first insulating layer has an elongated shape in a plan view, and one of a pair of ends in a long side direction is in contact with the first conductive layer, and the other is in contact with the second conductive layer, the semiconductor layer surrounds the first insulating layer, the first conductive layer, and the second conductive layer in a plan view, and is in contact with a pair of side surfaces of the first insulating layer parallel to a long side direction, a side surface of the first conductive layer, and a side surface of the second conductive layer; the second insulating layer is provided to cover the semiconductor layer in a first region between the first conductive layer and the second conductive layer; the third conductive layer is provided over the second insulating layer; the dielectric layer is disposed over the semiconductor layer in a second region between the first conductive layer and the second conductive layer; the fourth conductive layer is provided over the dielectric layer; Semiconductor device. 　 In claim 6, the dielectric layer comprises aluminum oxide; Semiconductor device. 　 In claim 6, the dielectric layer includes an insulating material exhibiting ferroelectricity; Semiconductor device. 　 In claim 6, the dielectric layer comprises hafnium oxide, zirconium oxide, or hafnium zirconium oxide; Semiconductor device. 　 In any one of claims 1 to 9, The height of the first insulating layer is 1 to 50 times the width in the short side direction in a plan view. Semiconductor device. 　 In any one of claims 1 to 9, a third insulating layer; the third insulating layer covers the first conductive layer, the second conductive layer, the semiconductor layer, and the first insulating layer, and has a groove portion that reaches the semiconductor layer and the first insulating layer; the second insulating layer is provided inside the groove to cover the semiconductor layer, the third conductive layer is provided so as to fill the groove portion; Semiconductor device. 　 In any one of claims 1 to 9, a third insulating layer; the third insulating layer covers the first conductive layer, the second conductive layer, the semiconductor layer, and the first insulating layer; the third insulating layer is in contact with an upper surface of the first insulating layer, an upper surface of the first conductive layer, and an upper surface of the second conductive layer; Semiconductor device. 　 In any one of claims 1 to 9, the semiconductor layer contains indium oxide; Semiconductor device. 　 In any one of claims 1 to 9, The semiconductor layer has a single crystal structure or a polycrystalline structure. Semiconductor device. 　 In any one of claims 1 to 9, the first conductive layer and the second conductive layer each have a first layer and a second layer; the first layer and the second layer are provided concentrically in this order, the second layer is in contact with the semiconductor layer; Semiconductor device. 　 In claim 15, the semiconductor layer includes indium oxide; the second layer includes an oxide containing indium; Semiconductor device. 　 A transistor having a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, a first insulating layer, and a second insulating layer, the first conductive layer and the second conductive layer each have a columnar shape and are provided apart from each other; the first insulating layer has an elongated shape in a plan view, and one of a pair of ends in a long side direction is in contact with the first conductive layer, and the other is in contact with the second conductive layer, the semiconductor layer surrounds the first insulating layer, the first conductive layer, and the second conductive layer in a plan view, and is in contact with a pair of side surfaces of the first insulating layer parallel to a long side direction, a side surface of the first conductive layer, and a side surface of the second conductive layer; the second insulating layer is provided between the first conductive layer and the second conductive layer to cover the semiconductor layer; the third conductive layer is provided over the second insulating layer; The off-state current per 1 μm of the channel width of the transistor is 1×10 −１８ A or below, Transistor. 　 forming a first conductive layer and a second conductive layer spaced apart from each other, each of the first conductive layer and the second conductive layer embedded in a first insulating layer; a step of removing a portion of the first insulating layer to process the first insulating layer into a wall shape whose end portions in a long side direction in a plan view are in contact with the first conductive layer and the second conductive layer; forming a semiconductor film over the first conductive layer, the second conductive layer, and the first insulating layer; performing anisotropic etching on the semiconductor film to expose an upper surface of the first conductive layer, an upper surface of the second conductive layer, and an upper surface of the first insulating layer, and forming a semiconductor layer surrounding each side surface of the first conductive layer, the second conductive layer, and the first insulating layer. A method for manufacturing a semiconductor device. 　 forming a first conductive layer and a second conductive layer spaced apart from each other, each of the first conductive layer and the second conductive layer embedded in a first insulating layer; forming a first layer including crystals in contact with upper surfaces of the first insulating layer, the first conductive layer, and the second conductive layer; removing a portion of the first insulating layer that is not covered by the first layer, and processing the first insulating layer into a wall shape whose end portion in a long side direction in a plan view is in contact with the first conductive layer and the second conductive layer; forming a semiconductor film having a single crystal structure or a polycrystalline structure to cover the first conductive layer, the second conductive layer, the first insulating layer, and the first layer; performing anisotropic etching on the semiconductor film to expose an upper surface of the first conductive layer, an upper surface of the second conductive layer, and an upper surface of the first insulating layer, and forming a semiconductor layer surrounding each side surface of the first conductive layer, the second conductive layer, and the first insulating layer. A method for manufacturing a semiconductor device. 　 In claim 18 or claim 19, After forming the semiconductor layer, forming a second insulating layer covering a portion of the semiconductor layer and a portion of the first insulating layer; forming a third conductive layer over the second insulating layer; A method for manufacturing a semiconductor device. 　 In claim 18 or claim 19, After forming the semiconductor layer, forming a third insulating layer covering the first conductive layer, the second conductive layer, the first insulating layer, and the semiconductor layer; forming a groove in the third insulating layer, the groove reaching the semiconductor layer and the first insulating layer; forming a second insulating layer inside the groove to cover the semiconductor layer and the first insulating layer; and forming a third conductive layer inside the groove to cover the second insulating layer. A method for manufacturing a semiconductor device. 　 forming a first conductive layer and a second conductive layer spaced apart from each other, each of the first conductive layer and the second conductive layer embedded in a first insulating layer; a step of removing a portion of the first insulating layer to process the first insulating layer into a wall shape whose end portions in a long side direction in a plan view are in contact with the first conductive layer and the second conductive layer; forming a semiconductor film over the first conductive layer, the second conductive layer, and the first insulating layer; anisotropically etching the semiconductor film to expose an upper surface of the first conductive layer, an upper surface of the second conductive layer, and an upper surface of the first insulating layer, and forming a semiconductor layer surrounding each side surface of the first conductive layer, the second conductive layer, and the first insulating layer; forming a sacrificial layer covering the semiconductor layer between the first conductive layer and the second conductive layer; supplying a first element to a region of the semiconductor layer that is not covered by the sacrificial layer; and removing the sacrificial layer. A method for manufacturing a semiconductor device. 　 forming a first conductive layer and a second conductive layer spaced apart from each other, each of the first conductive layer and the second conductive layer embedded in a first insulating layer; forming a first layer including crystals in contact with upper surfaces of the first insulating layer, the first conductive layer, and the second conductive layer; removing a portion of the first insulating layer that is not covered by the first layer, and processing the first insulating layer into a wall shape whose end portion in a long side direction in a plan view is in contact with the first conductive layer and the second conductive layer; forming a semiconductor film having a single crystal structure or a polycrystalline structure to cover the first conductive layer, the second conductive layer, the first insulating layer, and the first layer; anisotropically etching the semiconductor film to expose an upper surface of the first conductive layer, an upper surface of the second conductive layer, and an upper surface of the first insulating layer, and forming a semiconductor layer surrounding each side surface of the first conductive layer, the second conductive layer, and the first insulating layer; forming a sacrificial layer covering the semiconductor layer between the first conductive layer and the second conductive layer; supplying a first element to a region of the semiconductor layer that is not covered by the sacrificial layer; and removing the sacrificial layer. A method for manufacturing a semiconductor device. 　 In claim 22 or claim 23, the first element is one or more selected from titanium, aluminum, tantalum, tungsten, tin, silicon, germanium, zirconium, hafnium, antimony, magnesium, hydrogen, boron, phosphorus, and a noble gas; A method for manufacturing a semiconductor device. 　 In claim 22 or claim 23, forming a third insulating layer covering the sacrificial layer after supplying the first element; planarizing an upper portion of the third insulating layer so that an upper surface of the sacrificial layer is exposed; removing the sacrificial layer to expose the semiconductor layer and the first insulating layer; forming a second insulating layer in contact with the semiconductor layer and the first insulating layer; forming a third conductive layer over the second insulating layer; A method for manufacturing a semiconductor device. 　 In claim 19 or claim 23, the semiconductor layer is formed using an indium oxide film, the first layer is formed using an indium oxide film, an indium tin oxide film, a zinc oxide film, an indium gallium oxide film, a gallium zinc oxide film, an aluminum zinc oxide film, an indium aluminum zinc oxide film, an indium gallium zinc oxide film, or an indium tin zinc oxide film; A method for manufacturing a semiconductor device. 　 In any one of claims 18, 19, 22, and 23, After forming the semiconductor film, a heat treatment is performed; The heat treatment is carried out at a temperature of 250°C or higher and 650°C. A method for manufacturing a semiconductor device.

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