Display device and display method

Abstract

[Problem] To make it possible to suppress decreases in the resolution of a displayed image and in a display speed. [Solution] This display device comprises a display unit and a control unit. The display unit has pixels arranged in a matrix form that emit light according to held pixel signals on the basis of an image signal. The control unit updates the pixel signals of a prescribed row according to an update of the image signal, maintains the pixel signals of a row other than the prescribed row, and executes first driving for causing the pixels to emit light via sequential scanning of the rows. The control unit is also capable of changing the row for updating the pixel signals according to the update of the image signal.

Description

Display device and display method

[0001] The present disclosure relates to a display device and a display method.

[0002] An image captured by an imaging device is transmitted to a display device and displayed thereon. In this case, if the frame rate increases, it becomes difficult to display the image on the display device while maintaining synchronization with the imaging device. For this reason, in order to match the increase in frame rate, the amount of data of the image signal is reduced and the image is displayed (see Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2022-088434

[0004] However, if the data amount of the image signal is reduced, the resolution of the displayed image will decrease.

[0005] Therefore, the present disclosure provides a display device and a display method that can suppress a decrease in the resolution and display speed of a displayed image.

[0006] In order to solve the above problems, the present disclosure provides a display device including: a display unit in which pixels that emit light according to pixel signals held based on an image signal are arranged in a matrix; and a control unit that performs a first drive that updates the pixel signals of a predetermined row in response to an update of the image signal, maintains the pixel signals of rows different from the predetermined row, and causes the pixels to emit light by sequentially scanning the rows.

[0007] The control unit may change the row for updating the pixel signal in response to updating the image signal.

[0008] The control unit may update the pixel signal after completing a predetermined process on the pixels in the row for which the pixel signal is to be updated.

[0009] The control unit may stop the predetermined processing of pixels in a row where the pixel signal is maintained.

[0010] The control unit may start the predetermined processing of pixels in a row in which the pixel signal is to be updated before updating the image signal.

[0011] In the sequential scanning of the rows, the period from the start to the end of scanning of one row of the display unit corresponds to one horizontal period, and the control unit may continue the specified processing for a period longer than the one horizontal period and update the pixel signal after the specified processing is completed.

[0012] The pixel may have a light emitting element and a first transistor that controls a current supplied to the light emitting element, and the predetermined processing may be processing to correct a threshold value of the first transistor.

[0013] The control unit may change the pixel signals every n rows, where n is a natural number, in response to updating of the image signal.

[0014] The control unit may also be capable of stopping light emission of rows that maintain the pixel signals in rows other than the predetermined row.

[0015] The control unit may also be capable of performing a second drive in which, in response to updating of the pixel signal, the image signal to be held in the pixels arranged in one row of the display unit is also held in the pixels arranged in one row adjacent to the one row, causing the pixels to emit light.

[0016] The control unit may be capable of changing the combination of two consecutive rows of the display unit in response to updating of the image signal, and performing a third drive in which the image signal held in the pixels arranged in one of the two rows is also held in the pixels arranged in the other of the two rows, causing the pixels to emit light.

[0017] The control unit may change the combination of the two consecutive rows between a combination with an upper row and a combination with a lower row in turn in response to updating of the image signal.

[0018] The control unit may be capable of selecting one of the first drive, the second drive, and the third drive.

[0019] In the first driving, the control unit may maintain the image signals of odd-numbered rows for the image signals obtained by thinning out the image signals of odd-numbered rows, and maintain the image signals of even-numbered rows for the image signals obtained by thinning out the image signals of even-numbered rows.

[0020] In the first driving, the control unit may maintain image signals of odd-numbered rows for one of the two image signals that are consecutive in time series, and maintain image signals of even-numbered rows for the other image signal.

[0021] In the first driving, the control unit may maintain the image signals of odd-numbered rows for the image signals in which the image signals of even-numbered rows are assigned as the same image signal to two consecutive rows, and may maintain the image signals of even-numbered rows for the image signals in which the image signals of odd-numbered rows are assigned as the same image signal to two consecutive rows.

[0022] The control unit may also be capable of updating the pixel signals of multiple pixels in the same row in response to updating the image signal, maintaining the pixel signals of pixels other than the multiple pixels in the same row, and performing driving to cause the pixels to emit light.

[0023] The pixel may generate the plurality of image signals such that the interval between light emission periods in the plurality of image signals is less than a predetermined period.

[0024] The pixel element may include: a first transistor that controls a current supplied to a light-emitting element in accordance with a voltage supplied to a first terminal; a first capacitor that holds the voltage supplied to the first terminal; a second transistor that samples a signal voltage based on the image signal of an image signal line; a second capacitor that holds the signal voltage sampled by the second transistor as the pixel signal; and a third transistor that connects the second capacitor and the first capacitor and transfers charge accumulated in the second capacitor to the first capacitor, thereby setting a voltage corresponding to the signal voltage in the first capacitor.

[0025] In order to solve the above-mentioned problems, the present disclosure provides a display method for a display device having a display unit in which pixels that emit light according to pixel signals held based on an image signal are arranged in a matrix, the display method including: updating the pixel signals of a predetermined row in response to an update of the image signal; maintaining the pixel signals of rows other than the predetermined row; and executing a first drive that causes the pixels to emit light by line-sequential scanning.

[0026] 1 is a block diagram showing an overall schematic of a display device according to an embodiment of the present disclosure. FIG. 1 is a diagram showing an example configuration of a display unit. FIG. 2 is a detailed block diagram of the display unit. FIG. 3 is a diagram showing an example pixel circuit and peripheral circuits. FIG. 4 is a timing waveform diagram of an example operation of driving the display unit in normal drive mode. FIG. 5 is a schematic diagram showing the relationship between a field image signal and a display image signal in normal drive mode. FIG. 6 is a time chart showing an example operation in normal drive mode. FIG. 7 is a schematic diagram showing the relationship between a field image signal and a display image signal in doubler drive mode. FIG. 8 is a time chart showing an example operation in doubler drive mode. FIG. 9 is a schematic diagram showing the relationship between a field image signal and a display image signal in MARS drive mode. FIG. 10 is a diagram showing an example operation in which moving image flicker occurs in a display device. FIG. 11 is a schematic diagram showing the relationship between a field image signal and a display image signal. FIG. 12 is a time chart showing an example operation in interlace-like drive mode. FIG. 13 is a diagram explaining the effect of changing image signals between odd-numbered rows and even-numbered rows. FIG. 14 is a diagram showing signals between components in a display device. FIG. 15 is a time chart showing an example operation in a horizontal period in a line. FIG. 16 is a diagram showing a schematic shading of an image displayed in normal drive mode. FIG. 17 is a diagram showing a schematic shading of an image displayed in interlace mode. 1 is a diagram showing a schematic representation of an image displayed in interlace-like drive mode using shading; a schematic diagram showing the relationship between a field image signal and a display image signal; a time chart showing an example of operation in tabular drive mode and MARS drive mode; a time chart showing an example of operation in a horizontal period in a line (row); a schematic diagram showing the relationship between a field image signal and a display image signal; a diagram showing the relationship between image signals and processing codes; a time chart showing an example of processing according to processing codes; a time chart showing an example of processing according to processing codes; a time chart showing an example of processing according to processing codes; a time chart showing an example of processing according to processing codes; a time chart showing an example of operation in a horizontal period in a line; a schematic diagram showing the relationship between a field image signal and a display image signal; a time chart showing an example of operation in an even-numbered row in the case of interlace input; a time chart showing an example of operation in an odd-numbered row in the case of interlace input; a time chart showing an example of operation in a horizontal period in a line in interlace input; a time chart showing an example of an emission period; a time chart showing an example of an emission period in interlace-like drive; a time chart showing an example of an emission period in interlace-like drive. FIG. 2 is a diagram illustrating an example of the configuration of a pixel.1 is a diagram showing another example of the configuration of a pixel. 2 is a diagram showing another example of the configuration of a pixel. 3 is a diagram showing another example of the configuration of a pixel. 4 is a diagram showing another example of the configuration of a pixel. 5 is a diagram showing another example of the configuration of a pixel. 6 is a diagram showing another example of the configuration of a pixel. 7 is a diagram showing another example of the configuration of a pixel. 8 is a diagram showing another example of the configuration of a pixel. 9 is a diagram showing an example of the appearance of a head mounted display. 10 is a diagram showing an example of the appearance of another head mounted display. 11 is a front view showing an example of the appearance of a digital still camera. 12 is a side view showing an example of the appearance of a digital still camera. 13 is a diagram showing an example of the appearance of a television device 1. 14 is a diagram showing an example of the appearance of a smartphone. 15 is a diagram showing an example of the interior of a vehicle as seen from the rear of the vehicle. 16 is a diagram showing an example of the interior of a vehicle as seen from the left rear of the vehicle.

[0027] Hereinafter, embodiments of a display device and a display method will be described with reference to the drawings. The following description will focus on the main components of the display device and the display method, but the display device and the display method may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0028] (First embodiment)

[0029] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In one or more embodiments shown in the present disclosure, elements included in each embodiment can be combined with each other, and the combined result also forms part of the embodiment shown in the present disclosure. In the drawings, elements having the same or equivalent functions or elements with the same names are given the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0030] FIG. 1 is a schematic diagram illustrating the overall configuration of a display device according to an embodiment of the present disclosure. FIG. 1 is a block diagram illustrating an example of the overall configuration of a display device 1 according to the present disclosure. The display device 1 in FIG. 1 illustrates an example of the overall configuration when the light-emitting element is, for example, an LED (Light Emitting Diode). LEDs include LEDs used in μLED displays and OLEDs (Organic Light Emitting Diodes) used in organic EL displays. Note that the display device 1 according to the present disclosure is not necessarily limited to LEDs and can be applied to various display devices 1 such as liquid crystal display devices.

[0031] 1 includes an input unit 2, an operation unit 4, a control unit 6, and a display unit 10. The input unit 2 is, for example, a high-speed interface. An image signal is input to the input unit 2 from an imaging device.

[0032] The operation unit 4 is, for example, a change-over switch. For example, the operation unit 4 outputs a display mode signal having information about the display mode to the control unit 6 in response to switching of the change-over switch. Note that if the information about the display mode is associated with the header of the image signal, it is possible to use the information about the display mode associated with the header of the image signal.

[0033] The control unit 6 executes display control according to the image signal and the display mode information on the display unit 10. That is, the control unit 6 controls the horizontal control unit 30 (see FIG. 2) and the vertical drive unit 42 (see FIG. 2) based on the display mode information.

[0034] FIG. 2 is a diagram showing an example of the configuration of the display unit 10. The display unit 10 has pixels arranged in a matrix, each emitting light in response to a pixel signal stored based on an image signal. Specifically, the display unit 10 includes a pixel array unit 20, which includes a plurality of pixels, each including an LED, arranged two-dimensionally in a matrix, and a drive circuit arranged around the pixel array unit 20. The drive circuit includes a horizontal control unit 30 and a vertical drive unit 42. The vertical drive unit 42 sequentially selects a predetermined row of pixels in the horizontal direction in the pixel array unit 20 in the vertical direction. The horizontal control unit 30 writes pixel signals based on the image signal to the pixel groups in the predetermined row selected by the vertical drive unit 42. In normal driving, the vertical drive unit 42 selects one row at a time in sequence, but depending on the display mode, it is also possible to simultaneously select multiple rows. In this case, the horizontal control unit 30 can write pixel signals based on the image signal to the pixel groups in the multiple rows, emit light based on the pixel signals, and so on.

[0035] 3 is a detailed block diagram of the display unit 10. The display unit 10 in FIG. 3 includes a pixel array unit 20 in which a plurality of unit pixels, each including an LED, are two-dimensionally arranged in a matrix, a horizontal control unit 30, and a vertical drive unit 42. The vertical drive unit 42 includes a write scan unit 401, a drive scan unit 402, and an auxiliary drive scan unit 403. The unit pixels include a pixel 201R that emits red (R), a pixel 201G that emits blue (B), and a pixel 201B that emits green (G). When there is no need to particularly distinguish between the individual RGB pixels, they will be referred to as pixel 201.

[0036] Here, an example of the configuration of the display device in FIG. 3 is shown, where the display device is compatible with color display. A unit pixel, which is a unit for forming a color image, includes multiple RGB pixels. However, the unit pixel is not limited to a combination of pixels of the three primary colors of RGB. In the case of a monochrome display device, one unit pixel may include only one pixel of a single color. Alternatively, one unit pixel may be configured by adding pixels of one or more colors to the pixels of the three primary colors. For example, a pixel that emits white (W) light may be added to the unit pixel to improve brightness.

[0037] In the pixel array unit 20, for the two-dimensional array of pixels 201, scanning lines 211, driving lines 212, and auxiliary driving lines 213 are wired in the row direction for each pixel row. Furthermore, for the two-dimensional array of pixels 201, signal lines 214 are wired in the column direction for each pixel column. More specifically, for the two-dimensional array of pixels 201R, signal lines 214R are wired in the column direction for each pixel column. For the two-dimensional array of pixels 201G, signal lines 214G are wired in the column direction for each pixel column. For the two-dimensional array of pixels 201B, signal lines 214B are wired in the column direction for each pixel column. When there is no need to particularly distinguish between the individual RGB signal lines, they will be referred to as signal lines 214.

[0038] The scanning lines 211 are connected to output terminals of the corresponding rows of the write scanning unit 401. The driving lines 212 are connected to output terminals of the corresponding rows of the driving scanning unit 402. The auxiliary driving lines 213 are connected to output terminals of the corresponding rows of the auxiliary driving scanning unit 403. The signal lines 214 are connected to output terminals of the corresponding columns of the horizontal control unit 30.

[0039] The write scanning unit 401 is configured with a shift register circuit and the like, and is driven under the control of the control unit 6. This write scanning unit 401 sequentially supplies a write scanning signal WS1 to the scanning lines 211 when writing a signal voltage of an image signal or an offset voltage (described later) to each pixel 201 of the pixel array unit 20. This executes row sequential scanning, which scans each pixel 201 of the pixel array unit 20 in order row by row. Note that, according to the display mode of this embodiment, multiple rows may be scanned simultaneously in the row sequential scanning. In this case, it is also possible to simultaneously scan multiple rows that are not vertically consecutive.

[0040] The drive scanning unit 402, like the write scanning unit 401, is configured with a shift register circuit and the like, and is driven under the control of the control unit 6. The drive scanning unit 402 controls whether the pixels 201 emit light or not (light quenching) by supplying a light emission control signal DS to the drive lines 212 in synchronization with the scanning by the write scanning unit 401.

[0041] The auxiliary drive scanning unit 403, like the write scanning unit 401, is configured with a shift register circuit and the like, and is driven under the control of the control unit 6. This auxiliary drive scanning unit 403 supplies a drive signal AZ1 to the auxiliary drive line 213 in synchronization with the scanning by the write scanning unit 401, thereby executing control to prevent the pixel 201 from emitting light during the non-light emitting period.

[0042] The horizontal control unit 30 executes control to output a signal voltage under the control of the control unit 6. The horizontal control unit 30 selectively outputs a signal voltage Vsig or a voltage Vofs of a field image signal having luminance information supplied from the imaging device (see FIG. 1). Note that in this embodiment, the image signal is described as a field image signal, but the image signal is not limited to a field image signal. Also, the field image signal according to this embodiment may include a frame image signal. Furthermore, when odd-numbered rows or even-numbered rows of a field image signal are input as an image signal, this may be referred to as interlaced input. Also, the image signal may be simply referred to as an image. Furthermore, in this embodiment, signal information held in each pixel 201 according to the image signal corresponds to a pixel signal. For example, the signal voltage Vsig corresponds to the pixel signal.

[0043] Here, the voltage Vofs is a voltage equivalent to a reference voltage for the signal voltage Vsig of the field image signal (for example, a voltage equivalent to the black level of the field image signal), or a voltage close to that. The voltage Vofs is an initialization voltage used when performing the correction process described later.

[0044] The signal voltage Vsig / voltage Vofs alternatively output from the horizontal control unit 30 is written to each pixel 201 of the pixel array unit 20 via the signal line 214 in units of pixel rows selected by scanning by the write scanning unit 401.

[0045] 4 is a diagram showing an example circuit of a pixel (pixel circuit) 201 and peripheral circuits (horizontal control unit 30, vertical drive unit 42). The light-emitting unit of the pixel 201 includes an LED 21. The LED 21 is an example of a current-driven electro-optical element whose light emission luminance changes according to the value of a current flowing through the device.

[0046] The pixel 201 emits light in response to a pixel signal held based on a field image signal. For example, the pixel 201 is composed of an LED 21 and an element drive circuit that drives the LED 21 by passing a current through the LED 21. The cathode electrode of the LED 21 is connected to a common power supply line 35 that is wired in common to all the pixels 201. The voltage of the common power supply line 35 is a voltage Vca.

[0047] The element drive circuit that drives the LED 21 includes a drive transistor 22, a sampling transistor 23, a light-emission control transistor 24, a switching transistor 25, a capacitor Cs1, and an auxiliary capacitor Csub. In this embodiment, the pixel (pixel circuit) 201 is formed on a semiconductor such as silicon, rather than on an insulator such as a glass substrate. The drive transistor 22 is a P-channel MOS transistor (PMOS transistor).

[0048] Furthermore, in this embodiment, like the drive transistor 22, the sampling transistor 23, light-emitting control transistor 24, and switching transistor 25 are also P-channel MOS transistors. The drive transistor 22, sampling transistor 23, light-emitting control transistor 24, and switching transistor 25 each have four terminals (source / gate / drain / backgate) instead of three terminals (source / gate / drain). A power supply voltage VC is applied to the backgate of each transistor. In other words, the well potential of each transistor is set to VC.

[0049] In the pixel 201, the sampling transistor 23 samples the signal voltage Vsig supplied from the horizontal control unit 30 through a signal line 214, thereby writing a field image signal to the gate node (gate electrode) of the drive transistor 22. The drive transistor 22 controls the light emission of the LED 21 in accordance with the voltage applied to the gate electrode. The gate electrode of the drive transistor 22 corresponds to the first terminal of the drive transistor that controls the light emission of the light-emitting element. The first terminal is a control terminal, drain terminal, or source terminal, and is the control terminal in this embodiment.

[0050] The light-emission control transistor 24 is connected between a power supply node of a power supply voltage VC and the source electrode (source node) of the drive transistor 22, and controls whether the LED 21 emits light or not when driven by a light-emission control signal DS. The switching transistor 25 is connected between the drain electrode (drain node) of the drive transistor 22 and a common reference line 36 common to all pixels. When driven by a drive signal AZ1, the switching transistor 25 controls the LED 21 not to emit light during its non-emission period. The common reference line 36 has a reference voltage Vss and functions as a current drain node.

[0051] The capacitor Cs1 is connected between the gate electrode (gate node) of the driving transistor 22 and the source electrode of the driving transistor 22, and holds the signal voltage Vsig written by sampling by the sampling transistor 23. That is, the signal voltage Vsig held in the capacitor Cs1 according to this embodiment corresponds to the pixel signal held based on the field image signal.

[0052] The voltage of the capacitor Cs1 is applied to the gate electrode. The drive transistor 22 drives the LED 21 by passing a drive current corresponding to the voltage held by the capacitor Cs1 through the LED 21. The auxiliary capacitor Csub is connected between the source electrode of the drive transistor 22 and a node at a fixed potential (in this example, the power supply node of the power supply voltage VC). The auxiliary capacitor Csub suppresses fluctuations in the source voltage of the drive transistor 22 when the signal voltage Vsig is written, and also functions to set the gate-source voltage Vgs of the drive transistor 22 to the threshold voltage Vth of the drive transistor 22.

[0053] 5 is a timing waveform diagram of an example of operation when the display unit 10 (see FIG. 4) is driven in the normal drive mode, showing changes over time in the horizontal synchronization signal Hsync at the start of the horizontal period, the voltage Vofs / Vsig of the signal line 214, the light emission control signal DS, the write scanning signal WS1, the drive signal AZ1, the source voltage Vs of the drive transistor 22, the gate voltage Vg, and the anode potential of the organic EL diode.

[0054] Because the sampling transistor 23, light-emitting control transistor 24, and switching transistor 25 are P-channel MOS transistors, they are active when the write scanning signal WS1, light-emitting control signal DS, and drive signal AZ1 are at low voltages. They are inactive when the write scanning signal WS1, light-emitting control signal DS, and drive signal AZ1 are at high voltages. The sampling transistor 23, light-emitting control transistor 24, and switching transistor 25 are on (conductive) when the write scanning signal WS1, light-emitting control signal DS, and drive signal AZ1 are in the active state, and off (non-conductive) when they are in the inactive state.

[0055] One horizontal period (1H) starts when a horizontal synchronization signal Hsync, which indicates the start of a horizontal period, changes from a high voltage (high level) to a low voltage (low level). The horizontal synchronization signal Hsync is input from a synchronization counter (not shown).

[0056] At timing t0, the light emission control signal DS transitions from a high voltage to a low voltage, turning on the light emission control transistor 24. Next, at timing t1, the write scanning signal WS1 transitions from a high voltage to a low voltage, turning on the sampling transistor 23.

[0057] Also, at timing t1, the light-emission control signal DS is in a low voltage state and the light-emission control transistor 24 is on, so the source voltage Vs of the drive transistor 22 is the power supply voltage VC. A signal voltage Vsig is being output from the horizontal control unit 30 to the signal line 214. The signal voltage Vsig is sampled by the sampling transistor 23 and written to the gate electrode of the drive transistor 22, causing the gate voltage Vg of the drive transistor 22 to rise. In the example shown in the figure, VC (corresponding to the voltage for black luminance, for example) is written, and the gate voltage Vg is set to the power supply voltage VC.

[0058] Furthermore, the auxiliary drive scanning unit 403 activates the drive signal AZ1 (low potential state) from timing t1 to timing t8. During the period from timing t1 to timing t8, the LED 21 is forced into a non-light-emitting period. When the drive signal AZ1 becomes active, the switching transistor 25 turns on in response. When the switching transistor 25 turns on, an electrical short is established between the drain electrode of the drive transistor 22 (the anode electrode of the LED 21) and the common power supply line 35, which is the current drain node, via the switching transistor 25. Because the on-resistance of the switching transistor 25 is much smaller than that of the LED 21, the current flowing through the drive transistor 22 flows to the common power supply line 35 and not into the LED 21. As a result, during the non-light-emitting period of the LED 21, the current flowing through the drive transistor 22 does not flow into the LED 21. In other words, the LED 21 is prevented from emitting light during the non-light-emitting period. This enables the display panel to achieve high contrast.

[0059] At timing t2, the write scanning signal WS1 transitions from a low voltage to a high voltage, turning off the sampling transistor 23. Between timings t3 and t7, the voltage output from the horizontal control unit 30 to the signal line 214 is changed from the signal voltage Vsig to the voltage Vofs.

[0060] Between timing t4 and timing t5, the write scanning signal WS1 transitions from a high voltage to a low voltage, turning on the sampling transistor 23. Because the voltage of the signal line 214 is the voltage Vofs, the voltage Vofs is sampled by the sampling transistor 23 and written to the gate electrode of the drive transistor 22. The gate voltage Vg of the drive transistor 22 becomes the voltage Vofs.

[0061] At this time, the gate-source voltage Vgs of the drive transistor 22 is Vgs=Vofs-VC. In this way, the operation of setting the source voltage Vs of the drive transistor 22 to the power supply voltage VC and setting the gate voltage Vg of the drive transistor 22 to the voltage Vofs is the operation of preparation before threshold correction processing (threshold correction preparation). The power supply voltage VC corresponds to the initialization voltage of the source voltage Vs, and the voltage Vofs corresponds to the initialization voltage of the gate voltage Vg of the drive transistor 22.

[0062] Next, at timing t6, when the light-emission control signal DS transitions from a low voltage to a high voltage and the light-emission control transistor 24 turns off, the source electrode of the drive transistor 22 enters a floating state, and threshold correction processing is started with the gate voltage Vg of the drive transistor 22 maintained at voltage Vofs. That is, the source voltage Vs of the drive transistor 22 starts to decrease (drop) toward the voltage (Vg-Vth) obtained by subtracting the threshold voltage Vth from the gate voltage Vg of the drive transistor 22.

[0063] The threshold correction process is an operation in which the source voltage Vs of the drive transistor 22 is changed toward a voltage (Vg-Vth) obtained by subtracting the threshold voltage Vth of the drive transistor 22 from the voltage Vofs of the gate voltage Vg of the drive transistor 22 as a reference. As the threshold correction process progresses, the gate-source voltage Vgs of the drive transistor 22 converges to the threshold voltage Vth of the drive transistor 22. A voltage equivalent to this threshold voltage Vth is held in the capacitor Cs1.

[0064] At timing t8 when the threshold correction process has progressed, the drive signal AZ1 is set to an active state (low potential state). In response to this, the switching transistor 25 is turned on. Timing t8 is, for example, the timing at which the gate-source voltage Vgs has converged or nearly converged to the threshold voltage Vth.

[0065] At timing t9, the write scanning signal WS1 transitions from high to low, turning on the sampling transistor 23 and ending the threshold correction period. From timing t9 to timing t10, the horizontal control unit 30 outputs the signal voltage Vsig of the field image signal (a voltage corresponding to the desired luminance to be displayed in the pixel 201) to the signal line 214, and the signal voltage Vsig is sampled and written into the pixel 201. This operation of writing the signal voltage Vsig by the sampling transistor 23 causes the gate voltage Vg of the drive transistor 22 to become the signal voltage Vsig. The signal voltage Vsig is held in the capacitor Cs1.

[0066] When the signal voltage Vsig of this field image signal is written, the auxiliary capacitance Csub connected between the source electrode of the drive transistor 22 and the power supply node of the power supply voltage VC acts to suppress fluctuations in the source voltage Vs of the drive transistor 22. When the drive transistor 22 is driven by the signal voltage Vsig of the field image signal, the threshold voltage Vth of the drive transistor 22 is offset by the voltage equivalent to the threshold voltage Vth held in the capacitance Cs1.

[0067] At timing t11, the light-emission control signal DS transitions from a high voltage to a low voltage, turning on the light-emission control transistor 24. As a result, current is supplied to the drive transistor 22 from the power supply node of the power supply voltage VC through the light-emission control transistor 24.

[0068] With the sampling transistor 23 off, the gate electrode of the drive transistor 22 is electrically disconnected from the signal line 214 and is in a floating state. When the gate electrode of the drive transistor 22 is in a floating state, the capacitance Cs1 is connected between the gate and source of the drive transistor 22, and therefore the gate voltage Vg also fluctuates in conjunction with fluctuations in the source voltage Vs of the drive transistor 22.

[0069] That is, the source voltage Vs and gate voltage Vg of the drive transistor 22 rise while maintaining the gate-source voltage Vgs held in the capacitor Cs1. The source voltage Vs of the drive transistor 22 then rises to the light-emitting voltage Voled of the LED 21, which corresponds to the saturation current of the drive transistor 22.

[0070] The gate voltage Vg and source voltage Vs of the drive transistor 22 fluctuate while the gate-source voltage Vgs held in the capacitor Cs1, that is, the voltage across the capacitor Cs1, is maintained.

[0071] Then, the drain-source current Ids of the drive transistor 22 starts to flow through the LED 21, and the anode voltage of the LED 21 increases in accordance with the current Ids. When the anode voltage of the LED 21 eventually exceeds the threshold voltage Vthel of the LED 21, a current starts to flow through the LED 21, and the LED 21 starts to emit light.

[0072] The drive scanning unit 402 controls the operation of turning on the light-emission control transistor 24 at timing t11 and causing the LED 21 to start emitting light so that, for example, this operation is performed simultaneously for the pixels 201 in the same row in the pixel array unit 20. In the series of circuit operations described above, the threshold correction preparation, threshold correction, writing of the signal voltage Vsig (signal writing), and light-emission operation are performed, for example, in one horizontal period.

[0073] (Normal Drive Mode) Here, an example of operation in the normal drive mode by the control unit 6 will be described in detail. The normal drive mode is a mode in which drive is performed using a so-called progressive method. The control unit 6 according to this embodiment can perform drive in a format different from that of the input data.

[0074] FIG. 6 is a schematic diagram showing the relationship between input image signals and displayed image signals in the normal driving mode. Image signal g10 indicates the nth field image signal transmitted from the imaging device, and image signal g12 indicates the (n+1)th field image signal transmitted from the imaging device. Here, n, (n+1), etc. indicate the nth and (n+1)th field image signals transmitted from the imaging device. These image signals g10 and g12 include image signals corresponding to, for example, scanning lines from row 0 to row 1079. Furthermore, the image signals of each row correspond to pixel signals held by the pixel groups arranged in each row. That is, the pixel signals are held as signal voltages Vsig in the capacitances Cs1 of the pixels 201 (see FIG. 4). Note that image signals may also be referred to as video signals. Furthermore, rows may also be referred to as lines.

[0075] The image signal g14 indicates the nth field image signal written to each pixel 201 of the pixel array section 20, and the image signal g16 indicates the (n+1)th field image signal written to each pixel 201 of the pixel array section 20. In the normal drive mode, the image signal g10 is written to each pixel 201 of the pixel array section 20 as the image signal g14 and displayed. Similarly, the image signal g12 is written to each pixel 201 of the pixel array section 20 as the image signal g16 and displayed. In this way, in the normal drive mode, the image signal g10 transmitted nth is written to each pixel 201 of the pixel array section 20 and emits light. Subsequently, the image signal g12 transmitted n+1th is written to each pixel 201 of the pixel array section 20 and emits light.

[0076] 7 is a time chart showing an example of operation in the normal drive mode, illustrating changes over time in the vertical synchronization signal Vsync at the start of the vertical period, the horizontal synchronization signal Hsync at the start of the vertical period, the image signal VideoData written to each row of the pixel array unit 20, and the power Epower of the pixel array unit 20.

[0077] At timing tna, the vertical synchronization signal Vsync, which indicates the start of a vertical period, changes from a high voltage (high level) to a low voltage (low level), thereby starting one vertical period of frame n. Subsequently, at timing tnb, the horizontal synchronization signal Hsync, which indicates the start of a horizontal period, changes from a high voltage (high level) to a low voltage (low level), thereby starting one horizontal period for each row of the pixel array unit 20. During each horizontal period, the image signal g14 shown in FIG. 6 is written and displayed in the order of 0n to 1079n as the image signal VideoData corresponding to the scanning lines from row 0 to row 1079. The writing and display of the image signal VideoData ends at timing tnc. In this way, the pixel array unit 20 emits light by sequentially scanning the rows.

[0078] Similarly, at timing t(n+1)a, the synchronization signal Vsy(n+1), which indicates the start of a vertical period, changes from a high voltage (high level) to a low voltage (low level), thereby starting one vertical period of the (n+1) frame. Subsequently, at timing t(n+1)b, ​​the horizontal synchronization signal Hsync, which indicates the start of a horizontal period, changes from a high voltage (high level) to a low voltage (low level), thereby starting one horizontal period for each row of the pixel array unit 20. During each horizontal period, the image signal g14 shown in FIG. 6 is written to the scanning lines 0 to 1079 in the order of 0(n+1) to 1079(n+1), and the image signal VideoData is displayed. The writing and display of the image signal VideoData ends at timing t(n+1)c.

[0079] In this way, in the normal drive mode, the number of rows constituting the image signals g10 and g12 is the same as the number of sequentially scanned rows in the display image, making it possible to display high-resolution images.

[0080] (Doubler Drive) Here, an example of operation in the doubler drive mode by the control unit 6 will be described in detail. The doubler drive mode is a mode in which video data in the vertical direction is halved compared to the normal drive mode. Below, an example of operation in the doubler drive mode will be described in comparison with the normal drive mode. The doubler drive mode according to this embodiment differs from the normal drive mode in that pixel signals are written to the pixels 201 in every two rows of the pixel array unit 20. Furthermore, in general doubler drive, image signals for doubler drive are generated on the transmitting side and transmitted.

[0081] 8 is a schematic diagram showing the relationship between the input image signal and the displayed image signal in the doubler drive mode, in comparison with the normal drive mode. Image signal g10a indicates the nth field image signal for doubler drive transmitted from the imaging device, and image signal g12a indicates the (n+1)th field image signal for doubler drive transmitted from the imaging device. Here, n, (n+1), etc. indicate the nth and (n+1)th field image signals transmitted from the imaging device. As shown in FIG. 8, the image signals g10 and g12 for normal drive mode have different image signals for each row, whereas the image signals g10a and g12a for doubler drive have the same image signal for every two rows.

[0082] These image signals g10a and g12a have image signals corresponding to, for example, scanning lines from row 0 to row 1079. Furthermore, the image signals for each row have pixel signals corresponding to the number of pixels 201 in one row of the pixel array unit 20.

[0083] Image signal g14a indicates the nth field image signal written to each pixel 201 of the pixel array section 20, and image signal g16a indicates the (n+1)th field image signal written to each pixel 201 of the pixel array section 20. In the doubler drive mode, the image signal g10a is written to each pixel 201 of the pixel array section 20 as the image signal g14a and displayed. Similarly, the image signal g12a is written to each pixel 201 of the pixel array section 20 as the image signal g16a and displayed. In this way, the image signals g14 and g16 for the normal drive mode have different image signals for each row, whereas the image signals g14a and g16a for the doubler drive differ in that the same image signal is set for every two rows.

[0084] 9 is a time chart showing an example of operation in doubler drive mode in comparison with an example of operation in normal drive mode. The chart shows changes over time in the vertical synchronization signal Vsync at the start of a vertical period, the horizontal synchronization signal Hsync at the start of a vertical period, the image signal VideoData written to each row of the pixel array unit 20, and the power Epower of the pixel array unit 20. In doubler drive mode, the same image signal is set for every two rows as the image signals g14a and g16a for doubler drive, so one horizontal period is twice as long as one horizontal period in normal drive mode.

[0085] In the doubler drive mode, one vertical period of frame n begins when the vertical synchronization signal Vsync, which indicates the start of a vertical period, changes from a high voltage (high level) to a low voltage (low level) at timing tna. Subsequently, one horizontal period for each row of the pixel array unit 20 begins when the horizontal synchronization signal Hsync, which indicates the start of a horizontal period, changes from a high voltage (high level) to a low voltage (low level) at timing tnb. During each horizontal period, the image signal VideoData corresponding to the scanning lines from row 0 to row 1079 of the image signal g14a shown in FIG. 8 is written and displayed two rows at a time in the order 0n to 1078n. The writing and display of the image signal VideoData ends at timing tnc. In this way, the pixel array unit 20 emits light by sequentially scanning two rows at a time.

[0086] Similarly, at timing t(n+1)a, the synchronization signal Vsy(n+1)c, which indicates the start of a vertical period, changes from a high voltage (high level) to a low voltage (low level), thereby starting one vertical period of the (n+1) frame. Subsequently, at timing t(n+1)b, ​​the horizontal synchronization signal Hsync, which indicates the start of a horizontal period, changes from a high voltage (high level) to a low voltage (low level), thereby starting one horizontal period for each row of the pixel array unit 20. During each horizontal period, the image signal g14a shown in FIG. 8 is written and displayed in the order of 0(n+1) to 1078(n+1) as the image signal VideoData corresponding to the scanning lines from row 0 to row 1079.

[0087] In this way, in the doubler drive mode, the same image signal is set for every two rows of each pixel array unit 20, so the vertical resolution is lower than that in the normal drive mode. On the other hand, in the doubler drive mode, the operating speed of each pixel 201 is reduced by half compared to the operating speed in the normal drive mode. Therefore, the amount of power Epower consumed by the pixel array unit 20 in the doubler drive mode is reduced more than the amount of power Epower consumed by the pixel array unit 20 in the normal drive mode.

[0088] (MALS Drive) Here, an example of operation of the MALS drive mode by the control unit 6 will be described in detail. The MALS drive mode is a mode in which vertical video data is halved and even-numbered rows and odd-numbered rows are alternately thinned out in frame order. Below, an example of operation of the MALS drive mode will be described in comparison with the normal drive mode. The MALS drive mode according to this embodiment differs from the normal drive mode in that pixel signals are written to the pixels 201 in every two rows of the pixel array unit 20. It also differs from the doubler drive mode in that even-numbered rows and odd-numbered rows are alternately thinned out in frame order.

[0089] FIG. 10 is a schematic diagram showing the relationship between the input image signal and the displayed image signal in MARS drive mode, compared with the normal drive mode. Image signal g10b indicates the nth MARS drive field image signal transmitted from the imaging device, and image signal g12b indicates the (n+1)th MARS drive field image signal transmitted from the imaging device. Here, n, (n+1), etc. indicate the nth and (n+1)th field image signals transmitted from the imaging device. As shown in FIG. 10 , the image signals g10 and g12 for normal drive mode have different image signals for each row, whereas the image signals g10b and g12b for MARS drive have the same image signal for every two rows. Furthermore, the image signals g10b and g12b for MARS drive differ from the doubler drive mode in that even and odd rows are alternately thinned out in frame order.

[0090] These image signals g10b and g12b have image signals corresponding to, for example, scanning lines from row 0 to row 1079. Furthermore, the image signals for each row have pixel signals corresponding to the number of pixels 201 in one row of the pixel array unit 20 (see FIG. 4).

[0091] Image signal g14b indicates the nth field image signal written to each pixel 201 of the pixel array section 20, and image signal g16b indicates the (n+1)th field image signal written to each pixel 201 of the pixel array section 20. In the normal drive mode, image signal g10b is written to each pixel 201 of the pixel array section 20 as image signal g14b and displayed. Similarly, image signal g12b is written to each pixel 201 of the pixel array section 20 as image signal g16b and displayed. In this way, the image signals g14 and g16 for the normal drive mode have different image signals for each row, whereas the image signals g14b and g16b for the MARS drive are different in that the same image signal is set for every two rows.

[0092] Furthermore, when odd-numbered image signals in the image signal g12b are written (held) in units of two rows to each pixel 201 of the pixel array unit 20, the image signals are written one row later than when even-numbered image signals are written. As a result, when an image display based on the image signal g14b and an image display based on the image signal g16b are displayed consecutively, the decrease in vertical resolution as seen by the naked eye is suppressed more than in the tabular drive mode.

[0093] 11 is a time chart showing an example of operation in the MARS drive mode in comparison with an example of operation in the normal drive mode. The chart shows the changes over time of the vertical synchronization signal Vsync at the start of the vertical period, the horizontal synchronization signal Hsync at the start of the vertical period, the image signal VideoDbtb written to each row of the pixel array section 20, and the power Epower of the pixel array section 20. In the MARS drive mode, the image signals g14b and g16b for MARS drive are set to the same image signal every two rows, so one horizontal period is twice as long as one horizontal period in the normal drive mode.

[0094] In the MARS drive mode, one vertical period of frame n begins when the vertical synchronization signal Vsync, which indicates the start of a vertical period, changes from a high voltage (high level) to a low voltage (low level) at timing tnb. Subsequently, one horizontal period for each row of the pixel array unit 20 begins when the horizontal synchronization signal Hsync, which indicates the start of a horizontal period, changes from a high voltage (high level) to a low voltage (low level) at timing tnb. During each horizontal period, the image signal VideoDbtb corresponding to the scanning lines from row 0 to row 1079 of the image signal g14b shown in FIG. 8 is written two rows at a time in the order of 0n to 1078n and displayed. The writing and display of the image signal VideoDbtb ends at timing tnc.

[0095] Similarly, at timing t(n+1)b, ​​the synchronization signal Vsy(n+1)c, which indicates the start of a vertical period, changes from a high voltage (high level) to a low voltage (low level), thereby starting one vertical period of the (n+1) frame. Subsequently, at timing t(n+1)b, ​​the horizontal synchronization signal Hsync, which indicates the start of a horizontal period, changes from a high voltage (high level) to a low voltage (low level), thereby starting one horizontal period for each row of the pixel array unit 20. During each horizontal period, the image signal g14b shown in FIG. 8 is written and displayed in the order of 1(n+1) to 1079(n+1) as the image signals VideoDbtb corresponding to the scanning lines from row 0 to row 1079.

[0096] In this way, in the MARS drive mode, the same image signal is set for every two rows of each pixel array unit 20, so the vertical resolution is lower than that in the normal drive mode. On the other hand, in the MARS drive mode, the operating speed of each pixel 201 is reduced by half compared to the operating speed in the normal drive mode. Therefore, the amount of power Epower consumed by the pixel array unit 20 in the MARS drive mode is reduced compared to the amount of power Epower consumed by the pixel array unit 20 in the normal drive mode. Furthermore, because even rows and odd rows can be displayed alternately, when field images are displayed continuously, the reduction in vertical resolution as seen by the naked eye can be reduced more than in the doubler drive mode.

[0097] (Interlace-like driving) Here, an example of operation in the interlace-like driving mode by the control unit 6 will be described in detail. The interlace-like driving mode according to this embodiment differs from the normal driving mode in that, in response to updating of the field image signal, the image signals of predetermined rows of the pixel array unit 20 are updated, and the image signals of rows other than the predetermined rows are maintained. In the interlace-like driving mode according to this embodiment, the rows whose image signals are maintained and the rows whose image signals are changed are alternately switched between even-numbered rows and odd-numbered rows.

[0098] 12 is a schematic diagram showing the relationship between input image signals and displayed image signals in the interlace-like drive mode. Image signals g10 and g12 are the same data as the image signals g10 and g12 for the normal drive mode described above.

[0099] The image signal g14c indicates the nth field image signal written to each pixel 201 of the pixel array unit 20. In the interlace-like drive mode, the video signals of the even-numbered rows of the image signal g10 are set to each pixel 201 in the even-numbered rows of the pixel array unit 20. This updates the pixel signals of each pixel 201 in the even-numbered rows of the pixel array unit 20.

[0100] On the other hand, in the (n-1)th frame, the odd-numbered rows of the (n-1)th field image signal (not shown) set for the odd-numbered rows of the pixel array unit 20 are maintained without being updated in the nth frame. In this way, the image signal g10 is newly set for the even-numbered rows of the pixel array unit 20, and the (n-1)th field image signal is maintained in the set state for the odd-numbered rows.

[0101] Similarly, image signal g16c indicates the (n+1)th field image signal written to each pixel 201 in the pixel array unit 20. In the interlace-like drive mode, odd-numbered rows of image signal g12 are set to each pixel 201 in the odd-numbered rows of the pixel array unit 20. This updates the pixel signals of each pixel 201 in the odd-numbered rows of the pixel array unit 20.

[0102] On the other hand, in the (n+1) frame, the even rows of the n field image signal set in the even rows of the pixel array unit 20 in the n frame are maintained without being updated. In this way, in the (n+1) frame, the image signal g12 is newly set in the odd rows of the pixel array unit 20, and the n field image signal is maintained in the set state in the even rows.

[0103] 13 is a time chart showing an example of operation in the interlace-like drive mode, illustrating changes over time in the vertical synchronization signal Vsync at the start of the vertical period, the horizontal synchronization signal Hsync at the start of the vertical period, the image signal VideoDctc written to each row of the pixel array unit 20, and the power Epower of the pixel array unit 20.

[0104] In the interlace-like drive mode, one vertical period of frame n begins at timing tna when the vertical synchronization signal Vsync, which indicates the start of a vertical period, changes from high voltage (high level) to low voltage (low level). Subsequently, at timing tnc, the horizontal synchronization signal Hsync, which indicates the start of a horizontal period, changes from high voltage (high level) to low voltage (low level), thereby starting one horizontal period for each row of the pixel array unit 20. During each horizontal period, the image signals VideoDctc corresponding to the scanning lines from row 0 to row 1079 of the image signal g14c shown in FIGS. 12 and 13 are written to the even-numbered rows in the order 0n to 1078n, while the image signals for the odd-numbered rows are displayed while maintaining their original state. Writing and display of the image signal VideoDctc ends at timing tnc.

[0105] The power Epower of the pixel array unit 20 increases when 0n to 1078n of the image signal VideoDctc are written to the even-numbered rows. This increase in power Epower when writing to the even-numbered rows is equivalent to that in the normal drive mode. On the other hand, because the number of drive processes for the pixels 201 in the odd-numbered rows is reduced, the power Epower for the odd-numbered rows is lower than that in the normal drive mode. Therefore, the power Epower in the n-frame interlace-like drive mode is lower overall than that in the normal drive mode. Furthermore, because different image signals are set for the even-numbered rows and the odd-numbered rows, the vertical resolution is equivalent to that in the normal drive mode.

[0106] Similarly, at timing t(n+1)c, the synchronization signal Vsy(n+1)c, which indicates the start of the vertical period, changes from a high voltage (high level) to a low voltage (low level), thereby starting one vertical period of the (n+1) frame. Subsequently, at timing t(n+1)a, the horizontal synchronization signal Hsync, which indicates the start of the horizontal period, changes from a high voltage (high level) to a low voltage (low level), thereby starting one horizontal period for each row of the pixel array unit 20. During each horizontal period, the image signal g16c shown in FIGS. 12 and 13 is written to the odd-numbered rows in the order 1(n+1) to 1079(n+1) of the image signal VideoDctc corresponding to the scanning lines from row 0 to row 1079, while the image signal for the even-numbered rows is displayed while maintaining its original state. The writing and display of the image signal VideoDctc ends at timing tnc.

[0107] The power Epower of the pixel array unit 20 increases when the image signals VideoDctc from 1(n+1) to 1079(n+1) are written to odd-numbered rows. This increase in power Epower when writing to odd-numbered rows is equivalent to that in normal drive mode. On the other hand, because the number of drive processes for the pixels 201 in even-numbered rows is reduced, the power Epower for the even-numbered rows is lower than that in normal drive mode. Therefore, the power Epower in the interlace-like drive mode for the (n+1)th frame is lower overall than that in normal drive mode. Furthermore, because different image signals are set for the even-numbered rows and the odd-numbered rows, the vertical resolution is equivalent to that in normal drive mode.

[0108] In this way, in the interlace-like drive mode, pixel signals are updated for each row of the pixel array unit 20 while image signals for the other rows are maintained, so that the vertical resolution is maintained at the same level as the resolution in the normal drive mode. On the other hand, in the interlace-like drive mode, pixel signals are updated for each row of the pixel array unit 20 while image signals for the other rows are maintained, so that the amount of power Epower consumed in the interlace-like drive mode is reduced compared to the amount consumed in the normal drive mode.

[0109] 14A and 14B are diagrams illustrating the effect of changing the image signals between odd-numbered rows and even-numbered rows. Fig. 14A is a diagram schematically illustrating the state of pixels 201 in frame n, and Fig. 14B is a diagram schematically illustrating the state of pixels 201 in frame n+1. For ease of explanation, Figs. 14A and 14B illustrate two columns of pixels 201.

[0110] Fig. 14C is a diagram schematically illustrating the shading of a displayed image. Fig. 14D is a diagram illustrating, as a comparative example, an example in which an n-field image in normal drive mode is displayed and an image is displayed in n+1 frames while maintaining the image data.

[0111] 5 and as shown in A and B of Fig. 14, the pixels 201 in odd-numbered rows in the nth frame perform a series of circuit operations, including threshold correction preparation, threshold correction, writing of the signal voltage Vsig (signal update), and light-emitting operation. On the other hand, the pixels 201 in even-numbered rows in the nth frame omit the threshold correction preparation, threshold correction, and writing of the signal voltage Vsig (signal update) in the series of circuit operations, and only perform a light-emitting operation based on the pixel signal (signal maintenance) written to the capacitor Cs1 in the n-1th frame.

[0112] More specifically, in the nth frame, after the pixel 201 in the odd-numbered row (see FIG. 5) finishes emitting light, the DS signal is maintained at a high level from t0 to t11 in the nth frame, and then goes low at t11. The AZ1 signal is maintained at a low level from t1 to t8, and then goes low at t8. The DS signal is maintained at a high level throughout the horizontal period of the nth frame. As a result, the pixel signal written to the capacitor Cs1 is maintained in the capacitor Cs1 for one vertical period spanning the nth to n+1th frame periods.

[0113] The pixel signals written to the capacitor Cs1 have a reduced amount of sustained charge as the retention period increases. Therefore, the display image of the odd-numbered rows g0 to g1079 in the n+1 frame has a lower density than the odd-numbered rows g0 to g1079 in the n frame. As a result, for example, as shown in FIG. 14D, if an n field image is displayed and an image is displayed in the n+1 frame while maintaining the image data, the difference in density between the n field image and the n+1 field image will be perceived as, for example, flicker. In contrast, in the interlace-like driving according to this embodiment, the pixel signals of the even rows in the n+1 frame are updated and displayed in a grid pattern. Therefore, the display is performed with the reduction in pixel signals written to the capacitor Cs1 suppressed. As a result, the rows with reduced display density are spaced one row apart. Furthermore, the odd and even rows with reduced display density are interchanged between the n frame and the n+1 frame. Therefore, when the nth frame and the n+1th frame are displayed consecutively, the decrease in density is suppressed when viewed visually, and the flicker is also suppressed from being recognized.

[0114] Here, an example of operation in the normal drive mode and the interlace-like drive mode in the horizontal period for lines n to n+3 will be described with reference to Figures 15 and 16. Figure 15 is a diagram schematically showing signals between components in the display device 1.

[0115] 15, video data for each line is input to the input unit 2. This video data corresponds to a field image signal. In this embodiment, the image signal in the case of interlaced input may be referred to as a field image signal.

[0116] The control unit 6 outputs a TCON intermediate processing signal to the input unit 2. Here, "TCON" is given to the output signal from the control unit 6 that involves timing control. Also, "H" is given to the signal related to the horizontal control unit 30, and "V" is given to the signal related to the vertical drive unit 42.

[0117] The input unit 2 performs intermediate processing on the video data for each line in accordance with the TCON intermediate processing signal, and generates a signal voltage Vsig (see FIG. 5) for each pixel as processed effective data for each line. The input unit 2 then supplies the processed effective data for each line to the horizontal control unit 30.

[0118] The horizontal control unit 30 supplies pixel signals HS based on processed valid data to the pixels 201 in the corresponding row of the pixel array unit 20 in accordance with the TCON output signal Ht input from the control unit 6. The pixel signals HS include a signal voltage Vsig and a voltage Vofs (see FIG. 5 ) for each pixel 201.

[0119] The vertical drive unit 42 outputs a light emission control signal DS (see Figure 5), a write scanning signal WS1 (see Figure 5), and a drive signal AZ1 (see Figure 5) as a pixel drive signal VS to each pixel 201 of the pixel array unit 20 in accordance with the TCON output signal Vt input from the control unit 6.

[0120] FIG. 16 is a time chart showing an example of operation during a horizontal period for lines n to n+3 (rows). This figure explains an example of operation in interlace-like drive mode, comparing it with an example of operation in normal drive mode. The diagram shows the changes over time in the horizontal synchronization signal Hsync at the start of the horizontal period, video data, TCON intermediate processing, TCON output signal Ht, TCON output signal Vt, pixel signal HS, and pixel drive signal VS for lines n to n+3. Here, the TCON output signal Vt represents a control command excluding the light-emitting operation. That is, the TCON output signal Vt includes a correction operation signal for executing a correction operation and an associated drive operation signal. Because the light-emitting operation is performed for all lines, the vertical drive unit 42 controls the light-emitting operation when the TCON output signal Vt is absent, and executes the correction operation, associated drive operation, and light-emitting operation when the TCON output signal Vt is present.

[0121] First, an example of operation in the normal drive mode will be described. In the normal drive mode, one horizontal period for line n begins when the horizontal synchronization signal Hsync, which indicates the start of a horizontal period, changes from a high voltage (high level) to a low voltage (low level) at timing tn. The horizontal synchronization signal Hsync is output from the control unit 6 to each component.

[0122] The input unit 2 inputs the video data of the n+1 line as valid data while the video data is at a high level based on timing tn. The input unit 2 performs valid data processing to convert the video data of the n+1 line into a signal voltage Vsig for each pixel 201 in response to the input of the video data of the n+1 line while the TCON intermediate processing is at a high level, and supplies the data to the horizontal control unit 30.

[0123] The horizontal control unit 30 stores the signal voltage Vsig for each pixel 201 on the (n+1)th line, which is supplied during the horizontal period for the nth line, in a register (not shown) while the TCON output signal Ht is at a high level.

[0124] During a period when the TCON output signal Ht, pixel signal HS, and pixel drive signal VS (n Line) are at a high level, the pixels 201 on the nth line perform a series of circuit operations, including threshold correction preparation, threshold correction, writing of the signal voltage Vsig (signal update), and light emission, based on the signal voltage Vsig and voltage Vofs for each pixel 201. The signal voltage Vsig for each pixel 201 on the nth line is the signal voltage Vsig that is supplied during the horizontal period of the n-1th line and stored in a register.

[0125] Similarly, in the normal drive mode, one horizontal period for the n+1 line starts when the horizontal synchronization signal Hsync, which indicates the start of a horizontal period, changes from a high voltage (high level) to a low voltage (low level) at timing tn+1.

[0126] The input unit 2 inputs the video data of the n+2 line as valid data while the video data is at a high level based on timing tn+1. The input unit 2 performs valid data processing to convert the video data of the n+2 line into a signal voltage Vsig for each pixel 201 in response to the input of the video data of the n+2 line while the TCON intermediate processing is at a high level, and supplies the data to the horizontal control unit 30.

[0127] The horizontal control unit 30 stores the signal voltage Vsig for each pixel 201 on the n+2th line, which is supplied during the horizontal period for the n+1th line, in a register while the TCON output signal Ht is at a high level.

[0128] During a period when the TCON output signal Ht, pixel signal HS, and pixel drive signal VS (n Line) are at a high level, the pixels 201 on the n+1 line perform a series of circuit operations, including threshold correction preparation, threshold correction, writing of the signal voltage Vsig (signal update), and light emission, based on the signal voltage Vsig and voltage Vofs for each pixel 201. The signal voltage Vsig for each pixel 201 on the n+1 line is the signal voltage Vsig supplied during the horizontal period of the n line and stored in the register. This process is repeated for the n+2 and subsequent lines.

[0129] Next, an example of operation in the interlace drive mode will be described, taking an example in which pixel signals are maintained on the nth and n+2th lines.

[0130] As in the normal drive mode, the input unit 2 inputs the video data of the n+1 line as valid data while the video data is at a high level based on timing tn. The input unit 2 performs valid data processing to convert the video data of the n+1 line into a signal voltage Vsig for each pixel 201 in response to the input of the video data of the n+1 line while the TCON intermediate processing is at a high level, and supplies the data to the horizontal control unit 30.

[0131] The horizontal control unit 30 stores the signal voltage Vsig for each pixel 201 on the (n+1)th line, which is supplied during the horizontal period for the nth line, in a register while the TCON output signal Ht is at a high level.

[0132] During a period in which the pixel drive signal VS(n Line) is at a high level, the pixels 201 on the nth line perform a light emitting operation based on the pixel signal for each pixel 201 held in the previous frame. During the horizontal period of the nth line, threshold correction preparation, threshold correction, and writing of the signal voltage Vsig (signal update) are not performed, thereby reducing power consumption.

[0133] Similarly, at timing tn+1, the horizontal synchronization signal Hsync indicating the start of a horizontal period changes from a high voltage (high level) to a low voltage (low level), thereby starting one horizontal period for the n+1 line.

[0134] Based on timing tn+1, the input unit 2 inputs the video data of line n+2 as valid data while the video data is at a high level. Since a pixel signal is already being held in line n+2, the input unit 2 stops processing the valid data and also stops the TCON output signal Ht.

[0135] During a period when the TCON output signal Vt, pixel signal HS, and pixel drive signal VS (n Line) are at a high level, the pixels 201 on the n+1 line perform a series of circuit operations, including threshold correction preparation, threshold correction, writing of the signal voltage Vsig (signal update), and light emission, based on the signal voltage Vsig and voltage Vofs for each pixel 201. The signal voltage Vsig for each pixel 201 on the n+1 line is the signal voltage Vsig supplied during the horizontal period of the n line and stored in the register. This process is repeated for the n+2 and subsequent lines.

[0136] As can be seen from these, during the horizontal periods of lines n and n+2 in which pixel signals are held from the previous frame, operations Pn and Pn+2 related to threshold correction preparation, threshold correction, and writing of the signal voltage Vsig (signal update) are stopped, thereby reducing power consumption. Also, during the horizontal periods of lines n+1 and n+3 in which pixel signals are updated, operations Pn+1 and Pn+3 related to generating the signal voltage Vsig are stopped, thereby reducing power consumption.

[0137] 17 is a diagram showing a typical image displayed in grayscale in the normal drive mode, in which all lines are displayed, thereby suppressing a decrease in vertical resolution.

[0138] 18 is a diagram showing an image displayed in interlace mode using grayscale. In interlace mode, only odd and even lines are displayed alternately, resulting in reduced display brightness. Furthermore, unless the frame rate at which field images are displayed is increased, a reduction in vertical resolution becomes visible.

[0139] 19 is a diagram showing, in grayscale, an image displayed in the interlace-like drive mode according to this embodiment. In the interlace-like drive mode, all lines are displayed, so the display brightness is maintained at the same level as in the normal drive mode. In this way, in the interlace-like drive mode, all lines are displayed, so a decrease in vertical resolution is suppressed. Therefore, even if the frame rate is reduced, the decrease in vertical resolution is not visually noticeable. Furthermore, power consumption can be reduced compared to the normal drive mode.

[0140] As described above, in the interlace-like drive mode according to this embodiment, the rows in which pixel signals are maintained and the rows in which pixel signals are updated are alternately switched in response to updating of the image signals in the pixel array unit 20. This maintains the vertical resolution, and because pixel signals are updated every other row, it is possible to reduce power consumption in the pixel array unit 20.

[0141] (Second embodiment) The display device 1 according to the second embodiment differs from the display device 1 according to the first embodiment in that tabular driving and MARS driving are possible even in the case of normal input. The differences from the display device 1 according to the first embodiment will be described below.

[0142] 20 is a schematic diagram showing the relationship between a field image signal and a display image signal when the input image signal is an interlaced input. Image signals g10 and g12 are the same data as in FIG. 6, with unused data shown grayed out. The display device 1 according to the second embodiment has a tabular drive mode 2 for tabular drive in the case of normal input, and a MARS drive mode 2 for MARS drive.

[0143] (Tabular drive mode 2) In tabular drive mode 2, image signal g14a indicates the nth field image signal written to each pixel 201 of the pixel array section 20, and image signal g16a indicates the (n+1)th field image signal written to each pixel 201 of the pixel array section 20. In tabular drive mode 2, every two even-numbered rows of the image signal g10 are written as image signal g14a to each pixel 201 of the pixel array section 20 and displayed.

[0144] Similarly, two odd-numbered rows of the image signal g12 are written as the image signal g16a to each pixel 201 of the pixel array unit 20 and displayed. In this way, the image signals g10a and g12a for the tabular drive mode shown in Fig. 8 have the same image signal for two rows, whereas the tabular drive mode 2 differs in that the same image signal is set for every two rows using the image signals g10 and g12 whose values ​​are different for each row.

[0145] In this way, the display device 1 according to this embodiment enables the tabular drive mode using the image signals g10 and g12 for normal drive. Therefore, even if the image capture device cannot generate the image signals g10a and g12a for the tabular drive mode, tabular drive is possible.

[0146] (MARS drive mode 2) In MARS drive mode 2, image signal g14b indicates the nth field image signal written to each pixel 201 of the pixel array section 20, and image signal g16b indicates the (n+1)th field image signal written to each pixel 201 of the pixel array section 20. In MARS drive mode 2, two even-numbered rows of the image signal g10 are written as image signal g14a to each pixel 201 of the pixel array section 20 and displayed.

[0147] Next, two odd-numbered rows of the image signal g12 are written as image signals g16a to each pixel 201 of the pixel array unit 20 and displayed. When two odd-numbered image signals in the image signal g12 are written (held) to each pixel 201 of the pixel array unit 20, the image signals are written one row later than when the even-numbered image signals were written. As a result, when an image display based on the image signal g14b and an image display based on the image signal g16b are displayed consecutively, the decrease in vertical resolution as seen by the naked eye is suppressed more than in tabular drive mode 2.

[0148] In this way, in the display device 1 according to this embodiment, the MARS drive mode is possible using the image signals g10 and g12 for normal drive. Therefore, even if the image capture device cannot generate the image signals g10a and g12a for the MARS drive mode, for example, MARS drive is possible.

[0149] 21 is a time chart showing an example of operation in tabular drive mode 2 and MARS drive mode 2 with interlaced input. The chart shows changes over time in the vertical synchronization signal Vsync at the start of the vertical period, the horizontal synchronization signal Hsync at the start of the vertical period, the image signal VideoDctc written to each row of the pixel array section 20, and the power Epower of the pixel array section 20. Tabular drive mode 2 and MARS drive mode 2 perform similar driving except for the write row in the (n+1)th field image, and will therefore be described together.

[0150] In tabular drive mode 2, one vertical period of frame n begins at timing tna when the vertical synchronization signal Vsync, which indicates the start of a vertical period, changes from high voltage (high level) to low voltage (low level). Subsequently, at timing tnc, the horizontal synchronization signal Hsync, which indicates the start of a horizontal period, changes from high voltage (high level) to low voltage (low level), thereby starting one horizontal period for each row of the pixel array unit 20. During each horizontal period, Dctc0n to 1078n of the image signal Video, which correspond to even-numbered rows from row 0 to row 1079 of the image signal g10 shown in FIG. 20, are written in order, two rows at a time. Meanwhile, image signals VideoDctc 1n to 1079n, which correspond to odd-numbered rows, remain unwritten. Writing of the image signal VideoDctc and display end at timing tnc.

[0151] The power Epower of the pixel array unit 20 increases when image signals VideoDctc 0n to 1078n are written every two rows. The power Epower that increases when image signals VideoDctc 0n to 1078n for the even rows are written is equivalent to two rows. On the other hand, image signals 1n to 1079n for the odd rows are not written, so the power Epower for image signals 1n to 1079n for the odd rows is lower than in the normal drive mode.

[0152] Similarly, in each horizontal period of one vertical period of frame n+1, image signals VideoDctc 1(n+1) to 1079(n+1), which correspond to odd-numbered rows from row 0 to row 1079 of image signal g12c shown in FIG. 20, are written in sequence, two rows at a time. Meanwhile, image signals VideoDctc0 (n+1) to 1078(n+1), which correspond to even-numbered rows, remain unwritten. Writing and display of the image signal VideoDctc ends at timing tnc.

[0153] The power Epower of the pixel array unit 20 increases when image signals VideoDctc 1(n+1) to 1079(n+1) are written every two rows. The power Epower increases when odd-numbered rows of the image signal VideoDctc 1(n+1) to 1079(n+1) are written by two rows. On the other hand, because image signals 1(n+1) to 1079(n+1) for even-numbered rows are not written, the power Epower for the even-numbered image signals 1(n+1) to 1079(n+1) is lower than in normal drive mode. In this way, tabular drive mode 2 enables display equivalent to that of normal tabular drive even with normal input.

[0154] In MARS drive mode 2, driving equivalent to tabular drive mode 2 is performed in frame n. That is, in each horizontal period in frame n, image signals VideoDctc 0n to 1078n corresponding to the even-numbered rows from row 0 to row 1079 of the image signal g10 shown in FIG. 20 are written in order, two rows at a time. Meanwhile, image signals VideoDctc 1n to 1079n corresponding to the odd-numbered rows are maintained in an unwritten state. Writing of the image signal VideoDctc and display are completed at timing tnc.

[0155] Next, in each horizontal period of the n+1 frame, image signals VideoDctc 1(n+1) to 1079(n+1), corresponding to odd-numbered rows from row 0 to row 1079 of the image signal g12 shown in FIG. 20, are written in sequentially, two rows at a time. The written rows are shifted by one row from the written rows in frame n. Meanwhile, image signals VideoDctc 0(n+1) to 1078(n+1), corresponding to even-numbered rows, remain unwritten. Writing of the image signal VideoDctc and display are completed at timing tnc. In this way, in MARS drive mode 2, even with normal input, a display equivalent to that of normal MARS drive is possible.

[0156] As explained above, according to this embodiment, by executing n frames in which 0n to 1078n of the image signal VideoDctc corresponding to the even rows are written two rows at a time, and n+1 frames in which 1n to 1079n of the image signal VideoDctc corresponding to the odd rows are written two rows at a time, Mars drive and tabular drive are possible even in the case of normal input.

[0157] Third Embodiment A display device 1 according to a third embodiment differs from the display device 1 according to the first embodiment in that, in a series of circuit operations of a pixel 201 that updates a pixel signal, processing other than a light-emitting operation starts in a horizontal period preceding a horizontal period in which light is emitted. The differences from the display device 1 according to the first embodiment will be described below.

[0158] (Interlace-like drive mode 2) Fig. 22 is a time chart showing an example of operation in a horizontal period for lines n to n+3 (rows) in interlace-like drive mode 2. For comparison, Fig. 22 also shows a time chart for the interlace-like drive mode described in Fig. 16. As with Fig. 16, the changes over time in the horizontal synchronization signal Hsync at the start of the horizontal period, video data, TCON intermediate processing, TCON output signal Ht, TCON output signal Vt, pixel signal HS, and pixel drive signal VS for lines n to n+3 are shown.

[0159] 22 shows an example of updating pixel signals in rows n+1 and n+3. In the interlace-like drive mode, a series of circuit operations of the pixels 201 in rows n+1 and n+3 during the horizontal period of timing tn+1 includes threshold correction preparation, threshold correction, writing of the signal voltage Vsig (signal update), and light emission. Here, an example of the operation of the pixel 201 in row n+1 will be described.

[0160] As described above, during a period when the TCON output signal Vt is at a high level, the correction operation signal and the drive signal are supplied as the processing signal pna to the vertical drive unit 42. Furthermore, during a period when the pixel signal HS is at a high level, valid data (variable value) which is the signal voltage Vsig for each pixel 201 and the correction operation signal (fixed value) which is the voltage Vofs are supplied as the processing signal pnb to the pixel 201. As a result, in the pixels 201 in the n+1th row, threshold correction preparation, threshold correction, writing of the signal voltage Vsig (signal update), and light emitting operation are performed as the processing pnc.

[0161] In contrast to these, in interlace-like drive mode 2, the control unit 60 supplies the correction operation signal of the processing signal pna for the pixels 201 in the n+1th row as a processing signal pna2 to the vertical drive unit 42 while the TCON output signal Vt is at a high level in the horizontal period tn. Also, while the pixel signal HS is at a high level in the horizontal period tn, a correction operation signal (fixed value) having a voltage Vofs is supplied to the pixels 201 as a processing signal pnb2.

[0162] As a result, during the horizontal period tn when the pixel drive signal VS(n+1) is at a high level, the vertical drive unit 42 executes threshold correction preparation and threshold correction for the pixels 201 in the n+1th row as process pnc2. For example, during the horizontal period tn, the vertical drive unit 42 executes processing at timings t0 to t9 (see FIG. 5) for the pixels 201 in the n+1th row as process pnd.

[0163] Furthermore, during the horizontal period tn+1, the control unit 60 supplies the drive signal of the processed signal pna for the pixels 201 in the n+1th row as a processed signal pna3 to the vertical drive unit 42 while the TCON output signal Vt is at a high level. Furthermore, during the period when the pixel signal HS is at a high level, the signal voltage Vsig is supplied to the pixels 201 as a processed signal pnb3.

[0164] As a result, during the horizontal period tn when the pixel drive signal VS(n+1) is at a high level, the vertical drive unit 42 writes the signal voltage Vsig (signal update) to the pixels 201 in the n+1th row and performs a light emission operation as process pnc3. For example, during the horizontal period tn, the vertical drive unit 42 performs the process of transitioning to timing t9 (see FIG. 5 ) on the pixels 201 in the n+1th row as process pnc3.

[0165] As described above, according to this embodiment, the threshold correction preparation, threshold correction, writing of the signal voltage Vsig (signal update), and light emission operation for the pixel 201 are performed over two horizontal periods. This makes it possible to complete the threshold correction preparation, threshold correction, writing of the signal voltage Vsig (signal update), and light emission operation within two horizontal periods, and the drive operation of the pixel 201 can be shortened to, for example, half the period of one horizontal period.

[0166] (Fourth embodiment) A display device 1 according to a fourth embodiment differs from the display device 1 according to the first embodiment in that the repetition period of the rows in which pixel signals are changed can be changed. The differences from the display device 1 according to the first embodiment will be described below.

[0167] (Interlace-like drive mode 3) Here, a description will be given of an example of operation of the control unit 6 in interlace-like drive mode 3. Interlace-like drive mode 3 is an interlace-like drive mode that makes it possible to change the repetition period of rows in which pixel signals are changed.

[0168] 23 is a schematic diagram showing the relationship between input image signals and displayed image signals in interlace-like drive mode 3. Image signals g10 and g12 are equivalent data to the image signals g10 and g12 used in the normal drive mode described above. The (n+2) image signal g18 is the (n+2)th input field image signal. As described above, n, n+1, and n+2 represent the nth, n+1st, and n+2nd input field image signals, respectively.

[0169] Image signal g20 indicates the nth field image signal written to each pixel 201 of the pixel array unit 20. In interlace-like drive mode 3, the video signal of row j (j = k × z) of image signal g10 is set to each pixel 201 in row j of the pixel array unit 20. This updates the pixel signals of each pixel 201 in row j of the pixel array unit 20. Meanwhile, pixel signals of other rows are maintained without being updated. z is an integer between 0 and 359. k is the repeating cycle of the rows whose pixel signals are changed, and in FIG. 23, k = 3.

[0170] Similarly, image signal g12 indicates the (n+1)th field image signal written to each pixel 201 in the pixel array unit 20. In interlace-like drive mode 3, as described above, the video signal of row j (j=k×z+1) of the (n+1)th image signal g12 is set to each pixel 201 in row j of the pixel array unit 20. This updates the pixel signals of each pixel 201 in row j of the pixel array unit 20. Meanwhile, the pixel signals of the other rows are maintained without being updated.

[0171] Similarly, image signal g20 indicates the (n+2)th field image signal written to each pixel 201 in the pixel array unit 20. In interlace-like drive mode 3, as described above, the video signal of row j (j = k × z + 2) of the n+2 image signal g20 is set to each pixel 201 in row j of the pixel array unit 20. This updates the pixel signals of each pixel 201 in row j of the pixel array unit 20. Meanwhile, pixel signals of other rows are maintained without being updated. From frame n+3 onwards, similar to the n, n+1, and n+2 field images, the repetition period of the changed rows is 3. In this embodiment, the repetition period k = 3, but this is not limited thereto and may be any period equal to or greater than 2. As can be seen from these, as k increases, the power consumption of the pixel array unit 20 is reduced and the vertical resolution decreases.

[0172] As described above, according to this embodiment, the repetition period k of the rows in which pixel signals are changed can be changed, which makes it possible to set the power consumption and vertical resolution of the pixel array unit 20 within a desired range.

[0173] Fifth Embodiment A display device 1 according to a fifth embodiment differs from the display device 1 according to the first embodiment in that the display device 1 executes processing in accordance with processing codes associated with various image signals. The differences from the display device 1 according to the first embodiment will be described below.

[0174] 24 is a diagram showing the relationship between the image signals g10, g12, g10a, and g12a and the processing codes. The image signals g10, g12, g10a, and g12a are equivalent to the image signals g10, g12, g10a, and g12a shown in FIG.

[0175] The image signals g14a and g16a are equivalent to the image signals g14a and g16a shown in Fig. 8. The image signals g14b and g16b are equivalent to the image signals g14b and g16b shown in Fig. 10. The image signals g14c and g16c are equivalent to the image signals g14c and g16c shown in Fig. 12.

[0176] The image signals g14d and g16d are image signals set by interlaced driving using the doubler according to this embodiment. The image signal g14d in the nth field is set by two even-numbered field image signals. The image signal g16d in the n+1th field is set by two odd-numbered field image signals.

[0177] An example of a display operation according to processing codes Pr11 to Pr17 will be described using Figures 25 to 29. Figures 25 to 29 show the changes over time in the vertical synchronization signal Vsync at the start of the vertical period, the horizontal synchronization signal Hsync at the start of the vertical period, and the output signal of the horizontal control unit 30. They also show the changes over time in the display signal of each row (each stage) of the pixel array unit 20. For ease of explanation, Figures 25 to 29 show the display timing of rows 1 to 3 and 1076 to 1079 of the pixel array unit 20.

[0178] 25 is a time chart showing an example of processing according to process codes Pr11 and Pr12. Process code Pr11 is an example of operation corresponding to doubler drive mode 2, and process code Pr12 is an example of operation corresponding to the interlace drive mode using the doubler.

[0179] In an example of operation corresponding to doubler drive mode 2, one vertical period of frame n begins when the vertical synchronization signal Vsync, indicating the start of a vertical period, changes from high voltage (high level) to low voltage (low level) at timing tna. Subsequently, the horizontal synchronization signal Hsync, indicating the start of a horizontal period, changes from high voltage (high level) to low voltage (low level) at timing tnb, starting one horizontal period for each row of the pixel array unit 20. During each horizontal period, image signals VideoDctc0n to 1078n corresponding to even-numbered rows from row 0 to row 1079 of the image signal g10 shown in FIG. 24 are written in order, two rows at a time, to emit light. Meanwhile, image signals VideoDctc1n to 1079n corresponding to odd-numbered rows remain unwritten. Writing of the image signal VideoDctc and display end at timing tnc.

[0180] Similarly, during each horizontal period of one vertical period of frame n+1, image signals VideoDctc1(n+1) to 1079(n+1), which correspond to odd-numbered rows from row 0 to row 1079 of image signal g12 shown in FIG. 24, are written in order, two rows at a time. Meanwhile, image signals VideoDctc0(n+1) to 1078(n+1), which correspond to even-numbered rows, remain unwritten. Writing and display of image signals VideoDctc are completed at timing t(n+1)c.

[0181] In an example of operation corresponding to the doubler interlace drive mode, during each horizontal period of one vertical period of frame n, image signals VideoDctc0n to 1078n corresponding to the even-numbered rows from row 0 to row 1079 of the image signal g10 shown in Figure 24 are written in two rows at a time, causing light to be emitted. Meanwhile, image signals VideoDctc 1n to 1079n corresponding to the odd-numbered rows are maintained in an unwritten state. Writing of the image signal VideoDctc and display are completed at timing tnc.

[0182] Similarly, during each horizontal period of one vertical period of frame n+1, image signals VideoDctc 1(n+1) to 1079(n+1), corresponding to odd-numbered rows from row 0 to row 1079 of image signal g12 shown in FIG. 24, are written in two rows at a time. Meanwhile, image signals VideoDctc 0(n+1) to 1078(n+1), corresponding to even-numbered rows, are left unwritten. Writing and display of image signal VideoDctc ends at timing t(n+1)c. In this way, it is possible to display images corresponding to doubler drive mode 2 and doubler interlaced drive mode for image signals g10 and g12.

[0183] 26 is a time chart showing an example of processing according to process codes Pr13 and Pr14. Process code Pr13 is an example of operation corresponding to an interlace drive mode using a doubler, and process code Pr14 is an example of operation corresponding to an interlace-like drive mode.

[0184] In an example of operation corresponding to the doubler interlace drive mode, in each horizontal period of one vertical period of n frames, image signals VideoDctc 0n to 1078n corresponding to the even-numbered rows of row 0 to row 1078 of the image signal g10a shown in Figure 24 are written in two rows at a time and emit light. Meanwhile, image signals VideoDctc 1n to 1079n corresponding to the odd-numbered rows remain unwritten. Writing of the image signal VideoDctc and display end at timing tnc.

[0185] Similarly, in each horizontal period of one vertical period of frame n+1, image signals VideoDctc 1(n+1) to 1079(n+1), which correspond to odd-numbered rows from row 0 to row 1079 of the image signal g12a shown in FIG. 24, are written in sequence, two rows at a time. Meanwhile, image signals VideoDctc 0(n+1) to 1078(n+1), which correspond to even-numbered rows, remain unwritten. Writing and display of the image signal VideoDctc ends at timing t(n+1)c.

[0186] In an operation example corresponding to the iterative-like drive mode, in each horizontal period of one vertical period of n frames, image signals VideoDctc 0n to 1078n corresponding to even-numbered rows from row 0 to row 1079 of the image signal g10 shown in FIG. 24 are written in order and emit light. Meanwhile, image signals VideoDctc 1n to 1079n corresponding to odd-numbered rows are maintained in the state in which they were written in the n-1 frame and emit light. Writing of the image signal VideoDctc and display are completed at timing tnc.

[0187] Similarly, during each horizontal period of one vertical period of frame n+1, image signals VideoDctc 1(n+1) to 1079(n+1) corresponding to odd-numbered rows from row 0 to row 1079 of image signal g12 shown in Figure 24 are written in order and emit light. Meanwhile, image signals VideoDctc 0(n+1) to 1078(n+1) corresponding to even-numbered rows are maintained in the state in which they were written in frame n and emit light. Writing and display of image signals VideoDctc ends at timing t(n+1)c.

[0188] 27 is a time chart showing an example of processing according to process codes Pr15 and Pr16. Process code Pr15 is an example of operation corresponding to the interlace drive mode using a doubler. Process code Pr16 is an example of operation corresponding to the MARS drive mode.

[0189] In an example of operation corresponding to the doubler interlace drive mode, in each horizontal period of one vertical period of n frames, image signals VideoDctc0n to 1078n corresponding to the even-numbered rows from row 0 to row 1078 of the image signal g10a shown in Figure 24 are written in two rows at a time and emit light. Meanwhile, image signals VideoDctc 1n to 1079n corresponding to the odd-numbered rows remain unwritten. Writing of the image signal VideoDctc and display end at timing tnc.

[0190] Similarly, in each horizontal period of one vertical period of frame n+1, image signals VideoDctc 1(n+1) to 1079(n+1), which correspond to odd-numbered rows from row 0 to row 1079 of the image signal g12a shown in FIG. 24, are written in sequence, two rows at a time. Meanwhile, image signals VideoDctc 0(n+1) to 1078(n+1), which correspond to even-numbered rows, remain unwritten. Writing and display of the image signal VideoDctc ends at timing t(n+1)c.

[0191] In an example of operation corresponding to the MARS drive mode, in each horizontal period of one vertical period of n frames, image signals VideoDctc 0n to 1078n corresponding to the even-numbered rows from row 0 to row 1079 of the image signal g10 shown in Figure 24 are written in order and emit light. Meanwhile, image signals VideoDctc 1n to 1079n corresponding to the odd-numbered rows are maintained in an unwritten state for the n-1 frame. Writing of the image signal VideoDctc and display are completed at timing tnc.

[0192] Similarly, in each horizontal period of one vertical period of the n+1 frame, 1(n+1) to 1079(n+1) of the image signal VideoDctc corresponding to the odd-numbered rows from row 0 to row 1079 of the image signal g12 shown in Fig. 24 are written in order and emit light. Note that the two even-numbered rows of the nth frame and the two odd-numbered rows of the n+1th frame are shifted by one row.

[0193] On the other hand, 0(n+1) to 1078(n+1) of the image signal VideoDctc corresponding to the even-numbered rows are maintained in a state where they are not written for n frames. At timing t(n+1)c, the writing and display of the image signal VideoDctc is completed.

[0194] FIG. 28 is a time chart showing an example of processing according to the processing code Pr17. The processing code Pr17 is an example of operation corresponding to the interlace-like drive mode.

[0195] In an operation example corresponding to the iterative-like drive mode, in each horizontal period of one vertical period of n frames, image signals VideoDctc 0n to 1078n corresponding to even-numbered rows from row 0 to row 1079 of the image signal g10a shown in FIG. 24 are written in order and emit light. Meanwhile, image signals VideoDctc 1n to 1079n corresponding to odd-numbered rows are maintained in the state in which they were written in the n-1 frame and emit light. Writing and display of the image signal VideoDctc ends at timing tnc.

[0196] Similarly, during each horizontal period of one vertical period of frame n+1, image signals VideoDctc 1(n+1) to 1079(n+1) corresponding to odd-numbered rows from row 1 to row 1079 of the image signal g12a shown in Figure 24 are written in order and emit light. Meanwhile, image signals VideoDctc 0(n+1) to 1078(n+1) corresponding to even-numbered rows are maintained in the state in which they were written in frame n and emit light. Writing and display of the image signal VideoDctc ends at timing t(n+1)c.

[0197] As described above, according to this embodiment, the control unit 6 executes processing in accordance with processing codes Pr11 to Pr17. As a result, even when the input image signals are the same ((image signals g10, g12) or (image signals g10a, g12a)), it is possible to make the displayed image correspond to any of doubler drive, doubler interlace drive, MARS drive, and interlace-like drive, depending on the purpose.

[0198] Sixth Embodiment The display device 1 according to the sixth embodiment differs from the display device 1 according to the first embodiment in that the correction process is continued during the horizontal period. The differences from the display device 1 according to the third embodiment will be described below.

[0199] (Interlace-like drive mode 4) Figure 29 is a time chart showing an example of operation in a horizontal period for lines n to n+3 (rows) in interlace-like drive mode 4. Interlace-like drive mode 4 is an interlace-like drive mode that allows threshold correction preparation, threshold correction, and the write (signal update) period of the signal voltage Vsig to continue over two horizontal periods. The diagram shows changes over time in the horizontal synchronization signal Hsync at the start of the horizontal period, video data, TCON intermediate processing, TCON output signal Ht, TCON output signal Vt, pixel signal HS, and pixel drive signal VS for lines n to n+3. The interlace-like drive mode is equivalent to the drive shown in Figure 16.

[0200] 29 , in interlace-like drive mode 4, a processing period Pr29, which is a period for threshold correction preparation, threshold correction, and writing (signal update) of the signal voltage Vsig, is made to continue over two horizontal periods, and two rows, line n and line n+1, are simultaneously illuminated. To execute the processing period Pr29, the periods of the TCON output signal Vt and the pixel signal HS are also made to continue over two horizontal periods.

[0201] This makes it possible to complete the threshold correction preparation, threshold correction, writing of the signal voltage Vsig (signal update), and light-emitting operation consecutively over two horizontal periods, eliminating the need to complete the threshold correction preparation, threshold correction, writing of the signal voltage Vsig (signal update), and light-emitting operation over one horizontal period, further shortening the drive operation of the pixel 201 over one horizontal period.

[0202] Seventh Embodiment A display device 1 according to a seventh embodiment differs from the display device 1 according to the first embodiment in that it performs interlace-like driving for interlace input. The differences from the display device 1 according to the first embodiment will be described below.

[0203] (Interlace-Like Drive Mode 5) Interlace-Like Drive Mode 5 is a mode in which interlace-like drive is performed for interlace input. FIG. 30 is a schematic diagram showing the relationship between the input image signal and the displayed image signal in the case of interlace input. Image signals g10c and g12c are data equivalent to the image signals g10 and g12 used in the normal drive mode described above. When the image signal is interlace, for example, image signal g10c differs from image signal g10 (see FIG. 12) in that signals from odd rows of image signal g10 are transmitted after signals from even rows of image signal g10. Similarly, n+1 image signal g12c differs from image signal g10 (see FIG. 12) in that signals from odd rows of image signal g12 are transmitted after signals from even rows of n+1 image signal g12.

[0204] The image signal g14c indicates the nth field image signal to be written to each pixel 201 of the pixel array unit 20. In the interlace-like drive mode, for example, the signal of the even-numbered row of the image signal g10 transmitted earlier is set to each pixel 201 in the even-numbered row of the pixel array unit 20.

[0205] On the other hand, in the (n-1)th frame, the odd-numbered row signals of the (n-1)th field image signal (not shown) set for the odd-numbered rows of the pixel array unit 20 are maintained without being updated in the nth frame. In this way, even when the input image signal is interlaced, the image signal g10 is set for the even-numbered rows of the pixel array unit 20, and the (n-1)th field image signal is maintained set for the odd-numbered rows.

[0206] Similarly, image signal g16c indicates the (n+1)th field image signal written to each pixel 201 of the pixel array unit 20. In the interlace-like drive mode, odd-numbered rows of the image signal g12 are set to each pixel 201 in the odd-numbered rows of the pixel array unit 20. On the other hand, the even-numbered row signals of the nth field image signal set to the even-numbered rows of the pixel array unit 20 in the nth frame are maintained without being updated in the (n+1)th frame. In this way, even when the input image signal is interlace, in the (n+1)th frame, the image signal g12 is set to the odd-numbered rows of the pixel array unit 20, and the nth field image signal is maintained set to the even-numbered rows.

[0207] 31 is a time chart showing an example of operation in the even-numbered rows in the case of interlaced input, showing changes over time in the vertical synchronization signal Vsync at the start of the vertical period, the horizontal synchronization signal Hsync at the start of the vertical period, the image signal VideoDctc written to the even-numbered rows of the pixel array unit 20, and the power Epower of the pixel array unit 20.

[0208] In interlace-like drive mode 4 for interlace input, one vertical period of frame n begins when the vertical synchronization signal Vsync, which indicates the start of a vertical period, changes from high voltage (high level) to low voltage (low level) at timing tna. Subsequently, the horizontal synchronization signal Hsync, which indicates the start of a horizontal period, changes from high voltage (high level) to low voltage (low level) at timing tnc, which starts one horizontal period for each row of the pixel array unit 20. During each horizontal period, the image signals VideoDctc corresponding to the scanning lines from row 0 to row 1079 of the image signal g14c shown in FIG. 30 are written to the even-numbered rows in the order 0n to 1078n, while the image signals for the odd-numbered rows are displayed while maintaining their original state. Writing and display of the image signal VideoDctc ends at timing tnc. In the nth frame, 0n to 1078n of the image signal VideoDctc are written continuously to the even-numbered rows, so the writing and light emission time for the nth frame is reduced to half of that in the normal drive mode.

[0209] The power Epower of the pixel array unit 20 increases when 0n to 1078n of the image signal VideoDctc are written to the even-numbered rows. The power Epower that increases when writing to the even-numbered rows is the same as in the normal drive mode.

[0210] 32 is a time chart showing an example of operation in odd-numbered rows in the case of interlaced input, showing changes over time in the vertical synchronization signal Vsync at the start of the vertical period, the horizontal synchronization signal Hsync at the start of the vertical period, the image signal VideoDctc written to the even-numbered rows of the pixel array unit 20, and the power Epower of the pixel array unit 20.

[0211] In the interlace-like drive mode for interlace input, one vertical period of frame n+1 begins when the vertical synchronization signal Vsync, which indicates the start of a vertical period, changes from high voltage (high level) to low voltage (low level) at timing t(n+1)a. Subsequently, one horizontal period begins for each row of the pixel array unit 20 when the horizontal synchronization signal Hsync, which indicates the start of a horizontal period, changes from high voltage (high level) to low voltage (low level) at timing t(n+1)c. During each horizontal period, the image signal VideoDctc corresponding to the scanning lines from row 0 to row 1079 of the image signal g16c shown in FIG. 30 is written to the odd-numbered rows in the order 1(n+1) to 1079(n+1), while the image signal for the even-numbered rows is displayed while maintaining its original state. The writing and display of the image signal VideoDctc ends at timing tnc. In the n+1 frame, 1(n+1) to 1079(n+1) of the image signal VideoDctc are continuously written to the odd-numbered rows, so the writing and light emission time of the n+1 frame in the normal drive mode is reduced to half.

[0212] The power Epower of the pixel array unit 20 increases when 1(n+1) to 1079(n+1) of the image signal VideoDctc are written to the odd-numbered rows. The power Epower that increases when writing to the odd-numbered rows is the same as in the normal drive mode.

[0213] FIG. 33 is a time chart showing an example of horizontal period operation for lines n to n+3 (rows) in interlaced input. The diagram shows the changes over time in the horizontal synchronization signal Hsync at the start of the horizontal period, video data, TCON intermediate processing, TCON output signal Ht, TCON output signal Vt, pixel signal HS, and pixel drive signal VS for lines n to n+3. Here, the TCON output signal Vt represents a control command excluding light-emitting operation. That is, the TCON output signal Vt includes a correction operation signal for executing a correction operation and an associated drive operation signal. Since light-emitting operation is performed for all lines, the vertical drive unit 42 controls the light-emitting operation when the TCON output signal Vt is absent, and executes the correction operation, associated drive operation, and light-emitting operation when the TCON output signal Vt is present.

[0214] In the interlace-like drive mode for interlace input, one horizontal period at timing tn starts when a horizontal synchronization signal Hsync indicating the start of a horizontal period changes from a high voltage (high level) to a low voltage (low level) at timing tn. The horizontal synchronization signal Hsync is output from the control unit 6 to each component.

[0215] The input unit 2 inputs the video data of the n+3 line as valid data while the video data is at a high level based on timing tn. The input unit 2 performs valid data processing to convert the video data of the n+3 line into a signal voltage Vsig for each pixel 201 in response to the input of the video data of the n+3 line while the TCON intermediate processing is at a high level, and supplies the data to the horizontal control unit 30.

[0216] The horizontal control unit 30 stores the signal voltage Vsig for each pixel 201 on the n+3 line, which is supplied during the horizontal period at timing tn, in a register while the TCON output signal Ht is at a high level.

[0217] During a period when the TCON output signal Ht, the pixel signal HS, and the pixel drive signal VS (n Line) are at a high level, the pixels 201 on the nth line perform a light emitting operation based on the signal voltage Vsig (held signal) of each pixel 201. The signal voltage Vsig of each pixel 201 on the nth line is the signal voltage Vsig supplied in the previous frame and held by each pixel 201.

[0218] During a period in which the TCON output signal Ht, pixel signal HS, and pixel drive signal VS (n Line) are at a high level, the pixels 201 on the n+1 line perform a series of circuit operations, including threshold correction preparation, threshold correction, writing of the signal voltage Vsig (signal update), and light emission, based on the signal voltage Vsig and voltage Vofs of each pixel 201. The signal voltage Vsig of each pixel 201 on the n+1 line is the signal voltage Vsig that is supplied during the horizontal period of timing tn-1 and stored in a register.

[0219] Similarly, at timing tn+1, the horizontal synchronization signal Hsync indicating the start of a horizontal period changes from a high voltage (high level) to a low voltage (low level), thereby starting one horizontal period at timing tn+1.

[0220] The input unit 2 inputs the video data of line n+5 as valid data while the video data is at a high level based on timing tn+1. The input unit 2 performs valid data processing to convert the video data of line n+5 into a signal voltage Vsig for each pixel 201 in response to the input of the video data of line n+5 while the TCON intermediate processing is at a high level, and supplies the data to the horizontal control unit 30.

[0221] The horizontal control unit 30 stores the signal voltage Vsig for each pixel 201 on the n+5th line, which is supplied during the horizontal period at timing tn+1, in a register while the TCON output signal Ht is at a high level.

[0222] During a period in which the TCON output signal Ht, the pixel signal HS, and the pixel drive signal VS (n Line) are at a high level, the pixels 201 on the n+2 line perform a light emitting operation based on the signal voltage Vsig (held signal) of each pixel 201. The signal voltage Vsig of each pixel 201 on the n+2 line is the signal voltage Vsig supplied in the previous frame and held by each pixel 201.

[0223] During a period when the TCON output signal Ht, pixel signal HS, and pixel drive signal VS (n Line) are at a high level, the pixels 201 on the n+3 line perform a series of circuit operations, including threshold correction preparation, threshold correction, writing of the signal voltage Vsig (signal update), and light emission, based on the signal voltage Vsig and voltage Vofs for each pixel 201. The signal voltage Vsig for each pixel 201 on the n+3 line is the signal voltage Vsig supplied during the horizontal period at timing tn and stored in the register. This process is repeated from timing tn+2 onwards.

[0224] As described above, according to this embodiment, when image signals are input interlaced, when the image signals VideoDctc for the even-numbered rows 0n to 1078n are successively written, the image signals VideoDctc for the odd-numbered rows 1(n+1) to 1079(n+1) are maintained and two rows are caused to emit light at a time. Alternatively, when the image signals VideoDctc for the odd-numbered rows 1(n+1) to 1079(n+1) are successively written, the image signals VideoDctc for the even-numbered rows 0n to 1078n are maintained and two rows are caused to emit light at a time. This makes it possible to reduce the writing and emission time for the pixels 201 of the pixel array unit 20 to half that of the normal drive mode.

[0225] Eighth Embodiment The display device 1 according to the eighth embodiment differs from the display devices 1 according to the first to seventh embodiments in that the display device 1 adjusts the luminance by adjusting the display period. The differences from the display devices 1 according to the first to seventh embodiments will be described below.

[0226] FIG. 34 is a time chart showing an example of a light-emission period. It shows the vertical synchronization signal Vsync at the start of the vertical period, the horizontal synchronization signal Hsync at the start of the horizontal period, and the light-emission periods of lines 0 to 3 in normal drive mode over time. From the top, examples are shown for a basic case where the display is completed in one frame with high brightness and high light-emission duty, Case 1 where the display is completed in one frame with low brightness and low light-emission duty, Case 2 where the display is completed in two frames with low brightness and low light-emission duty, and Case 3 where the display is completed in two frames with medium brightness and low light-emission duty. For ease of explanation, the light-emission periods of rows 0 to 4 of the pixel array unit 20 are shown schematically. The nth frame starts at timing tna, the n+1th frame starts at timing t(n+1)a, and the n+2th frame starts at timing t(n+2)a.

[0227] In the basic form, the light emission duty is generated in one frame cycle, and high brightness is achieved with a high duty such as 90%. In contrast, Case 1 is an example in which the light emission duty is generated in one frame cycle, and low brightness is achieved with a low duty. In this way, brightness can be adjusted by adjusting the light emission period.

[0228] Case 2 is an example in which the light emission duty is formed in a two (multiple) frame cycle, and the light emission period of the even / odd lines is divided by frame to achieve low brightness. In other words, this driving corresponds to interlaced driving. In this way, brightness adjustment is possible by adjusting the light emission row.

[0229] Case 3 is an example in which, unlike Case 2, a period in which light emission overlaps between frames is provided to prevent excessive reduction in brightness. In this way, brightness adjustment is possible by providing a period in which light emission overlaps.

[0230] 35 is a time chart showing an example of a light emission period in interlace-like driving, which shows the vertical synchronization signal Vsync at the start of the vertical period, the horizontal synchronization signal Hsync at the start of the horizontal period, and the light emission period of lines 0 to 3 in normal drive mode over time.

[0231] From top to bottom, examples are shown of the basic form, Case 1, Case 2, Case 4 where display is completed in one frame in interlace-like drive with high brightness and high light-emitting duty, and Case 5 where display is completed in two frames in interlace-like drive with low brightness and low light-emitting duty. As comparative examples, the basic form, Case 1, and Case 2 of the normal drive mode are also shown. Here, for ease of explanation, the light-emitting periods of rows 0 to 4 of the pixel array unit 20 are shown schematically. The nth frame starts at timing tna, the n+1th frame starts at timing t(n+1)a, and the n+2th frame starts at timing t(n+2)a.

[0232] In case 4, the light emission duty is generated in one frame cycle, and high brightness is achieved with a high duty of 90% or the like. The rows where pixel signals are maintained are indicated by dashed lines. The brightness in case 4 is the same as that of the basic type.

[0233] Case 5 is an example in which the light emission duty is formed in a two (or more) frame cycle, and the light emission period of the even / odd lines is divided by frame to achieve low brightness. In this way, brightness can be adjusted by adjusting the light-emitting rows even in interlace-like driving. Note that case 5 has a display state equivalent to case 2. In other words, even in interlace-like driving, by setting rows that do not emit light, a display equivalent to that in interlace driving is possible.

[0234] FIG. 36 is a time chart showing an example of a light-emission period in interlace-like driving. It shows the vertical synchronization signal Vsync at the start of the vertical period, the horizontal synchronization signal Hsync at the start of the horizontal period, and the light-emission periods of lines 0 to 3 in normal driving mode over time. From top to bottom, the chart shows examples of the basic form, Case 4, Case 6 and Case 5, in which the display is completed in one frame with low brightness and low light-emission duty, and Case 7, in which the display is completed in two frames with interlace-like driving with medium brightness and medium light-emission duty. For comparison, Cases 4 and 5 in normal driving mode are also shown. For ease of explanation, the light-emission periods of rows 0 to 4 of the pixel array unit 20 are shown schematically. The nth frame starts at timing tna, the n+1th frame starts at timing t(n+1)a, and the n+2th frame starts at timing t(n+2)a. In general, the longer the display interval between frames and the higher the brightness, the more visible flicker becomes. For this reason, in FIG. 36, the priorities of flicker resistance and video response are set differently depending on the purpose.

[0235] Case 5 is an example in which flicker resistance is prioritized over video response. Case 6 has a shorter light emission period than Case 1. Case 6 is an example in which the light emission duty is formed in one frame cycle, resulting in low brightness and low light emission duty. Case 6 is an example in which video response is prioritized over flicker resistance.

[0236] Case 7 is an example in which the light emission duty is formed in a two-frame cycle (multiple frames), resulting in medium brightness and medium light emission duty. Rows in which pixel signals are maintained are indicated by dashed lines. Case 7 is an example in which the display periods of multiple frames are continuous, and flicker resistance is prioritized over video response.

[0237] As described above, according to this embodiment, it is possible to adjust the luminance, flicker resistance, and moving image response by adjusting the light emission period (light emission duty).

[0238] 1 has a pixel circuit including a light-emitting element such as an organic EL element for each pixel. Various modifications are possible for the specific circuit configuration of the pixel circuit. Representative circuit configurations are described below.

[0239] (First concrete example)

[0240] 37 shows an example configuration of pixel PIX. Pixel PIX has a capacitor C01, transistors MN02 and MN03, and a light-emitting element EL. Transistors MN02 and MN03 are N-type metal oxide semiconductor field effect transistors (MOSFETs). The gate of transistor MN02 is connected to a control line WSL, the other of its source and drain is connected to a signal line SGL, and one of its source and drain is connected to the gate of transistor MN03 and one end of capacitor C01. One end of capacitor C01 is connected to one of the source and drain of transistor MN02 and the gate of transistor MN03, and the other end is connected to one of the source and drain of transistor MN03 and the anode of light-emitting element EL. The gate of transistor MN03 is connected to one of the source and drain of transistor MN02 and one end of capacitor C01, the other of the source and drain is connected to the power supply line VCCP, and one of the source and drain is connected to the other end of capacitor C01 and the anode of light-emitting element EL. The anode of light-emitting element EL is connected to one of the source and drain of transistor MN03 and the other end of capacitor C01, and the cathode is connected to power supply line Vcath. The voltage of power supply line VCCP is switched appropriately between a first voltage and a second voltage lower than the first voltage.

[0241] With this configuration, in pixel PIX, when transistor MN02 is turned on, the voltage across capacitor C01 is set based on the pixel signal supplied from signal line SGL. During a period when the voltage of power supply line VCCP is at a first voltage, transistor MN03 passes a current corresponding to the voltage across capacitor C01 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MN03. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. During a period when the voltage of power supply line VCCP is at a second voltage, light-emitting element EL is turned off.

[0242] (Second Specific Example) Figure 38 shows another example of the configuration of pixel PIX. This pixel PIX has capacitors C11 and C12, transistors MP12 to MP15, and a light-emitting element EL. Transistors MP12 to MP15 are P-type MOSFETs. The gate of transistor MP12 is connected to a control line WSL, one of its source and drain is connected to a signal line SGL, and the other of its source and drain is connected to the gate of transistor MP14 and the other end of capacitor C12. One end of capacitor C11 is connected to a power supply line VCCP, and the other end is connected to one end of capacitor C12, the other of the source and drain of transistor MP13, and one of the source and drain of transistor MP14. One end of capacitor C12 is connected to the other end of capacitor C11, the other of the source and drain of transistor MP13, and one of the source and drain of transistor MP14, and the other end is connected to the other of the source and drain of transistor MP12 and the gate of transistor MP14. The gate of transistor MP13 is connected to the control line DSL, one of its source and drain is connected to the power supply line VCCP, and the other of its source and drain is connected to one of the source and drain of transistor MP14, the other end of capacitor C11, and one end of capacitor C12. The gate of transistor MP14 is connected to the other of the source and drain of transistor MP12 and the other end of capacitor C12, one of its source and drain is connected to the other of the source and drain of transistor MP13, the other end of capacitor C11, and one end of capacitor C12, and the other of its source and drain is connected to the anode of the light-emitting element EL and one of the source and drain of transistor MP15. The gate of transistor MP15 is connected to the control line AZSL, one of its source and drain is connected to the other of the source and drain of transistor MP14 and the anode of the light-emitting element EL, and the other of its source and drain is connected to the power supply line VSS.

[0243] With this configuration, in pixel PIX, when transistor MP12 is turned on, the voltage across capacitor C12 is set based on the pixel signal supplied from signal line SGL. Transistor MP13 is turned on and off based on the signal on control line DSL. While transistor MP13 is on, transistor MP14 passes a current corresponding to the voltage across capacitor C12 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP14. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP15 is turned on and off based on the signal on control line AZSL. While transistor MP15 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0244] The transistors MP12 to MP15 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP12 and MP15 may be a transistor using an oxide semiconductor.

[0245] (Third Specific Example) Figure 39 shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C21, transistors MN22 to MN25, and a light-emitting element EL. Transistors MN22 to MN25 are N-type MOSFETs. The gate of transistor MN22 is connected to a control line WSL, the other of its source and drain is connected to a signal line SGL, and one of its source and drain is connected to the gate of transistor MN24 and one end of capacitor C21. One end of capacitor C21 is connected to one of the source and drain of transistor MN22 and the gate of transistor MN24, and the other end is connected to one of the source and drain of transistor MN24, the other of the source and drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN23 is connected to a control line DSL, the other of its source and drain is connected to a power supply line VCCP, and one of its source and drain is connected to the other of the source and drain of transistor MN24. The gate of transistor MN24 is connected to one of the source and drain of transistor MN22 and one end of capacitor C21, the other of the source and drain is connected to one of the source and drain of transistor MN23, one of the source and drain is connected to the other end of capacitor C21, the other of the source and drain of transistor MN25, and the anode of the light-emitting element EL. The gate of transistor MN25 is connected to control line AZSL, the other of the source and drain is connected to one of the source and drain of transistor MN24, the other end of capacitor C21, and the anode of the light-emitting element EL, and one of the source and drain is connected to power supply line VSS.

[0246] With this configuration, in pixel PIX, when transistor MN22 is turned on, the voltage across capacitor C21 is set based on the pixel signal supplied from signal line SGL. Transistor MN23 is turned on and off based on the signal on control line DSL. While transistor MN23 is on, transistor MN24 passes a current corresponding to the voltage across capacitor C21 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MN24. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN25 is turned on and off based on the signal on control line AZSL. While transistor MN25 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0247] The transistors MN22 to MN25 may be transistors using low temperature polysilicon (LTPS). At least one of the transistors MN22 and MN25 may be a transistor using an oxide semiconductor.

[0248] (Fourth Specific Example)

[0249] 40 shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C31, transistors MP32 to MP36, and a light-emitting element EL. Transistors MP32 to MP36 are P-type MOSFETs. The gate of transistor MP32 is connected to a control line WSL, one of its source and drain is connected to a signal line SGL, and the other of its source and drain is connected to the gate of transistor MP33, the other of the source and drain of transistor MP34, and the other end of capacitor C31. One end of capacitor C31 is connected to a power supply line VCCP, and the other end is connected to the other of the source and drain of transistor MP32, the gate of transistor MP33, and the other of the source and drain of transistor MP34. The gate of transistor MP34 is connected to control line AZSL1, one of its source and drain is connected to the other of the source and drain of transistor MP33 and one of the source and drain of transistor MP35, the other of its source and drain is connected to the other of the source and drain of transistor MP32, the gate of transistor MP33, and the other end of capacitor C31. The gate of transistor MP35 is connected to control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP33 and one of the source and drain of transistor MP34, and the other of its source and drain is connected to one of the source and drain of transistor MP36 and the anode of the light-emitting element EL. The gate of transistor MP36 is connected to control line AZSL2, one of its source and drain is connected to the other of the source and drain of transistor MP35 and the anode of the light-emitting element EL, and the other of its source and drain is connected to the power supply line VSS.

[0250] With this configuration, in pixel PIX, when transistor MP32 is turned on, the voltage across capacitor C31 is set based on the pixel signal supplied from signal line SGL. Transistor MP35 is turned on and off based on the signal on control line DSL. While transistor MP35 is on, transistor MP33 passes a current corresponding to the voltage across capacitor C31 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP33. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP34 is turned on and off based on the signal on control line AZSL1. While transistor MP34 is on, the drain and gate of transistor MP33 are connected to each other. Transistor MP36 is turned on and off based on the signal on control line AZSL2. While transistor MP36 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0251] The transistors MP32 to MP36 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP32, MP34, and MP36 may be a transistor using an oxide semiconductor.

[0252] (Fifth Specific Example)

[0253] 41 shows another example of the configuration of pixel PIX. One end of capacitor C48 is connected to signal line SGL1, and the other end is connected to power supply line VSS. One end of capacitor C49 is connected to signal line SGL1, and the other end is connected to signal line SGL2. Transistor MP49 is a P-type MOSFET, with its gate connected to control line WSL2, one of its source and drain connected to signal line SGL1, and the other connected to signal line SGL2.

[0254] The pixel PIX includes a capacitor C41, transistors MP42 to MP46, and a light-emitting element EL. The transistors MP42 to MP46 are P-type MOSFETs. The gate of transistor MP42 is connected to a control line WSL1, one of its source and drain is connected to a signal line SGL2, and the other of its source and drain is connected to the gate of transistor MP43 and the other end of capacitor C41. One end of capacitor C41 is connected to a power supply line VCCP, and the other end is connected to the other of the source and drain of transistor MP42 and the gate of transistor MP43. The gate of transistor MP43 is connected to the other of the source and drain of transistor MP42 and the other end of capacitor C41, one of its source and drain is connected to the power supply line VCCP, and the other of its source and drain is connected to one of the sources and drains of transistors MP44 and MP45. The gate of transistor MP44 is connected to control line AZSL1, one of its source and drain is connected to the other of the source and drain of transistor MP43 and one of the source and drain of transistor MP45, and the other of its source and drain is connected to signal line SGL2. The gate of transistor MP45 is connected to control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP43 and one of the source and drain of transistor MP44, and the other of its source and drain is connected to one of the source and drain of transistor MP46 and the anode of the light-emitting element EL. The gate of transistor MP46 is connected to control line AZSL2, one of its source and drain is connected to the other of the source and drain of transistor MP45 and the anode of the light-emitting element EL, and the other of its source and drain is connected to power supply line VSS.

[0255] With this configuration, in pixel PIX, when transistor MP42 is turned on, the voltage across capacitor C41 is set based on the pixel signal supplied to signal line SGL1. Transistor MP45 is turned on and off based on the signal on control line DSL. While transistor MP45 is on, transistor MP43 passes a current corresponding to the voltage across capacitor C41 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP43. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MP44 is turned on and off based on the signal on control line AZSL1. While transistor MP44 is on, the drain of transistor MP43 and signal line SGL2 are connected to each other. Transistor MP46 is turned on and off based on the signal on control line AZSL2. While transistor MP46 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0256] The transistors MP42 to MP46 and MP49 may be transistors using low temperature polysilicon (LTPS). At least one of the transistors MP42, MP46 and MP49 may be a transistor using an oxide semiconductor.

[0257] (Sixth Specific Example)

[0258] 42 shows another example of the configuration of the pixel PIX. A plurality of pixels PIX are arranged in a matrix in a display area 100, and the display area 100 is provided between a first control unit 40 and a second control unit 70.

[0259] The first control unit 40 includes transmission gates TG45 and TG46, transistors MP56 and MP57, and a capacitor C61. Transistors MP56 and MP57 are P-type MOSFETs. One end of the transmission gate TG45 receives a pixel signal, and the other end is connected to the signal line 14a. One end of the transmission gate TG46 is connected to the signal line 14b, and the other end is connected to the power supply line Vorst. One end of the capacitor C61 is connected to the signal line 14a, and the other end is connected to the power supply line VSS1. The gate of the transistor MP56 is connected to the control line INIL, one of the source and drain is connected to the power supply line Vini, and the other is connected to the signal line 14b. The gate of the transistor MP57 is connected to the control line ELL, one of the source and drain is connected to the power supply line Vel, and the other is connected to the signal line 14b.

[0260] The second control unit 70 has a transmission gate TG72, a transistor MP73, and a capacitor C82. The transistor MP73 is a P-type MOSFET. One end of the transmission gate TG72 is connected to the signal line 14a, and the other end is connected to the other of the source and drain of the transistor MP73 and one end of the capacitor C82. The gate of the transistor MP73 is connected to the control line REFL, one of the source and drain is connected to the power supply line Vref, and the other of the source and drain is connected to the other end of the transmission gate TG72 and one end of the capacitor C82. One end of the capacitor C82 is connected to the other end of the transmission gate TG72 and the other of the source and drain of the transistor MP73, and the other end is connected to the signal line 14b.

[0261] The pixel PIX includes a capacitor C132, transistors MP121 to MP125, and a light-emitting element EL. The transistors MP121 to MP125 are P-type MOSFETs. The gate of the transistor MP122 is connected to the control line WSL, one of the source and drain is connected to the signal line 14b, and the other of the source and drain is connected to the gate of the transistor MP121 and the other end of the capacitor C132. One end of the capacitor C132 is connected to the power supply line Vel, and the other end is connected to the other of the source and drain of the transistor MP122 and the gate of the transistor MP121. The gate of the transistor MP121 is connected to the other of the source and drain of the transistor MP122 and the other end of the capacitor C132, one of the source and drain is connected to the power supply line Vel, and the other of the source and drain is connected to one of the sources and drains of the transistors MP123 and MP124. The gate of transistor MP123 is connected to the control line AZSL, one of its source and drain is connected to the other of the source and drain of transistor MP121 and one of the source and drain of transistor MP124, and the other of its source and drain is connected to signal line 14b. The gate of transistor MP124 is connected to the control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP121 and one of the source and drain of transistor MP123, and the other of its source and drain is connected to one of the source and drain of transistor MP125 and the anode of the light-emitting element EL. The gate of transistor MP125 is connected to the control line AZSL, the other of its source and drain is connected to the power supply line Vorst, and one of its source and drain is connected to the other of the source and drain of transistor MP124 and the anode of the light-emitting element EL.

[0262] With this configuration, in pixel PIX, when transistor MP122 is turned on, the voltage across capacitor C132 is set based on the pixel signal supplied to one end of transmission gate TG45. Transistor MP124 is turned on and off based on the signal on control line DSL. While transistor MP124 is on, transistor MP121 passes a current corresponding to the voltage across capacitor C132 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP121. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistors MP123 and MP125 are turned on and off based on the signal on control line AZSL. While transistor MP123 is on, the other of the source and drain of transistor MP121 and one of the source and drain of transistor MP124 are connected to signal line 14b. While transistor MP125 is on, the voltage of the anode of light-emitting element EL is initialized by being set to the voltage of power supply line Vorst. Furthermore, transistor MP56 is turned on and off based on the signal on control line INIL, transistor MP57 is turned on and off based on the signal on control line ELL, and transistor MP73 is turned on and off based on the signal on control line REFL. When transistor MP56 is turned on, signal line 14b is set to the voltage of power supply line Vini, and when transistor MP57 is turned on, signal line 14b is set to the voltage of power supply line Vel. When transistor MP73 is turned on, one end of capacitor C82 is set to the voltage of power supply line Vref, thereby being initialized.

[0263] The transistors MP121 to MP125, MP56, and MP57 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP122 and MP125 may be a transistor using an oxide semiconductor.

[0264] (Seventh Specific Example)

[0265] 43 shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C51, transistors MP52 to MP60, and a light-emitting element EL. Transistors MP52 to MP60 are P-type MOSFETs. The gate of transistor MP52 is connected to a control line WSL, one of its source and drain is connected to a signal line SGL, and the other of its source and drain is connected to the other of the source and drain of transistor MP53 and one of the source and drain of transistor MP54. The gate of transistor MP53 is connected to a control line DSL, one of its source and drain is connected to a power supply line VCCP, and the other of its source and drain is connected to the other of the source and drain of transistor MP52 and one of the source and drain of transistor MP54. The gate of transistor MP54 is connected to one of the source and drain of transistor MP55, the other of the source and drain of transistor MP57, and the other end of capacitor C51, with one of its source and drain connected to the other of the sources and drains of transistors MP52 and MP53, and the other connected to one of the sources and drains of transistors MP58 and MP59. Capacitor C51 has one end connected to the power supply line VCCP, and the other end connected to the gate of transistor MP54, one of the source and drain of transistor MP55, and the other of the source and drain of transistor MP57. Capacitor C51 may include two capacitors connected in parallel. The gate of transistor MP55 is connected to control line AZSL1, with one of its source and drain connected to the gate of transistor MP54, the other of the source and drain of transistor MP57, and the other end of capacitor C51, and the other connected to one of the source and drain of transistor MP56. The gate of the transistor MP56 is connected to the control line AZSL1, one of the source and drain is connected to the other of the source and drain of the transistor MP55, and the other of the source and drain is connected to the power supply line VSS.The gate of transistor MP57 is connected to the control line WSL, the other of its source and drain is connected to the gate of transistor MP54, one of the source and drain of transistor MP55, and the other end of capacitor C51, and one of its source and drain is connected to the other of the source and drain of transistor MP58. The gate of transistor MP58 is connected to the control line WSL, the other of its source and drain is connected to one of the source and drain of transistor MP57, and one of its source and drain is connected to the other of the source and drain of transistor MP54 and one of the source and drain of transistor MP59. The gate of transistor MP59 is connected to the control line DSL, one of its source and drain is connected to the other of the source and drain of transistor MP54 and one of the source and drain of transistor MP58, and the other of its source and drain is connected to one of the source and drain of transistor MP60 and the anode of the light-emitting element EL. The gate of the transistor MP60 is connected to the control line AZSL2, one of the source and drain is connected to the other of the source and drain of the transistor MP59 and the anode of the light-emitting element EL, and the other of the source and drain is connected to the power supply line VSS.

[0266] With this configuration, in pixel PIX, transistors MP52, MP54, MP58, and MP57 are turned on, and the voltage across capacitor C51 is set based on the pixel signal supplied from signal line SGL. Transistors MP53 and MP59 are turned on and off based on the signal on control line DSL. While transistors MP53 and MP59 are on, transistor MP54 passes a current corresponding to the voltage across capacitor C51 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP54. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistors MP55 and MP56 are turned on and off based on the signal on control line AZSL1. While transistors MP55 and MP56 are on, the gate voltage of transistor MP54 is initialized by being set to the voltage of power supply line VSS. Transistor MP60 is turned on and off based on the signal on control line AZSL2. During the period in which the transistor MP60 is in the on state, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0267] The transistors MP52 to MP60 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP55 to MP58 and MP60 may be a transistor using an oxide semiconductor.

[0268] (Eighth Specific Example)

[0269] 44 shows another example of the configuration of the pixel PIX. The signal on the control line WSNL and the signal on the control line WSPL are mutually inverted signals.

[0270] The pixel PIX includes capacitors C61 and C62, transistors MN63, MP64, and MN65 to MN67, and a light-emitting element EL. The transistors MN63, MN65 to MN67 are N-type MOSFETs, and the transistor MP64 is a P-type MOSFET. The gate of the transistor MN63 is connected to a control line WSNL, and the other of its source and drain is connected to a signal line SGL and one of the source and drain of the transistor MP64, and one of its source and drain is connected to the other of the source and drain of the transistor MP64, one end of the capacitors C61 and C62, and the gate of the transistor MN65. The gate of the transistor MP64 is connected to a control line WSPL, and one of its source and drain is connected to the signal line SGL and the other of the source and drain of the transistor MN63, and the other of the source and drain is connected to one of the source and drain of the transistor MN63, one end of the capacitors C61 and C62, and the gate of the transistor MN65. The capacitor C61 is configured using, for example, a metal oxide metal (MOM) capacitor, with one end connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, one end of capacitor C62, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C61 may be configured using, for example, a metal oxide semiconductor (MOS) capacitor or a metal insulator metal (MIM) capacitor. The capacitor C62 is configured using, for example, a MOS capacitor, with one end connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, one end of capacitor C61, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C62 may be configured using, for example, a MOM capacitor or a MIM capacitor. The other end of capacitor C62 may be connected to the power supply line VSS3 (not shown).The gate of transistor MN65 is connected to one of the source and drain of transistor MN63, the other of the source and drain of transistor MP64, and one end of capacitors C61 and C62, the other of its source and drain is connected to the power supply line VCCP, and one of its source and drain is connected to the other of the sources and drains of transistors MN66 and MN67. The gate of transistor MN66 is connected to control line AZL, the other of its source and drain is connected to one of the source and drain of transistor MN65 and the other of the source and drain of transistor MN67, and one of its source and drain is connected to power supply line VSS1. The gate of transistor MN67 is connected to control line DSL, the other of its source and drain is connected to one of the source and drain of transistor MN65 and the other of the source and drain of transistor MN66, and one of its source and drain is connected to the anode of the light-emitting element EL. Alternatively, the transistor MN67 and the control line DSL may be omitted, and one of the source and drain of the transistor MN65 may be connected to the other of the source and drain of the transistor MN66 and the anode of the light-emitting element EL.

[0271] With this configuration, in pixel PIX, when at least one of transistors MN63 and MP64 is turned on, the voltage across capacitors C61 and C62 is set based on the pixel signal supplied from signal line SGL. Transistor MN67 is turned on and off based on the signal on control line DSL. While transistor MN65 is on, it passes a current corresponding to the voltage across capacitors C61 and C62 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP65. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN66 may be turned on and off based on the signal on control line AZL. Transistor MN66 may also function as a resistor element having a resistance value corresponding to the signal on control line AZL. In this case, transistors MN65 and MN66 form a so-called source follower circuit.

[0272] The transistors MN63, MP64, and MN65 to MN67 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MN63, MP64, and MN66 may be a transistor using an oxide semiconductor.

[0273] (Ninth Specific Example)

[0274] 45 shows another example of the configuration of pixel PIX. This pixel PIX has a capacitor C71, transistors MN72 to MN77, and a light-emitting element EL. Transistors MN72 to MN77 are N-type MOSFETs. The gate of transistor MN72 is connected to a control line WSL, the other of its source and drain is connected to a signal line SGL, and one of its source and drain is connected to one of the source and drain of transistor MN74 and the other of the source and drain of transistor MN75. One end of capacitor C71 is connected to the gate of transistor MN74 and one of the source and drain of transistor MN76, and the other end is connected to the other of the source and drain of transistor MN77, one of the source and drain of transistor MN75, and the anode of the light-emitting element EL. The gate of transistor MN73 is connected to control line DLS1, the other of its source and drain is connected to power supply line VCCP, one of its source and drain is connected to the other of transistor MN74 and the other of transistor MN76. The gate of transistor MN74 is connected to one of the source and drain of transistor MN76 and one end of capacitor C71, the other of its source and drain is connected to one of the source and drain of transistor MN73 and the other of the source and drain of transistor MN76, one of its source and drain is connected to one of the source and drain of transistor MN72 and the other of the source and drain of transistor MN75. The gate of transistor MN75 is connected to control line DSL2, the other of its source and drain is connected to one of the source and drain of transistor MN72 and one of the source and drain of transistor MN74, and one of its source and drain is connected to the other end of capacitor C71, the other of the source and drain of transistor MN77, and the anode of light-emitting element EL.The gate of transistor MN76 is connected to control line AZSL, the other of its source and drain is connected to one of the source and drain of transistor MN73 and the other of the source and drain of transistor MN74, one of its source and drain is connected to the gate of transistor MN74 and one end of capacitor C71. The gate of transistor MN77 is connected to control line AZSL, the other of its source and drain is connected to the other end of capacitor C71, one of the source and drain of transistor MN75, and the anode of light-emitting element EL, and one of its source and drain is connected to power supply line VSS.

[0275] With this configuration, in pixel PIX, transistors MN72, MN74, and MN76 are turned on, and the voltage across capacitor C71 is set based on the pixel signal supplied from signal line SGL. Transistor MN73 is turned on and off based on the signal on control line DSL1, and transistor MN75 is turned on and off based on the signal on control line DSL2. While transistors MN73 and MN75 are on, transistor MN74 passes a current corresponding to the voltage across capacitor C71 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MN74. In this way, pixel PIX emits light at a luminance corresponding to the pixel signal. Transistor MN77 is turned on and off based on the signal on control line AZSL. While transistor MN77 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0276] The transistors MN72 to MN77 may be transistors using low temperature polycrystalline silicon (LTPS). The transistor MN76 may be a transistor using an oxide semiconductor. <Application Examples> Next, application examples of the display systems described in the above embodiments and modifications will be described.

[0277] 46 shows an example of the appearance of a head-mounted display 110. The head-mounted display 110 has, for example, ear hooks 112 for wearing on the user's head on both sides of a glasses-shaped display unit 111. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 110.

[0278] (Application Example 2) FIG. 47 shows an example of the appearance of another head-mounted display 120. The head-mounted display 120 is a see-through head-mounted display having a main body 121, an arm 122, and a lens barrel 123. This head-mounted display 120 is attached to eyeglasses 128. The main body 121 has a control board and a display unit for controlling the operation of the head-mounted display 120. The display unit emits image light of a display image. The arm 122 connects the main body 121 to the lens barrel 123 and supports the lens barrel 123. The lens barrel 123 projects the image light supplied from the main body 121 via the arm 122 toward the user's eyes via lenses 129 of the eyeglasses 128. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 120.

[0279] The head-mounted display 120 is a so-called light guide plate type head-mounted display, but is not limited to this and may be, for example, a so-called birdbath type head-mounted display. The birdbath type head-mounted display includes, for example, a beam splitter and a partially transparent mirror. The beam splitter outputs light encoded with image information toward the mirror, and the mirror reflects the light toward the user's eyes. Both the beam splitter and the partially transparent mirror are partially transparent. This allows light from the surrounding environment to reach the user's eyes.

[0280] (Application Example 3) Figures 48A and 48B show an example of the appearance of a digital still camera 130, with Figure 48A showing a front view and Figure 48B showing a rear view. This digital still camera 130 is a single-lens reflex camera with interchangeable lenses and includes a camera body 131, a photographing lens unit 132, a grip 133, a monitor 134, and an electronic viewfinder 135. The photographing lens unit 132 is an interchangeable lens unit and is provided near the center of the front of the camera body 311. The grip 133 is provided on the left side of the front of the camera body 311, and is held by the photographer. The monitor 134 is provided to the left of the center of the back of the camera body 131. The electronic viewfinder 135 is provided above the monitor 134 on the back of the camera body 131. By looking through this electronic viewfinder 135, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 132 and determine the composition. The techniques according to the above-described embodiments and the like can be applied to the electronic viewfinder 135.

[0281] 49 shows an example of the appearance of a television device 140. The television device 140 has an image display screen unit 141 including a front panel 142 and a filter glass 143. The techniques according to the above-described embodiments and the like can be applied to this image display screen unit 141.

[0282] 50 shows an example of the appearance of a smartphone 150. The smartphone 150 has a display unit 151 that displays various information and an operation unit 152 that includes buttons and the like that accept operation inputs from a user. The techniques according to the above-described embodiments and the like can be applied to this display unit 151.

[0283] (Application Example 6) Figures 51A and 51B show an example configuration of a vehicle to which the technology of the present disclosure is applied, where Figure 51A shows an example of the interior of the vehicle as seen from the rear of vehicle 200, and Figure 51B shows an example of the interior of the vehicle as seen from the left rear of vehicle 200.

[0284] The vehicle in Figures 51A and 51B has a center display 2010, a console display 202, a head-up display 203, a digital rearview mirror 204, a steering wheel display 205, and a rear entertainment display 106.

[0285] The center display 2010 is disposed on the dashboard 261 in a position facing the driver's seat 262 and the passenger's seat 263. FIG. 51A illustrates an example of a horizontally elongated center display 2010 extending from the driver's seat 262 side to the passenger's seat 263 side, but the screen size and location of the center display 2010 are not limited to this. The center display 2010 can display information detected by various sensors. As a specific example, the center display 2010 can display an image captured by an image sensor, a distance image to obstacles in front of or to the side of the vehicle measured by a ToF sensor, and the body temperature of an occupant detected by an infrared sensor. The center display 2010 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information.

[0286] The safety-related information includes information based on sensor detection results, such as detection of drowsiness, distraction, child mischief, whether a seatbelt is fastened, and whether a passenger is abandoned. The operation-related information includes gesture information related to passenger operations detected using sensors. The gestures may include operations of various in-vehicle equipment, such as air conditioning, navigation, audiovisual (AV) equipment, and lighting. The life log includes life logs of all passengers. For example, the life log includes a record of each passenger's behavior. By acquiring and storing the life log, it is possible to determine the condition of the passengers at the time of an accident. The health-related information includes the passenger's body temperature detected using a temperature sensor and information on the passenger's health condition estimated based on the detected body temperature. Alternatively, the passenger's health condition information may be estimated based on the passenger's face captured by an image sensor. Furthermore, the passenger's health condition information may be estimated based on the passenger's responses obtained through an automated voice conversation with the passenger. The authentication / identification-related information includes information on a keyless entry function that uses a sensor to perform facial authentication, a function that automatically adjusts the seat height and position by facial recognition, etc. The entertainment-related information includes information on AV device operations by occupants detected by the sensor, and information on content to be displayed that is appropriate for the occupants detected and recognized by the sensor.

[0287] The console display 202 can be used to display, for example, life log information. The console display 202 is disposed near a shift lever 265 on a center console 264 between a driver's seat 262 and a passenger seat 263. The console display 202 can also display information detected by various sensors. The console display 202 may also display an image of the vehicle's surroundings captured by an image sensor, or an image showing the distance to an obstacle around the vehicle.

[0288] The head-up display 203 is virtually displayed behind a windshield 266 in front of the driver's seat 262. The head-up display 203 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. Since the head-up display 203 is often virtually disposed in front of the driver's seat 262, it is suitable for displaying information directly related to vehicle operation, such as the vehicle speed, the remaining fuel level, and the remaining battery level.

[0289] The digital rearview mirror 204 can not only display the rear of the vehicle, but also display the state of passengers in the rear seats, and can therefore be used to display life log information of passengers in the rear seats, for example.

[0290] The steering wheel display 205 is disposed near the center of the vehicle's steering wheel 267. The steering wheel display 205 can be used to display at least one of, for example, safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 205 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information related to the operation of AV equipment, air conditioning equipment, etc.

[0291] The rear entertainment display 206 is attached to the back side of the driver's seat 262 and the passenger seat 263 and is intended for viewing by rear seat passengers. The rear entertainment display 206 can be used to display at least one of, for example, safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, since the rear entertainment display 206 is located in front of the rear seat passengers, information related to the rear seat passengers is displayed on the rear entertainment display 206. The rear entertainment display 206 may display, for example, information related to the operation of an AV device or an air conditioning system, or may display the results of measurements of the body temperature of the rear seat passengers by the temperature sensor 5.

[0292] The techniques according to the above-described embodiments can be applied to the center display 2010, the console display 202, the head-up display 203, the digital rearview mirror 204, the steering wheel display 205, and the rear entertainment display 206.

[0293] The present technology may be configured as follows. (1) A display device including: a display unit in which pixels that emit light according to pixel signals held based on an image signal are arranged in a matrix; and a control unit that performs a first drive that updates the pixel signals of a predetermined row in response to an update of the image signal, maintains the pixel signals of rows other than the predetermined row, and causes the pixels to emit light by row sequential scanning. (2) The display device according to (1), in which the control unit changes the row in which the pixel signals are updated in response to an update of the image signal. (3) The display device according to (1) or (2), in which the control unit updates the pixel signals after completing predetermined processing of pixels in the row in which the pixel signals are updated. (4) The display device according to (3), in which the control unit stops the predetermined processing of pixels in the row in which the pixel signals are maintained. (5) The display device according to (3) or (4), in which the control unit starts the predetermined processing of pixels in the row in which the pixel signals are updated before updating the image signal. (6) The display device according to (3) or (4), wherein in the row sequential scanning, the period from the start to the end of scanning per row of the display unit corresponds to one horizontal period, and the control unit continues the predetermined process for a period longer than one horizontal period and updates the pixel signal after the predetermined process is completed. (7) The display device according to any one of (3) to (6), wherein the pixel has a light-emitting element and a first transistor that controls a current supplied to the light-emitting element, and the predetermined process is a process of correcting a threshold value of the first transistor. (8) The display device according to any one of (1) to (7), wherein the control unit changes the pixel signal every n rows, where n is a natural number, in response to updating the image signal. (9) The display device according to any one of (1) to (8), wherein the control unit is also capable of stopping light emission of rows other than the predetermined row that maintain the pixel signal. (10) The display device according to any one of (1) to (9), wherein the control unit is also capable of performing a second drive in which, in response to updating of the pixel signals, the image signals to be held in the pixels arranged in one row of the display unit are also held in the pixels arranged in one row adjacent to the one row, thereby causing the pixels to emit light.(11) The display device according to (10), wherein the control unit is capable of changing the combination of two consecutive rows of the display unit in response to updating of the image signal, and is also capable of performing a third drive in which the image signal held in the pixels arranged in one of the two rows is held in the pixels arranged in the other of the two rows, causing the pixels to emit light. (12) The display device according to (11), wherein the control unit is capable of changing the combination of the two consecutive rows between a combination with an upper row and a combination with a lower row in response to updating of the image signal. (13) The display device according to (11) or (12), wherein the control unit is capable of selecting any of the first drive, the second drive, and the third drive. (14) The display device according to any one of (1) to (13), wherein the control unit, in the first drive, maintains the image signals of odd-numbered rows for the image signal obtained by thinning out the image signals of odd-numbered rows, and maintains the image signals of even-numbered rows for the image signal obtained by thinning out the image signals of even-numbered rows. (15) The display device according to any one of (1) to (13), wherein, in the first driving, the control unit maintains the image signals of odd-numbered rows for one of the two chronologically consecutive image signals, and maintains the image signals of even-numbered rows for the other image signal. (16) The display device according to any one of (1) to (13), wherein, in the first driving, the control unit maintains the image signals of odd-numbered rows for the image signals in which the image signals of even-numbered rows are assigned as the same image signal to two consecutive rows, and maintains the image signals of even-numbered rows for the image signals in which the image signals of odd-numbered rows are assigned as the same image signal to two consecutive rows. (17) The display device according to any one of (1) to (16), wherein the control unit is also capable of updating the pixel signals of multiple pixels in the same row in response to updating the image signals, and maintaining the pixel signals of pixels other than the multiple pixels in the same row, to perform driving to cause the pixels to emit light. (18) The display device according to (17), wherein the pixel generates the plurality of image signals such that the interval between light emission periods of the plurality of image signals is shorter than a predetermined period.(19) The display device according to any one of (1) to (18), comprising: a first transistor that controls a current supplied to a light-emitting element in accordance with a voltage supplied to a first terminal, a first capacitance that holds the voltage supplied to the first terminal, a second transistor that samples a signal voltage based on the image signal of an image signal line, a second capacitance that holds the signal voltage sampled by the second transistor as the pixel signal, and a third transistor that connects the second capacitance and the first capacitance and sets a voltage corresponding to the signal voltage to the first capacitance by transferring charge accumulated in the second capacitance to the first capacitance. (20) A display method for a display device having a display unit in which pixels that emit light in accordance with pixel signals held based on an image signal are arranged in a matrix, the display method comprising: updating the pixel signals of predetermined rows in accordance with updating the image signal; maintaining the pixel signals of rows excluding the predetermined row; and performing a first drive that causes the pixels to emit light by line sequential scanning.

[0294] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0295] 1: display device, 6: control unit, 10: display unit, 201: pixels, g10, g10a, g10c, g12, g12a, g12c, g18: image signals

Claims

1. A display device comprising: a display unit in which pixels that emit light according to pixel signals held based on an image signal are arranged in a matrix; and a control unit that executes a first drive that updates the pixel signals of a predetermined row in response to an update of the image signal, maintains the pixel signals of rows other than the predetermined row, and causes the pixels to emit light by sequentially scanning the rows.

2. The display device according to claim 1, wherein the control unit changes the row for updating the pixel signal in response to updating of the image signal.

3. The display device according to claim 1, wherein the control unit updates the pixel signals after completing predetermined processing of pixels in a row for which the pixel signals are to be updated.

4. The display device according to claim 3, wherein the control unit stops the predetermined processing of pixels in a row where the pixel signal is maintained.

5. The display device according to claim 3, wherein the control unit starts the predetermined processing of pixels in a row in which the pixel signal is to be updated before updating the image signal.

6. The display device according to claim 3, wherein in the row sequential scanning, the period from the start to the end of scanning per row of the display unit corresponds to one horizontal period, and the control unit continues the specified processing for a period longer than the one horizontal period, and updates the pixel signal after the specified processing is completed.

7. The display device according to claim 3, wherein the pixel has a light-emitting element and a first transistor that controls a current supplied to the light-emitting element, and the predetermined process is a process of correcting a threshold value of the first transistor.

8. The display device according to claim 1, wherein the control unit changes the pixel signals every n rows, where n is a natural number, in response to updating of the image signals.

9. The display device according to claim 1, wherein the control unit is also capable of stopping light emission of rows that maintain the pixel signals of rows other than the predetermined row.

10. The display device according to claim 1, wherein the control unit is also capable of performing a second drive in which, in response to updating of the pixel signals, the image signals held by the pixels arranged in one row of the display unit are also held by the pixels arranged in one row adjacent to the one row, causing the pixels to emit light.

11. The display device according to claim 10, wherein the control unit is capable of changing the combination of two consecutive rows of the display unit in response to updating of the image signal, and also performing a third drive in which the image signal held by the pixels arranged in one of the two rows is held by the pixels arranged in the other of the two rows, causing the pixels to emit light.

12. The display device according to claim 11, wherein the control unit changes the combination of the two consecutive rows between a combination with the upper row and a combination with the lower row in turn in response to updating of the image signal.

13. The display device according to claim 11, wherein the control unit is capable of selecting one of the first drive, the second drive, and the third drive.

14. The display device according to claim 1, wherein, in the first driving mode, the control unit maintains the image signals of odd-numbered rows for the image signals obtained by thinning out the image signals of odd-numbered rows, and maintains the image signals of even-numbered rows for the image signals obtained by thinning out the image signals of even-numbered rows.

15. The display device according to claim 1, wherein, in the first driving mode, the control unit maintains the image signals of odd-numbered rows for one of the two chronologically consecutive image signals, and maintains the image signals of even-numbered rows for the other image signal.

16. The display device according to claim 1, wherein, in the first drive, the control unit maintains the image signals of odd-numbered rows for the image signals in which the image signals of even-numbered rows are assigned as the same image signal to two consecutive rows, and maintains the image signals of even-numbered rows for the image signals in which the image signals of odd-numbered rows are assigned as the same image signal to two consecutive rows.

17. The display device according to claim 1, wherein the control unit is also capable of updating the pixel signals of multiple pixels in the same row in response to updating the image signal, and maintaining the pixel signals of pixels other than the multiple pixels in the same row, thereby performing driving to cause the pixels to emit light.

18. The display device according to claim 17, wherein the pixel generates the plurality of image signals so that the interval between the light emission periods of the plurality of image signals is less than a predetermined period.

19. The display device according to claim 1, wherein the pixel comprises: a first transistor that controls a current supplied to a light-emitting element in accordance with a voltage supplied to a first terminal; a first capacitor that holds the voltage supplied to the first terminal; a second transistor that samples a signal voltage based on the image signal of an image signal line; a second capacitor that holds the signal voltage sampled by the second transistor as the pixel signal; and a third transistor that connects the second capacitor and the first capacitor and transfers charge accumulated in the second capacitor to the first capacitor, thereby setting a voltage corresponding to the signal voltage in the first capacitor.

20. A display method for a display device having a display unit in which pixels that emit light according to pixel signals held based on an image signal are arranged in a matrix, the display method comprising: updating the pixel signals of a predetermined row in response to an update of the image signal; maintaining the pixel signals of rows other than the predetermined row; and executing a first drive that causes the pixels to emit light by line-sequential scanning.

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