Semiconductor device and water jacket
The water jacket with widened protrusion spacing in perpendicular directions addresses the pressure loss issue in smaller semiconductor modules, improving heat dissipation efficiency by allowing non-uniform cooling water flow.
Patent Information
- Application Number
- PCT/JP2025/016875
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-06-03
- Filing Date
- 2025-05-08
- Publication Date
- 2025-12-11
AI Technical Summary
As semiconductor modules become smaller, the cross-sectional area of the cooling water flow path becomes smaller, leading to significantly increased pressure loss due to protrusions in the water jacket, which hampers effective heat dissipation performance.
The water jacket is designed with protrusions arranged in two perpendicular directions, and the spacing between these protrusions is widened in certain areas to reduce pressure loss while maintaining or improving heat dissipation performance.
This configuration reduces pressure loss of cooling water while enhancing heat dissipation performance by allowing non-uniform flow and increasing flow rate near the heat dissipation base, without significantly increasing thermal resistance.
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Figure JP2025016875_11122025_PF_FP_ABST
Abstract
Description
Semiconductor device and water jacket
[0001] The present invention relates to a semiconductor device and a water jacket.
[0002] In semiconductor devices used in power conversion devices such as inverter devices, a method is known in which a water jacket is used to flow cooling water between a heat dissipation base to which the substrate is joined in order to dissipate heat from a semiconductor element mounted on the substrate (see, for example, Patent Documents 1 to 4).When the heat dissipation base is flat, the water jacket may be provided with a protrusion that protrudes toward the heat dissipation base.
[0003] JP 2005-252151 A JP 2023-135202 A JP 2023-023518 A JP 2014-197637 A
[0004] Incidentally, it is desirable that the above-mentioned protrusions protruding from the water jacket are arranged in two mutually perpendicular directions in order to improve the heat dissipation performance of the semiconductor element by causing the cooling water to flow unevenly and increasing the flow rate near the heat dissipation base.
[0005] However, as semiconductor modules become smaller, the cross-sectional area of the cooling water flow path becomes smaller, and the pressure loss of the cooling water due to the protrusions becomes significantly larger.
[0006] An object of the present invention is to provide a semiconductor device and a water jacket that can reduce pressure loss of cooling water while improving the heat dissipation performance of a semiconductor element.
[0007] In one aspect, a semiconductor device comprises a semiconductor element, a substrate on which the semiconductor element is mounted, a heat dissipation base joined to the substrate, and a water jacket for flowing cooling water between the surface of the heat dissipation base opposite the substrate, wherein the water jacket has a wall portion parallel to the heat dissipation base and a plurality of protrusions arranged in a first direction and a second direction perpendicular to the thickness direction of the semiconductor element and perpendicular to each other, and protruding from the wall portion toward the heat dissipation base, and wherein the spacing between the plurality of protrusions in at least one of the first direction and the second direction is wider in some parts.
[0008] In another aspect, the water jacket is a water jacket for flowing cooling water between a surface of a heat dissipation base joined to a substrate on which a semiconductor element is mounted and the surface opposite the substrate, and has a wall portion arranged parallel to the heat dissipation base, and a plurality of protrusions arranged in first and second directions perpendicular to the thickness direction of the semiconductor element and perpendicular to each other, and protruding from the wall portion toward the heat dissipation base, and the spacing between the plurality of protrusions in at least one of the first and second directions is widened in some parts.
[0009] According to this aspect, it is possible to reduce pressure loss of the cooling water while improving the heat dissipation performance of the semiconductor element.
[0010] FIG. 1 is a front view showing the internal structure of a semiconductor device in one embodiment; FIG. 2 is a plan view showing a water jacket in a comparative example (protrusion occupancy rate 100%); FIG. 3 is a plan view showing a water jacket in one embodiment (protrusion occupancy rate 40%); FIG. 4 is a plan view showing a water jacket in one embodiment (protrusion occupancy rate 35%); FIG. 5 is a plan view showing a water jacket in one embodiment (protrusion occupancy rate 15%); and FIG. 6 is a plan view showing a water jacket in a comparative example (no protrusions: protrusion occupancy rate 0%). FIG. 7 is a graph showing the relationship between protrusion occupancy rate and pressure loss and thermal resistance of cooling water. FIG. 8 is a graph showing the relationship between protrusion occupancy rate and flow velocity of cooling water. FIG. 9 is a graph showing the relationship between flow velocity of cooling water and thermal resistance. FIG. 10 is a front view showing the tip shape of protrusions in one embodiment; and FIG. 11 is a front view showing the tip shape of protrusions in a modified example of one embodiment.
[0011] A semiconductor device and a water jacket according to an embodiment of the present invention will be described below with reference to the drawings. Note that the present invention is not limited to the embodiment described below, and can be modified appropriately within the scope of the present invention.
[0012] FIG. 1 is a front view showing the internal structure of a semiconductor device 100 according to an embodiment.
[0013] 2A to 2E are plan views showing the water jacket 110 for each protrusion occupancy ratio.
[0014] 1 to 2E and FIGS. 6 and 7 (described later), the thickness direction Dt of the semiconductor element 10 is defined as the Z direction, and of the X direction (first direction D1) and Y direction (second direction D2) that are perpendicular to the Z direction and perpendicular to each other, the first direction D1 in which the cooling water W flows is defined as the positive X direction. In some cases, the X direction may be referred to as the left-right direction, the Y direction as the front-back direction, and the Z direction as the up-down direction. These directions are terms used for convenience of explanation, and the corresponding relationships between the X direction, Y direction, and Z direction change depending on the mounting orientation of the semiconductor device 100.
[0015] The semiconductor device 100 according to the present embodiment is a power semiconductor device that is applied to a power conversion device such as a power control unit, and constitutes an inverter circuit. The semiconductor device 100 and the water jacket 110 can be used for any purpose, but may be used, for example, as an inverter device for an in-vehicle or industrial motor.
[0016] 1 includes a semiconductor module 1 and a water jacket 110. The semiconductor module 1 includes, for example, six semiconductor elements 10, for example, three laminated substrates 20, and a heat dissipation base 30.
[0017] 1 is mounted on a laminated substrate 20 (circuit board 22) with a bonding material S1, such as solder, and is connected to another circuit board 22 with a conductor wire, a metal wiring board, etc. The semiconductor element 10 is formed in a square or rectangular shape in plan view using a semiconductor substrate made of, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), diamond, or the like.
[0018] The semiconductor element 10 may be a switching element such as an insulated gate bipolar transistor (IGBT) or a power metal oxide semiconductor field effect transistor (MOSFET), or a diode such as a free wheeling diode (FWD). The switching element and the diode may be connected in anti-parallel. Alternatively, the semiconductor element 10 may be a reverse conducting (RC) IGBT element in which an IGBT and an FWD are integrated, a power MOSFET element, or a reverse blocking (RB) IGBT element having sufficient withstand voltage against reverse bias.
[0019] Two semiconductor elements 10 are mounted on each of the three laminated substrates 20. The laminated substrate 20 is an example of a substrate on which the semiconductor elements 10 are mounted. The laminated substrate 20 is formed, for example, of a DCB (Direct Copper Bonding) substrate, an AMB (Active Metal Brazing) substrate, or a metal-based substrate. The laminated substrate 20 is formed, for example, in a rectangular shape when viewed from above. Each of the two laminated substrates 20 has an insulating plate 21, a circuit board 22, and a heat sink 23.
[0020] The insulating plate 21 is made of, for example, aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), aluminum oxide and zirconium oxide (ZrO 2 The insulating plate 21 is formed of a ceramic material such as a composite material with a ceramic material, a resin material such as epoxy, or a sealing material such as an epoxy resin material using a ceramic material as a filler. The insulating plate 21 may also be called an insulating layer or an insulating film.
[0021] The circuit board 22 is formed on the upper surface of the insulating plate 21. The number of circuit boards 22 formed on the upper surface of a single insulating plate 21 may be any number equal to or greater than one. The circuit board 22 is a metal layer such as copper foil, and, for example, a plurality of circuit boards 22 are formed in the shape of islands on the insulating plate 21 while being electrically insulated from one another. The circuit board 22 may also be called a circuit pattern, a circuit layer, a wiring board, a wiring pattern, a wiring layer, etc.
[0022] The heat sink 23 is formed on the lower surface of the insulating plate 21. The heat sink 23 is preferably formed from a metal plate with good thermal conductivity, such as copper or aluminum. The heat sink 23 is joined to the upper surface 30a of the heat sink base 30 with a joining material S2, such as solder. The heat sink 23 may also be called a heat dissipation layer.
[0023] As described above, the six semiconductor elements 10 and three laminated substrates 20 arranged on the heat dissipation base 30 constitute three sets of semiconductor units, each set consisting of two semiconductor elements 10 and one laminated substrate 20, forming, for example, a three-phase inverter circuit. However, the number and configuration of the semiconductor elements 10 and the laminated substrates 20 are not particularly limited. Furthermore, although the six semiconductor elements 10 and the three laminated substrates 20 are arranged in a straight line along the X direction, they may also be arranged in a straight line along the Y direction, or may be arranged in multiple rows in the X and Y directions.
[0024] A rectangular frame-shaped resin case is placed on top of the heat dissipation base 30 so as to surround the six semiconductor elements 10 and the three laminated substrates 20, and this case is filled with a sealing material (e.g., resin or gel) so as to cover the six semiconductor elements 10 and the three laminated substrates 20. This sealing material may be formed by transfer molding or potting.
[0025] The heat dissipation base 30 is made of, for example, copper or aluminum. The heat dissipation base 30 preferably has a rectangular flat plate shape extending in a first direction D1 (X direction) and a second direction D2 (Y direction) perpendicular to the thickness direction Dt of the semiconductor element 10. In this case, the upper surface 30a and the lower surface 30b of the heat dissipation base 30 have a flat shape. As an example, as shown by the two-dot chain lines (imaginary lines) in Figures 2A to 2E, the heat dissipation base 30 extends in the first direction D1 by a length slightly shorter than the water jacket 110 and extends in the second direction D2 by the same length as the water jacket 110.
[0026] As described above, the laminated substrate 20 (heat dissipation plate 23) is bonded to the upper surface 30a of the heat dissipation base 30 by the bonding material S2. The lower surface 30b of the heat dissipation base 30 is the surface opposite to the laminated substrate 20, and cooling water W flows between the lower surface 30b and the water jacket 110 described below. Note that, although the lower surface 30b of the heat dissipation base 30 has a planar shape (flat surface) as described above, it may be provided with protrusions similar to the protrusions 112 of the water jacket 110 described below.
[0027] The water jacket 110 is attached to the lower part of the heat dissipation base 30 by fastening screws, for example. The water jacket 110 is provided, for example, in an inverter case of an inverter device.
[0028] The water jacket 110 is made of a die-cast material such as aluminum alloy (ADC12). The water jacket 110 has a rectangular parallelepiped shape with an opening at the top, and coolant W flows inside. The coolant W flows in a first direction D1 (positive side in the X direction) and transfers heat from the heat dissipation base 30. The coolant W is a liquid such as water containing additives such as antifreeze, anti-rust agents, and antioxidants. To ensure watertightness inside the water jacket 110, a seal such as an O-ring may be disposed between the periphery of the upper surface of the water jacket 110 and the periphery of the lower surface 30b of the heat dissipation base 30.
[0029] A wall 111 extending in the X and Y directions parallel to the heat dissipation base 30 is provided inside the water jacket 110. This wall 111 is provided at a position that rises on the positive side in the Z direction (toward the heat dissipation base 30) between an inlet passage 113 provided at the end of the water jacket 110 on the negative side in the X direction and an outlet passage 114 provided at the end of the water jacket 110 on the positive side in the X direction. The wall 111 is desirably provided at a position close to the heat dissipation base 30 so that the cooling water W flows near the underside 30b of the heat dissipation base 30.
[0030] The wall portion 111 is provided with a plurality of protrusions 112 that protrude toward the heat dissipation base 30 (positive side in the Z direction). As shown in FIG. 2A and other figures, these protrusions 112 are arranged in each of the first direction D1 (X direction) and the second direction D2 (Y direction). The protrusions 112 are, for example, formed integrally with the wall portion 111. The length of the protrusions 112 in the Z direction is preferably at least half the length of the distance between the heat dissipation base 30 (lower surface 30b) and the wall portion 111 (the flow path of the cooling water W) in the Z direction. The protrusions 112 may also be called convex portions, protruding portions, bosses, pin fins, etc.
[0031] As shown in Fig. 6, the protrusion 112 preferably has a cylindrical shape with a hemispherical tip 112a on the heat dissipation base 30 side. Furthermore, as shown in a modified example in Fig. 7, the protrusion 122 may have a cylindrical shape with a tapered tip 122a on the heat dissipation base 30 side. While the protrusion 122 shown in Fig. 7 has a cylindrical shape with the upper end (the end on the positive side in the Z direction) cut by an oblique plane, the protrusion 122 may have a shape cut by an oblique plane over the entire Z direction. Furthermore, the cut oblique surface of the protrusion 122 preferably faces the negative side in the X direction, but may face in another direction.
[0032] The protrusion 112 (protrusion 122) has a cylindrical shape, and therefore has a circular shape when viewed in the thickness direction Dt (in a plan view) of the semiconductor element 10. The protrusion 112 may have an elliptical shape when viewed in the thickness direction Dt, but is preferably a perfect circle. Note that the protrusion 112 may have another shape, such as a polygonal shape, when viewed in the thickness direction Dt.
[0033] 2A (Comparative Example), a protrusion occupancy rate (number of protrusions) of 100% indicates that the protrusions 112 are arranged in a staggered pattern across the entire wall portion 111 facing the heat dissipation base 30, with five protrusions 112 evenly spaced in the second direction D2 and 16 rows of the protrusions 112 arranged in the second direction D2 and equally spaced a length L1 in the first direction D1. In other words, a protrusion occupancy rate (number of protrusions) of 100% indicates that the multiple protrusions 112 are arranged evenly in both the first direction D1 and the second direction D2 across the entire wall portion 111 facing the heat dissipation base 30, without spreading out in some areas. The gaps between the protrusions 112 in the first direction D1 and the gaps between the protrusions 112 in the second direction D2 are narrower than the diameters (lengths in the X and Y directions) of the protrusions 112. That is, each of the length L1, which is the spacing in the first direction D1, and the length L2, which is the spacing in the second direction D2, is longer than the diameter of the protrusions 112 and shorter than twice the diameter of the protrusions 112. Furthermore, although it is desirable that the protrusions 112 be arranged in a staggered pattern, the positions in the second direction D2 (or the first direction D1) of two protrusions 112 adjacent to each other in the first direction D1 (or the second direction D2) may be the same.
[0034] 2A, the region (wall portion 111) where the protrusions 112 are provided includes regions directly below the four central semiconductor elements 10 of the six semiconductor elements 10 (i.e., positions in the first direction D1 and the second direction D2 that are the same as those of the four semiconductor elements 10). Note that in FIG. 2A and FIGS. 2B to 2E described below, the positions of the semiconductor elements 10 are indicated by two-dot chain lines (imaginary lines).
[0035] In the example of a protrusion occupancy rate of 40% shown in Fig. 2B, 60% of the protrusions 112 out of the above-mentioned 100% protrusion occupancy rate are removed, resulting in 40% of the number of protrusions 112 (e.g., 32) compared to the example of a 100% protrusion occupancy rate. Note that in Fig. 2B and Figs. 2C to 2D described below, the positions of the protrusions 112 that are removed from the state of a 100% protrusion occupancy rate shown in Fig. 2A are indicated by dotted lines.
[0036] 2A from the upstream side in the first direction D1 (the negative side in the X direction), the protrusions 112 are missing from the third, fourth, fifth, eighth, ninth, twelfth, and thirteenth rows (positions different from directly below the semiconductor elements 10 in the first direction D1) and the sixteenth row (the same position as directly below the semiconductor elements 10 in the first direction D1). As a result, the protrusions 112 are arranged so that there are two rows that overlap with each semiconductor element 10 (the semiconductor elements 10 that overlap with the wall portions 111 in a planar view), and the interval in the first direction D1 between the second row and the sixth row, which include positions (the third to fifth rows) that are different from directly below the semiconductor elements 10, is increased to a length L1a (length L1a>length L1, i.e., four times length L1). Furthermore, between the seventh and tenth rows, which include positions (eighth and ninth rows) that are not directly below the semiconductor elements 10, and between the eleventh and fourteenth rows, which include positions (twelfth and thirteenth rows) that are not directly below the semiconductor elements 10, the spacing in the first direction D1 is increased to a length L1b (length L1a > length L1, i.e., three times length L1). That is, the multiple protrusions 112 are arranged so as to overlap with each semiconductor element 10 (semiconductor element 10 that overlaps with wall portion 111 in plan view) in plan view.
[0037] In the example shown in FIG. 2B , two of the five protrusions 112 are missing in the first, seventh, eleventh, and fifteenth rows. As a result, the spacing in the second direction D2 between the second and fourth protrusions 112 from the negative Y-direction side is increased to a length L2a. The spacing (length L2) between the protrusions 112 in the second direction D2 may also be increased at a position different from the semiconductor element 10. The spacing (lengths L1 and L2) between the protrusions 112 may be increased in at least one of the first direction D1 and the second direction D2. At least one of the multiple protrusions 112 aligned along the second direction D2 overlaps with the semiconductor element 10 in a planar view.
[0038] In the example of a protrusion occupancy rate of 35% shown in Fig. 2C, 65% of the protrusions 112 are removed from the above-mentioned 100% protrusion occupancy rate, resulting in 35% (e.g., 28) of the protrusions 112 provided compared to the example of a 100% protrusion occupancy rate. In the example shown in Fig. 2C, one protrusion 112 is removed from each of the second, sixth, tenth, and fourteenth rows compared to the example of a 40% protrusion occupancy rate shown in Fig. 2B.
[0039] In the example of a protrusion occupancy rate of 15% shown in Fig. 2D, the number of protrusions 112 is 15% (e.g., 12) compared to the example of a protrusion occupancy rate of 100%, by removing 85% of the protrusions 112 from the above-mentioned 100% protrusion occupancy rate. In the example shown in Fig. 2D, two more protrusions 112 are removed from each of the first, second, sixth, seventh, tenth, eleventh, fourteenth, and fifteenth rows than in the example of a protrusion occupancy rate of 35% shown in Fig. 2C.
[0040] In the comparative example shown in FIG. 2E where the protrusion occupancy rate is 0%, not a single protrusion 112 is provided on the wall portion 111.
[0041] 5, when the protrusion occupancy rate is 0% (see FIG. 2E), the flow velocity of the cooling water W flowing through the water jacket 110 is below 1 m / s, as represented by the four diamonds. On the other hand, when the protrusion occupancy rate is 100% (see FIG. 2A), the flow velocity of the cooling water W exceeds 2.5 m / s, as represented by the four circles. Each of the four diamonds and four circles represents the average flow velocity directly below the central four semiconductor elements 10 of the six semiconductor elements 10 (at the midpoint between the heat dissipation base 30 and the protrusions 112).
[0042] In this way, by providing the protrusions 112 on the wall portion 111, it can be said that the flow rate of the cooling water W in the vicinity of the heat dissipation base 30 (at the intermediate height between the heat dissipation base 30 and the protrusions 112) can be increased.
[0043] As a result, the thermal resistance Rth [°C / W] from the bonding material S1 that bonds the semiconductor element 10 and the laminated substrate 20 to the cooling water W when the protrusion occupancy rate is 100% (see FIG. 2A) is significantly lower than when the protrusion occupancy rate is 0% (see FIG. 2E). This can be attributed to the fact that the faster the flow rate, the more the thermal resistance Rth can be reduced.
[0044] Next, as shown in Figure 4, the flow velocities at the four locations (average flow velocities at the mid-height between the heat dissipation base 30 and the protrusions 112 directly below the four central semiconductor elements 10) for protrusion occupancy rates of 100% (see Figure 2A), 80%, 40% (see Figure 2B), 35% (see Figure 2C), 20%, and 0% (see Figure 2E) decrease gradually as the protrusion occupancy rate decreases from 100% to 40%, but decrease significantly when the protrusion occupancy rate falls below 40%.
[0045] Therefore, as shown in FIG. 3 , the average thermal resistance Rth (right axis) at each of the four locations where the protrusion occupancy rate is 100% (see FIG. 2A ), 80%, 40% (see FIG. 2B ), 35% (see FIG. 2C ), and 0% (see FIG. 2E ) is 0.246 [°C / W] when the protrusion occupancy rate is 100%, and 0.395 [°C / W] when the protrusion occupancy rate is 0%, but while it increases gradually as the protrusion occupancy rate decreases from 100% to 40%, it increases significantly when the protrusion occupancy rate falls below 40%.
[0046] The pressure loss of the cooling water W (the pressure difference between the inlet path 113 and the outlet path 114) is 6.8 kPa when the protrusion occupancy rate is 0%, and when the protrusion occupancy rate is 100%, the protrusions 112 obstruct the flow of the cooling water W, so the pressure drops to 27.9 kPa, which is about four times as much. However, there is no significant difference between when the protrusion occupancy rate decreases from 100% to 40% and when the protrusion occupancy rate falls below 40%.
[0047] From the above, it can be seen that while reducing the protrusion occupancy rate from 100% to 40%, the increase in thermal resistance Rth can be made gradual while reducing the pressure loss of the cooling water W. Furthermore, when the protrusion occupancy rate is reduced to less than 40%, the increase in thermal resistance Rth becomes significant. Therefore, in order to reduce the pressure loss of the cooling water W while improving the heat dissipation performance of the semiconductor element 10 without incurring a significant increase in thermal resistance Rth, it is particularly desirable to reduce the protrusion occupancy rate from 100% to 40%. However, since a protrusion occupancy rate of less than 40% can reduce the pressure loss more than a protrusion occupancy rate of 40% or more, it can also be said that reducing the protrusion occupancy rate to less than 40% is effective from the perspective of reducing pressure loss.
[0048] Furthermore, since the protrusions 112 are arranged in each of the first direction D1 and the second direction D2, it can be said that the cooling water W can flow non-uniformly and the flow rate can be increased near the lower surface 30b of the heat dissipation base 30. Moreover, as described above, since the intervals (lengths L1, L2) between the multiple protrusions 112 in (at least one of) the first direction D1 and the second direction D2 are partially widened (lengths L1a, L1b, L2a), it can be said that the number of protrusions 112 is reduced, which can reduce pressure loss of the cooling water W and cause the cooling water W to flow more non-uniformly, compared to when the intervals (lengths L1, L2) are constant.
[0049] As described above, in this embodiment, the semiconductor device 100 includes the semiconductor element 10, the laminated substrate 20, which is an example of a substrate on which the semiconductor element 10 is mounted, the heat dissipation base 30 joined to the laminated substrate 20, and the water jacket 110 for flowing cooling water W between the surface (lower surface 30b) of the heat dissipation base 30 opposite the laminated substrate 20. The water jacket 110 has a wall 111 provided parallel to the heat dissipation base 30, and a plurality of protrusions 112 arranged in each of a first direction D1 and a second direction D2 perpendicular to the thickness direction Dt of the semiconductor element 10 and perpendicular to each other, and protruding from the wall 111 toward the heat dissipation base 30. The spacing (lengths L1, L2) between the plurality of protrusions 112 in at least one of the first direction D1 and the second direction D2 is partially widened (lengths L1a, L1b, L2a).
[0050] By arranging the protrusions 112 in the first direction D1 and the second direction D2 in this manner, the cooling water W can flow non-uniformly between the lower surface 30b of the heat dissipation base 30 and the wall portion 111, and the flow rate can be increased near the lower surface 30b of the heat dissipation base 30, compared to an embodiment in which, for example, a plurality of band-shaped or linear members extending in the second direction D2 in a plan view are arranged at intervals in the first direction D1. Furthermore, by partially widening the spacing (lengths L1, L2) between the plurality of protrusions 112 in at least one of the first direction D1 and the second direction D2 (lengths L1a, L1b, L2a), the number of protrusions 112 can be reduced, thereby reducing pressure loss of the cooling water W and making the flow of the cooling water W more non-uniform, thereby improving the heat dissipation performance of the heat dissipation base 30, compared to an embodiment in which the spacing is constant. Therefore, according to this embodiment, the pressure loss of the cooling water W can be reduced while improving the heat dissipation performance of the semiconductor element 10. Furthermore, with a simple configuration in which the spacing (lengths L1, L2) between the multiple protrusions 112 is widened in some places, it is possible to reduce the pressure loss of the cooling water W while improving the heat dissipation performance of the semiconductor element 10, as described above, without complicating the structure of the water jacket 110 or the structure of the flow path of the cooling water W inside it.
[0051] Furthermore, in this embodiment, the number of protrusions 112 is 40% or more but less than 100% of the number of protrusions 112 arranged in each of the first direction D1 and the second direction D2 over the entire area of the wall portion 111 facing the heat dissipation base 30 compared to when the spacing between the protrusions 112 is not widened in the above-mentioned part and the protrusion occupancy rate is 100% in Figure 2A.
[0052] As a result, as shown in FIG. 3 , when the protrusion occupancy rate is reduced to less than 40%, the increase in thermal resistance Rth becomes significant, but while the protrusion occupancy rate is reduced from 100% to 40%, the increase in thermal resistance Rth can be made gradual while reducing the pressure loss of the cooling water W.
[0053] In this embodiment, the spacing (length L1) between the multiple protrusions 112 is wider at positions in the first direction D1 (an example of at least one of the first direction D1 and the second direction D2) that are different from the positions of the semiconductor elements 10 (i.e., positions corresponding to the third, fourth, fifth, eighth, ninth, twelfth, and thirteenth rows of the protrusions 112 in FIG. 2A counting from the upstream side in the first direction D1) (lengths L1a and L1b shown in FIG. 2B). That is, the multiple protrusions 112 are arranged so as to overlap with each semiconductor element 10 (the semiconductor element 10 that overlaps with the wall portion 111 in a plan view).
[0054] This increases the flow rate near the lower surface 30b of the heat dissipation base 30 directly below the semiconductor element 10. This further improves the heat dissipation performance of the semiconductor element 10.
[0055] In this embodiment, as shown in Fig. 6, the tips 112a of the multiple protrusions 112 on the heat dissipation base 30 side are hemispherical. As shown in Figs. 2B to 2D, the multiple protrusions 112 are circular when viewed in the thickness direction Dt of the semiconductor element 10. In a modification of this embodiment, as shown in Fig. 7, the tips 122a of the multiple protrusions 122 on the heat dissipation base 30 side are tapered.
[0056] With these configurations, the cooling water W is guided along the tips 112a, 122a of the protrusions 112, 122 in the positive Z direction, thereby increasing the flow rate near the lower surface 30b of the heat dissipation base 30. This further improves the heat dissipation performance of the semiconductor element 10. Furthermore, when the tips 112a, 122a of the protrusions 112, 122 are hemispherical or tapered, the pressure loss can also be reduced by reducing the proportion of the protrusions 112, 122 that account for the flow path cross section, compared to cylindrical protrusions of the same length in the Z direction.
[0057] Below, some of the inventions described in the specification and drawings of this application will be additionally noted.
[0058] <Supplementary Note 1> A semiconductor device comprising: a semiconductor element; a substrate on which the semiconductor element is mounted; a heat dissipation base joined to the substrate; and a water jacket for flowing cooling water between the surface of the heat dissipation base opposite the substrate, wherein the water jacket has a wall portion provided parallel to the heat dissipation base; and a plurality of protrusions protruding from the wall portion toward the heat dissipation base and arranged in a first direction and a second direction that are perpendicular to the thickness direction of the semiconductor element and perpendicular to each other, and wherein the spacing between the plurality of protrusions in at least one of the first direction and the second direction is widened in some parts.
[0059] <Supplementary Note 2> The semiconductor device described in Supplementary Note 1, characterized in that the number of the protrusions is 40% or more but less than 100% of that in a case where the spacing between the protrusions is not wider in the portion of the wall portion facing the heat dissipation base and the spacing between the protrusions is uniformly spaced in each of the first direction and the second direction.
[0060] <Supplementary Note 3> The semiconductor device according to Supplementary Note 1 or 2, wherein the spacing between the plurality of protrusions in at least one of the first direction and the second direction is wider at a position different from the semiconductor element.
[0061] <Supplementary Note 4> The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein the tips of the plurality of protrusions on the heat dissipation base side are hemispherical.
[0062] <Supplementary Note 5> The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein the tips of the plurality of protrusions on the heat dissipation base side are tapered.
[0063] <Supplementary Note 6> The semiconductor device according to any one of Supplementary Notes 1 to 5, wherein the plurality of protrusions are circular when viewed in the thickness direction of the semiconductor element.
[0064] <Supplementary Note 7> A water jacket for flowing cooling water between a substrate on which a semiconductor element is mounted and a surface of a heat dissipation base joined to the substrate on the opposite side of the substrate, the water jacket having a wall portion provided parallel to the heat dissipation base, and a plurality of protrusions protruding from the wall portion toward the heat dissipation base and arranged in a first direction and a second direction that are perpendicular to the thickness direction of the semiconductor element and perpendicular to each other, and wherein the spacing between the plurality of protrusions in at least one of the first direction and the second direction is wider in some parts.
[0065] As described above, the present invention has the effect of being able to reduce pressure loss of cooling water in semiconductor devices and water jackets while improving the heat dissipation performance of semiconductor elements, and is particularly useful for inverter devices for industrial or electrical equipment.
[0066] This application is based on Japanese Patent Application No. 2024-090145, filed on June 3, 2024, the contents of which are incorporated herein in their entirety.
[0067] REFERENCE SIGNS LIST 1 semiconductor module 10 semiconductor element 20 laminated substrate (substrate) 21 insulating plate 22 circuit board 23 heat sink 30 heat sink base 30a upper surface 30b lower surface 100 semiconductor device 110 water jacket 111 wall portion 112 projection 112a tip 113 inlet path 114 outlet path 122 projection 122a tip Dt thickness direction D1 first direction D2 second direction S1, S2 bonding material W cooling water
Claims
1. A semiconductor device comprising: a semiconductor element; a substrate on which the semiconductor element is mounted; a heat dissipation base joined to the substrate; and a water jacket for flowing cooling water between the surface of the heat dissipation base opposite the substrate, wherein the water jacket has a wall portion parallel to the heat dissipation base and a plurality of protrusions arranged in first and second directions perpendicular to the thickness direction of the semiconductor element and perpendicular to each other, protruding from the wall portion toward the heat dissipation base, and wherein the spacing between the plurality of protrusions in at least one of the first and second directions is wider in some places.
2. The semiconductor device according to claim 1, characterized in that the number of the protrusions is 40% or more but less than 100% of that in the case where the spacing between the protrusions is not wider in the first direction and the second direction over the entire surface of the wall portion facing the heat dissipation base and the spacing between the protrusions is not wider in the part but is arranged at equal intervals.
3. The semiconductor device according to claim 1 or 2, characterized in that the spacing between the plurality of protrusions in at least one of the first direction and the second direction is wider at a position different from that of the semiconductor element.
4. The semiconductor device according to claim 1, wherein the tips of the plurality of protrusions on the heat dissipation base side are hemispherical.
5. The semiconductor device according to claim 1, wherein the tips of the plurality of protrusions on the heat dissipation base side are tapered.
6. The semiconductor device according to claim 1, wherein the plurality of protrusions are circular when viewed in the thickness direction of the semiconductor element.
7. A water jacket for flowing cooling water between a substrate on which a semiconductor element is mounted and a surface of a heat dissipation base joined to the substrate on the opposite side of the substrate, the water jacket having a wall portion provided parallel to the heat dissipation base, and a plurality of protrusions arranged in first and second directions perpendicular to the thickness direction of the semiconductor element and perpendicular to each other, protruding from the wall portion toward the heat dissipation base, wherein the spacing between the plurality of protrusions in at least one of the first and second directions is wider in some places.
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