Printed wiring board

Abstract

A printed wiring board 10 comprises: an insulating substrate 2a which has a surface 2a1 and to which a through hole 2e is provided; a conductor layer 2b which is provided on the surface 2a1; and a conductive through-via 2d which is provided in the through hole 2e and is electrically connected to the conductor layer 2b. The conductor layer 2b includes: a surface portion 2b1 which is in contact with the surface 2a1 of the insulating substrate 2a outside the through hole 2e; and a smooth surface portion 2g which is in contact with the conductive through-via 2d in the through hole 2e and is smoother than the surface portion 2b1. The conductive via 2d includes bismuth regions B which contain bismuth as a main component, and the total sum of the outer peripheral lengths of the bismuth regions B per cross-sectional unit area of the conductive through-via 2d is 0.25 / μm or less.

Description

printed wiring board

[0001] The present invention relates to a printed wiring board.

[0002] Vias made using a metal-bonded conductive paste, which combines a highly conductive metal such as copper or silver with a tin-based solder, and multilayer wiring boards using such vias, are used in many electronic devices as an environmentally friendly wiring manufacturing technology that does not require plating for interlayer connections, and are expected to see further development in the future. Paste vias made using a combination of Cu powder and Sn—Bi powder have particularly attracted attention. This is due to the fact that Sn—Bi has a low eutectic temperature of 139°C, allowing for production using a relatively low-temperature process, and that they do not use expensive In or environmentally harmful Pb. Vias made using this combination of materials have stable connection reliability even in high-temperature processes such as reflow soldering, and several such techniques are known (see, for example, Patent Document 1).

[0003] Patent Document 1 discloses a multilayer wiring board having a via-hole conductor in which a region mainly composed of a Cu—Sn alloy is the majority, and a region mainly composed of Cu and a region mainly composed of Bi are surrounded by the majority of the region. ６ Sn ５ and Cu ３ It contains two types of intermetallic compounds, Cu and Sn, and more than 90% of Cu-Sn alloys are Cu. ３ According to Patent Document 1, by using such a via-hole conductor, it is possible to obtain a via having a stable metal structure and high connection reliability even after post-processing involving heating or after long-term use.

[0004] Patent No. 5099272

[0005] Meanwhile, with the recent trend toward higher density electronic circuits, there has been a growing demand for smaller conductive paste vias. However, the finer the via structure, the greater the load on the via during thermal shock testing. Therefore, printed wiring boards with fine via structures have the problem of failure due to via breakage. In particular, in the technology described in Patent Document 1, when the via diameter is φ100 μm or less and the via length is 50 μm or less, cracks may occur originating from the Bi regions scattered around the Cu—Sn alloy in the via structure, potentially increasing the via resistance. Furthermore, in Patent Document 1, the region primarily composed of Bi has an irregular, uneven, or needle-like outer shape. Bi has lower rigidity and strength than the surrounding Cu—Sn alloy, and the boundary between the two is a concentration field of externally applied strain, making it prone to becoming a starting point for fracture. In particular, near the boundary with the conductive layer, stress concentration in such amorphous Bi regions may cause via fracture and lead to a break between the via and the conductive layer. Furthermore, there is a concern that the strength of the boundary between Bi and Cu--Sn may decrease due to a change in the crystalline structure caused by a local eutectic melting reaction near the eutectic temperature of Sn--Bi.

[0006] The problem to be solved by the present invention is to provide a printed wiring board having excellent durability and capable of suppressing the occurrence of failures due to disconnection of vias.

[0007] [1] Aspect 1 of the present invention is a printed wiring board comprising: an insulating layer having a first surface and having a through hole provided therein; a first conductor layer provided on the first surface; and a via provided in the through hole and electrically connected to the first conductor layer, wherein the first conductor layer comprises a surface portion in contact with the first surface of the insulating layer outside the through hole, and a smooth surface portion in contact with the via within the through hole and smoother than the surface portion in contact with the first surface; the via includes a bismuth region containing bismuth as a main component; and the sum of the perimeter lengths of the bismuth regions per unit area of ​​a cross section of the via is 0.25 / μm or less.

[0008] [2] Aspect 2 of the present invention is a printed wiring board comprising: an insulating layer having a first surface and having a through hole; a first conductor layer provided on the first surface; and a via provided in the through hole and electrically connected to the first conductor layer, wherein the first conductor layer has a surface in contact with the first surface of the insulating layer outside the through hole, and a smooth surface portion in contact with the via within the through hole and smoother than the surface in contact with the first surface, and the via is a printed wiring board including a spherical bismuth region containing bismuth as a main component.

[0009] [3] Aspect 3 of the present invention is the printed wiring board of aspect 1 or 2, wherein the vias are formed using solder powder containing SnBi and metal powder mainly composed of copper, and the compounding ratio of the solder powder to the metal powder is 0.5 to 2.0 by weight (solder powder / metal powder).

[0010] [4] A fourth aspect of the present invention is the printed wiring board according to the first or second aspect, wherein the average diameter of the cross section of the bismuth region is 4 μm or more.

[0011] [5] A fifth aspect of the present invention is the printed wiring board of the fourth aspect, in which the average diameter of the bismuth region in the cross section of the via is 7 μm or more.

[0012] [6] A sixth aspect of the present invention is the printed wiring board of any one of the first to fifth aspects, wherein the depth of the smooth surface portion from the contact position between the surface portion and the via is 0.5 to 4 μm.

[0013] [7] Aspect 7 of the present invention is a printed wiring board according to any one of aspects 1 to 6, wherein the via includes a first connection surface that contacts the smooth surface portion and a second connection surface opposite the first connection surface, the printed wiring board includes a second conductor layer that is electrically connected to the via at the second connection surface, and the area of ​​the first connection surface is smaller than the area of ​​the second connection surface.

[0014] [8] Aspect 8 of the present invention is a method for manufacturing a printed wiring board, comprising the steps of: forming a first conductor layer on a first surface of an insulating layer; forming a through hole in the insulating layer; smoothing a portion of the first conductor layer exposed in the through hole to form a smooth surface portion; filling the through hole with a conductive paste containing bismuth; stacking a second conductor layer so as to be in contact with the conductive paste; and hot-pressing a laminate including the insulating layer, the first conductor layer, the conductive paste, and the second conductor layer to form a via, wherein the hot-pressing is performed by increasing the pressure to a predetermined level, and then increasing the temperature to a predetermined level while maintaining the pressure, and holding the predetermined pressure and temperature for 40 to 180 minutes, wherein the predetermined pressure is 3 to 6 MPa, and the predetermined temperature is 140 to 200°C.

[0015] According to the present invention, it is possible to provide a printed wiring board having excellent durability and capable of suppressing the occurrence of failures due to disconnection of vias.

[0016] FIG. 1 is a schematic cross-sectional view of a printed wiring board according to an embodiment of the present invention. FIG. 2 is an enlarged cross-sectional view of portion II in FIG. 1. FIG. 3(a) is a backscattered electron image of a cross section of a conductive via in a printed wiring board according to an embodiment of the present invention, taken by a scanning electron microscope. FIG. 3(b) is an image of the printed wiring board after binarization processing in the same field of view as FIG. 3(a). FIG. 4(a) is a backscattered electron image of a cross section of a conductive via in a printed wiring board according to an embodiment of the present invention, taken by a scanning electron microscope, and is a diagram of Bi mapping results obtained by EDS analysis in the same field of view as FIG. 4(a). FIG. 5 is a schematic cross-sectional view of a conventional printed wiring board. FIG. 6(a) is a backscattered electron image of a cross section of a via in a conventional printed wiring board, taken by a scanning electron microscope. FIG. 6(b) is an image of the conventional printed wiring board after binarization processing in the same field of view as FIG. 6(a). FIGS. 7(a) to 7(c) are diagrams for explaining a method for evaluating the shape of bismuth regions B in a printed wiring board according to an embodiment of the present invention. 8(a) to 8(g) are enlarged cross-sectional views illustrating a manufacturing method for a wiring substrate base material constituting a printed wiring board according to an embodiment of the present invention. FIG. 9 is a cross-sectional view illustrating a state before assembly of a printed wiring board according to an embodiment of the present invention. FIGS. 10(a) to 10(h) are views illustrating a process for forming a bismuth region B according to an embodiment of the present invention. FIG. 11 is an enlarged cross-sectional view corresponding to FIG. 2 illustrating a modified example of the printed wiring board 10 according to an embodiment of the present invention. FIG. 12(a) is a cross-sectional image of a conductive via 2d in Example 1, and FIG. 12(b) is a cross-sectional image of a conductive via 2d in Comparative Example 1.

[0017] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will now be described with reference to the accompanying drawings. Fig. 1 is a schematic cross-sectional view of a printed wiring board 10 according to this embodiment, and Fig. 2 is an enlarged cross-sectional view showing part II in Fig. 1.

[0018] 1, printed wiring board 10 in this embodiment is formed by stacking first to fourth wiring substrate base materials 1 to 4. First, the configuration of second wiring substrate base material 2 will be described.

[0019] The second wiring substrate base 2 includes an insulating substrate 2a, multiple conductive layers 2b, an adhesive layer 2c, and conductive vias 2d. The insulating substrate 2a is made of an insulating resin material. Examples of resin materials that make up the insulating substrate 2a include polyimide, polyethylene terephthalate, polyethylene naphthalate, polyester, and liquid crystal polymer (LCP). The thickness of the insulating substrate 2a is preferably 12 to 50 μm.

[0020] The conductive layer 2b is a patterned wiring and is provided on one surface 2a1 of the insulating substrate 2a (see FIG. 9 ). The conductive layer 2b is made of a conductive material such as copper. In this embodiment, the conductive layer 2b is a patterned wiring, but the configuration of the conductive layer 2b is not particularly limited thereto. For example, the conductive layer 2b may be provided on the entire surface 2a1 of the first insulating substrate 2a. As shown in FIG. 2 , the conductive layer 2b has a surface portion 2b1 in contact with the surface 2a1 of the insulating substrate 2a and a smooth surface portion 2g that is smoother than the surface portion 2b1 in contact with the insulating substrate 2a. The smooth surface portion 2g is formed by performing a smoothing treatment on the surface of the conductive material that constitutes the conductive layer 2b, as described below. The arithmetic mean roughness Ra (Japanese Industrial Standard JIS B0601:2001) of the smooth surface portion 2g is preferably 1 μm or less, more preferably 0.8 μm or less, even more preferably 0.6 μm or less, and particularly preferably 0.5 μm or less. The maximum height roughness Rz (Japanese Industrial Standard JIS B0601:2001) of the smooth surface portion 2g is preferably 3 μm or less, more preferably 2 μm or less, and even more preferably 1.5 μm or less. In this embodiment, since the conductive layer 2b has the smooth surface portion 2g, it is possible to suppress the occurrence of damage caused by unevenness on the surface of the conductive layer 2b.

[0021] The adhesive layer 2c is adhered to the entire lower surface of the insulating substrate 2a. The adhesive layer 2c is not particularly limited, but an epoxy adhesive can be used.

[0022] As shown in FIG. 2 , the conductive via 2d is made of a columnar conductive paste filled in a through-hole 2e formed in the insulating substrate 2a. The upper end (top surface) of the conductive via 2d is connected to the smooth surface portion 2g of the conductive layer 2b. The upper end of the conductive via 2d protrudes upward in the figure from the surface 2a1 of the insulating substrate 2a and the surface portion 2b1 of the conductive layer 2b, and penetrates into the conductive layer 2b. The lower end (bottom surface) of the conductive via 2d is connected to the conductive layer 1b (described below) of the first wiring substrate base 1. Because the conductive layer 2b has the smooth surface portion 2g, a smooth alloy layer is formed at the interface between the conductive via 2d and the smooth surface portion 2g, and the conductive via 2d and the smooth surface portion 2g are firmly connected. As a result, the printed wiring board 100 of this embodiment has high connection reliability between the conductive via 2d and the conductive layer 2b and reduced connection resistance between the conductive via 2d and the conductive layer 2b. The inner diameter of the conductive via 2d is not particularly limited, but is preferably 50 to 150 μm.

[0023] Because the conductive via 2d penetrates the conductive layer 2b, the smooth surface portion 2g of the conductive layer 2b is located further inward than the surface portion 2b1. The depth D of the smooth surface portion 2g is expressed as the distance from the contact position between the surface portion 2b1 and the conductive via 2d to the smooth surface portion 2g. The depth D of the smooth surface portion 2g is preferably 0.5 to 4.0 μm (0.5≦D≦4.0). Because the smooth surface portion 2g penetrates into the conductive layer 2b, the conductive layer 2b has an inner wall portion 2b2. Therefore, the conductive via 2d is not only bonded to the smooth surface portion 2g of the conductive layer 2b in the vertical direction in the figure, but also bonded to the inner wall portion 2b2 of the conductive layer 2b in the horizontal direction in the figure. In this embodiment, the contact between the conductive via 2d and the inner wall portion 2b2 of the conductive layer 2b restricts the horizontal movement of the conductive via 2d. Therefore, the conductive via 2d is prevented from being misaligned with respect to the conductive layer 2b, and the connection reliability between the conductive via 2d and the conductive layer 2b can be further improved.

[0024] FIG. 11 is an enlarged cross-sectional view corresponding to FIG. 2 , illustrating a modified example of the printed wiring board 10. In the embodiment shown in FIG. 2 , the width (diameter) of the conductive via 2d is substantially constant in the vertical direction in the figure, but the configuration of the conductive via 2d is not particularly limited thereto. For example, as shown in FIG. 11 , the width of the conductive via 2d does not have to be constant in the vertical direction. In FIG. 11 , the width of the conductive via 2d increases downward in the figure. That is, the area of ​​the first connection surface 2d1 of the conductive via 2d that contacts the smooth surface portion 2g is smaller than the area of ​​the second connection surface 2d2 of the conductive via 2d that contacts the conductive layer 1b. Although not particularly limited, the via diameter at the first connection surface 2d1 is 60 to 100 μm. Although not particularly limited, the via diameter at the second connection surface 2d2 is 85 to 140 μm.

[0025] 2, the insulating substrate 2a and the conductive vias 2d have approximately the same height, but the configuration of the insulating substrate 2a and the conductive vias 2d is not particularly limited to this. For example, as shown in Fig. 11, the conductive vias 2d may protrude downward from the insulating substrate 2a in the drawing. As a result, in the embodiment shown in Fig. 11, the conductive vias 2d have a cross-sectional shape that is within the first region F surrounded by the insulating substrate 2a. １ and a second region F surrounded by the adhesive layer 2c. ２ The first region F of the conductive via 2d includes １ The second region F of the conductive via 2d has a tapered shape that conforms to the shape of the through hole 2e. ２ The conductive vias 2d have a curved shape that widens toward the adhesive layer 2c. The curved shape of the conductive vias 2d is formed by hardening the conductive paste 2D that constitutes the conductive vias 2d by hot pressing, as will be described later.

[0026] 1 , the third wiring substrate base 3 has an insulating substrate 3 a, a plurality of conductive layers 3 b, an adhesive layer 3 c, and a plurality of conductive vias 3 d. The configurations of the insulating substrate 3 a, the conductive layer 3 b, the adhesive layer 3 c, and the conductive vias 3 d are not particularly limited, but are similar to the configurations of the insulating substrate 2 a, the conductive layer 2 b, the adhesive layer 2 c, and the conductive vias 2 d, respectively.

[0027] The fourth wiring substrate base 4 has an insulating substrate 4 a, a plurality of conductive layers 4 b, an adhesive layer 4 c, and a plurality of conductive vias 4 d. The configurations of the insulating substrate 4 a, the conductive layer 4 b, the adhesive layer 4 c, and the conductive vias 4 d are not particularly limited, but are similar to the configurations of the insulating substrate 2 a, the conductive layer 2 b, the adhesive layer 2 c, and the conductive vias 2 d, respectively.

[0028] The first wiring substrate base 1 includes an insulating substrate 1a, a plurality of conductive layers 1b, and an adhesive layer 1c. The configurations of the insulating substrate 1a, the conductive layers 1b, and the adhesive layer 1c are not particularly limited, but are similar to the configurations of the insulating substrate 2a, the conductive layers 2b, and the adhesive layer 2c, respectively.

[0029] Although FIG. 1 illustrates the first to fourth wiring substrates 1 to 4 as if the conductive layers 1b to 4b have the same wiring pattern, the configuration of the conductive layers 1b to 4b is not particularly limited thereto. The conductive layers 1b to 4b may be designed according to the requirements of the circuit wiring configuration of the printed wiring board 10. The second to fourth wiring substrates 2 to 4 each have the same number of conductive vias 2d to 4d, but the number of conductive vias may be selected arbitrarily for each wiring substrate. The first wiring substrate 1 does not have conductive vias, but conductive vias may be provided in the first wiring substrate 1 as needed. In this embodiment, the printed wiring board 10 includes the first to fourth wiring substrates 1 to 4, but the configuration of the printed wiring board 10 is not particularly limited thereto. For example, the printed wiring board 10 may include only the first and second wiring substrates 1 and 2, or may include more wiring substrates.

[0030] The configurations of the conductive vias 2d to 4d will be described in detail below. Here, the conductive via 2d will be described. As shown in FIG. 2, the conductive via 2d includes a bismuth region B, a high-melting-point metal region M, and a resin region R.

[0031] The bismuth region B is a region containing a metal whose main component is bismuth, and has a spherical shape. Examples of metals other than bismuth contained in the bismuth region B include Sn and SnBi. The bismuth region B contained in the conductive via 2d can be detected, for example, by performing EDS (Energy Dispersive Spectroscopy) analysis on a cross section of the conductive via 2d.

[0032] Figure 3(a) is a backscattered electron image taken by a scanning electron microscope of the cross section of conductive via 2d of printed wiring board 10 in this embodiment, and Figure 3(b) is an image of printed wiring board 10 after binarization processing in the same field of view as Figure 3(a).

[0033] When the cross section of the conductive via 2d is observed with a scanning electron microscope, the total perimeter length of the bismuth region B per unit area of ​​the cross section is 0.25 / μm (μm / μm ２ ) or less. The sum of the perimeters of the bismuth regions B per unit area of ​​the cross section of the conductive via 2d is more preferably 0.2 / μm or less, and even more preferably 0.15 / μm or less. The lower limit of the sum of the perimeters of the bismuth regions B per unit area is not particularly limited, but is preferably 0.05 / μm or more. The sum of the perimeters of the bismuth regions B can be measured using a backscattered electron image of the cross section of the conductive via 2d obtained by a scanning electron microscope. For example, the sum of the perimeters of the bismuth regions B can be determined by binarizing the backscattered electron image obtained by the scanning electron microscope using image analysis software (product name "ImageJ Ver. 1.52", manufactured by the National Institute of Health, Inc.) at a predetermined threshold value. Specifically, first, the printed wiring board 10 is cut at a cross section through which the conductive via 2d passes, to expose the cross section of the conductive via 2d. Next, the cross section of the conductive via 2d is observed using a scanning electron microscope to obtain an image of the cross section of the conductive via 2d. As shown in FIG. 3(a), the obtained image is divided into an observation area A ｏｂ Set the observation area A. ｏｂA threshold value for image analysis was set so that the area containing bismuth (the area that is white relative to the other areas in FIG. 3(a)) could be identified, and binarization processing was performed by image analysis. As shown in FIG. 3(b), the bismuth area A Ｂｉ In FIG. 3(b), each closed area is a bismuth area A detected by binarization processing. Ｂｉ Next, the binarized image is analyzed to determine the bismuth region A Ｂｉ Finally, calculate the perimeter [μm] of the calculated bismuth region A Ｂｉ The total perimeter of the observation area A ｏｂ Area [μm ２ ], the sum of the perimeter lengths of the bismuth regions B per unit area in the cross section of the conductive via 2d [μm / μm ２ ] can be obtained. ｏｂ The area may be an area that sufficiently includes the cross section of the conductive via 2d, and may be, for example, a range of 60 μm×45 μm. Observation and binarization using a scanning electron microscope may be performed under the following conditions, for example: Scanning electron microscope—output: 15 kV, measurement magnification: 900x Binarization—observation area A ｏｂ Image size: 588 x 441 pixels = 60 x 45 μm, lower limit of 256 levels of shading: 150, upper limit of 256 levels of shading: 175

[0034] Fig. 4(a) is a backscattered electron image taken by a scanning electron microscope of the cross section of conductive via 2d of printed wiring board 10 in this embodiment, and Fig. 4(b) is a diagram showing the Bi mapping results by EDS analysis in the same field of view as Fig. 4(a) of printed wiring board 10. In Fig. 3(a), the white area relatively to the other areas was determined to be the area containing bismuth, but the presence of bismuth in the white area in the backscattered electron image of the cross section of conductive via 2d can be confirmed by EDS analysis. For example, by performing EDS analysis in the same field of view as the backscattered electron image of the cross section of conductive via 2d shown in Fig. 4(a), it can be confirmed that bismuth is present in the white area in Fig. 4(a), as shown in Fig. 4(b).

[0035] In the printed wiring board 10 of this embodiment, at least one observation area A ｏｂ It is sufficient if the sum of the perimeter lengths of the bismuth regions B per unit area in the cross section of the conductive via 2d calculated based on the above is 0.25 / μm or less. However, in order to perform a more accurate evaluation using a sufficient measurement area, multiple observation regions A ｏｂ It is more preferable that the sum of the perimeter lengths of the bismuth regions B per unit area is calculated for each of the observation regions A in the plurality of cross sections, and the average value of the sum of the perimeter lengths of the bismuth regions B per unit area is 0.25 / μm or less. ｏｂ The total area of ​​the ２ It is more preferable that the average value of the sum of the perimeter lengths of the bismuth regions B obtained within the above range is 0.25 / μm or less.

[0036] The larger the sum of the perimeter lengths of the bismuth regions B per unit area of ​​the cross section of the conductive via 2d, the more non-uniform the shape of the bismuth regions B is, and the more uneven or needle-like the surface shape of the bismuth regions B is. Conversely, the smaller the sum of the perimeter lengths of the bismuth regions B in the cross section of the conductive via 2d, the less uneven the surface is and the more spherical the bismuth regions B are present.

[0037] FIG. 5 is a schematic cross-sectional view of a conventional printed wiring board, FIG. 6(a) is a backscattered electron image of a cross section of a via in the conventional printed wiring board taken by a scanning electron microscope, and FIG. 6(b) is an image of the conventional printed wiring board after binarization processing in the same field of view as FIG. 6(a).

[0038] 5, in the conventional printed wiring board 1000, the interior of the conductive via 300 formed using a conductive paste containing conductive particles such as Cu, Sn—Bi, or the like and a resin such as an epoxy resin is heated after formation, and the Bi portions 310 have a shape with acute angles and protrusions, and the Bi portions 310 are dispersed between the conductors 320 (intermetallic compound particles) and at positions in contact with the electrodes 200. When the cross section of the conductive via 300 of such a conventional printed wiring board 1000 is observed with a scanning electron microscope, a structure in which white bismuth regions are finely dispersed is seen, as shown in FIGS. In such a via structure, when thermal stress occurs due to the difference in thermal expansion coefficient between the insulating layer (substrate) 100 and the resin 330 contained in the conductive via 300, the stress tends to concentrate on the Bi portion 310, which has a sharp angle or a protruding shape, and cracks may occur in the conductive via 300 starting from the Bi portion 310, causing an increase in the electrical resistance of the conductive via 300 or a failure due to breakage of the conductive via 300.

[0039] In contrast, in the printed wiring board 10 of this embodiment, the sum of the perimeter lengths of the bismuth regions B in the cross section of the conductive via 2d is 0.25 / μm or less, and the bismuth regions B are present in the conductive via 2d in a spherical shape (including cases where they are approximately spherical; the same applies below) as shown in Fig. 2. Therefore, stress is less likely to be applied to the bismuth regions B, and the occurrence of disconnection of the conductive via 2d can be suppressed.

[0040] In particular, as mentioned above, the smaller the via size, the greater the load due to thermal stress per unit volume of the via tends to be. In the printed wiring board 10 of this embodiment, the sum of the outer perimeter lengths of the bismuth regions B per unit area of ​​the cross section of the conductive via 2d is 0.25 / μm or less, so that even if the structure of the conductive via 2d is a minute structure with an inner diameter of 100 μm or less and a length of 50 μm or less, the occurrence of breakage of the conductive via 2d can be suppressed, and the occurrence of failure of the printed wiring board 10 can be suppressed.

[0041] Furthermore, in the printed wiring board 10 of this embodiment, the conductive layer 2b has a smooth surface portion 2g that contacts the conductive via 2d. This allows the bismuth to be spheroidized even near the conductive layer 2b during the formation of the conductive via 2d, as described below. Therefore, the bismuth region B is present in a spherical shape even near the interface between the conductive via 2d and the conductive layer 2b. Therefore, stress is less likely to be applied to the bismuth region B even near the interface between the conductive via 2d and the conductive layer 2b, and the occurrence of disconnection due to the destruction of the conductive via 2d can be suppressed.

[0042] In addition, the sum of the cross-sectional areas of the bismuth regions B per unit area of ​​the cross section of the conductive via 2d is 0.10 (μm ２ / μm ２ ) or less, and more preferably 0.08 or less. The lower limit of the sum of the cross-sectional areas of the bismuth regions B per unit area is not particularly limited, but is preferably 0.04 or more. The sum of the cross-sectional areas of the bismuth regions B can be determined by performing image analysis using binarization processing on an image of the cross section of the conductive via 2d observed by a scanning electron microscope in the same manner as for the sum of the perimeter lengths of the bismuth regions B. Specifically, for the obtained image, ｏｂ and set the observation area A ｏｂ By performing EDS analysis and performing binarization processing by image analysis, the bismuth region A Ｂｉ The area detected as bismuth area A was analyzed by image analysis. Ｂｉ Cross-sectional area [μm ２ Calculate the calculated bismuth area A Ｂｉ The cross-sectional areas of the observation area A are summed up. ｏｂ Area [μm ２ ], the sum of the cross-sectional areas of the bismuth regions B per unit area in the cross section of the conductive via 2d [μm ２ / μm ２ ] can be obtained. ｏｂ may be set to the same value as the sum of the perimeter lengths of the bismuth regions B.

[0043] The larger the sum of the cross-sectional areas of the bismuth regions B per unit area of ​​the cross section of the conductive via 2d, the more non-uniform the shape of the bismuth regions B, indicating that the surface shape of the bismuth regions B is uneven or needle-like. Conversely, the smaller the sum of the cross-sectional areas of the bismuth regions B in the cross section of the conductive via 2d, the more uniform the shape of the bismuth regions B is, with fewer unevenness on the surface, and an overall spherical shape. In the printed wiring board 10 of this embodiment, since the sum of the cross-sectional areas of the bismuth regions B in the cross section of the conductive via 2d is 0.10 or less, a stress concentration field is less likely to be formed, and therefore, the occurrence of disconnection of the conductive via 2d can be suppressed.

[0044] Furthermore, the number of bismuth regions B per unit area of ​​the cross section of the conductive via 2d is 0.01 / μm ２ Preferably, the number is 0.008 particles / μm or less. ２ The lower limit of the number of bismuth regions B per unit area is not particularly limited, but is preferably 0.003 / μm ２ The number of bismuth regions B in the cross section of the conductive via 2d can be determined in the same way as for the sum of the perimeter lengths of the bismuth regions B, by performing image analysis using binarization processing on an image of the cross section of the conductive via 2d observed by a scanning electron microscope, and counting the number of detected bismuth regions B. Specifically, for the obtained image, ｏｂ and set the observation area A ｏｂ By performing EDS analysis and performing binarization processing by image analysis, the bismuth region A Ｂｉ The area detected as bismuth area A was analyzed by image analysis. Ｂｉ The number of bismuth particles in the measured area A is counted. Ｂｉ The number of observation areas A ｏｂ Area [μm ２ ], the number of bismuth regions B per unit area in the cross section of the conductive via 2d [pieces / μm ２ ] can be obtained. ｏｂ may be set to the same value as the sum of the perimeter lengths of the bismuth regions B.

[0045] Although not particularly limited, the volume ratio of the bismuth region B to the total volume of the bismuth region B and the high-melting-point metal region M is 13 to 16%. The volume ratio of the bismuth region B can be determined by measurement using a method such as EDS element mapping.

[0046] The high melting point metal region M is a region containing a metal or metal compound having a melting point higher than that of bismuth. The metal and metal compound contained in the high melting point metal region M include Cu, Cu, ６ Sn ５ Although not particularly limited, the volume ratio of the high melting point metal region M to the total volume of the bismuth region B and the high melting point metal region M is preferably 84 to 87%. The volume ratio of the high melting point metal region M can be determined by measurement using a method such as EDS element mapping.

[0047] The resin region R is a region containing resin scattered within the high-melting-point metal region M. The resin contained in the resin region R is not particularly limited, but an epoxy resin is preferred because of its excellent heat resistance and low linear expansion coefficient. As shown in FIG. 2, a portion of the resin region R surrounds the bismuth region B.

[0048] In this embodiment, the bismuth region B included in the conductive via 2d of the printed wiring board 10 includes a region having a spherical shape. Whether the bismuth region B has a spherical shape is determined by the following method. First, the cross section of the conductive via 2d is measured using a scanning electron microscope, and EDS analysis is performed on the obtained image to identify the region containing bismuth and detect the resin region present around the region containing bismuth. Based on the shape of the resin region around the region containing bismuth, the cross-sectional shape of the bismuth region is identified and it is determined whether the cross-sectional shape of the bismuth region is circular.

[0049] A method for evaluating the shape of the bismuth region B will be specifically described with reference to FIGS. 7(a) to 7(c). FIGS. 7(a) to 7(c) are diagrams for explaining the method for evaluating the shape of the bismuth region B. First, the cross section of the conductive via 2d is measured using a scanning electron microscope, and EDS analysis is performed on the acquired image to identify the region containing bismuth, as shown in FIG. 7(a). In FIG. 7(a), the EDS analysis confirmed that the white region contains bismuth. Next, attention is focused on the resin region surrounding the region containing bismuth, and a threshold is set so that the resin region can be detected by image analysis, and binarization processing is performed. As a result, as shown in FIG. 7(b), the resin region A in FIG. 7(a) is identified. ｒe Next, the adjacent resin regions A in FIG. ｒe are connected by the shortest distance to form a provisional region P, as shown in FIG. 7( c). This provisional region P is assumed to be the cross section of the bismuth region B. The periphery of the provisional region P is also assumed to be the periphery of the cross section of the bismuth region B. In this case, the provisional region P also includes solid solution portions other than bismuth in the image of FIG. 7( a), which are also assumed to be the bismuth region B. The provisional region P is then compared with the EDS analysis results, and if the proportion of bismuth element in the provisional region P is 50% or more, it can be confirmed that the provisional region P is the bismuth region B. After confirming that the provisional region P is the bismuth region B in this way, the circularity of the provisional region P is calculated based on the periphery and area of ​​the provisional region P. If the circularity of the provisional region P is 0.8 or more, it can be determined that the cross section of the bismuth region B is circular, and therefore it can be determined that the bismuth region B has a spherical shape. Alternatively, the aspect ratio of the provisional region P may be calculated, and if the aspect ratio is 1.4 or less, it may be determined that the cross-sectional shape of the bismuth region B is circular and the bismuth region B has a spherical shape. It is preferable that 80% or more of the bismuth regions B included in the conductive via 2d are spherical. Specifically, evaluation is performed on 10 or more provisional regions P, and it is preferable that 80% or more of them are spherical.

[0050] The average diameter of the cross section of the bismuth region B is preferably 4 μm or more, more preferably 7 μm or more. There is no particular upper limit to the average diameter of the cross section of the bismuth region B, but it is usually 10 μm or less. Therefore, it is more preferable that the average diameter of the bismuth region B is 7 to 10 μm. If the average diameter of the cross section of the bismuth region B is too small, the strength of the entire conductive via 2d may decrease. The average diameter of the cross section of the bismuth region B is calculated as follows. First, an image of the cross section of the conductive via 2d is obtained by observation with a scanning electron microscope. For the obtained image, observation region A is ｏｂ and set the observation area A ｏｂ A plurality of bismuth regions B are detected by image analysis using the same binarization process as above, and the inner diameters of the detected plurality of bismuth regions B are calculated as the equivalent diameter of a circle having the same cross-sectional area. The average value of the inner diameters of the cross sections of the plurality of bismuth regions B calculated in this way can be calculated to obtain the average diameter of the cross section of the bismuth region B. ｏｂ The length may be a region including a plurality of bismuth regions B (for example, a region including 10 or more bismuth regions B), but may be set to the same as the sum of the perimeter lengths of the bismuth regions B, for example.

[0051] The configuration of the conductive via 2d has been described above, but the conductive vias 3d and 4d also have the same configuration as the conductive via 2d.

[0052] 8(a) to 8(g) are enlarged cross-sectional views for explaining a manufacturing method of the second wiring substrate base material 2 that constitutes the printed wiring board 10 in this embodiment, and FIG. 9 is a cross-sectional view showing the state before assembly of the printed wiring board 10 in this embodiment.

[0053] The printed wiring board 10 of this embodiment can be manufactured by the following method. First, the first to fourth wiring substrate base materials 1 to 4 that make up the printed wiring board 10 are fabricated by the following method. Note that here, the method for manufacturing the second wiring substrate base material 2 will be described as a representative example.

[0054] First, as an example of a starting substrate, a single-sided copper-clad laminate (CCL) is prepared, in which copper foil is attached to the entire surface 2a1 of a polyimide resin film serving as an insulating substrate 2a, forming a conductive layer 2b. Next, as shown in FIG. 8( a), a conductive layer 2b for wiring having a desired circuit pattern is formed on the surface 2a1 of the insulating substrate 2a. The circuit pattern is obtained by forming an etching resist pattern (etching mask) corresponding to the circuit pattern on the copper foil surface of the CCL by photolithography, and then chemically etching the copper foil. For this etching, an etchant mainly composed of ferric chloride can be used, for example.

[0055] In commercially available CCLs, the arithmetic mean roughness of the surface 2a1 of the conductive layer 2b that contacts the insulating substrate 2a is generally about 2 μm. This surface can be treated as a rough surface from a microscopic perspective. Figures 8(a) to 8(g) exaggerate the roughness of this surface.

[0056] Next, an adhesive layer 2c is formed on the other surface of the insulating substrate 2a using, for example, a 25 μm thick epoxy thermosetting resin film adhesive. For the adhesive layer 2c, an adhesive such as an acrylic resin or a thermoplastic adhesive may be used, and for example, a resin adhesive in the form of varnish may be applied to the surface of the insulating substrate 2a.

[0057] 8(b), a resin film F made of polyimide resin, for example, having a thickness of 25 μm, is attached to the surface of the adhesive layer 2c. The resin film F may be a plastic film such as PET or PEN instead of polyimide. Alternatively, a film that can be attached or peeled off by UV irradiation may be formed on the surface of the adhesive layer 2c.

[0058] Next, as shown in FIG. 8( c), through-holes 2e are formed through the insulating substrate 2a, adhesive layer 2c, and resin film F. The through-holes 2e are formed by laser processing from the resin film F side toward the conductive layer 2b side. For example, a YAG laser, a carbon dioxide laser, or an excimer laser can be used for the laser processing. The through-holes 2e become via holes in which conductive vias 2d are formed. By forming the through-holes 2e, the inner surface of the conductive layer 2b, i.e., the bottom surface of the via, is exposed within the through-holes 2e. Note that the laser processing may form a rough surface portion 2f on the inner surface of the conductive layer 2b, which has large irregularities with an arithmetic mean roughness Ra of 3 μm or more.

[0059] After the through-holes 2e are formed, a desmear process is carried out. ４ and O ２ A plasma desmear process using a mixed gas of these or an inert gas such as Ar, or a wet desmear process can be used.

[0060] 8(d), the portion of the conductive layer 2b exposed in the through-hole 2e, particularly the rough surface portion 2f, is subjected to a smoothing treatment to form a smooth surface portion 2g. The arithmetic mean roughness Ra of the smooth surface portion 2g is preferably 1 μm or less, more preferably 0.8 μm or less, and even more preferably 0.6 μm or less. The maximum height roughness Rz of the smooth surface portion 2g is preferably 3 μm or less, and more preferably 2 μm or less.

[0061] For example, chemical wet etching can be used as a smoothing treatment method. Specifically, chemical wet etching involves dissolving the inner surface of the conductive layer 2b using a chemical etching solution consisting of at least one selected from the group consisting of sulfuric acid hydrate, sulfuric acid, hydrochloric acid, iron chloride solution, and copper chloride solution. This method allows for accurate and easy formation of the smooth surface portion 2g having a smooth surface with an arithmetic mean roughness Ra of 1 μm or less. When performing chemical wet etching, it is preferable to adjust the amount of etching so that the depth D of the smooth surface portion 2g (see FIGS. 2 and 11) is 0.5 to 4 μm.

[0062] Other methods of smoothing treatment may include a sandblasting method in which abrasive grains are collided with the rough surface portion 2f to smooth it, a laser ablation method in which the rough surface portion 2f is vaporized with a laser to smooth it, or a plasma dry etching method in which the rough surface portion 2f is physically etched in a plasma gas atmosphere to smooth it.

[0063] Here, each method of smoothing processing will be described in more detail.

[0064] 1. Chemical wet etching method: One example of chemical wet etching is a method in which sulfuric acid and hydrogen peroxide are used to dissolve the copper of the conductive layer 2b in copper sulfate. Advantages of this method include low cost because a common processing solution is used, and ease of smoothing because the amount (speed) of etching can be easily adjusted by controlling the concentration, temperature, etc. This is the most preferable method compared to the various other methods described below.

[0065] 2. Sandblasting: Sandblasting is a method of smoothing the inner surface of the conductive layer 2b by spraying abrasive grains directly or a mixture of abrasive grains and water (abrasive) onto the inner surface of the conductive layer 2b. The advantage of this method is that it is a physical polishing process and does not cause a chemical reaction with the substrate, resulting in little ion contamination after processing.

[0066] 3. Laser ablation method: The laser ablation method is a method for smoothing the inner surface of the conductive layer 2b by irradiating the inner surface of the conductive layer 2b (the target) with a high-energy-density laser beam, causing a localized, rapid temperature rise in the irradiated area, and liquefying or vaporizing the irradiated area. One advantage of this method is that the smoothed shape can be easily adjusted by adjusting the laser energy (frequency or intensity).

[0067] 4. Plasma dry etching: Plasma dry etching is a method of smoothing the inner surface of the conductive layer 2b by irradiating it with a plasma gas such as Ar to polish the surface. The advantage of this method is that it allows for much finer and more precise smoothing than the abrasive grains used in sandblasting.

[0068] Next, as shown in Fig. 8(e), a conductive paste 2D is supplied to the upper surface of the resin film F, and the conductive paste 2D is squeegeeed with a squeegee S and screen-printed to fill the space inside the through-hole 2e as shown in Fig. 8(f). The conductive paste 2D is then dried. As the conductive paste 2D, a conductive paste containing solder powder containing Sn and Bi, metal powder mainly composed of copper, and an epoxy resin or the like is preferably used.

[0069] The metal powder is primarily composed of copper, and preferably contains 80 to 90% by weight of copper. The metal powder is preferably treated to be oxidation-resistant with an oxidation-resistant film made of metal or resin. An example of a metallic oxidation-resistant film is one made of silver.

[0070] The metal powder preferably contains one or more metal elements selected from the group consisting of Ti, V, Cr, Mn, Co, Ni, and Zn as a diffusion-impeding element. Among these diffusion-impeding elements, the metal powder more preferably contains Ni and Zn. The content of the diffusion-impeding element is preferably 0.5 to 10 wt % relative to 100 wt % of the metal powder. As will be described later, when the metal powder contains a diffusion-impeding element, alloying of Sn and Cu (Cu ６ Sn ５ Since the formation of bismuth particles (the formation of bismuth particles) proceeds relatively slowly from the surface of the metal powder, Bi tends to aggregate in the SnBi melt, and bismuth regions B are formed in a shape close to a sphere.

[0071] The blending ratio of the solder powder to the metal powder is preferably 0.5 to 2.0 by weight (solder powder / metal powder), and more preferably 1.0 to 1.5.

[0072] Next, as shown in FIG. 8( g), the resin film F is peeled off. This exposes the upper end of the dried conductive paste 2D' protruding from the upper surface of the adhesive layer 2c by the height of the thickness of the resin film F. The protruding height of the conductive paste 2D' can be adjusted by selecting the thickness of the resin film F. In this manner, a second wiring substrate base 2 is produced, which includes conductive paste 2D' that will become conductive vias 2d. The third wiring substrate base 3 and the fourth wiring substrate base 4 are also produced using the same procedure. The first wiring substrate base 1 is also produced using the procedure shown in FIG. 8( a).

[0073] 9, the first to fourth wiring substrate base materials 1 to 4 are laminated. At this time, the layers are laminated so that the protruding portions of the conductive pastes 2D' to 4D' of each wiring substrate come into contact with the conductive layers 1b to 3b of the wiring substrate base material disposed underneath. For example, the first wiring substrate base material 1 and the second wiring substrate base material 2 are laminated so that the conductive paste 20D' of the second wiring substrate base material 2 comes into contact with the conductive layer 1b of the first wiring substrate base material 1.

[0074] Next, with the first to fourth wiring substrate bases 1 to 4 stacked, a hot press is performed along the stacking direction to bake the conductive pastes 2D' to 4D' and form the conductive vias 2d to 4d. In this way, the printed wiring board 10 shown in FIG. 1 is produced.

[0075] 10A to 10H are diagrams illustrating the process of forming the bismuth region B in this embodiment.

[0076] The reason why the bismuth regions B in the conductive vias 2d-4d of the printed wiring board 10 of this embodiment have a spherical shape is believed to be because the bismuth regions B are formed by the following process. First, as shown in FIG. 10( a), the conductive paste contains solder powder containing Sn and Bi and metal powder primarily composed of copper. The second to fourth wiring substrate bases 2-4 filled with such conductive paste are stacked and pressed to apply pressure, thereby bonding the solder powder and metal powder together, as shown in FIG. 10( b). Next, the second to fourth wiring substrate bases 2-4 are heated under pressure, causing the solder powder to melt and form a state in which solid Sn and Sn—Bi molten liquid coexist, as shown in FIG. 10( c). At this time, because the second to fourth wiring substrate bases 2-4 are pressed under high pressure, the metal particles are in close contact with each other, and the Sn—Bi molten liquid does not penetrate between the metal particles and remains in the form of droplets. Thereafter, as shown in FIG. 10(d), Sn in the melt diffuses onto the surface of the metal powder (Cu), Sn and Cu are alloyed, and Cu is formed on the surface of the metal powder. ６ Sn ５ is formed. Furthermore, the amount of Sn diffused into the metal powder is compensated by dissolving solid Sn. Here, diffusion-hindering elements contained in the metal powder, such as Ti, V, Cr, Mn, Co, Ni, and Zn, react quickly with Sn, thereby inhibiting the diffusion of Sn into the metal powder. Therefore, in the process shown in FIG. 10(d), mass transfer in the melt becomes faster than diffusion, and the melt composition remains uniform. Next, as shown in FIG. 10(e), when the Sn-Bi melt composition reaches a eutectic ratio of Bi:Sn = 53:43, all of the solid Sn dissolves. Furthermore, as shown in FIG. 10(f), as the diffusion and outflow of Sn continues, the Bi concentration in the SnBi melt gradually increases, and solid Bi begins to precipitate. Next, as shown in FIG. 10(g), the diffusion and outflow of Sn continues, the solid Bi grows while maintaining its spherical shape, and the amount of SnBi melt decreases. Finally, as shown in Fig. 10(h), all the Sn in the Sn-Bi melt diffuses into the metal powder, and the remaining Bi solidifies while maintaining its spherical shape. In this way, the bismuth region B is formed, and the via structure shown in Fig. 2 is formed.

[0077] On the other hand, conventional printed wiring boards use conductive pastes containing metal powders that do not contain diffusion-inhibiting elements, which is thought to result in rapid diffusion of Sn into Cu and alloying of Cu and Sn, resulting in Bi being dispersed without agglomeration, as shown in Figure 5.

[0078] Furthermore, in the process of producing the second wiring substrate base 2, if the conductive layer 2b is not subjected to a smoothing treatment, the conductive paste 2D' is hot-pressed while in contact with the rough surface portion 2f (see FIG. 8(c)). In this case, there is a risk that the spheroidization of Bi may be hindered near the rough surface portion 2f, resulting in a structure in which the bismuth regions are finely dispersed. In contrast, in this embodiment, the conductive layer 2b has a smooth surface portion 2g, and the conductive paste 2D' is hot-pressed while in contact with the smooth surface portion 2g. It is believed that this allows the spheroidization of Bi to be prevented even near the interface with the conductive layer 2b, and that bismuth regions B having a spherical shape are formed.

[0079] The pressure conditions in the hot press are preferably 2 MPa or more, more preferably 2 to 6 MPa, and even more preferably 3 to 6 MPa. By setting the pressure conditions within the above range, alloying of the Sn contained in the solder powder and the Cu contained in the metal powder is promoted, the resistance value of the conductive via 2d is reduced, and the connection reliability of the conductive via 2d is improved. If the pressure conditions in the formation of the conductive via 2d are less than 2 MPa, Sn and Cu do not alloy, the resistance value of the conductive via 2d increases, and the connection reliability of the conductive via 2d tends to deteriorate. If the pressure conditions are more than 6 MPa, the alloying of Sn and Cu is accelerated, and spherical bismuth regions B are not formed, which tends to deteriorate the connection reliability of the conductive via 2d.

[0080] The heating temperature in the hot press is preferably 140 to 200°C, more preferably 170 to 190°C. If the heating temperature is too low, Sn and Cu do not alloy, the resistance value of the conductive via 2d increases, and the connection reliability of the conductive via 2d tends to deteriorate. On the other hand, if the heating temperature is too high, the amount of SnBi melt increases due to heating, and it penetrates into the periphery, so that the spherical bismuth region B tends not to be formed.

[0081] The holding time in the pressurized and heated state in the hot press is preferably 40 minutes or more, more preferably 40 to 180 minutes, and even more preferably 40 to 120 minutes. If the holding time is less than 40 minutes, there is a risk that the adhesive will not harden sufficiently and that Sn and Cu will not be alloyed sufficiently.

[0082] In particular, the hot pressing is preferably performed by increasing the pressure to a predetermined pressure of 3 to 6 MPa, then heating to a predetermined temperature of 140 to 200°C while maintaining the pressure, and holding the predetermined pressure and temperature for 40 to 180 minutes. It is more preferable to increase the pressure to a predetermined pressure of 3 to 6 MPa, then heating to a predetermined temperature of 170 to 190°C while maintaining the pressure, and holding the predetermined pressure and temperature for 40 to 120 minutes. For example, a method of increasing the pressure stepwise, such as holding at a predetermined first pressure, then increasing the pressure to a predetermined second pressure, and then holding at the second pressure again, is not preferable. Furthermore, a method of increasing the temperature stepwise, such as holding at a predetermined first temperature, then heating to a predetermined second temperature, and then holding at the second temperature again, is not preferable. When hot pressing is performed using such a method of increasing the pressure or temperature stepwise, even when a conductive paste containing a metal powder containing a diffusion-hindering element is used, the alloying of Sn and Cu may not proceed properly, and spherical bismuth regions may not be formed. In this embodiment, a conductive paste containing a metal powder containing the above-mentioned diffusion-impeding element is pressurized to a predetermined pressure of 3 to 6 MPa, then heated to a predetermined temperature of 140 to 200°C while maintaining the pressure, and cured in a heating press that holds the paste for 40 to 180 minutes while maintaining the predetermined pressure and temperature, thereby forming a spherical bismuth region B.

[0083] As described above, in the printed wiring board 10 of this embodiment, the sum of the perimeter lengths of the bismuth regions B per unit area in the cross section of the conductive via 2d is 0.25 / μm or less, and the bismuth regions B are present in a spherical shape within the conductive via 2d. Therefore, stress is less likely to be applied to the bismuth regions B, and failures due to disconnection of the conductive via 2d can be suppressed. Furthermore, in the printed wiring board 10 of this embodiment, the conductive layer 2b has a smooth surface portion 2g, so that the spheroidization of the bismuth is not hindered even near the conductive layer 2b, and the bismuth regions B are present in a spherical shape. Therefore, destruction of the conductive via 2d near the interface between the conductive via 2d and the conductive layer 2b can be suppressed, and failures due to disconnection can be suppressed. Thus, the printed wiring board 10 of this embodiment has excellent durability in that it can suppress failures due to disconnection of the conductive vias 2d to 4d. The durability of the printed wiring board 10 can be evaluated by measuring the defect rate and the wiring resistance increase rate through a thermal shock test using a temperature cycle tester.

[0084] It should be noted that the above-described embodiments have been described to facilitate understanding of the present invention, and are not intended to limit the present invention. Therefore, each element disclosed in the above-described embodiments is intended to include all design modifications and equivalents that fall within the technical scope of the present invention.

[0085] For example, in the above embodiment, the first to fourth wiring substrate base materials 1 to 4 are configured as so-called FPCs, which use a flexible material as the insulating substrate, but they may also be configured as so-called RPCs, which use a glass epoxy resin or the like as the insulating substrate. Also, a single-layer or multi-layer core wiring substrate may be used instead of the first wiring substrate base material 1. When forming printed wiring board 10 by stacking on first wiring substrate base material 1, core wiring substrate, etc., it is not necessary to stack all of the second to fourth wiring substrate base materials 2 to 4; it is sufficient that at least one wiring substrate base material with conductive vias is stacked.

[0086] Furthermore, at least one of the insulating substrates of the first to fourth wiring substrate base materials 1 to 4 may be made of, for example, an insulating substrate made of glass fiber impregnated with a resin adhesive, in which case adhesive layers such as adhesive layers 1c to 4c may not be provided.

[0087] In the method for producing the second wiring substrate 2 described above, the rough surface 2f generated in the through-hole 2e by laser processing is smoothed, but the target of the smoothing process is not limited to this. For example, a copper foil that has been roughened in advance according to the product or manufacturing purpose may be prepared, and after a through-hole is formed in an insulating substrate, the copper foil may be attached to close the through-hole. Even in such a case, the copper foil surface exposed in the through-hole can be smoothed.

[0088] The present invention will be described in more detail below with reference to examples, but the present invention is not limited to these examples.

[0089] Example 1 The connection structure using vias 2d shown in FIG. 11 was manufactured by the following procedure. First, a single-sided copper-clad board was prepared, in which copper foil was attached as the conductive layer 2b to the entire surface 2a1 of one side 2a1 of a polyimide resin film serving as the insulating substrate 2a. Next, a 25 μm-thick epoxy thermosetting resin film adhesive was laminated as the adhesive layer 2c on the other side of the insulating substrate 2a. Next, a 25 μm-thick polyimide resin film F was attached to the surface of the adhesive layer 2c. Next, a through hole 2e with a diameter of 60 to 120 μm was formed by laser processing, penetrating the insulating substrate 2a, the adhesive layer 2c, and the resin film F. Thereafter, a CF ４ and O ２A plasma desmear process was performed using a mixed gas of the above materials. Next, the rough surface portion 2f (bottom) of the conductive layer 2b in the through-hole 2e was smoothed by chemical wet etching to form a smooth surface portion 2g. The wet etching was performed so that the smooth surface was positioned 0.5 to 4.0 μm below the surface of the conductive layer 2b. The arithmetic mean roughness Ra of the smooth surface portion 2g was 0.03 μm, and the maximum height roughness Rz was 0.11 μm. Next, the through-hole 2e was filled with a conductive paste 2D. The conductive paste used was a Sn-Bi solder powder, a copper powder treated with silver for oxidation resistance and containing Ni and Zn as diffusion-inhibiting elements (the total content of Ni and Zn relative to 100 wt.% of the copper powder was 0.5 to 10 wt.%), and an epoxy resin, with a solder powder / copper powder weight ratio of 1.3. Next, a copper foil with a thickness of 12 μm was prepared as the conductive layer 1b. This copper foil was laminated so as to contact the protruding portion of the conductive paste 2D' and the adhesive layer 2c. The laminate thus obtained was pressed using a hot press. After increasing the pressure to 3 to 6 MPa, the temperature was increased to 160 to 180°C while maintaining the pressure, and the pressing was carried out by holding the pressure and temperature for 1 hour. This resulted in a laminate having a connection structure with vias 2d as shown in FIG. 3.

[0090] <Cross-sectional observation of conductive vias> The obtained laminate was cut in a vertical direction so as to expose the cross-sections of the conductive vias 2d. Cross-sectional images of the conductive vias 2d were obtained using a metallurgical microscope. The cross-sectional images are shown in Fig. 12(a) and Fig. 12(b). Fig. 12(a) is a cross-sectional image of the conductive vias 2d in Example 1, and Fig. 12(b) is a cross-sectional image of the vias 2d in Comparative Example 1.

[0091] <Arithmetic mean roughness Ra and maximum height roughness Rz of smooth surface portion> A cross-sectional image of the conductive via 2d obtained using a metallurgical microscope was observed, and the heights of 10 points (5 convex points and 5 concave points) with large irregularities relative to the average height on the smooth surface portion 2g of the conductive layer 2b were measured. Based on the measured values ​​of these 10 points, the arithmetic mean roughness Ra and maximum height roughness Rz of the smooth surface portion 2g were measured. The measurement results are shown in Table 1. In Table 1, the smooth surface portion 2g was referred to as the "via bottom."

[0092] <Average diameter of bismuth region B> A backscattered electron image of the cross section of the conductive via 2d was obtained using a scanning electron microscope, and the image was analyzed by the method described above to determine the average diameter of the bismuth region B. The average diameter of the bismuth region B was 4 to 7 μm.

[0093] <Temperature Cycle Test> Ninety test samples were prepared using the resulting laminate as test samples, and the resistance value of the conductive vias 2d was measured using a resistance meter. A temperature cycle test was performed on each test sample using a temperature cycle tester (product name "WINTECH", manufactured by ETAC). The test conditions were a temperature range of -40 to +85°C, a test time of 30 minutes, and 500 cycles. The resistance value of each via 2d after 500 cycles was measured using a resistance meter, and the failure rate was calculated. The failure rate is the ratio of the number of test samples with resistance failures to the total number of test samples. A resistance failure was determined when the rate of change (rate of increase) in resistance before and after the test sample was 100% or more. The results are shown in Table 1.

[0094] <High-Temperature Storage Test> Ninety test samples were prepared, and the resistance value of the conductive vias 2d was measured using a resistance meter. Each test sample was subjected to a moisture absorption reflow test in accordance with JEDEC MSL Level 3. Each test sample was then placed in a thermostatic chamber set at 150°C and left there for 250 hours. After 250 hours, the test samples were removed from the thermostatic chamber, the resistance values ​​were measured, and the defect rate was calculated. The results are shown in Table 1.

[0095] Comparative Example 1 A laminate was obtained in the same manner as in Example 1, except that the conductive layer 2b was not subjected to a smoothing treatment. Evaluations were performed in the same manner as in Example 1, except for the arithmetic mean roughness and maximum height roughness of the smooth surface portion and the average diameter of the bismuth region. In Comparative Example 1, the arithmetic mean roughness and maximum height roughness of the rough surface portion 2f were measured instead of the smooth surface portion 2g. The results are shown in Table 1.

[0096]

[0097] As shown in FIG. 12( a), in Example 1, in which the smoothing treatment was performed, a bismuth region was formed throughout the entire cross section of the conductive via 2d. The average diameter of the bismuth region B was also relatively large, at 4 to 7 μm. In particular, it was confirmed that relatively large spherical bismuth regions B were formed near the interface between the conductive via 2d and the conductive layer 2b. In Example 1, the failure rate was 0% even after the temperature cycle test and the high-temperature storage test, and the connection reliability was excellent. On the other hand, in Comparative Example 1, in which the smoothing treatment was not performed, the size of the bismuth regions B was generally smaller than that of Example 1, as shown in FIG. 12( b). In particular, it was confirmed that the formation of intermetallic compounds did not progress near the interface between the conductive via 2d and the conductive layer 2b, and the formation of spherical bismuth regions B was insufficient. In Comparative Example 1, the failure rate was high after the temperature cycle test and the high-temperature storage test, resulting in poor connection reliability.

[0098] 100... Printed wiring board 1 to 4... First wiring board base material to fourth wiring board base material 1a to 4a... Insulating substrate 1a1 to 4a1... Surface 1b to 4b... Conductive layer 1c to 4c... Adhesive layer 2d to 4d... Conductive via 2e to 4e... Through hole 2f... Surface rough part 2g... Smooth surface part 2b1... Surface part 2D, 2D' to 4D'...Conductive paste B...Bismuth region M...High melting point metal region R...Resin region

Claims

1. A printed wiring board comprising: an insulating layer having a first surface and having a through hole provided therein; a first conductor layer provided on said first surface; and a via provided in said through hole and electrically connected to said first conductor layer, wherein said first conductor layer has a surface portion that contacts said first surface of said insulating layer outside said through hole, and a smooth surface portion that contacts said via within said through hole and is smoother than said surface portion that contacts said first surface, wherein said via includes a bismuth region containing bismuth as a main component, and wherein the sum of the perimeter lengths of said bismuth regions per unit area of ​​a cross section of said via is 0.25 / μm or less.

2. A printed wiring board comprising: an insulating layer having a first surface and having a through hole provided therein; a first conductor layer provided on the first surface; and a via provided in the through hole and electrically connected to the first conductor layer, wherein the first conductor layer has a surface that contacts the first surface of the insulating layer outside the through hole, and a smooth surface portion that contacts the via within the through hole and is smoother than the surface that contacts the first surface, and the via includes a spherical bismuth region containing bismuth as a main component.

3. A printed wiring board according to claim 1 or 2, wherein the vias are formed using solder powder containing SnBi and metal powder whose main component is copper, and the compounding ratio of the solder powder to the metal powder is 0.5 to 2.0 by weight (solder powder / metal powder).

4. A printed wiring board according to claim 1 or 2, wherein the average diameter of the cross section of the bismuth region is 4 μm or more.

5. A printed wiring board according to claim 4, wherein the average diameter of the bismuth region in the cross section of the via is 7 μm or more.

6. A printed wiring board according to any one of claims 1 to 5, wherein the depth of said smooth surface portion from the contact position between said surface portion and said via is 0.5 to 4 μm.

7. A printed wiring board according to any one of claims 1 to 6, wherein the via includes a first connection surface in contact with the smooth surface portion and a second connection surface opposite the first connection surface, the printed wiring board is provided with a second conductor layer electrically connected to the via at the second connection surface, and the area of ​​the first connection surface is smaller than the area of ​​the second connection surface.

8. A method for manufacturing a printed wiring board, comprising: forming a first conductor layer on a first surface of an insulating layer; forming a through hole in the insulating layer; smoothing a portion of the first conductor layer exposed in the through hole to form a smooth surface portion; filling the through hole with a conductive paste containing bismuth; stacking a second conductor layer so that it is in contact with the conductive paste; and hot-pressing a laminate including the insulating layer, the first conductor layer, the conductive paste, and the second conductor layer to form a via, wherein the hot-pressing is carried out by increasing the pressure to a predetermined level, then increasing the temperature to a predetermined level while maintaining the pressure, and holding the predetermined pressure and temperature for 40 to 180 minutes, wherein the predetermined pressure is 3 to 6 MPa, and the predetermined temperature is 140 to 200°C.

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