Store instruction scheduling method and apparatus, device, and storage medium

Abstract

The present disclosure provides a store instruction scheduling method and apparatus, a device, and a storage medium. The solution comprises: acquiring a plurality of target cache entries; setting a status bit register and a countdown register for each target cache entry; within any clock cycle, decrementing the countdown of the register by one, and changing the status bit set for a target cache entry into which a store instruction is written; determining whether the number of occupied target cache entries is greater than or equal to a first threshold, determining whether the countdown of the countdown register is zero, and determining whether the status bit of the status bit register set for each target cache entry is equal to a second threshold, so as to obtain a second determination result, and on the basis of the second determination result, changing the status bit and resetting the countdown; and when the set status bit is equal to the second threshold, writing the store instruction cached in each target cache entry into a cache memory. Thus, there is no need to continuously occupy a cache port and bandwidth.

Description

Store instruction scheduling method and device, equipment and storage medium

[0001] Cross-reference to Related Applications

[0002] The present disclosure is based on and claims priority from Chinese Patent Application No. 202410765486.1 filed on June 14, 2024, the content of which is hereby incorporated by reference in its entirety into the present disclosure. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of computer, and particularly relates to a Store instruction scheduling method, device, equipment and storage medium. BACKGROUND

[0004] Generally, the addresses corresponding to Store instructions are continuous, and some cache memories or lower storage systems can be quickly filled by continuous Store instructions. However, in the case of multiple Store instructions, the multiple Store instructions continuously perform write operations on the cache memory or the lower storage system, which can cause the occupation of cache ports and bandwidth, and can cause the blocking of Store instruction buffer pipelines, and additional hardware overheads can occur. SUMMARY

[0005] The present disclosure aims to at least solve one of the technical problems in the related art to some extent.

[0006] To this end, a first object of the present disclosure is to provide a Store instruction scheduling method to combine multiple Store instructions and write them into a cache memory or a lower storage system together, so as to avoid unnecessary occupation of cache ports and bandwidth.

[0007] A second object of the present disclosure is to provide a Store instruction scheduling device.

[0008] A third object of the present disclosure is to provide an electronic device.

[0009] A fourth object of the present disclosure is to provide a computer-readable storage medium.

[0010] A fifth object of the present disclosure is to provide a computer program product.

[0011] To achieve the above object, the first aspect of the present disclosure provides a method for scheduling a store instruction, comprising: obtaining a plurality of target cache entries for storing data of a store instruction; setting a state bit register with a preset bit number for each target cache entry and setting a unified countdown register for the target cache entries, wherein the initial state bit of the state bit register with the preset bit number is zero, and the countdown register is set with an initial countdown; in response to any beat corresponding to the target cache entries, decreasing the countdown register by one, if the store instruction to be written into the target cache entries is received, judging whether the store instruction is written into the occupied target cache entries to obtain a first judgment result, based on the first judgment result, changing the state bit of the state bit register set for the target cache entries to which the store instruction is written, wherein the occupied target cache entries represent that the target cache entries have been written into the store instruction; in any beat, judging whether the number of the occupied target cache entries is greater than or equal to a first threshold, judging whether the countdown register is zero, and judging whether the state bit of the state bit register set for each target cache entry is equal to a second threshold to obtain a second judgment result, based on the second judgment result, changing the state bit of the state bit register set for each target cache entry and resetting the countdown register; for each target cache entry, if the state bit of the state bit register set for the target cache entry is equal to the second threshold, writing the data stored by the store instruction cached in the target cache entry into a cache memory or a lower storage system at one time.

[0012] To achieve the above object, the second aspect of the present disclosure provides a storage instruction scheduling device, comprising: a first obtaining module, configured to obtain a plurality of target cache items for caching data stored by a storage instruction; a setting module, configured to set a state bit register with a preset bit number for each target cache item and set a unified countdown register for the target cache items, wherein the initial state bit of the state bit register with the preset bit number is zero, and the countdown register is set with an initial countdown; a first changing module, configured to, in response to any beat corresponding to the target cache item, decrease the countdown register by one, and if the storage instruction to be written into the target cache item is received, judge whether the storage instruction is written into the occupied target cache item to obtain a first judgment result, and based on the first judgment result, change the state bit of the state bit register set for the target cache item to which the storage instruction is written; a second changing module, configured to, in any beat, judge whether the number of occupied target cache items is greater than or equal to a first threshold, judge whether the countdown register is zero, and judge whether the state bit of the state bit register set for each target cache item is equal to a second threshold to obtain a second judgment result, and based on the second judgment result, change the state bit of the state bit register set for each target cache item and reset the countdown register; and a writing module, configured to, for each target cache item, if the state bit of the state bit register set for the target cache item is equal to the second threshold, write the data stored by the storage instruction cached by the target cache item into a cache memory or a lower storage system at one time.

[0013] To achieve the above object, the third aspect of the present disclosure provides an electronic device, comprising: a processor and a memory connected with the processor in communication; the memory stores computer execution instructions; and the processor executes the computer execution instructions stored in the memory to implement the storage instruction scheduling method disclosed by the embodiments of the present disclosure.

[0014] To achieve the above object, the fourth aspect of the present disclosure provides a computer readable storage medium, wherein the computer readable storage medium stores computer execution instructions, and the computer execution instructions are executed by a processor to implement the storage instruction scheduling method disclosed by the embodiments of the present disclosure.

[0015] To achieve the above object, the fifth aspect of the present disclosure provides a computer program product, comprising a computer program, which, when executed by a processor, implements the storage instruction scheduling method disclosed by the embodiments of the present disclosure.

[0016] The storage number instruction scheduling method, device, electronic equipment and storage medium provided by the present disclosure include the following steps: obtaining a plurality of target cache items for buffering data stored by a storage number instruction; setting a state bit register with a preset bit number for each target cache item and setting a unified countdown register for the target cache items; in response to any beat corresponding to the target cache items, decreasing the countdown register by one; if a storage number instruction to be written into the target cache items is received, determining whether the storage number instruction is written into an occupied target cache item to obtain a first determination result; based on the first determination result, changing the state bit of the state bit register set for the target cache item to which the storage number instruction is written; in any beat, determining whether the number of occupied target cache items is greater than or equal to a first threshold, determining whether the countdown of the countdown register is zero, and determining whether the state bit of the state bit register set for each target cache item is equal to a second threshold to obtain a second determination result; based on the second determination result, changing the state bit of the state bit register set for each target cache item and resetting the countdown of the countdown register; for each target cache item, if the state bit of the state bit register set for the target cache item is equal to the second threshold, writing the data stored by the storage number instruction buffered by the target cache item into a cache memory or a lower storage system at one time. Thus, the state bit register is set for each target cache item of the storage number instruction buffer, and a unified countdown register is set. The state bit of the state bit register set for each target cache item can be used to monitor the storage number instruction written into the target cache item. When the storage number instruction buffer reaches a certain number of occupied target cache items, the plurality of storage number instructions written into the target cache items are combined and written into the cache memory or the lower storage system at one time, without constantly occupying the cache port and bandwidth, thereby reducing the blocking of the pipeline caused by the storage number instruction buffer.

[0017] Additional aspects and advantages of the present disclosure will be made apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure, together with the description.

[0019] FIG. 1 is a flowchart of a storage number instruction scheduling method according to an embodiment of the present disclosure;

[0020] FIG. 2 is a flowchart of a storage number instruction scheduling method according to an embodiment of the present disclosure;

[0021] Fig. 3 is a structural schematic diagram of a store instruction scheduling apparatus provided by an embodiment of the present disclosure;

[0022] Fig. 4 is a structural schematic diagram of an electronic device provided by an embodiment of the present disclosure.

[0023] The above-described figures have shown specific embodiments of the present disclosure, which will be described in more detail hereinafter. These figures and the written description are not intended to limit the scope of the present disclosure in any way, but to illustrate the concept of the present disclosure to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0024] The exemplary embodiments will be described in detail herein with reference to the attached drawings. Unless otherwise indicated, the same numbers on different drawings represent the same or similar elements. The following detailed description does not limit the present disclosure in any way. Instead, it is intended to provide an example of apparatus and methods in accordance with the present disclosure as detailed in the appended claims.

[0025] It should be noted that the acquisition, storage, use, processing, etc. of data in the technical solutions of the present disclosure comply with relevant provisions of national laws and regulations.

[0026] The technical solutions of the present disclosure and how the technical solutions of the present disclosure solve the above-mentioned technical problems will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described again in some embodiments. The embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0027] Fig. 1 is a flowchart of a store instruction scheduling method provided by an embodiment of the present disclosure.

[0028] As shown in Fig. 1, the method comprises the following steps:

[0029] Step 101, acquiring a plurality of target cache items for caching data stored by a store instruction.

[0030] It should be noted that the store instruction scheduling method provided by the embodiments of the present disclosure can be executed by a store instruction scheduling apparatus (also referred to as a store instruction scheduler), wherein the store instruction scheduling apparatus can be implemented by software and / or hardware. The store instruction scheduling apparatus can be an electronic device or can be configured in an electronic device to implement the store instruction scheduling function.

[0031] In the embodiments of the present disclosure, the store instruction scheduling method is configured in an electronic device as an example.

[0032] The electronic device can be any device with computing capability, such as a personal computer, a mobile terminal, a server, etc. The mobile terminal can be a vehicle-mounted device, a mobile phone, a tablet computer, a personal digital assistant, a wearable device, etc. The mobile terminal has various operating systems, touch screens, and / or display screens.

[0033] It can be understood that there are multiple target cache items in the store instruction buffer, and each target cache item is used to cache data stored by a store instruction. One target cache item can cache multiple store instructions.

[0034] In step 102, a state bit register with a preset number of bits is set for each target cache item, and a unified countdown register is set for the target cache item. The initial state bit of the state bit register with a preset number of bits is zero, and the initial countdown of the countdown register is set.

[0035] It can be understood that the specific value of the preset number of bits can be pre-set according to actual conditions, and the specific value of the preset number of bits is not specifically limited in this embodiment.

[0036] It can be understood that the specific value of the initial countdown of the countdown register can be pre-set according to actual needs, and the specific value of the preset number of bits is not specifically limited in this embodiment.

[0037] For example, the value of the initial countdown can be set to 1024, and the countdown register starts counting down from 1024.

[0038] In step 103, in response to any beat corresponding to the target cache item, the countdown register is decremented by one. If a store instruction to be written into the target cache item is received, it is determined whether the store instruction is written into the occupied target cache item to obtain a first determination result. Based on the first determination result, the state bit of the state bit register set for the target cache item to which the store instruction is written is changed. The occupied target cache item indicates that the target cache item has been written with a store instruction.

[0039] It should be noted that one beat refers to one clock cycle of the processor, and the state jump of the pipeline in the processor is in units of clock cycles.

[0040] In some examples, the memory number instruction to be written into the target cache item is obtained, the address corresponding to the memory number instruction to be written is compared with the address of each target cache item, if there is a target cache item address same as the address corresponding to the memory number instruction, it is determined that the memory number instruction is written into the occupied target cache item, if there is no target cache item address same as the address corresponding to the memory number instruction, the memory number instruction is written into an unoccupied target cache item, and the address of the target cache item where the memory number instruction is written is set as the address corresponding to the memory number instruction.

[0041] In the present example, in the case that the first determination result indicates that the memory number instruction is written into the occupied target cache item, the state bit of the state bit register set for the target cache item where the written memory number instruction is located is reset to zero.

[0042] Correspondingly, in the case that the first determination result indicates that the memory number instruction is written into the unoccupied target cache item, a positive integer is randomly selected from the value range greater than zero to less than or equal to the third threshold value, and the state bit of the state bit register set for the target cache item where the written memory number instruction is located is reset to the positive integer, wherein the third threshold value is a positive integer, and the unoccupied target cache item means that the target cache item has not been written with the memory number instruction.

[0043] In some examples, the preset bit number of the state bit register set for each target cache item is obtained, the preset bit number is calculated to determine the first numerical result, the first numerical result is reduced by one to determine the second threshold value, and the first numerical result is reduced by two to determine the third threshold value.

[0044] For example, the first numerical result can be expressed by the formula: 2 k = n, wherein k represents the preset bit number, n represents the first numerical result, the second threshold value can be represented as n-1, and the third threshold value can be represented as n-2.

[0045] In step 104, whether the number of occupied target cache items is greater than or equal to the first threshold value, whether the countdown of the countdown register is zero, and whether the state bit of the state bit register set for each target cache item is equal to the second threshold value are determined in any shot to obtain a second determination result, based on the second determination result, the state bit of the state bit register set for each target cache item is changed, and the countdown of the countdown register is reset.

[0046] In the present example, in the case where the second determination result indicates that the countdown register countdown is not zero, the number of occupied target cache entries is greater than or equal to the first threshold value, and there is no target cache entry in which the state bit of the state bit register set by the target cache entry is equal to the second threshold value, the state bit of the state bit register set by each target cache entry is incremented by one, and the countdown register countdown is reset to the initial countdown, or, in the current beat, the state bit of the state bit register set by each target cache entry is continuously incremented by one until there is a target cache entry in which the state bit of the state bit register set by the target cache entry is equal to the second threshold value, and the countdown register countdown is reset to the initial countdown.

[0047] In the present example, in the case where the second determination result indicates that the countdown register countdown is zero, and there is no target cache entry in which the state bit of the state bit register set by the target cache entry is equal to the second threshold value, the state bit of the state bit register set by each target cache entry is incremented by one, and the countdown register countdown is reset to the initial countdown.

[0048] In some examples, in the case where the number of occupied target cache entries is greater than or equal to the first threshold value in any beat, the countdown register countdown is reset to the initial countdown.

[0049] It should be noted that the first threshold value can be pre-set according to actual needs, which will not be described here.

[0050] For example, if the storage instruction buffer has 32 target cache entries in total, the first threshold value is set to 16 entries, and in the case where the number of occupied target cache entries in the storage instruction buffer is greater than or equal to 16 entries, the countdown register countdown is reset to the initial countdown 1024.

[0051] In the present example, after the state bit of the target cache entry equal to the second threshold value is continuously incremented by one in the current beat until there is a target cache entry in which the state bit of the state bit register set by the target cache entry is equal to the second threshold value, and the countdown register countdown is reset to the initial countdown, the data stored by the storage instruction cached by the target cache entry with the state bit equal to the second threshold value is written to the cache memory or the lower-level storage system at one time.

[0052] Step 105, for each target cache entry, in the case where the state bit of the state bit register set by the target cache entry is equal to the second threshold value, the data stored by the storage instruction cached by the target cache entry is written to the cache memory or the lower-level storage system at one time.

[0053] For example, if each target cache item is to be written into a 512-bit cache block (Cache block) and a 39-bit physical address storage instruction buffer, because the 512-bit Cache block is 64 bytes (2 8 = 64) within the block, the Cache block offset address Block_offset is 8 bits, the Cache block address Block_paddr is 31 bits, the 512-bit Cache block corresponds to 64 bytes (1 byte is 8 bits), the byte mask (Bytemask) is 64 bits, which corresponds to 64 bytes, indicating whether the target cache item is written by the storage instruction. Bytemask is 0, indicating that the target cache item has not been written by the storage instruction, Bytemask is 1, indicating that the target cache item has been written by the storage instruction, and when Bytemask is all 1, it indicates that the Cache block has been fully written by the storage instruction. The fields of the storage instruction buffer are shown in Table 1:

[0054] Table 1: Storage instruction buffer field table

[0055] In this example, the storage instruction buffer has 32 target cache items. When the processor is initialized, the valid bit of each target cache item is set to 0. The operating system writes the control and status register to set the initial value of the countdown counter register to 1024, and the first threshold is 16 items.

[0056] It can be understood that the Cache block offset address Block_offset is used to indicate the 64-byte position of the Cache block.

[0057] It should be noted that in this example, the fields of the storage instruction buffer are represented by hexadecimal numbers, and the storage instruction buffer status bit register is 4 bits, so n is 4 times the power of 2, i.e. n is equal to 16.

[0058] It should be noted that when the storage instruction is written to the target cache item, the storage instruction can be collected. As shown in Table 1 above, the item with a block address of 0xffffffffffffffff has been collected into a cache line, and when the status bit is n-1, i.e. f (decimal 15), the target cache item is written into the cache memory.

[0059] The method provided by the embodiment of the present disclosure comprises the following steps: obtaining a plurality of target cache items used for buffering data stored by a store number instruction; setting a state bit register with a preset bit number for each target cache item and setting a unified countdown register for the target cache item; in response to any beat corresponding to the target cache item, decreasing the countdown register by one; if a store number instruction to be written into the target cache item is received, determining whether the store number instruction is written into an occupied target cache item to obtain a first determination result; based on the first determination result, changing the state bit of the state bit register set for the target cache item to which the store number instruction is written; in any beat, determining whether the number of occupied target cache items is greater than or equal to a first threshold, determining whether the countdown of the countdown register is zero, and determining whether the state bit of the state bit register set for each target cache item is equal to a second threshold to obtain a second determination result; based on the second determination result, changing the state bit of the state bit register set for each target cache item and resetting the countdown of the countdown register; for each target cache item, if the state bit of the state bit register set for the target cache item is equal to the second threshold, writing the data stored by the store number instruction buffered by the target cache item into a cache memory or a lower storage system at one time, thereby setting a state bit register for each target cache item of the store number instruction buffer and setting a unified countdown register; through the state bit of the state bit register set for each target cache item, the store number instruction written into the target cache item can be monitored; when the store number instruction buffer reaches a certain number of occupied target cache items, the plurality of store number instructions written into the target cache item are combined and written into the cache memory or the lower storage system at one time, without constantly occupying the cache port and bandwidth, thereby reducing the blocking of the pipeline caused by the store number instruction buffer.

[0060] In some examples, in order to avoid the situation that the plurality of store number instructions buffered in the target cache item cannot fill the entire cache memory, thereby being written into the cache memory or the lower storage system respectively, resulting in excessive port occupation and bandwidth waste, the state bit of the state bit register set for the target cache item can be adjusted when the state bit of the state bit register set for the target cache item has not reached the second threshold, and the plurality of store number instructions can also be collected and written into the same cache memory or lower storage system.

[0061] Based on the above embodiments, in order to clearly understand the adjustment of the status bit of the status bit register set by the target cache item when the status bit of the status bit register set by the target cache item has not yet reached the second threshold, the following is an exemplary description with reference to Figure 2.

[0062] Figure 2 is a flowchart of the data storage instruction scheduling method provided in the embodiments of this disclosure.

[0063] As shown in Figure 2, the method may include:

[0064] Step 201: If a request instruction is received instructing the storage instructions of each target cache item to be written to the cache memory or the lower-level storage system, the status bit of the status bit register of each target cache item is set to the second threshold.

[0065] Step 202: When the status bit of the status bit register set in each target cache item is equal to the second threshold, write the cached data instruction of each target cache item to the cache memory or the lower-level storage system.

[0066] It is understandable that multiple store instructions cached within the same target cache entry correspond to the same cache memory or underlying storage system.

[0067] This disclosure provides a data storage instruction scheduling method. If a request instruction is received instructing that all data storage instructions cached in each target cache entry be written to a cache memory or underlying storage system, the status bits of the status registers for each target cache entry are set to a second threshold. When the status bits of the status registers for each target cache entry are equal to the second threshold, the data storage instructions cached in each target cache entry are written to the cache memory or underlying storage system. Therefore, by adjusting the status bits of the status registers for each target cache entry to the second threshold, multiple data storage instructions can be collected and written to the same cache memory or underlying storage system even when multiple data storage instructions cached in each target cache entry cannot fill the corresponding cache memory or underlying storage system.

[0068] Figure 3 is a schematic diagram of the structure of a data storage instruction scheduling device provided in an embodiment of this disclosure.

[0069] As shown in Figure 3, the data storage instruction scheduling device 300 includes: a first acquisition module 301, a setting module 302, a first change module 303, a second change module 304, a third change module 305, and a writing module 306.

[0070] The first acquisition module 301 is used to acquire multiple target cache entries for the data stored by the cache storage instruction;

[0071] The setting module 302 is configured to set a preset number of status bit registers for each target cache item and set a unified countdown register for the target cache item, wherein the initial status bit of the preset number of status bit registers is zero, and the countdown register is set with an initial countdown;

[0072] The first changing module 303 is configured to decrease the countdown register by one in response to any beat corresponding to the target cache item, and if a storage number instruction to be written into the target cache item is received, to determine whether the storage number instruction is written into the occupied target cache item to obtain a first determination result, and to change the status bit of the status bit register set for the target cache item to which the storage number instruction is written based on the first determination result, wherein the occupied target cache item indicates that the target cache item has been written with the storage number instruction.

[0073] The second changing module 304 is configured to determine whether the number of the occupied target cache items is greater than or equal to a first threshold, whether the countdown register is zero, and whether the status bit of the status bit register set for each target cache item is equal to a second threshold in any beat to obtain a second determination result, and to change the status bit of the status bit register set for each target cache item and reset the countdown register based on the second determination result.

[0074] The writing module 305 is configured to write the data stored in the storage number instruction cached by each target cache item into the cache memory or the lower storage system at one time in the case that the status bit of the status bit register set for the target cache item is equal to the second threshold.

[0075] In an embodiment of the application, the second changing module 304 comprises:

[0076] The first changing unit 3041 is configured to increase the status bit of the status bit register set for each target cache item by one and reset the countdown register to the initial countdown in the case that the second determination result indicates that the countdown register is not zero, the number of the occupied target cache items is greater than or equal to the first threshold, and there is no target cache item whose status bit of the status bit register is equal to the second threshold among the target cache items, or to increase the status bit of the status bit register set for each target cache item by one in the current beat until there is a target cache item whose status bit of the status bit register is equal to the second threshold, and reset the countdown register to the initial countdown, wherein the second threshold is a positive integer.

[0077] The second changing unit 3042 is configured to, in a case where the second determination result indicates that the countdown register countdown is zero and the state bit of the state bit register set by each target cache item is equal to the second threshold value, increase the state bit of the state bit register set by each target cache item by one, and reset the countdown register countdown to the initial countdown.

[0078] In an embodiment of the application, the first changing module 303 is specifically configured to:

[0079] In a case where the first determination result indicates that the store number instruction is written into the target cache item that has been occupied, the state bit of the state bit register set by the target cache item to which the store number instruction is written is reset to zero;

[0080] In a case where the first determination result indicates that the store number instruction is written into the target cache item that has not been occupied, a positive integer is randomly selected from a value range greater than zero and less than or equal to the third threshold value, and the state bit of the state bit register set by the target cache item to which the store number instruction is written is reset to the positive integer, where the third threshold value is a positive integer, and the target cache item that has not been occupied indicates that the target cache item has not been written into the store number instruction.

[0081] In an embodiment of the application, in the current beat, the state bit of the state bit register set by each target cache item is increased by one until the state bit of the state bit register set by the target cache item is equal to the second threshold value, and the countdown register countdown is reset to the initial countdown, where the second threshold value is a positive integer. After that, the writing module 305 is specifically configured to:

[0082] In a case where the state bit of the state bit register set by the target cache item is equal to the second threshold value, the data stored by the store number instruction cached by the target cache item is written into the cache memory or the lower storage system at one time.

[0083] In an embodiment of the application, in any beat, the device further comprises a fourth changing module 306, which is specifically configured to

[0084] In a case where the number of the target cache items that have been occupied is greater than or equal to the first threshold value, the countdown register countdown is reset to the initial countdown.

[0085] In an embodiment of the application, the device further comprises a fifth changing module 307, which is specifically configured to:

[0086] If the request instruction indicates that the store number instruction cached by each target cache item is written into the cache memory or the lower storage system, the state bit of the state bit register set by each target cache item is set to the second threshold value;

[0087] The writing module 305 is specifically configured to write the count instruction cached by each target cache item into the cache memory or the lower storage system in a case where the state bit of the state bit register set for each target cache item is equal to the second threshold value.

[0088] In an embodiment of the application, the device further comprises a determining module 308, which is specifically configured to:

[0089] acquire a preset bit number of the state bit register set for each target cache item;

[0090] perform calculation on the preset bit number to determine a first numerical result;

[0091] perform subtraction one on the first numerical result to determine a second threshold value;

[0092] perform subtraction two on the first numerical result to determine a third threshold value.

[0093] The count instruction scheduling device provided by the embodiments of the present disclosure can be used to execute the technical solutions of the count instruction scheduling method in the above embodiments, and the implementation principles and technical effects are similar, which will not be described here again.

[0094] The storage number instruction scheduling device provided by the embodiment of the present disclosure includes: obtaining a plurality of target cache items used for caching data stored by a storage number instruction; setting a state bit register with a preset bit number for each target cache item and setting a unified countdown register for the target cache items; in response to any beat corresponding to the target cache items, decreasing the countdown register by one, and if a storage number instruction to be written into the target cache items is received, judging whether the storage number instruction is written into an occupied target cache item to obtain a first judgment result, and based on the first judgment result, changing the state bit of the state bit register set for the target cache item to which the storage number instruction is written; in any beat, judging whether the number of occupied target cache items is greater than or equal to a first threshold, judging whether the countdown of the countdown register is zero, and judging whether the state bit of the state bit register set for each target cache item is equal to a second threshold to obtain a second judgment result, based on the second judgment result, changing the state bit of the state bit register set for each target cache item and resetting the countdown of the countdown register; for each target cache item, if the state bit of the state bit register set for the target cache item is equal to the second threshold, the data stored by the storage number instruction cached by the target cache item is written into a cache memory or a lower storage system at one time, thereby setting a state bit register for each target cache item of the storage number instruction buffer and setting a unified countdown register, and through the state bit of the state bit register set for each target cache item, the storage number instruction written into the target cache item can be monitored, when the storage number instruction buffer reaches a certain number of occupied target cache items, the plurality of storage number instructions written into the target cache items are combined and written into the cache memory or the lower storage system at one time, without constantly occupying the cache port and bandwidth, and the blocking of the pipeline caused by the storage number instruction buffer is reduced.

[0095] FIG. 4 is a structural schematic diagram of an electronic device provided by the embodiment of the present disclosure. As shown in FIG. 4, the electronic device can include a memory 401, a processor 402, and computer instructions stored on the memory 401 and executable on the processor 402.

[0096] The processor 402 implements the storage number instruction scheduling method provided in the above embodiment when executing the instructions.

[0097] Further, the electronic device 400 further includes:

[0098] The communication interface 403 is used for communication between the memory 401 and the processor 402.

[0099] The memory 401 is used for storing computer instructions executable on the processor 402.

[0100] The memory 401 can include a high-speed RAM memory, and can also include a non-volatile memory, for example, at least one disk memory.

[0101] The processor 402 is configured to execute a program to implement the memory instruction scheduling method provided in the above embodiments.

[0102] If the memory 401, the processor 402 and the communication interface 403 are implemented independently, the communication interface 403, the memory 401 and the processor 402 can be connected to each other through a bus and complete communication between each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For convenience of representation, only one thick line is used in FIG. 4, but it does not mean that there is only one bus or only one type of bus.

[0103] Optionally, in a specific implementation, if the memory 401, the processor 402 and the communication interface 403 are integrated on a chip, the memory 401, the processor 402 and the communication interface 403 can complete communication between each other through an internal interface.

[0104] The processor 402 can be a Central Processing Unit (CPU), or an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present disclosure.

[0105] The embodiments of the present disclosure further provide a chip for running instructions, which is configured to execute the memory instruction scheduling method in the above embodiments.

[0106] The embodiments of the present disclosure further provide a computer readable storage medium, which stores computer instructions, and when the computer instructions run on a computer, the computer executes the memory instruction scheduling method in the above embodiments.

[0107] The embodiment of the present disclosure further provides a computer program product, which comprises a computer program stored in a computer readable storage medium, at least one processor can read the computer program from the computer readable storage medium, and the at least one processor can implement the storage instruction scheduling method in the above embodiment when executing the computer program.

[0108] In the description of the present disclosure, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise explicitly and specifically limited.

[0109] In the description of the present disclosure, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the present description, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in the present description and the features of the different embodiments or examples without contradiction.

[0110] Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present disclosure, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A method for scheduling a store instruction, the method comprising: obtaining a plurality of target cache entries for caching data stored by a store instruction; setting a state bit register with a preset number of bits for each of the target cache entries and setting a unified countdown register for the target cache entries, wherein an initial state bit of the state bit register is zero and the countdown register is set with an initial countdown; in response to any tick corresponding to the target cache entries, decrementing the countdown register by one, and if the store instruction to be written into the target cache entries is received, determining whether the store instruction is written into the occupied target cache entries to obtain a first determination result, and based on the first determination result, changing the state bit of the state bit register set for the target cache entries to which the store instruction is written; in any tick, determining whether the number of the occupied target cache entries is greater than or equal to a first threshold, determining whether the countdown register is zero, and determining whether the state bit of the state bit register set for each of the target cache entries is equal to a second threshold to obtain a second determination result, based on the second determination result, changing the state bit of the state bit register set for each of the target cache entries and resetting the countdown register; and in the case that the state bit of the state bit register set for each of the target cache entries is equal to the second threshold, writing the data stored by the store instruction cached in the target cache entries into a cache memory or a lower storage system at one time. The changing the state bit of the state bit register set for each of the target cache entries and the resetting the countdown register based on the second determination result comprises: in the case that the second determination result indicates that the countdown register is not zero, the number of the occupied target cache entries is greater than or equal to the first threshold, and there is no target cache entry in each of the target cache entries in which the state bit of the state bit register set for the target cache entry is equal to the second threshold, adding one to the state bit of the state bit register set for each of the target cache entries and resetting the countdown register to the initial countdown, or, in the current tick, constantly adding one to the state bit of the state bit register set for each of the target cache entries until there is the target cache entry in which the state bit of the state bit register set for the target cache entry is equal to the second threshold, and resetting the countdown register to the initial countdown, wherein the second threshold is a positive integer. ​ ​ ​ ​ 2. The method of claim 1, wherein, ​ ​ in a case where the second judgment result indicates that the state bit of the state bit register set by the target cache entry is equal to a second threshold value in a case where the countdown register countdown is zero and in each of the target cache entries, the state bit of the state bit register set by the target cache entry is equal to the second threshold value, the state bit of the state bit register set by each of the target cache entries is incremented by one, and the countdown register countdown is reset to the initial countdown.

3. The method of claim 1 or 2, wherein, The first judgment result is based on the first judgment result, the state bit of the state bit register set by the target cache entry written into the store instruction is changed, and the occupied target cache entry is used to indicate that the target cache entry has been written into the store instruction. In a case where the first judgment result indicates that the store instruction is written into the occupied target cache entry, the state bit of the state bit register set by the target cache entry written into the store instruction is reset to zero. In a case where the first judgment result indicates that the store instruction is written into the unoccupied target cache entry, a positive integer is randomly selected from a value range greater than zero to less than or equal to a third threshold value, and the state bit of the state bit register set by the target cache entry written into the store instruction is reset to the positive integer, wherein the third threshold value is a positive integer, and the unoccupied target cache entry is used to indicate that the target cache entry has not been written into the store instruction.

4. The method of claim 2, wherein, The state bit of the state bit register set by each of the target cache entries is incremented by one in the current frame until there is a case where the state bit of the state bit register set by the target cache entry is equal to a second threshold value, and the countdown register countdown is reset to the initial countdown, wherein the second threshold value is a positive integer. In a case where the state bit of the state bit register set by the target cache entry is equal to a second threshold value, the data stored by the store instruction cached by the target cache entry is written into the cache memory or the lower storage system at one time.

5. The method of any one of claims 1-4, wherein, In any frame, including: In a case where the number of occupied target cache entries is greater than or equal to a first threshold value, the countdown register countdown is reset to the initial countdown.

6. The method of any one of claims 1-4, wherein, The method comprises: If the request instruction indicates that the store instruction cached by each of the target cache entries is written into the cache memory or the lower storage system, the state bit of the state bit register set by each of the target cache entries is set to a second threshold value. In a case where the state bit of the state bit register set by each of the target cache entries is equal to a second threshold value, the store instruction cached by each of the target cache entries is written into the cache memory or the lower storage system.

7. The method of claim 3, wherein, The second threshold value and the third threshold value, including: Obtaining a preset bit number of the state bit register set by each of the target cache entries; The preset bit number is calculated to determine a first numerical result; The first numerical result is decremented by one to determine the second threshold value; Subtracting two from the first numerical result to determine the third threshold value.

8. An apparatus for scheduling a store instruction, comprising: a first obtaining module, configured to obtain a plurality of target cache entries for caching data stored by a store instruction; a setting module, configured to set a preset number of state bit registers for each of the target cache entries and set a unified countdown register for the target cache entries, wherein an initial state bit of the state bit register is zero and the countdown register is set with an initial countdown; a first changing module, configured to, in response to any beat corresponding to the target cache entry, decrease the countdown register by one, and, if the store instruction to be written into the target cache entry is received, determine whether the store instruction is written into the occupied target cache entry to obtain a first determination result, and change a state bit of the state bit register set for the target cache entry to which the store instruction is written based on the first determination result, wherein the occupied target cache entry indicates that the target cache entry has been written into the store instruction; a second changing module, configured to, in any beat, determine whether a number of the occupied target cache entries is greater than or equal to a first threshold value, determine whether the countdown register is zero, and determine whether the state bit of the state bit register set for each of the target cache entries is equal to a second threshold value to obtain a second determination result, change the state bit of the state bit register set for each of the target cache entries and reset the countdown register based on the second determination result; a writing module, configured to, for each of the target cache entries, write data stored by the store instruction cached by the target cache entry into a cache memory or a lower storage system at one time when the state bit of the state bit register set for the target cache entry is equal to the second threshold value.

9. An electronic device, comprising: a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the store instruction scheduling method according to any one of claims 1-7 when executing the computer program.

10. A computer readable storage medium, having a computer program stored thereon, wherein the computer program is executable on a processor to implement the store instruction scheduling method according to any one of claims 1-7.

11. A computer program product, comprising a computer program, wherein the computer program is executable on a processor to implement the store instruction scheduling method according to any one of claims 1-7.

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