Image sensor, imaging device, and image-sensor control method

Abstract

The present invention improves read speed in a column-based analog to digital converter (ADC)-type image sensor.　A pre-stage circuit sequentially generates: a reset level when a floating diffusion layer is initialized; and a signal level when a signal charge is transferred. A first capacitive element holds the reset level. A second capacitive element holds the signal level. A short-circuit transistor short-circuits one end of each of the first and second capacitive elements when the signal level exceeds a prescribed threshold. A post-stage circuit sequentially outputs the reset level and the signal level.

Description

Image sensor, imaging device, and method for controlling image sensor

[0001] The present technology relates to an image sensor, and more particularly to an image sensor that performs analog-to-digital (AD) conversion for each column, an imaging device, and a method for controlling the image sensor.

[0002] Conventionally, in image sensors, in order to miniaturize pixels, a column ADC (Analog to Digital Converter) method has been used in which an ADC is arranged for each column outside a pixel array unit and pixel signals are read out row by row. For example, an image sensor has been proposed that switches a floating diffusion (FD) capacitance depending on illuminance and reads out pixel signals using the column ADC method (see, for example, Patent Document 1). This image sensor reads out the signal level for each row, determines whether the illuminance is high or not when the readout is completed, switches the FD capacitance depending on the determination result, and reads out the signal level again.

[0003] Japanese Patent Application Laid-Open No. 2022-000945

[0004] In the conventional technology described above, the dynamic range is expanded by switching the FD capacitance according to the illuminance, but the image sensor needs to read out the signal level twice for each row, which results in a slower readout speed compared to when the signal level is read out only once for each row.

[0005] This technology was developed in light of these circumstances, and aims to improve the readout speed in a column ADC type image sensor.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof relates to an image sensor and a control method thereof, including: a front-stage circuit that sequentially generates a reset level when a floating diffusion layer is initialized and a signal level when a signal charge is transferred, a first capacitive element that holds the reset level, a second capacitive element that holds the signal level, a short-circuiting transistor that short-circuits one end of each of the first and second capacitive elements when the signal level exceeds a predetermined threshold, and a rear-stage circuit that sequentially outputs the reset level and the signal level, thereby improving the readout speed.

[0007] In addition, in this first aspect, the display device may further include a selection circuit that selects one of the one ends of the first and second capacitance elements and connects it to the subsequent circuit, and the other ends of the first and second capacitance elements are commonly connected to the previous circuit, thereby providing an effect that the first and second capacitance elements are connected in parallel to the subsequent circuit under high illuminance.

[0008] In addition, in this first aspect, a determination circuit may be further provided that determines whether the signal level exceeds the threshold and outputs the determination result to the short-circuit transistor as a first determination result, thereby providing the effect of determining illuminance for each column.

[0009] In addition, in this first aspect, the display device may further include an analog-to-digital converter that converts the reset level and the signal level into digital signals in sequence, and a correction circuit that corrects the digital signals based on the first determination result, thereby achieving the effect of correcting the digital signals under high illuminance conditions.

[0010] In addition, in this first aspect, the determination circuit may further determine whether the reset level exceeds a predetermined threshold and output the determination result as a second determination result, and the correction circuit may correct the digital signal based on each of the first and second determination results, thereby preventing the occurrence of sunspots.

[0011] In addition, in the first aspect, a selection transistor may be further provided that opens and closes a path between the one end of one of the first and second capacitance elements and the short-circuiting transistor in accordance with a predetermined selection signal, thereby preventing the signal level from being destroyed by a short circuit before reading.

[0012] In addition, in this first aspect, the circuit may further include a first selection transistor that opens and closes a path between the one end of the first capacitance element and the short-circuiting transistor in accordance with a predetermined selection signal, and a second selection transistor that opens and closes a path between the one end of the second capacitance element and the short-circuiting transistor in accordance with the selection signal, thereby preventing a signal level from being destroyed by a short circuit before readout and ensuring symmetry of the circuit.

[0013] In addition, in this first aspect, the display device may further include a selection circuit that selects one of one ends of the first and second capacitance elements and connects it to a node between the upstream circuit and the downstream circuit, and the other ends of the first and second capacitance elements are connected to a predetermined power supply voltage, thereby providing an effect that the first and second capacitance elements are connected in parallel to the downstream circuit under high illuminance.

[0014] According to a second aspect of the present technology, there is provided an imaging device including: a front-stage circuit that sequentially generates a reset level when a floating diffusion layer is initialized and a signal level when a signal charge is transferred, a first capacitance element that holds the reset level, a second capacitance element that holds the signal level, a short-circuiting transistor that short-circuits one end of each of the first and second capacitance elements when the signal level exceeds a predetermined threshold, a rear-stage circuit that sequentially outputs the reset level and the signal level, and a signal processing circuit that processes the output reset level and signal level, thereby improving the readout speed of the imaging device.

[0015] 1 is a block diagram showing an example of a configuration of an imaging device according to a first embodiment of the present technology. FIG. 2 is a block diagram showing an example of a configuration of an image sensor according to the first embodiment of the present technology. FIG. 3 is a circuit diagram showing an example of a configuration of a pixel according to the first embodiment of the present technology. FIG. 4 is a circuit diagram showing an example of a configuration of a pixel to which a selection transistor is added according to the first embodiment of the present technology. FIG. 5 is a block diagram showing an example of a configuration of a column signal processing circuit according to the first embodiment of the present technology. FIG. 6 is a circuit diagram showing an example of a configuration of a column circuit according to the first embodiment of the present technology. FIG. 7 is a timing chart showing an example of a global shutter operation of the image sensor according to the first embodiment of the present technology. FIG. 8 is a timing chart showing an example of a readout operation according to the first embodiment of the present technology. FIG. 9 is a timing chart showing an example of a readout operation in a comparative example. FIG. 10 is a flowchart showing an example of operation of the image sensor according to the first embodiment of the present technology. FIG. 11 is a flowchart showing an example of a correction process according to the first embodiment of the present technology. FIG. 12 is a circuit diagram showing an example of a configuration of a pixel according to a third embodiment of the present technology. It is a block diagram showing an example of a schematic configuration of a vehicle control system.It is an explanatory diagram showing an example of installation positions of an outside-vehicle information detection unit and an imaging unit.

[0016] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example in which one end of each of a pair of capacitance elements is short-circuited under high illuminance) 2. Second embodiment (an example in which one end of each of a pair of capacitance elements is short-circuited under high illuminance, and the presence or absence of sunspots is determined) 3. Third embodiment (an example in which one end of each of a pair of capacitance elements is short-circuited under high illuminance, and the other end of each is connected to a power supply voltage) 4. Example of application to a mobile body

[0017] 1 is a block diagram showing an example of the configuration of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 is a device that captures image data, and includes an imaging lens 110, an image sensor 200, a recording unit 120, and an imaging control unit 130. The imaging device 100 is assumed to be a digital camera or an electronic device with an imaging function (such as a smartphone or a personal computer).

[0018] The image sensor 200 captures image data under the control of the imaging control unit 130. The image sensor 200 supplies the image data to the recording unit 120 via a signal line 209.

[0019] The imaging lens 110 focuses light and guides it to the image sensor 200. The imaging control unit 130 controls the image sensor 200 to capture image data. The imaging control unit 130 supplies an imaging control signal including, for example, a vertical synchronization signal VSYNC to the image sensor 200 via a signal line 139. The recording unit 120 records the image data.

[0020] Here, the vertical synchronization signal VSYNC is a signal that indicates the timing of imaging, and a periodic signal with a constant frequency (such as 60 Hz) is used as the vertical synchronization signal VSYNC.

[0021] It should be noted that although the imaging device 100 records image data, the image data may be transmitted to an external device. In this case, an external interface for transmitting the image data is further provided. Alternatively, the imaging device 100 may further display the image data. In this case, a display unit is further provided.

[0022] 2 is a block diagram showing a configuration example of an image sensor 200 according to the first embodiment of the present technology. The image sensor 200 includes a vertical scanning circuit 211, a pixel array unit 220, a timing control circuit 212, a DAC (Digital to Analog Converter) 213, and a column signal processing circuit 250. In the pixel array unit 220, a plurality of pixels 300 are arranged in a two-dimensional lattice pattern.

[0023] Hereinafter, a group of pixels 300 arranged in the horizontal direction will be referred to as a "row," and a group of pixels 300 arranged in a direction perpendicular to the rows will be referred to as a "column."

[0024] The timing control circuit 212 controls the operation timing of the vertical scanning circuit 211 , the DAC 213 , and the column signal processing circuit 250 in synchronization with a vertical synchronization signal VSYNC from the imaging control unit 130 .

[0025] The DAC 213 generates a sawtooth ramp signal by DA (Digital to Analog) conversion and supplies the generated ramp signal to the column signal processing circuit 250.

[0026] The vertical scanning circuit 211 sequentially selects and drives rows to output analog pixel signals. The pixels 300 photoelectrically convert incident light to generate analog pixel signals. The pixels 300 supply the pixel signals to the column signal processing circuit 250.

[0027] The column signal processing circuit 250 performs signal processing such as AD conversion processing and CDS processing on pixel signals for each column. The column signal processing circuit 250 supplies image data made up of the processed signals to the recording unit 120. The column signal processing circuit 250 is an example of a signal processing circuit as defined in the claims.

[0028] 3 is a circuit diagram showing a configuration example of a pixel 300 according to the first embodiment of the present technology. The pixel 300 includes a front-stage circuit 310, capacitance elements 321 and 322, a selection transistor 323, a short-circuit transistor 324, a selection circuit 330, a rear-stage reset transistor 341, and a rear-stage circuit 350.

[0029] Furthermore, vertical signal lines 308 and control lines 309 are wired in the vertical direction for each column in the pixel array unit 220. The vertical signal lines 308 transmit pixel signals to the column signal processing circuit 250, and the control lines 309 transmit determination results Sat from the column signal processing circuit 250. Details of the determination results Sat will be described later. The potential of the vertical signal lines 308 (in other words, the level of the pixel signals) is denoted by Vin.

[0030] Furthermore, the circuits and elements in the image sensor 200 can be distributed and arranged on the stacked pixel chip 201 and circuit chip 202. For example, the pre-stage circuit 310 is arranged on the pixel chip 201, and the circuits after the capacitive elements 321 and 322 are arranged on the circuit chip 202. The circuits and elements in the image sensor 200 can also be arranged on a single semiconductor chip. Furthermore, the circuits and elements in the image sensor 200 can also be distributed and arranged on three or more semiconductor chips.

[0031] The pre-stage circuit 310 includes a photoelectric conversion element 311 , a transfer transistor 312 , an FD reset transistor 313 , an FD 314 , a pre-stage amplification transistor 315 , and a current source transistor 316 .

[0032] The photoelectric conversion element 311 generates electric charges by photoelectric conversion. The transfer transistor 312 transfers the electric charges from the photoelectric conversion element 311 to the FD 314 in accordance with a transfer signal TRG from the vertical scanning circuit 211.

[0033] The FD reset transistor 313 extracts charge from the FD 314 to initialize it in accordance with an FD reset signal RST from the vertical scanning circuit 211. The FD 314 accumulates charge and generates a voltage according to the amount of charge. The pre-amplification transistor 315 forms a source follower circuit and outputs a signal at a level according to the voltage of the FD 314 to a pre-stage node 320.

[0034] The sources of the FD reset transistor 313 and the pre-amplification transistor 315 are connected to the power supply voltage VDD. The current source transistor 316 is connected to the drain of the pre-amplification transistor 315. The current source transistor 316 supplies a current id1 that corresponds to the bias voltage VB from the vertical scanning circuit 211.

[0035] One end of each of the capacitance elements 321 and 322 is connected to the selection circuit 330, and the other end is commonly connected to the previous-stage node 320. The capacitance elements 321 and 322 are examples of the first and second capacitance elements set forth in the claims.

[0036] The selection transistor 323 opens and closes the path between one end of one of the capacitance elements 321 and 322 (for example, the capacitance element 321 ) and the short-circuit transistor 324 in accordance with a selection signal SEL from the vertical scanning circuit 211 .

[0037] The short-circuit transistor 324 shorts one end of each of the capacitance elements 321 and 322 in accordance with the determination result Sat from the column signal processing circuit 250 when the selection transistor 323 is in an on state.

[0038] The selection circuit 330 selects one of one ends of the capacitance elements 321 and 322 and connects it to a subsequent node 340. The selection circuit 300 includes selection transistors 331 and 332. The selection transistor 331 opens and closes the path between the capacitance element 321 and the subsequent node 340 in accordance with a selection signal S1 from the vertical scanning circuit 211. The selection transistor 332 opens and closes the path between the capacitance element 322 and the subsequent node 340 in accordance with a selection signal S2 from the vertical scanning circuit 211.

[0039] The subsequent reset transistor 341 initializes the level of the subsequent node 340 to a predetermined potential Vreg in accordance with a subsequent reset signal RB from the vertical scanning circuit 211. A potential different from the power supply voltage VDD (for example, a potential lower than VDD) is set to the potential Vreg.

[0040] The subsequent circuit 350 includes a subsequent amplification transistor 351 and a subsequent selection transistor 352. The subsequent amplification transistor 351 forms a source follower circuit and outputs a signal at a level corresponding to the level of the subsequent node 340. The subsequent selection transistor 352 outputs the signal from the subsequent amplification transistor 351 to the vertical signal line 308 as a pixel signal in accordance with a selection signal SEL from the vertical scanning circuit 211.

[0041] Note that, for example, nMOS (n-channel Metal Oxide Semiconductor) transistors are used as various transistors (such as the transfer transistor 312) in the pixel 300.

[0042] At the start of exposure, the vertical scanning circuit 211 supplies a high-level FD reset signal RST and a transfer signal TRG to all pixels, thereby initializing the photoelectric conversion elements 311. Hereinafter, this control will be referred to as "PD reset."

[0043] Then, just before the end of exposure, the vertical scanning circuit 211 sets the subsequent reset signal RB and the selection signal S1 to high level for all pixels, and supplies a high-level FD reset signal RST for the entire pulse period. This initializes the FD 314, and a level corresponding to the level of the FD 314 at that time is held in the capacitive element 321. This control is hereinafter referred to as "FD reset."

[0044] The level of the FD 314 when the FD is reset and the level corresponding to that level (the retention level of the capacitive element 321 and the level of the vertical signal line 308) will hereinafter be collectively referred to as the "P phase" or "reset level."

[0045] At the end of exposure, the vertical scanning circuit 211 sets the subsequent reset signal RB and the selection signal S2 to high level for all pixels, and supplies a high-level transfer signal TRG for the pulse period, thereby transferring a signal charge according to the amount of exposure to the FD 314, and a level according to the level of the FD 314 at that time is held in the capacitance element 322.

[0046] The level of the FD 314 when transferring the signal charge and the level corresponding to that level (the level held by the capacitive element 322 and the level of the vertical signal line 308) will hereinafter be collectively referred to as the "D phase" or "signal level."

[0047] This type of exposure control, in which exposure starts and ends simultaneously for all pixels, is called a global shutter system. This exposure control causes the front-end circuits 310 of all pixels to sequentially generate reset levels and signal levels. The reset levels are held in the capacitance elements 321, and the signal levels are held in the capacitance elements 322.

[0048] After the exposure is completed, the vertical scanning circuit 211 sequentially selects rows and outputs the reset level and signal level of the selected row. When outputting the reset level, the vertical scanning circuit 211 sets the selection signal SEL for the selected row to high level and supplies a high-level selection signal S1 for a predetermined period. This connects the capacitive element 321 to the subsequent node 340, and the subsequent circuit 350 outputs the reset level to the column signal processing circuit 250 via the vertical signal line 308. The column signal processing circuit 250 also reads out the reset level.

[0049] After reading out the reset level, the vertical scanning circuit 211 supplies a high-level subsequent-stage reset signal RB for the pulse period while keeping the selection signal SEL for the selected row at a high level. This initializes the level of the subsequent-stage node 340. At this time, both the selection transistor 331 and the selection transistor 332 are in an open state, and the capacitance elements 321 and 322 are disconnected from the subsequent-stage node 340.

[0050] After initializing the subsequent node 340, the vertical scanning circuit 211 supplies a high-level selection signal S2 for a predetermined period while keeping the selection signal SEL for the selected row at a high level. As a result, the capacitive element 322 is connected to the subsequent node 340, and the subsequent circuit 350 outputs a signal level to the column signal processing circuit 250 via the vertical signal line 308. The column signal processing circuit 250 also reads out the signal level.

[0051] During the signal level readout period, the column signal processing circuit 250 determines for each column whether the signal level exceeds a predetermined threshold (in other words, whether the illuminance is higher than a predetermined value), and supplies the determination result as the aforementioned Sat to each column via the control line 309. For example, if the signal level exceeds the threshold, the determination result Sat is set to a high level, and if the signal level is equal to or lower than the threshold, the determination result Sat is set to a low level.

[0052] In the selected row, the short-circuit transistor 324 in the column where the determination result Sat is at a high level shorts one end of each of the capacitance elements 321 and 322 via the select transistor 323 that is in an on state. This short-circuit connects the capacitance elements 321 and 322 in parallel to the subsequent node 340. This attenuates the amplitude of the signal level compared to when only the capacitance element 322 is connected. For example, if the capacitance value of the capacitance element 321 is the same as that of the capacitance element 322, the attenuation ratio is 1 / 2.

[0053] In the rows other than the selected row, the selection transistors 323 are in the off state, so that one end of each of the capacitance elements 321 and 322 in each column is not short-circuited, thereby preventing the signal level from being destroyed by a short circuit before reading.

[0054] Furthermore, the capacitance value of the capacitance element 321 may be different from that of the capacitance element 322. For example, the capacitance value of the capacitance element 321 on the P-phase side may be set to G (G is a real number greater than 1) times that of the capacitance element 322 on the D-phase side. In this case, the attenuation factor is 1 / (1+G). In this way, the ratio of the capacitance values ​​of the capacitance elements 321 and 322 is adjusted according to the set attenuation factor.

[0055] 4, from the viewpoint of symmetry, a selection transistor 325 can be further inserted between one end of the capacitance element 322 and the short-circuit transistor 324. The selection transistor 325 opens and closes the path between one end of the capacitance element 322 and the short-circuit transistor 324 in accordance with a selection signal SEL.

[0056] 5 is a block diagram showing an example of the configuration of the column signal processing circuit 250 according to the first embodiment of the present technology. The column signal processing circuit 250 includes a plurality of column circuits 260 and a digital signal processing circuit 252. The column circuits 260 are arranged for each column. Each column circuit 260 includes a load MOS transistor 251, an ADC 270, a determination circuit 280, and a digital correction circuit 290.

[0057] The load MOS transistor 251 supplies a constant current id2 to the vertical signal line 308 of the corresponding column. During readout, the timing control circuit 212 applies a bias voltage V ＬＭ is applied.

[0058] The ADC 270 converts the analog pixel signal into a digital signal. The potential of the vertical signal line 308 (in other words, the level Vin of the pixel signal) and the ramp signal RMP from the DAC 213 are input to the ADC 270. The ADC 270 then outputs the digital signal after AD (Analog to Digital) conversion as Din to the digital correction circuit 290.

[0059] The determination circuit 280 determines whether the signal level Vin during the transfer of the signal charge exceeds a threshold value (in other words, whether the illuminance is higher than a predetermined value). The determination circuit 280 outputs a determination result Sat to the pixels 300 in the corresponding column via a control line 309, and also outputs the determination result Sat to the digital correction circuit 290. The determination result Sat is an example of a first determination result described in the claims.

[0060] The digital correction circuit 290 corrects the digital signal Din based on the determination result Sat, and outputs the corrected digital signal Dout to the digital signal processing circuit 252.

[0061] The digital signal processing circuit 252 performs various signal processing on the digital signal Dout and outputs image data in which the processed signals are arranged to the recording unit 120.

[0062] 6 is a circuit diagram showing an example of the configuration of the column circuit 260 according to the first embodiment of the present technology. The ADC 270 includes a comparator 271 and a counter 272. The determination circuit 280 includes a comparator 281 and a latch circuit 282. The digital correction circuit 290 includes a gain correction unit 291 and a multiplexer 292.

[0063] The comparator 271 in the ADC 270 compares the level Vin of the pixel signal with the level of the ramp signal RMP. The comparator 271 supplies the comparison result to the counter 272. The counter 272 counts the count value over a period until the comparison result is inverted. The type of counter 272 is not limited, and various counters such as a binary counter or a Gray code counter can be used.

[0064] The ADC 270 sequentially reads out the reset level, which is Vin when the FD 314 is initialized, and the signal level, which is Vin when the signal charge is transferred.

[0065] For example, the counter 272 counts down during the readout period of the reset level and counts up during the readout period of the signal level. This allows for correlated double sampling (CDS) processing to determine the difference between the reset level and the signal level. Note that the ADC 270 may be configured to perform only AD conversion, with a subsequent circuit performing CDS processing.

[0066] The ADC 270 supplies the digital signal after AD conversion and CDS processing to the gain correction unit 291 as Din.

[0067] Furthermore, the comparator 281 in the determination circuit 280 compares the pixel signal level Vin with a predetermined threshold value Vth. This comparator 281 supplies the determination result to a clock terminal of the latch circuit 282. For example, when Vin exceeds Vth (in other words, when the illuminance is higher than a predetermined value), the comparator 281 outputs a high-level comparison result, and when Vin is equal to or lower than Vth, the comparator 281 outputs a low-level comparison result.

[0068] The latch circuit 282 updates the held value in response to a control signal TD from the timing control circuit 212 based on the comparison result of the comparator 281. This control signal TD is input to an input terminal D of the latch circuit 282 and is controlled to, for example, a high level during the period in which the illuminance is determined. If the comparison result is a high level (i.e., Vin exceeds Vth), the latch circuit 282 updates the held value in response to the control signal TD. On the other hand, if the comparison result is a low level (i.e., Vin is equal to or lower than Vth), the latch circuit 282 transitions to a hold state.

[0069] A clear signal CLR from the timing control circuit 212 is input to a clear terminal C of the latch circuit 282. When the clear signal CLR is at a high level, the latch circuit 282 sets the held value to an initial value (for example, a low level). The latch circuit 282 also outputs the held value from an output terminal Q as a determination result Sat to the pixels 300 in the corresponding column and to the multiplexer 292.

[0070] The gain correction unit 291 in the digital correction circuit 290 performs correction by multiplying the digital signal Din by a digital gain that is the reciprocal of the attenuation rate. For example, if the attenuation rate is 1 / 2, a digital gain of "2" is used. The gain correction unit 291 supplies the corrected digital signal as Din' to the multiplexer 292.

[0071] The multiplexer 292 selects either the uncorrected digital signal Din or the corrected digital signal Din' based on the determination result Satt. When the determination result Satt is high level (i.e., the signal level exceeds the threshold Vth), the multiplexer 292 selects the corrected digital signal Din' and outputs it as Dout to the digital signal processing circuit 252. On the other hand, when the determination result Satt is low level (i.e., the signal level is equal to or lower than the threshold Vth), the multiplexer 292 selects the uncorrected digital signal Din and outputs it as Dout to the digital signal processing circuit 252.

[0072] [Example of Image Sensor Operation] Fig. 7 is a timing chart showing an example of global shutter operation in the first embodiment of the present technology. The vertical scanning circuit 211 supplies a high-level FD reset signal RST and a high-level transfer signal TRG to all rows (in other words, all pixels) from timing T0 immediately before the start of exposure to timing T1 after the pulse period has elapsed. This causes the PDs of all pixels to be reset, and exposure is started simultaneously for all rows.

[0073] Here, RST_[n] and TRG_[n] in the figure indicate signals to pixels in the nth row out of N rows, where N is an integer indicating the total number of rows, and n is an integer from 1 to N.

[0074] Then, at timing T2 just before the end of the exposure period, the vertical scanning circuit 211 supplies a high-level FD reset signal RST for the entire pulse period while setting the subsequent reset signal RB and selection signal S1 to high levels for all pixels. This causes the FD of all pixels to be reset, and the reset level is sampled and held. Here, RB_[n] and S1_[n] in the figure indicate signals to the pixels in the nth row.

[0075] At timing T3 after timing T2, the vertical scanning circuit 211 returns the selection signal S1 to low level.

[0076] At timing T4, when exposure ends, the vertical scanning circuit 211 supplies a high-level transfer signal TRG for the entire pulse period while setting the subsequent reset signal RB and selection signal S2 to a high level for all pixels. This causes the signal level to be sampled and held. The level of the previous-stage node 320 also drops from the reset level (VDD-Vsig) to the signal level (VDD-Vgs-Vsig). Here, VDD is the power supply voltage, and Vsig is the net signal level obtained by CDS processing. Vgs is the gate-source voltage of the previous-stage amplification transistor 315. Also, S1_[n] in the figure indicates the signal to the pixel in the nth row.

[0077] At timing T5 after timing T4, the vertical scanning circuit 211 returns the selection signal S2 to low level.

[0078] Furthermore, the vertical scanning circuit 211 controls the current source transistors 316 of all rows (all pixels) to supply a current id1. Here, id1_[n] in the figure indicates the current of the pixel in the nth row. Because a large current causes a large IR drop, the current id1 needs to be on the order of several nanoamperes (nA) to several tens of nanoamperes (nA). Meanwhile, the load MOS transistors 251 of all columns are in the off state, and no current id2 is supplied to the vertical signal line 308.

[0079] 8 is a timing chart showing an example of a readout operation according to the first embodiment of the present technology. During a readout period for the nth row from timing T10 to timing T16, the vertical scanning circuit 211 sets the selection signal SEL for the nth row to a high level. Here, SEL_[n] in the figure indicates a signal to the pixels in the nth row.

[0080] The timing control circuit 212 also supplies a high-level clear signal CLR_[n] to the nth row over a pulse period from timing T10, thereby initializing the latch circuit 282. In the figure, CLR_[n] indicates a signal to the pixels in the nth row.

[0081] Furthermore, the vertical scanning circuit 211 supplies a high-level subsequent-stage reset signal RB to the n-th row over the period from timing T10 to timing T11, thereby initializing the subsequent-stage node 340.

[0082] Then, over the period from timing T11 to timing T12, the vertical scanning circuit 211 supplies a high-level selection signal S1 to the n-th row, causing the subsequent circuit 350 to output a P-phase level (i.e., reset level).

[0083] Also, from immediately after timing T11 through timing T12, the DAC 213 gradually increases the ramp signal RMP. The ADC 270 compares the ramp signal RMP with the level Vin (reset level) of the vertical signal line 308, and counts the count value until the comparison result is inverted. This allows the reset level to be read out. In the figure, the dashed dotted line indicates the trajectory of the ramp signal RMP.

[0084] Then, the vertical scanning circuit 211 supplies a high-level subsequent reset signal RB to the n-th row over the period from timing T12 to timing T13, thereby initializing the subsequent node 340.

[0085] Then, over the period from timing T13 to timing T16, the vertical scanning circuit 211 supplies a high-level selection signal S2 to the n-th row, causing the subsequent circuit 350 to output a D-phase level (i.e., signal level).

[0086] Furthermore, the timing control circuit 212 supplies a high-level control signal TD_[n] to the n-th row during an illuminance determination period from timing T13 to T15. The length of this determination period is set according to the threshold value Vth.

[0087] Assume that the signal level of the mth column exceeds the threshold Vth (in other words, the illuminance is higher than a predetermined value) at timing T14 during the illuminance determination period. m is an integer between 1 and M, where M is an integer indicating the total number of columns. The determination circuit 280 for the mth column outputs a high-level determination result Sat_[m] after timing T14. As a result, the amplitude of the signal level of the mth column in the selected row is attenuated after timing T14. In the figure, TD_[n] indicates the signal of the nth row, and Sat_[m] indicates the signal of the mth column.

[0088] In addition, in the column where the signal level is equal to or less than the threshold value Vth, the determination result Sat_[m] remains at a low level, and the signal level is read out without being attenuated.

[0089] From immediately after timing T15 to timing T16, the DAC 213 gradually increases the ramp signal RMP. The ADC 270 compares the ramp signal RMP with the level Vin (signal level) of the vertical signal line 308, and counts the count value until the comparison result is inverted. This allows the signal level to be read out.

[0090] Here, a comparative example is assumed in which the short-circuit transistor 324, the determination circuit 280, and the digital correction circuit 290 are not provided, and the amplitude of the signal level is not attenuated.

[0091] 9 is a timing chart showing an example of a read operation in the comparative example. In the comparative example, even if the signal level exceeds the threshold Vth after timing T13 (in other words, the illuminance is higher than a predetermined value), the signal level is read without attenuating the amplitude. The thick dotted line in the figure shows the trajectory of the signal level when the amplitude is attenuated.

[0092] As illustrated in the figure, in the comparative example, the output range of the DAC 213 and the input range of the ADC 270 need to be wider than when the amplitude is attenuated.

[0093] Furthermore, in the comparative example, if the pixel 300 is not saturated and the conversion efficiency when converting charge to voltage is constant, the dynamic range is limited by the width of the range of the vertical signal line 308. Conversely, if there is a margin in the signal amount Qs of the pixel 300 and the range of the vertical signal line 308 is insufficient, the dynamic range will be narrowed accordingly.

[0094] For example, the high potential side of the vertical signal line 308 is limited by the potential when the selection signals S1 and S2 are set to high level. Also, the low potential side of the vertical signal line 308 depends on the drain-source voltage of the load MOS transistor 251, but is limited by a value that does not degrade FPN (Fixed Pattern Noise) or PRNU (Photo Response Non-Uniformity).

[0095] In contrast, in the first embodiment, the pixel 300 attenuates the amplitude during high illuminance, allowing the ranges of the DAC 213 and the ADC 270 to be narrower than those of the comparative example. This shortens the count period of the ADC 270 compared to the comparative example, thereby improving the readout speed. Furthermore, because the range of the vertical signal line 308 is more flexible, the bias voltage of the load MOS transistor 251 can be reduced accordingly, thereby reducing power consumption. Furthermore, even if the range of the vertical signal line 308 is narrow, the pixel 300 can output a signal during high illuminance, eliminating the range constraint of the vertical signal line 308 and expanding the dynamic range compared to the comparative example.

[0096] Furthermore, in the first embodiment, the signal level for each row only needs to be read out once, so the readout speed can be improved compared to the image sensor described in the above-mentioned Patent Document 1.

[0097] 10 is a flowchart showing an example of the operation of the image sensor 200 according to the first embodiment of the present technology. This operation is started, for example, when a predetermined application for capturing image data is executed.

[0098] The vertical scanning circuit 211 exposes all pixels (step S901). Then, the vertical scanning circuit 211 selects a row to read (step S902). The column signal processing circuit 250 reads the reset level of the row (step S903) and determines, for each column, whether the signal level exceeds a threshold (in other words, whether the illuminance is high) (step S904).

[0099] If a certain column has high illuminance (step S904: Yes), the column signal processing circuit 250 attenuates the amplitude of the signal level of that column (step S905).

[0100] If the illuminance is not high (step S904: No), or after step S905, the column signal processing circuit 250 reads out the reset level of the row (step S906). Note that steps S904 and S905 are executed in parallel for all columns.

[0101] Then, the column signal processing circuit 250 executes the correction process for each column (step S910).Then, the image sensor 200 determines whether or not the readout of all rows has been completed (step S907).

[0102] If readout of all rows has not been completed (step S907: No), the image sensor 200 repeats step S902 and subsequent steps. On the other hand, if readout of all rows has been completed (step S907: Yes), the image sensor 200 ends the operation for imaging. When capturing multiple frames of image data consecutively, steps S901 to S907 are repeatedly executed in synchronization with a vertical synchronization signal.

[0103] 11 is a flowchart showing an example of the correction process according to the first embodiment of the present technology. The digital correction circuit 290 determines whether the illuminance determination result Sat is at a high level (in other words, high illuminance) (step S911).

[0104] If the determination result Sat is high (step S911: Yes), the digital correction circuit 290 corrects the digital signal using a digital gain corresponding to the attenuation rate and outputs the corrected digital signal (step S912). On the other hand, if the determination result Sat is low (step S911: No), the digital correction circuit 290 outputs the digital signal indicating the count value without correction (step S913). After step S912 or S913, the digital correction circuit 290 ends the correction process.

[0105] As described above, according to the first embodiment of the present technology, when the signal level exceeds the threshold, the short-circuiting transistor 324 shorts one end of each of the capacitive elements 321 and 322, thereby attenuating the amplitude of the signal level at high illuminance. This narrows the ranges of the DAC 213 and the ADC 270, thereby improving the readout speed. Furthermore, it is possible to reduce power consumption and expand the dynamic range.

[0106] 2. Second Embodiment In the first embodiment described above, the pixel 300 attenuates amplitude when the illuminance is high. However, in the image sensor 200, when extremely high-illuminance light is incident on the pixel, charge overflows from the photoelectric conversion element, reducing brightness and causing the pixel to become dark and sunspot-like, which is known as sunspot. The occurrence of sunspots can result in a deterioration in image quality. The image sensor 200 in this second embodiment differs from the first embodiment in that it corrects the digital signal when sunspots occur.

[0107] 12 is a circuit diagram showing a configuration example of a column circuit 260 according to the second embodiment of the present technology. The column circuit 260 according to the second embodiment differs from the first embodiment in that it further includes a latch circuit 283 and a multiplexer 293.

[0108] The latch circuit 283 is disposed in the determination circuit 280 , and the multiplexer 293 is disposed in the digital correction circuit 290 .

[0109] The latch circuit 283 updates the held value in response to a control signal TSUN from the timing control circuit 212 based on the comparison result of the comparator 281. This control signal TSUN is input to an input terminal D of the latch circuit 283 and is controlled to, for example, a high level during the period in which the presence or absence of sunspots is determined. If the comparison result is a high level, the latch circuit 283 updates the held value in response to the control signal TSUN. On the other hand, if the comparison result is a low level, the latch circuit 283 transitions to a hold state.

[0110] A clear signal CLR is input to a clear terminal C of the latch circuit 283. When the clear signal CLR is at a high level, the latch circuit 283 sets the held value to an initial value (for example, a low level). The latch circuit 283 also outputs the held value from an output terminal Q to the multiplexer 293 as a determination result SUN.

[0111] With the above circuit configuration, when the reset level exceeds the threshold Vth, it is determined that a sunspot will occur, and a high-level determination result SUN is output. On the other hand, when the reset level is equal to or lower than the threshold Vth, a low-level determination result SUN is output. Note that the determination result SUN is an example of the second determination result described in the claims.

[0112] Although the same threshold value Vth is used to determine illuminance and to determine the presence or absence of sunspots, this configuration is not limiting. It is also possible to use Vth1 as the threshold value for determining illuminance, and Vth2, a different threshold value, for determining the presence or absence of sunspots. In this case, a switch can be added to switch between Vth1 and Vth2 and output the result to the input terminal of the comparator 281. Alternatively, two comparators can be provided: one that compares Vth1 with Vin, and the other that compares Vth2 with Vin.

[0113] In the second embodiment, the multiplexer 292 outputs the selected digital signal to the multiplexer 293 .

[0114] The multiplexer 293 selects either the digital signal from the multiplexer 292 or the digital signal FC indicating the full code based on the determination result SUN. If the determination result SUN is high level (in other words, there are sunspots), the multiplexer 293 selects the digital signal FC and outputs it as Dout. On the other hand, if the determination result SUN is low level (in other words, there are no sunspots), the multiplexer 293 selects the digital signal from the multiplexer 292 and outputs it as Dout.

[0115] With the above-described circuit configuration, the digital correction circuit 290 can correct the digital signal using digital gain and full code based on the illuminance determination result Sat and the sunspot determination result SUN. When it is determined that sunspots exist, the digital correction circuit 290 replaces the signal with full code, thereby preventing sunspots from appearing in the image data and improving image quality.

[0116] 13 is a timing chart showing an example of a read operation according to the second embodiment of the present technology. The following description focuses on differences from the first embodiment.

[0117] Over the sunspot determination period from just before timing T11 to timing T12, the timing control circuit 212 supplies a high-level control signal TSUN_[n] to the nth row. In the figure, TSUN_[n] indicates the signal to the nth row.

[0118] Assume that during the sunspot determination period, immediately after timing T11, the reset level of the mth column exceeds the threshold Vth (in other words, it is determined that a sunspot exists). In this case, the determination circuit 280 for the mth column outputs a high-level determination result SUN_[m]. As a result, the digital signal for the mth column is corrected to a full code. In the figure, SUN_[m] represents the signal for the mth column.

[0119] In addition, in the column where the reset level is equal to or lower than the threshold value Vth, the determination result SUN_[m] remains at a low level, and the digital signal is not corrected to a full code.

[0120] 14 is a flowchart showing an example of the operation of the image sensor 200 according to the second embodiment of the present technology. The operation of the image sensor 200 according to the second embodiment differs from that according to the first embodiment in that step S908 is executed instead of step S903.

[0121] In the second embodiment, the column signal processing circuit 250 determines whether or not a sunspot exists when reading out the reset level (step S908).

[0122] 15 is a flowchart illustrating an example of a correction process according to the second embodiment of the present technology. The correction process according to the second embodiment differs from the first embodiment in that steps S914 and S915 are further executed.

[0123] The digital correction circuit 290 determines whether the sunspot determination result SUN is high (in other words, whether there are sunspots) (step S911). If the determination result SUN is high (step S914: Yes), the digital correction circuit 290 outputs the full code (step S915).

[0124] On the other hand, if the determination result SUN is at a low level (step S914: No), the digital correction circuit 290 executes step S911 and subsequent steps.

[0125] Thus, according to the second embodiment of the present technology, when the reset level exceeds the threshold, the digital correction circuit 290 corrects it to full code, thereby preventing sunspots from appearing in the image data.

[0126] 3. Third Embodiment In the first embodiment described above, the selection circuit 330 connects one end of each of the capacitance elements 321 and 322 to the subsequent node 340, and the other end of each is commonly connected to the previous node 320. However, the present invention is not limited to this circuit configuration. The image sensor 200 in this third embodiment differs from the first embodiment in that the selection circuit 330 connects one end of each of the capacitance elements 321 and 322 to the previous node 320, and the other end of each is connected to a power supply voltage.

[0127] 16 is a circuit diagram showing a configuration example of a pixel 300 according to a third embodiment of the present technology. A front-stage circuit 310 according to the third embodiment differs from that according to the first embodiment in that it includes a precharge transistor 317 and precharge selection transistors 318 and 319 instead of a current source transistor 316. Furthermore, in the pixel 300 according to the third embodiment, the rear-stage reset transistor 341 is omitted.

[0128] The precharge transistor 317 and the precharge selection transistor 318 are connected in series between the front-stage amplification transistor 315 and a ground terminal. A precharge control signal PC from the timing control circuit 212 is input to the gate of the precharge transistor 317. A precharge selection signal PSEL2 from the timing control circuit 212 is input to the gate of the precharge selection transistor 318.

[0129] The precharge selection transistor 319 is inserted between the connection node of the pre-stage amplification transistor 315 and the precharge transistor 317 and the pre-stage node 320. A precharge selection signal PSEL1 from the timing control circuit 212 is input to the gate of this precharge selection transistor 319.

[0130] The method of driving each transistor such as the precharge transistor 317 is described, for example, in FIG. 3 of US Pat. No. 2022 / 0094864.

[0131] Furthermore, the selection circuit 330 selects one of the ends of the capacitance elements 321 and 322 and connects it to a previous-stage node 320 between the previous-stage circuit 310 and the subsequent-stage circuit 350. The short-circuiting transistor 324 and the selection transistor 323 are connected in series between one end of the capacitance element 321 and one end of the capacitance element 322. Furthermore, the other ends of the capacitance elements 321 and 322 are connected to a power supply voltage.

[0132] In the circuit illustrated in the figure, similarly to the first embodiment, the short-circuit transistor 324 can short-circuit one end of each of the capacitance elements 321 and 322 at high illuminance to attenuate the amplitude of the signal level.

[0133] The second embodiment can be applied to the third embodiment.

[0134] As described above, according to the third embodiment of the present technology, the selection circuit 330 connects one end of each of the capacitive elements 321 and 322 to the previous-stage node 320, and the other end of each is connected to the power supply voltage, and the short-circuit transistor 324 is provided in the circuit. This makes it possible to attenuate the amplitude at high illuminance, similarly to the first embodiment.

[0135] 4. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0136] FIG. 17 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0137] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 17, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0138] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0139] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0140] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0141] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0142] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0143] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0144] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0145] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0146] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 17, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0147] FIG. 18 is a diagram showing an example of the installation position of the imaging unit 12031.

[0148] In FIG. 18, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0149] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0150] 18 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0151] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0152] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0153] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0154] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0155] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, the imaging device 100 of FIG. 1 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, the readout speed can be improved, and therefore the frame rate can be improved.

[0156] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0157] The effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0158] The present technology may also be configured as follows: (1) An image sensor comprising: a front-stage circuit that sequentially generates a reset level when a floating diffusion layer is initialized and a signal level when a signal charge is transferred; a first capacitance element that holds the reset level; a second capacitance element that holds the signal level; a short-circuiting transistor that short-circuits one end of each of the first and second capacitance elements when the signal level exceeds a predetermined threshold; and a rear-stage circuit that sequentially outputs the reset level and the signal level. (2) The image sensor according to (1), further comprising: a selection circuit that selects one of the one ends of the first and second capacitance elements and connects it to the rear-stage circuit, and the other ends of the first and second capacitance elements are commonly connected to the front-stage circuit. (3) The image sensor according to (1) or (2), further comprising a determination circuit that determines whether the signal level exceeds the threshold and outputs the determination result to the short-circuiting transistor as a first determination result. (4) The image sensor according to (3), further comprising: an analog-to-digital converter that converts the reset level and the signal level into digital signals in sequence; and a correction circuit that corrects the digital signal based on the first determination result. (5) The image sensor according to (4), wherein the determination circuit further determines whether the reset level exceeds a predetermined threshold and outputs the determination result as a second determination result, and the correction circuit corrects the digital signal based on each of the first and second determination results. (6) The image sensor according to any of (1) to (5), further comprising: a selection transistor that opens and closes a path between the short-circuit transistor and one end of one of the first and second capacitance elements in accordance with a predetermined selection signal. (7) The image sensor according to any of (1) to (5), further comprising: a first selection transistor that opens and closes a path between the short-circuit transistor and one end of the first capacitance element in accordance with a predetermined selection signal; and a second selection transistor that opens and closes a path between the short-circuit transistor and one end of the second capacitance element in accordance with the selection signal.(8) The image sensor according to (1), further comprising a selection circuit that selects one of one ends of the first and second capacitance elements and connects it to a node between the front-stage circuit and the rear-stage circuit, wherein the other ends of the first and second capacitance elements are connected to a predetermined power supply voltage. (9) An imaging device comprising: a front-stage circuit that generates a reset level when a floating diffusion layer is initialized and a signal level when a signal charge is transferred, a first capacitance element that holds the reset level, a second capacitance element that holds the signal level, a short-circuiting transistor that short-circuits one end of each of the first and second capacitance elements when the signal level exceeds a predetermined threshold, a rear-stage circuit that outputs the reset level and the signal level in sequence, and a signal processing circuit that processes the output reset level and signal level. (10) A control method for an image sensor, comprising: a first step of sequentially generating a reset level when a floating diffusion layer is initialized and a signal level when a signal charge is transferred; a short-circuiting step of short-circuiting one end of each of first and second capacitance elements that hold the reset level and the signal level when the signal level exceeds a predetermined threshold; and a second step of sequentially outputting the reset level and the signal level.

[0159] 100 Imaging device 110 Imaging lens 120 Recording unit 130 Imaging control unit 200 Image sensor 201 Pixel chip 202 Circuit chip 211 Vertical scanning circuit 212 Timing control circuit 213 DAC 220 Pixel array unit 250 Column signal processing circuit 251 Load MOS transistor 252 Digital signal processing circuit 260 Column circuit 270 ADC 271, 281 Comparator 272 Counter 280 Determination circuit 282, 283 Latch circuit 290 Digital correction circuit 291 Gain correction unit 292, 293 Multiplexer 300 Pixel 310 Pre-stage circuit 311 Photoelectric conversion element 312 Transfer transistor 313 FD reset transistor 314 FD 315 Pre-stage amplification transistor 316 Current source transistor 317 Precharge transistor 318, 319 Precharge selection transistor 320 Preceding node 321, 322 Capacitor element 323, 325, 331, 332 Selection transistor 324 Short-circuit transistor 330 Selection circuit 340 Subsequent node 341 Subsequent reset transistor 350 Subsequent circuit 351 Subsequent amplification transistor 352 Subsequent selection transistor 12031 Imaging section

Claims

1. An image sensor comprising: a front-stage circuit that sequentially generates a reset level when a floating diffusion layer is initialized and a signal level when a signal charge is transferred; a first capacitance element that holds the reset level; a second capacitance element that holds the signal level; a short-circuit transistor that short-circuits one end of each of the first and second capacitance elements when the signal level exceeds a predetermined threshold; and a rear-stage circuit that sequentially outputs the reset level and the signal level.

2. The image sensor according to claim 1, further comprising a selection circuit that selects one of the one ends of each of the first and second capacitance elements and connects it to the subsequent circuit, and the other ends of each of the first and second capacitance elements are commonly connected to the previous circuit.

3. The image sensor according to claim 1, further comprising a determination circuit that determines whether or not the signal level exceeds the threshold value and outputs the determination result to the short-circuit transistor as a first determination result.

4. The image sensor according to claim 3, further comprising: an analog-to-digital converter that converts the reset level and the signal level into digital signals in sequence; and a correction circuit that corrects the digital signals based on the first determination result.

5. The image sensor according to claim 4, wherein the determination circuit further determines whether the reset level exceeds a predetermined threshold value and outputs the determination result as a second determination result, and the correction circuit corrects the digital signal based on each of the first and second determination results.

6. The image sensor according to claim 1, further comprising a selection transistor that opens and closes a path between said one end of one of said first and second capacitance elements and said short-circuit transistor in accordance with a predetermined selection signal.

7. An image sensor according to claim 1, further comprising: a first selection transistor that opens and closes a path between said one end of said first capacitance element and said short-circuiting transistor in accordance with a predetermined selection signal; and a second selection transistor that opens and closes a path between said one end of said second capacitance element and said short-circuiting transistor in accordance with said selection signal.

8. The image sensor according to claim 1, further comprising a selection circuit that selects one of the ends of each of the first and second capacitance elements and connects it to a node between the front-stage circuit and the rear-stage circuit, and the other end of each of the first and second capacitance elements is connected to a predetermined power supply voltage.

9. An imaging device comprising: a front-stage circuit that sequentially generates a reset level when a floating diffusion layer is initialized and a signal level when a signal charge is transferred; a first capacitance element that holds the reset level; a second capacitance element that holds the signal level; a short-circuit transistor that short-circuits one end of each of the first and second capacitance elements when the signal level exceeds a predetermined threshold; a rear-stage circuit that sequentially outputs the reset level and the signal level; and a signal processing circuit that processes the output reset level and signal level.

10. A control method for an image sensor comprising: a first step of sequentially generating a reset level when a floating diffusion layer is initialized and a signal level when a signal charge is transferred; a short-circuiting step of short-circuiting one end of each of first and second capacitance elements that hold the reset level and the signal level when the signal level exceeds a predetermined threshold; and a second step of sequentially outputting the reset level and the signal level.

Images