Parallel instruction processing method and apparatus, and storage medium

Abstract

Disclosed in the present invention are a parallel instruction processing method and apparatus, and a storage medium. The method comprises: establishing an information table for storing instruction write-back task information, and storing, in the information table, write-back task information of a plurality of functional units in the next N delay cycles, N being the maximum number of delay cycles of write-back tasks of all instructions in an instruction set; taking an instruction to be transmitted in the current cycle as a target instruction, querying the information table to determine whether transmitting the target instruction in the current cycle causes a future write-back conflict, if not, taking the current cycle as a new instruction transmission cycle, and if yes, delaying one or more cycles until transmitting the target instruction in a delayed cycle does not cause a future write-back conflict, and taking the delayed cycle as a new instruction transmission cycle; and transmitting the target instruction in the new instruction transmission cycle, updating content of the information table, and storing, in the updated information table, write-back task information of all functional units in N delay cycles following the new instruction transmission cycle.

Description

Parallel instruction processing method, device and storage medium TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to, but are not limited to, the technical field of processor, and particularly relate to a parallel instruction processing method, device and storage medium. BACKGROUND

[0002] A multi-issue processor refers to a processor that can issue multiple instructions to corresponding functional units in one instruction cycle for parallel execution. The multi-issue processor usually has multiple functional units that execute different operations in parallel, thereby improving the execution efficiency of instructions.

[0003] In processor design, a register file is a very important component, and most instructions need to interact with the register file to read source operands from the register file and write results back to the register file. In a multi-issue processor, multiple instructions are executed in parallel in each cycle, and multiple functional units compete for limited register file write back port resources, which can easily cause write conflicts between instructions.

[0004] SUMMARY

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] Embodiments of the present disclosure provide a parallel instruction processing method, comprising:

[0007] establishing an information table for storing instruction write back task information, and storing write back task information of multiple functional units in N future delay cycles in the information table; wherein N is the maximum delay cycle number of write back tasks of all instructions in an instruction set;

[0008] taking an instruction to be issued in a current cycle as a target instruction, querying the information table to determine whether issuing the target instruction in the current cycle will cause future write back conflicts, if not, taking the current cycle as a new instruction issue cycle, and if yes, delaying for one or more cycles until issuing the target instruction in the delayed cycle will not cause future write back conflicts, and taking the delayed cycle as the new instruction issue cycle;

[0009] issuing the target instruction in the new instruction issue cycle, and updating the content of the information table, and storing write back task information of all functional units in N delay cycles after the new instruction issue cycle in the updated information table.

[0010] Embodiments of the present disclosure provide a parallel instruction processing device, comprising:

[0011] an information table establishing module configured to establish an information table for storing instruction write-back task information, and store write-back task information of a plurality of functional units in N future delay periods in the information table; wherein N is a maximum delay period number of write-back tasks of all instructions in the instruction set;

[0012] a query and judgment module configured to take an instruction to be emitted in a current period as a target instruction, query the information table to determine whether emitting the target instruction in the current period will cause future write-back conflict, take the current period as a new instruction emission period if the target instruction will not cause future write-back conflict, delay one or more periods until emitting the target instruction in a delayed period will not cause future write-back conflict, and take the delayed period as the new instruction emission period if the target instruction will cause future write-back conflict;

[0013] an instruction emission module configured to emit the target instruction in the new instruction emission period, and update content of the information table, and store write-back task information of all functional units in N delay periods after the new instruction emission period in the updated information table.

[0014] Embodiments of the present disclosure provide a parallel instruction processing device, comprising a memory and a processor, the memory stores a computer program, and the computer program is executed by the processor to implement steps of the parallel instruction processing method.

[0015] Embodiments of the present disclosure provide a non-transitory computer readable storage medium, the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement steps of the parallel instruction processing method.

[0016] Other features and advantages of the present disclosure will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present disclosure. Other advantages of the present disclosure will be realized and attained by the specific structures particularly pointed out in the description and the appended drawings.

[0017] Other aspects can become apparent to those of ordinary skill in the art upon reading and understanding the detailed description and the accompanying drawings.

[0018] SUMMARY

[0019] The accompanying drawings are included to provide a further understanding of the present disclosure, and constitute a part of the specification, and together with the embodiments of the present disclosure, serve to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0020] FIG. 1 is a flowchart of a parallel instruction processing method according to an embodiment of the present disclosure;

[0021] FIG. 2 is a processing flow diagram of delayed instruction emission according to an embodiment of the present disclosure;

[0022] Figure 3 is a structural schematic diagram of a parallel instruction processing apparatus according to an embodiment of the present disclosure;

[0023] Figure 4 is a structural schematic diagram of another parallel instruction processing apparatus according to an embodiment of the present disclosure.

[0024] DETAILED DESCRIPTION

[0025] The present disclosure describes a plurality of embodiments, but the description is exemplary rather than limiting, and it will be apparent to those of ordinary skill in the art that there can be many embodiments and implementations within the scope of the embodiments described in the present disclosure. Although many possible combinations of features are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are possible. Unless specifically intended to be limited, any feature or element of any embodiment can be used in combination with any other feature or element of any other embodiment, or in combination with any other feature or element of the same embodiment.

[0026] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed herein can also be combined with any conventional feature or element to form a unique application of the presently claimed disclosure. Any feature or element of any embodiment can also be combined with features or elements from other applications to form another unique application of the presently claimed disclosure. Accordingly, it should be understood that any feature shown and / or discussed in the present disclosure can be used alone or in any combination. The embodiments are therefore not limited to the specific embodiments that are shown and / or discussed, except insofar as limited by the claims and their equivalents. Further, various modifications and changes can be made within the scope of the appended claims.

[0027] Further, in describing representative embodiments, the specification can have presented the method and / or process as a particular sequence of steps. However, to the extent that the method or process depends on more than one step, the method or process should not be limited to the specific order of steps described. Other sequences of steps can be possible, depending on the implementation, without departing from the scope of the present disclosure. Accordingly, the specific order of steps set forth in the specification should not be construed as a limitation on the claims. Further, the claims should not be limited to the steps of the method and / or process set forth, as the method and / or process can vary and still fall within the scope of the present disclosure.

[0028] As shown in FIG. 1, the embodiment of the present disclosure provides a parallel instruction processing method, comprising:

[0029] S10, an information table for storing instruction write-back task information is established, and write-back task information of a plurality of functional units in N future delay periods is stored in the information table; wherein N is the maximum delay period number of write-back tasks of all instructions in the instruction set;

[0030] S20, a current period to-be-transmitted instruction is taken as a target instruction, the information table is queried to determine whether transmitting the target instruction in the current period will cause future write-back conflict, if not, the current period is taken as a new instruction transmission period, if yes, one or more periods are delayed until transmitting the target instruction in the delayed period will not cause future write-back conflict, and the delayed period is taken as the new instruction transmission period;

[0031] S30, the target instruction is transmitted in the new instruction transmission period, and the content of the information table is updated, and write-back task information of all functional units in N delay periods after the new instruction transmission period is stored in the updated information table.

[0032] The parallel instruction processing method provided by the embodiment of the present disclosure stores write-back task information of a plurality of functional units in N future delay periods by establishing an information table, before transmitting an instruction each time, a current period to-be-transmitted instruction is taken as a target instruction, the information table is queried to determine whether transmitting the target instruction in the current period will cause future write-back conflict, if not, the current period is taken as a new instruction transmission period, if yes, one or more periods are delayed until transmitting the target instruction in the delayed period will not cause future write-back conflict, and the delayed period is taken as the new instruction transmission period; the target instruction is transmitted in the new instruction transmission period, and the content of the information table is updated, and write-back task information of all functional units in N delay periods after the new instruction transmission period is stored in the updated information table. The method provided by the embodiment of the present disclosure can realize pipeline processing of a multi-transmission processor on parallel instructions on different hardware platforms, improve the processing efficiency of parallel instructions, and facilitate flexible configuration and scheduling of hardware resources (write-back port resources of functional units and register stacks of the multi-transmission processor).

[0033] In an exemplary embodiment, the instructions include Very Long Instruction Word (VLIW) instructions or Superscalar instructions.

[0034] In an exemplary embodiment, the period is one beat of a pipeline beat.

[0035] In an exemplary embodiment, the information table comprises M rows and N columns, and information whether the i-th functional unit has a write-back task in the future j-th delay cycle is stored in the i-th row and j-th column of the information table; wherein M is the total number of functional units; 1≤i≤M, 1≤j≤N.

[0036] In an exemplary embodiment, the information table comprises M rows and N columns, and the content of the information table is stored in a two-dimensional register matrix, which comprises M rows and N columns of registers, and the register in the i-th row and j-th column of the two-dimensional register matrix stores the information in the i-th row and j-th column of the information table; wherein M is the total number of functional units; 1≤i≤M, 1≤j≤N. Using a centralized two-dimensional register matrix is beneficial to the layout and wiring of the back-end module, and reduces the connection between the emission unit and the functional units. Without the centralized two-dimensional register matrix, the emission unit needs to be connected to each functional unit individually to interact with the information of the write-back task. After using the centralized two-dimensional register matrix, the emission unit only needs to query and maintain a two-dimensional register matrix, which is beneficial to the layout and wiring of the back-end module.

[0037] In an exemplary embodiment, the register of the two-dimensional register matrix is a single-bit register. Using a single-bit register can further reduce the hardware connection.

[0038] In an exemplary embodiment, the information whether the i-th functional unit has a write-back task in the future j-th delay cycle is represented by a flag bit; if there is a write-back task, the flag bit is set to 1; if there is no write-back task, the flag bit is set to 0.

[0039] Table 1 shows the storage content of an information table. As shown in Table 1, the storage content of the information table is flag bit information. The flag bit in the i-th row and j-th column is set to 1 to indicate that the i-th functional unit has a write-back task in the future j-th delay cycle, and the flag bit in the i-th row and j-th column is set to 0 to indicate that the i-th functional unit has no write-back task in the future j-th delay cycle. The storage content of the information table shown in Table 1 comprises 3 rows and 5 columns. Each row represents a functional unit, the top row represents the 1st functional unit, and the bottom row represents the 3rd functional unit. Each column represents a future delay cycle, the leftmost column represents the 1st delay cycle in the future, and the rightmost column represents the 5th delay cycle in the future.

[0040] Table 1

[0041] As shown in Table 1, the flag bit in the 5th column of the 1st row of the information table is 1, indicating that the 1st functional unit has a write-back task in the 5th future delay period. The flag bit in the 2nd column of the 2nd row of the information table is 1, indicating that the 2nd functional unit has a write-back task in the 2nd future delay period. The 3rd row of the information table is all 0s, indicating that the 3rd functional unit has no write-back task in the 5 future delay periods.

[0042] In an exemplary embodiment, querying the information table to determine whether transmitting the target instruction in the current period will cause a future write-back conflict comprises:

[0043] targeting a functional unit that will execute the target instruction as a target functional unit, and targeting a period in which a write-back task of the target instruction will be performed when the target instruction is transmitted in the current period as a target period;

[0044] querying the information table to determine whether the target functional unit already has a write-back task in the target period, and if so, determining that a first write-back conflict is detected, and otherwise, determining that a first write-back conflict is not detected;

[0045] if the first write-back conflict is not detected, querying the information table to determine whether a total number of write-back tasks that all functional units already have in the target period is less than a total number of write-back ports of the register file, and if so, determining that a second write-back conflict is not detected, and otherwise, determining that a second write-back conflict is detected;

[0046] if either the first write-back conflict or the second write-back conflict is detected, determining that transmitting the target instruction in the current period will cause a future write-back conflict, and if neither the first write-back conflict nor the second write-back conflict is detected, determining that transmitting the target instruction in the current period will not cause a future write-back conflict.

[0047] In an exemplary embodiment, if transmitting the target instruction will cause a future write-back conflict, delaying for one or more periods until transmitting the target instruction in a delayed period will not cause a future write-back conflict, and targeting the delayed period as a new instruction transmission period, as shown in FIG. 2, comprises:

[0048] performing the following steps a to d:

[0049] step a, delaying for one period;

[0050] step b, updating the contents of the information table with the delayed period as the current period;

[0051] step c, querying the updated information table to determine whether transmitting the target instruction in the current period will cause a future write-back conflict, and if so, returning to step a, and otherwise, performing step d;

[0052] Step d, taking the current cycle as a new instruction emission cycle.

[0053] In an exemplary embodiment, the updating the content of the information table with the delayed cycle as the current cycle comprises:

[0054] left shifting the content of the information table by one column, removing the content of the leftmost column from the information table, adding a new column at the rightmost side of the information table, and setting the flag bit of all rows of the new column to 0;

[0055] The information table comprises M rows and N columns, and the flag bit in the ith row and jth column of the information table is used to indicate whether the ith functional unit has a write-back task in the jth delay cycle in the future; if the functional unit has a write-back task, the flag bit is set to 1; if the functional unit does not have a write-back task, the flag bit is set to 0; M is the total number of functional units; 1≤i≤M, 1≤j≤N.

[0056] In an exemplary embodiment, the updating the content of the information table comprises storing write-back task information of all functional units in the N delay cycles after the new instruction emission cycle in the updated information table.

[0057] The functional unit that executes the target instruction is taken as a target functional unit, and the cycle in which the write-back task of the target instruction is taken as a target cycle when the target instruction is emitted in the new instruction emission cycle.

[0058] The flag bit in the information table that is used to indicate whether the target functional unit has a write-back task in the target cycle is set to indicate that there is a write-back task.

[0059] As shown in FIG. 3, the present disclosure provides a parallel instruction processing device, which comprises:

[0060] The information table establishing module 10 is configured to establish an information table for storing instruction write-back task information, and store write-back task information of a plurality of functional units in N delay cycles in the future in the information table; wherein N is the maximum delay cycle number of write-back tasks of all instructions in an instruction set;

[0061] The query and judgment module 20 is configured to take an instruction to be emitted in a current cycle as a target instruction, query the information table to determine whether emitting the target instruction in the current cycle will cause a future write-back conflict, take the current cycle as a new instruction emission cycle if the target instruction will not cause a future write-back conflict, delay one or more cycles until emitting the target instruction in a delayed cycle will not cause a future write-back conflict, and take the delayed cycle as a new instruction emission cycle if the target instruction will cause a future write-back conflict.

[0062] The instruction transmitting module 30 is configured to transmit the target instruction in the new instruction transmitting period, and update the content of the information table, in which the write-back task information of all functional units in N delay periods after the new instruction transmitting period is stored.

[0063] The parallel instruction processing device provided by the embodiment of the present disclosure stores the write-back task information of multiple functional units in future N delay periods through the information table establishing module, and the query and judgment module takes the instruction to be transmitted in the current period as a target instruction, queries the information table to determine whether transmitting the target instruction in the current period will cause future write-back conflict, delays one or more periods until transmitting the target instruction in the delayed period will not cause future write-back conflict if the target instruction will cause future write-back conflict, and takes the delayed period as a new instruction transmitting period. The instruction transmitting module transmits the target instruction in the new instruction transmitting period, and updates the content of the information table, in which the write-back task information of all functional units in N delay periods after the new instruction transmitting period is stored. The device provided by the embodiment of the present disclosure can implement the pipeline processing of the multiple-transmitting processor on parallel instructions on different hardware platforms, improve the processing efficiency of parallel instructions, and facilitate the flexible configuration and scheduling of hardware resources (write-back port resources of the functional units and register stacks of the multiple-transmitting processor).

[0064] In an exemplary embodiment, the instruction comprises a very long instruction word (VLIW) instruction or a superscalar instruction.

[0065] In an exemplary embodiment, the period is one beat of a pipeline beat.

[0066] In an exemplary embodiment, the information table comprises M rows and N columns, and the information whether the i th functional unit has a write-back task in the j th delay period in the future is stored in the i th row and the j th column of the information table; wherein M is the total number of functional units, 1≤i≤M, and 1≤j≤N.

[0067] In an exemplary embodiment, the information table comprises M rows and N columns, and the content of the information table is stored in a two-dimensional register matrix, the two-dimensional register matrix comprises M rows and N columns of registers, and the register in the i th row and the j th column of the two-dimensional register matrix stores the information in the i th row and the j th column of the information table; wherein M is the total number of functional units, 1≤i≤M, and 1≤j≤N. Using the centralized two-dimensional register matrix is beneficial to back-end layout and wiring, and reduces the connection between the transmitting unit and the functional unit.

[0068] In an exemplary embodiment, the registers of the two-dimensional register matrix are single-bit registers. Using single-bit registers can further reduce hardware wiring.

[0069] In an exemplary embodiment, the information whether there is a write-back task in the future jth delay cycle for the ith functional unit is represented by a flag bit; if there is a write-back task, the flag bit is set to 1; if there is no write-back task, the flag bit is set to 0.

[0070] In an exemplary embodiment, the querying and judging module is configured to query the information table to determine whether transmitting the target instruction in the current cycle will cause future write-back conflicts in the following manner:

[0071] taking the functional unit that will execute the target instruction as a target functional unit, and taking the cycle in which the write-back task of the target instruction will be executed when the target instruction is transmitted in the current cycle as a target cycle;

[0072] querying the information table to determine whether there is a write-back task for the target functional unit in the target cycle; if yes, it is determined that a first write-back conflict is detected, and if no, it is determined that a first write-back conflict is not detected;

[0073] if a first write-back conflict is not detected, querying the information table to determine whether the total number of write-back tasks that have existed for all functional units in the target cycle is less than the total number of write-back ports of the register file; if yes, it is determined that a second write-back conflict is not detected, and if no, it is determined that a second write-back conflict is detected;

[0074] if a first write-back conflict or a second write-back conflict is detected, it is determined that transmitting the target instruction in the current cycle will cause future write-back conflicts; if a first write-back conflict and a second write-back conflict are not detected, it is determined that transmitting the target instruction in the current cycle will not cause future write-back conflicts.

[0075] In an exemplary embodiment, the querying and judging module is configured to take a delayed cycle as a new instruction transmission cycle by performing the following steps a to d:

[0076] step a, delaying one cycle;

[0077] step b, updating the content of the information table with the delayed cycle as the current cycle;

[0078] step c, querying the updated information table to determine whether transmitting the target instruction in the current cycle will cause future write-back conflicts; if yes, returning to step a, and if no, performing step d;

[0079] step d, taking the current cycle as the new instruction transmission cycle.

[0080] In an exemplary embodiment, the querying and judging module is configured to update the content of the information table using the following method with the delayed period as the current period:

[0081] The content of the information table is shifted left by one column, the content of the leftmost column is removed from the information table, a new column is added to the rightmost side of the information table, and the flag bit of all rows of the new column is set to 0.

[0082] The information table includes M rows and N columns, the flag bit in the i-th row and the j-th column of the information table is used to indicate whether the i-th functional unit has a write-back task in the j-th delay period in the future, if the write-back task exists, the flag bit is set to 1, if the write-back task does not exist, the flag bit is set to 0, M is the total number of functional units, 1≤i≤M, 1≤j≤N.

[0083] In an exemplary embodiment, the instruction transmitting module is configured to update the content of the information table using the following method, and store the write-back task information of all functional units in the N delay periods after the new instruction transmitting period in the updated information table:

[0084] The functional unit that executes the target instruction is taken as the target functional unit, and the period in which the write-back task of the target instruction is located when the target instruction is transmitted in the new instruction transmitting period is taken as the target period.

[0085] The flag bit in the information table that is used to indicate whether the target functional unit has a write-back task in the target period is set to indicate that the write-back task exists.

[0086] As shown in FIG. 4, the embodiment of the disclosure provides a parallel instruction processing apparatus, which includes a memory and a processor, the memory stores a computer program, and the computer program is executed by the processor to implement the steps of the parallel instruction processing method.

[0087] The embodiment of the disclosure provides a non-transitory computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the steps of the parallel instruction processing method.

[0088] The following describes the parallel instruction processing process by taking a dual-transmit processor as an example.

[0089] Suppose the processor has 6 functional units, a two-dimensional register matrix (single bit) is established to carry the content of the information table, which stores the flag information of whether the 6 functional units have write back tasks in the future 6 delay cycles. The flag bit in the i-th row and the j-th column is set to 1, indicating that the i-th functional unit has a write back task in the future j-th delay cycle. The flag bit in the i-th row and the j-th column is set to 0, indicating that the i-th functional unit does not have a write back task in the future j-th delay cycle. The processor is dual-emitting, and the number of write back ports of the register file is limited to 2. 1≤i≤6, 1≤j≤6.

[0090] (I) Time 0 (0th beat of the pipeline)

[0091] Initialize the two-dimensional register matrix at the beginning of time 0, and initialize the storage content of the two-dimensional register matrix to all 0s. At the beginning of time 0, the storage content of the two-dimensional register matrix is shown in Table 2.

[0092] Table 2

[0093] Suppose there are two instructions to be emitted at time 0, where instruction 1 is executed by functional unit 5 and needs to be written back in the 5th delay cycle, and instruction 2 is executed by functional unit 6 and needs to be written back in the 6th delay cycle.

[0094] Take instruction 1 as the target instruction, functional unit 5 as the target functional unit, and the 5th delay cycle as the target cycle. Query the two-dimensional register matrix, find that the 5th row and the 5th column are 0, indicating that functional unit 5 does not need to be written back in the 5th delay cycle, so it is determined that there is no first write back conflict. Query the two-dimensional register matrix, find that the 5th column is all 0, indicating that all functional units do not need to be written back in the 5th delay cycle, and the total number of write back tasks of all functional units does not exceed the write back port number limit of the register file, it is determined that there is no second write back conflict. On the premise that no first write back conflict and second write back conflict are detected, it is determined that instruction 1 can be emitted. Emit instruction 1 to functional unit 5, and update the two-dimensional register matrix, set the 5th row and the 5th column of the two-dimensional register matrix to 1, indicating that functional unit 5 needs to be written back in the 5th delay cycle.

[0095] The instruction 2 is taken as the target instruction, the functional unit 6 is taken as the target functional unit, and the 6th delay cycle is taken as the target cycle. The two-dimensional register matrix is queried, and it is found that the 6th row and the 6th column are 0, indicating that the functional unit 6 does not need to write back in the 6th delay cycle, and thus it is determined that there is no first write-back conflict. The two-dimensional register matrix is queried, and it is found that all the 6th columns are 0, indicating that all the functional units do not need to write back in the 6th delay cycle, and the total number of write-back tasks of all the functional units does not exceed the write-back port number limit of the register file, and thus it is determined that there is no second write-back conflict. On the premise that no first write-back conflict and no second write-back conflict are detected, it is determined that the instruction 2 can be issued. The instruction 2 is issued to the functional unit 6, and the two-dimensional register matrix is updated, and the 6th row and the 6th column of the two-dimensional register matrix are set to 1, indicating that the functional unit 6 needs to write back in the 6th delay cycle.

[0096] At the end of time 0, the storage content of the two-dimensional register matrix is shown in Table 3.

[0097] Table 3

[0098] (B) Time 1 (1st beat of the pipeline)

[0099] At the beginning of time 1, the storage content of the two-dimensional register matrix is updated, and the information table stored by the two-dimensional register matrix is shifted one column to the left, and the content of the leftmost column is removed, and a new column is added to the rightmost side of the information table, and the flag bit of all the rows of the new column is set to 0.

[0100] At the beginning of time 1, the information table stored by the two-dimensional register matrix is shown in Table 4.

[0101] Table 4

[0102] Suppose that at time 1, two instructions are to be issued, in which instruction 1 is executed by the functional unit 5 and needs to write back in the 4th delay cycle, and instruction 2 is executed by the functional unit 6 and needs to write back in the 5th delay cycle.

[0103] The instruction 1 is taken as the target instruction, the functional unit 5 is taken as the target functional unit, and the 4th delay cycle is taken as the target cycle. The two-dimensional register matrix is queried, and it is found that the 5th row and the 4th column are 1, indicating that the functional unit 5 needs to write back in the 4th delay cycle, that is, the functional unit 5 already has a write-back task in the 4th delay cycle, and thus it is determined that there is a first write-back conflict. On the premise that the first write-back conflict has been detected, it is determined that the instruction 1 cannot be issued.

[0104] The instruction 2 is taken as the target instruction, the functional unit 6 is taken as the target functional unit, and the fifth delay period is taken as the target period. The two-dimensional register matrix is inquired, and it is found that the sixth row and the fifth column is 1, indicating that the functional unit 6 needs to write back in the fifth delay period, that is, the functional unit 6 already has a write back task in the fifth delay period, and thus it is determined that there is a first write back conflict. On the premise that the first write back conflict has been detected, it is determined that the instruction 2 cannot be transmitted.

[0105] At time 1, neither the instruction 1 nor the instruction 2 can be transmitted, and one delay period is waited.

[0106] At the end of time 1, the information table stored by the two-dimensional register matrix is not updated (remains unchanged).

[0107] (Three) Time 2 (second beat of the pipeline)

[0108] At the beginning of time 2, the storage content of the two-dimensional register matrix is updated, the information table stored by the two-dimensional register matrix is shifted one column to the left, the content of the leftmost column is removed, and a new column is added at the rightmost side of the information table, and the flag bit of all rows of the new column is set to 0.

[0109] At the beginning of time 2, the information table stored by the two-dimensional register matrix is shown in Table 5.

[0110] Table 5

[0111] Since the two instructions at time 1 are not sent at time 1, a delay of one period needs to be sent at time 2. Therefore, at time 2, there are two instructions to be transmitted, of which the instruction 1 is executed by the functional unit 5 and needs to be written back in the fourth delay period, and the instruction 2 is executed by the functional unit 6 and needs to be written back in the fifth delay period.

[0112] The instruction 1 is taken as the target instruction, the functional unit 5 is taken as the target functional unit, and the fourth delay period is taken as the target period. The two-dimensional register matrix is inquired, and it is found that the fifth row and the fourth column is 0, indicating that the functional unit 5 does not need to write back in the fourth delay period, and thus it is determined that there is no first write back conflict. The two-dimensional register matrix is inquired, and it is found that there is only one 1 (appearing in the sixth row) in the fourth column, indicating that only the functional unit 6 needs to write back in the fourth delay period, and the total number of write back tasks of all functional units does not exceed the write back port number limit (2) of the register file, and it is determined that there is no second write back conflict. On the premise that the first write back conflict and the second write back conflict are not detected, it is determined that the instruction 1 can be transmitted. The instruction 1 is transmitted to the functional unit 5, and the two-dimensional register matrix is updated, and the fifth row and the fourth column of the two-dimensional register matrix is set to 1, indicating that the functional unit 5 needs to write back in the fourth delay period.

[0113] The instruction 2 is taken as a target instruction, the functional unit 6 is taken as a target functional unit, and the 6th delay cycle is taken as a target cycle. The two-dimensional register matrix is queried, and it is found that the 6th row and the 5th column are 0, indicating that the functional unit 6 does not need to write back in the 5th delay cycle, and thus it is determined that there is no first write-back conflict. The two-dimensional register matrix is queried, and it is found that all the 5th columns are 0, indicating that all the functional units do not need to write back in the 5th delay cycle, and the total number of write-back tasks of all the functional units does not exceed the write-back port number limit of the register file, and it is determined that there is no second write-back conflict. On the premise that no first write-back conflict and no second write-back conflict are detected, it is determined that the instruction 2 can be issued. The instruction 2 is issued to the functional unit 6, and the two-dimensional register matrix is updated, and the 6th row and the 5th column of the two-dimensional register matrix are set to 1, indicating that the functional unit 6 needs to write back in the 5th delay cycle.

[0114] At the end of time 2, the storage content of the two-dimensional register matrix is shown in Table 6.

[0115] Table 6

[0116] The parallel instruction processing method provided in the embodiments of the present application can uniformly implement the pipeline processing of the parallel instruction of the multi-issue processor on different hardware platforms, improves the processing efficiency of the parallel instruction, and facilitates the flexible configuration and scheduling of the hardware resources (the write-back port resources of the functional units and the register file of the multi-issue processor). The parallel instruction processing method provided in the embodiments of the present application maintains the time information of the write-back tasks of different functional units by using a centralized two-dimensional register matrix, checks the corresponding row and column of the two-dimensional register matrix before sending the instruction to determine whether there is a register write-back port conflict in the functional unit or a conflict of the maximum write-back port number limit of the register file between the functional units, and then sends the instruction on the premise that there is no resource conflict, thereby improving the execution success rate of the instruction. The use of the centralized register matrix is beneficial to the back-end layout and wiring, and reduces the connection between the issue unit and the functional unit. Moreover, the regularized register matrix scheme has high flexibility and scalability, and can be easily adapted to various hardware platforms of the multi-issue processor, and uniformly allocates and schedules the resources of the multi-issue processor including different numbers of functional units and the register file with different write-back port number limits.

[0117] Those of ordinary skill in the art will realize that the function modules / units in the apparatus disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementation, the division between the function modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Certain components or all components can be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on computer-readable media, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As is well known to those of ordinary skill in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Further, it is common knowledge to those of ordinary skill in the art that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and can include any information delivery media.

[0118] It should be noted that the above-described embodiments or implementations are merely exemplary, but not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the forms and details of implementation without departing from the scope of the present disclosure.

Claims

1. A method for processing parallel instructions, comprising: Establish an information table for storing instruction write-back task information. The information table stores write-back task information of multiple functional units in the next N delay cycles; where N is the maximum number of delay cycles for write-back tasks of all instructions in the instruction set. The instruction expected to be launched in the current week is taken as the target instruction. The information table is queried to determine whether launching the target instruction in the current period will cause a future write-back conflict. If it will not cause a future write-back conflict, the current period is taken as a new instruction launch period. If it will cause a future write-back conflict, one or more periods are delayed until launching the target instruction in the delayed period will not cause a future write-back conflict. The delayed period is taken as a new instruction launch period. The target instruction is transmitted in the new instruction transmission cycle, and the contents of the information table are updated. The updated information table stores the write-back task information of all functional units within N delay cycles after the new instruction transmission cycle.

2. The method according to claim 1, wherein: The information table comprises M rows and N columns. The i-th row and j-th column of the information table stores information about whether the i-th functional unit has a write-back task in the j-th future delay period. Here, M is the total number of functional units; 1≤i≤M, 1≤j≤N.

3. The method according to claim 2, wherein: The contents of the information table are stored in a two-dimensional register matrix, which includes M rows and N columns of registers. The register in the i-th row and j-th column of the two-dimensional register matrix stores the information in the i-th row and j-th column of the information table.

4. The method according to claim 3, wherein: The registers in the two-dimensional register matrix are single-bit registers; The presence of a write-back task in the i-th functional unit during the j-th delay period is indicated by a flag; if a write-back task exists, the flag is set to 1. If there is no write-back task, the flag is set to 0.

5. The method according to claim 2, wherein: Querying the information table to determine whether issuing the target instruction in the current cycle will cause a future write-back conflict includes: The functional unit that executes the target instruction is designated as the target functional unit, and the period in which the write-back task of the target instruction is located when the target instruction is emitted in the current period is designated as the target period. The information table is queried to determine whether the target functional unit has a write-back task in the target period. If yes, it is determined that the first write-back conflict has been detected; otherwise, it is determined that the first write-back conflict has not been detected. If no first write-back conflict is detected, the information table is queried to determine whether the total number of write-back tasks that all functional units have existed in the target period is less than the total number of write-back ports in the register file. If yes, it is determined that no second write-back conflict has been detected; otherwise, it is determined that a second write-back conflict has been detected. If a first write-back conflict or a second write-back conflict is detected, it is determined that issuing the target instruction in the current cycle will cause a future write-back conflict; if neither a first write-back conflict nor a second write-back conflict is detected, it is determined that issuing the target instruction in the current cycle will not cause a future write-back conflict.

6. The method according to claim 1, wherein: If a future write-back conflict is caused, the target will be delayed by one or more cycles until it is launched in the delayed cycle. The instruction will not cause a future write-back conflict, and the delayed period will be used as the new instruction issue period, including: Perform the following steps a through d: Step a, delay by one cycle; Step b: Update the information table content using the delayed period as the current period; Step c: Query the updated information table to determine whether transmitting the target instruction in the current cycle will cause a future write-back conflict. If yes, return to step a; otherwise, proceed to step d. Step d: Use the current cycle as the new instruction issuance cycle.

7. The method according to claim 6, wherein: The method of updating the information table content using the delayed period as the current period includes: Shift the contents of the information table one column to the left, remove the contents of the leftmost column from the information table, add a new column on the far right of the information table, and set the flag of all rows in the new column to 0. The information table comprises M rows and N columns. The i-th row and j-th column of the information table stores a flag bit indicating whether the i-th functional unit has a write-back task in the j-th future delay period. If a write-back task exists, the flag bit is set to 1; if no write-back task exists, the flag bit is set to 0. M is the total number of functional units; 1≤i≤M, 1≤j≤N.

8. A parallel instruction processing apparatus, comprising: The information table creation module is configured to create an information table for storing instruction write-back task information. The information table stores write-back task information of multiple functional units within the next N delay cycles; where N is the maximum number of delay cycles for write-back tasks of all instructions in the instruction set. The query and judgment module is configured to take the instruction expected to be launched in the current week as the target instruction, query the information table to determine whether launching the target instruction in the current period will cause a future write-back conflict. If it will not cause a future write-back conflict, the current period will be used as a new instruction launch period. If it will cause a future write-back conflict, one or more periods will be delayed until launching the target instruction in the delayed period will not cause a future write-back conflict. The delayed period will then be used as a new instruction launch period. The command issuance module is configured to issue the target command in the new command issuance cycle and update the contents of the information table. The updated information table stores the write-back task information of all functional units within N delay cycles after the new command issuance cycle.

9. A parallel instruction processing apparatus, comprising: A memory and a processor, wherein the memory stores a computer program, which, when executed by the processor, implements the steps of the parallel instruction processing method according to any one of claims 1-7.

10. A non-transient computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the processing method of the parallel instructions according to any one of claims 1-7.

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