Shift register and driving method therefor, gate driver circuit, and display apparatus

Abstract

The embodiments of the present disclosure provide a shift register and a driving method therefor, a gate driver circuit, and a display apparatus. The shift register can comprise an input circuit, a first control circuit, a reset circuit, a second control circuit, and an output circuit. The first control circuit is configured for controlling a voltage of a first node according to a first voltage, a second clock signal, and a voltage of a second node. The reset circuit is configured for resetting the first node according to the voltage of the second node, a third clock signal, and a second voltage. The output circuit is configured for providing a scan driving signal by means of a signal output terminal according to the voltage of the second node, the second voltage, a voltage of a third node, and a fourth clock signal. A first clock signal and the fourth clock signal have a first high level and a first low level, are identical in frequency, and have a phase difference of 180 degrees. The second clock signal and the third clock signal have a second high level and a second low level, are identical in frequency, and have a phase difference of 180 degrees. The second high level is less than the first high level.

Description

Shift register and driving method thereof, gate driving circuit and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a shift register and driving method thereof, a gate driving circuit and a display device. BACKGROUND

[0002] Gate Driver on Array (GOA) technology makes the gate driving circuit on the array substrate to realize the function of scanning the pixels row by row. The gate driving circuit can include a plurality of cascaded shift registers. A scanning signal is output from the signal output end of the shift register to drive the pixels, and a cascaded signal can be output at the same time to drive the next stage shift register.

[0003] In the field of display, Organic Light-Emitting Diode (OLED) display devices have the characteristics of wide visual angle and fast response speed, and therefore are widely used. OLED display devices use the driving current provided by the driving transistor in the pixel circuit to drive the light emitting device to emit light.

[0004] SUMMARY

[0005] Embodiments of the present disclosure provide a shift register and driving method thereof, a gate driving circuit, an array substrate and a display device.

[0006] According to a first aspect of the present disclosure, a shift register is provided, which includes an input circuit, a first control circuit, a reset circuit, a second control circuit, and an output circuit. The input circuit is coupled to a signal input terminal, a first clock signal terminal, and a first node, and is configured to provide an input signal from the signal input terminal to the first node according to a first clock signal from the first clock signal terminal. The first control circuit is coupled to a first voltage terminal, a second clock signal terminal, the first node, and a second node, and is configured to control a voltage of the first node according to a first voltage from the first voltage terminal, a second clock signal from the second clock signal terminal, and a voltage of the second node. The reset circuit is coupled to the second node, a second voltage terminal, a third clock signal terminal, and the first node, and is configured to reset the first node according to the voltage from the second node, a third clock signal from the third clock signal terminal, and a second voltage from the second voltage terminal. The second control circuit is coupled to the first voltage terminal, the first node, and a third node, and is configured to control a voltage of the third node according to the first voltage and the voltage of the first node. The output circuit is coupled to the second node, the second voltage terminal, a signal output terminal, the third node, and a fourth clock signal terminal, and is configured to provide a scan driving signal through the signal output terminal according to the voltage of the second node, the second voltage, the voltage of the third node, and a fourth clock signal from the fourth clock signal terminal. The first clock signal and the fourth clock signal have a first high level and a first low level. The first clock signal and the fourth clock signal have the same frequency and a phase difference of 180 degrees. The second clock signal and the third clock signal have a second high level and a second low level. The second clock signal and the third clock signal have the same frequency and a phase difference of 180 degrees. The second high level is less than the first high level.

[0007] In embodiments of the present disclosure, the first clock signal and the second clock signal have the same frequency and phase, and the third clock signal and the fourth clock signal have the same frequency and phase.

[0008] In embodiments of the present disclosure, the first high level is the same as the first voltage, the first low level is the same as the second voltage, and the first low level is the same as the second low level.

[0009] In embodiments of the present disclosure, the first high level is 14V, the second high level is 6V, and the first low level and the second low level are -6V.

[0010] In embodiments of the present disclosure, the first high level is 14V, the second high level is 10V, and the first low level and the second low level are -6V.

[0011] In embodiments of the present disclosure, a high level of the input signal is less than the first high level and greater than or equal to the second high level.

[0012] In embodiments of the present disclosure, the input circuit includes a first transistor, a control electrode of the first transistor is coupled with the first clock signal terminal, a first electrode of the first transistor is coupled with the signal input terminal, and a second electrode of the first transistor is coupled with the first node.

[0013] In embodiments of the present disclosure, the first control circuit includes a second transistor and a third transistor. A control electrode of the second transistor is coupled with the first node, a first electrode of the second transistor is coupled with the second clock signal terminal, and a second electrode of the second transistor is coupled with the second node. A control electrode of the third transistor is coupled with the second clock signal terminal, a first electrode of the third transistor is coupled with the first voltage terminal, and a second electrode of the third transistor is coupled with the second node.

[0014] In embodiments of the present disclosure, the reset circuit includes a fourth transistor and a fifth transistor. A control electrode of the fourth transistor is coupled with the second node, a first electrode of the fourth transistor is coupled with the second voltage terminal, and a second electrode of the fourth transistor is coupled with the fourth node. A control electrode of the fifth transistor is coupled with the third clock signal terminal, a first electrode of the fifth transistor is coupled with the fourth node, and a second electrode of the fifth transistor is coupled with the first node.

[0015] In embodiments of the present disclosure, the second control circuit includes a sixth transistor. A control electrode of the sixth transistor is coupled with the first voltage terminal, a first electrode of the sixth transistor is coupled with the first node, and a second electrode of the sixth transistor is coupled with the third node.

[0016] In embodiments of the present disclosure, the output circuit includes a seventh transistor, an eighth transistor, and a capacitor. A control electrode of the seventh transistor is coupled with the third node, a first electrode of the seventh transistor is coupled with the fourth clock signal terminal, and a second electrode of the seventh transistor is coupled with the signal output terminal. A control electrode of the eighth transistor is coupled with the second node, a first electrode of the eighth transistor is coupled with the second voltage terminal, and a second electrode of the eighth transistor is coupled with the signal output terminal. A first terminal of the capacitor is coupled with the signal output terminal, and a second terminal of the capacitor is coupled with the third node.

[0017] In embodiments of the present disclosure, the input circuit includes a first transistor, a control electrode of the first transistor is coupled with the first clock signal terminal, a first electrode of the first transistor is coupled with the signal input terminal, and a second electrode of the first transistor is coupled with the first node. The first control circuit includes a second transistor and a third transistor. A control electrode of the second transistor is coupled with the first node, a first electrode of the second transistor is coupled with the second clock signal terminal, and a second electrode of the second transistor is coupled with the second node. A control electrode of the third transistor is coupled with the second clock signal terminal, a first electrode of the third transistor is coupled with the first voltage terminal, and a second electrode of the third transistor is coupled with the second node. The reset circuit includes a fourth transistor and a fifth transistor. A control electrode of the fourth transistor is coupled with the second node, a first electrode of the fourth transistor is coupled with the second voltage terminal, and a second electrode of the fourth transistor is coupled with the fourth node. A control electrode of the fifth transistor is coupled with the third clock signal terminal, a first electrode of the fifth transistor is coupled with the fourth node, and a second electrode of the fifth transistor is coupled with the first node. The second control circuit includes a sixth transistor. A control electrode of the sixth transistor is coupled with the first voltage terminal, a first electrode of the sixth transistor is coupled with the first node, and a second electrode of the sixth transistor is coupled with the third node. The output circuit includes a seventh transistor, an eighth transistor, and a capacitor. A control electrode of the seventh transistor is coupled with the third node, a first electrode of the seventh transistor is coupled with the fourth clock signal terminal, and a second electrode of the seventh transistor is coupled with the signal output terminal. A control electrode of the eighth transistor is coupled with the second node, a first electrode of the eighth transistor is coupled with the second voltage terminal, and a second electrode of the eighth transistor is coupled with the signal output terminal. A first end of the capacitor is coupled with the signal output terminal, and a second end of the capacitor is coupled with the third node.

[0018] In embodiments of the present disclosure, the seventh transistor has a bottom control electrode. The bottom control electrode is coupled with the third voltage terminal.

[0019] In embodiments of the present disclosure, the third voltage from the third voltage terminal is the same as the second low level.

[0020] In embodiments of the present disclosure, the second control circuit is alternatively coupled with the fourth voltage terminal, the first node, and the third node, and is configured to control the voltage of the third node according to the fourth voltage from the fourth voltage terminal and the voltage of the first node. The fourth voltage is the same as the second high level.

[0021] In embodiments of the present disclosure, the third control circuit includes a sixth transistor, a control electrode of the sixth transistor is coupled with the fourth voltage terminal, a first electrode of the sixth transistor is coupled with the first node, and a second electrode of the sixth transistor is coupled with the third node.

[0022] In embodiments of the present disclosure, the seventh transistor has a bottom control electrode. The bottom control electrode is coupled with the third voltage terminal. The third voltage from the third voltage terminal is equal to the second low level.

[0023] According to a second aspect of the present disclosure, a gate drive circuit is provided. The gate drive circuit comprises a plurality of cascaded shift registers according to any one of the first aspect of the present disclosure.

[0024] According to a third aspect of the present disclosure, a display device is provided. The display device comprises a gate drive circuit according to the second aspect of the present disclosure.

[0025] According to a fourth aspect of the present disclosure, a method for driving a shift register according to any one of the first aspect of the present disclosure is provided. The method comprises: in a first stage, providing an input signal to a first node and a third node, storing and maintaining a voltage difference between the third node and a signal output terminal; in a second stage, maintaining the voltage difference to make a voltage of the signal output terminal change with a fourth clock signal, thereby outputting the fourth clock signal at the signal output terminal. In a third stage, providing a first voltage to a second node according to a second clock signal, thereby outputting a second voltage at the signal output terminal. In a fourth stage, providing the second voltage to the first node according to a third clock signal, and outputting the second voltage at the signal output terminal; the first clock signal and the fourth clock signal have a first high level and a first low level. The first clock signal and the fourth clock signal have the same frequency and a phase difference of 180 degrees. The second clock signal and the third clock signal have a second high level and a second low level. The second clock signal and the third clock signal have the same frequency and a phase difference of 180 degrees. The second high level is less than the first high level. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the present disclosure, the drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of the present disclosure, and are not a limitation on the present disclosure. In the drawings:

[0027] FIG. 1 shows an exemplary circuit diagram of a shift register;

[0028] FIG. 2 shows a schematic block diagram of a shift register according to an embodiment of the present disclosure;

[0029] FIG. 3 shows an exemplary circuit diagram of a shift register according to an embodiment of the present disclosure;

[0030] FIG. 4 shows an exemplary circuit diagram of a shift register according to another embodiment of the present disclosure;

[0031] FIG. 5 shows an exemplary circuit diagram of a shift register according to yet another embodiment of the present disclosure;

[0032] FIG. 6 shows a timing diagram of various signals in the working process of the shift register shown in FIG. 3;

[0033] FIGS. 7A-7D show a comparison of the bias voltage experienced by the transistors in a shift register having two sets of clock signals as shown in FIG. 3 and a shift register having only one set of clock signals as shown in FIG. 1;

[0034] FIG. 8 shows a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure;

[0035] FIG. 9 shows a schematic diagram of a display device according to an embodiment of the present disclosure; and

[0036] FIG. 10 shows a schematic flowchart of a method for driving a shift register according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] In order to make the technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments, all other embodiments obtained by a person of ordinary skill in the art without any creative effort also fall within the scope of the present disclosure.

[0038] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the common meaning in the art of the present disclosure. The terms “first”, “second”, and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different constituent parts. Similarly, the terms “one”, “a”, or “the” and similar terms do not denote a quantity restriction, but mean that at least one exists. The terms “include”, “contain”, and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms “connected” or “coupled” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, and can be direct connections or indirect connections through intermediate media.

[0039] As described above, each stage of shift registers in the GOA can provide a scan signal to a pixel row to realize line-by-line scanning of the pixel row. In a common shift register, a set of clock signals is used to realize output of the scan signal. FIG. 1 shows a shift register 10. As shown in FIG. 1, the shift register 10 is coupled with only one set of clock signals. In order to ensure the voltage of the high level of the output scan signal, the high level of the clock signal needs to be high enough, which causes some transistors in the shift register 10 to work in an unnecessary high bias state, thereby causing threshold voltage drift of the transistors, reducing reliability and life of the transistors, and further affecting the display effect and life of the shift register and the display device. To solve this problem, the shift register provided by an embodiment of the present disclosure uses two sets of clock signals, and by reducing the value of the high level of one of the sets of clock signals, the working bias of some transistors is reduced while the high level of the scan signal is ensured.

[0040] Embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit, and a display device. Embodiments of the present disclosure and examples thereof are described in detail below with reference to the accompanying drawings.

[0041] FIG. 2 shows a schematic block diagram of a shift register according to an embodiment of the present disclosure. As shown in FIG. 2, the shift register 20 includes an input circuit 100, a first control circuit 200, a reset circuit 300, a second control circuit 400, and an output circuit 500. Details thereof are described below with reference to the accompanying drawings.

[0042] In an embodiment of the present disclosure, the input circuit 100 is coupled with a signal input terminal, a first clock signal terminal, and a first node N1, and can provide an input signal STV from the signal input terminal to the first node N1 according to a first clock signal CK1 from the first clock signal terminal. In an embodiment, the input circuit 100 is coupled with the first clock signal terminal to receive the first clock signal CK1. The input circuit 100 is coupled with the signal input terminal to receive the input signal STV. The input circuit 100 can provide the received input signal STV to the first node N1 according to the received first clock signal CK1.

[0043] The first control circuit 200 is coupled with the first voltage terminal, the second clock signal terminal, the first node N1 and the second node N2, and controls the voltage of the second node N2 according to the first voltage V1 from the first voltage terminal, the second clock signal CK2 from the second clock signal terminal and the voltage of the first node N1. In an embodiment, the first control circuit 200 is coupled with the first voltage terminal to receive the first voltage V1. The first control circuit 200 is coupled with the second clock signal terminal to receive the second clock signal CK2. The first control circuit 200 controls the voltage of the second node N2 according to the received second clock signal CK2 and the voltage of the first node N1. In an embodiment of the present disclosure, the first voltage V1 can be a high voltage, for example, 14V.

[0044] The reset circuit 300 is coupled with the second node N2, the second voltage terminal, the third clock signal terminal and the first node N1, and is configured to reset the first node N1 according to the voltage from the second node N2, the third clock signal CB2 from the third clock signal terminal and the second voltage V2 from the second voltage terminal. In an embodiment, the reset circuit 300 is coupled with the second voltage terminal to receive the second voltage V2. The reset circuit 300 is coupled with the third clock signal terminal to receive the third clock signal CB2. The reset circuit 300 provides the second voltage V2 to the first node N1 according to the third clock signal CB2 and the voltage of the second node N2 to reset the first node N1. In an embodiment of the present disclosure, the second voltage V2 can be a low voltage, for example, -6V. In an embodiment of the present disclosure, the second clock signal CK2 and the third clock signal CB2 are a set of clock signals. Specifically, the second clock signal CK2 and the third clock signal CB2 have a second high level VH2 and a second low level VL2. The second clock signal CK2 and the third clock signal CB2 have the same frequency and a phase difference of 180 degrees. In an embodiment of the present disclosure, the second high level VH2 is 8V and the second low level VL2 is -6V. In another embodiment of the present disclosure, the second high level VH2 is 10V and the second low level VL2 is -6V.

[0045] The second control circuit 400 is coupled with the first voltage terminal, the first node N1 and the third node N3, and is configured to control the voltage of the third node N3 according to the first voltage V1 and the voltage of the first node N1. In an embodiment of the present disclosure, the second control circuit 400 is coupled with the first voltage terminal to receive the first voltage V1. The second control circuit 400 provides the voltage of the first node N1 to the voltage of the third node N3 according to the first voltage V1.

[0046] Alternatively, in other implementations of the present disclosure, the second control circuit 400 is coupled with the fourth voltage terminal instead of the first voltage terminal. The second control circuit 400 is coupled with the fourth voltage terminal, the first node N1 and the third node N3, and is configured to control the voltage of the third node N3 according to the fourth voltage V4 from the fourth voltage terminal and the voltage of the first node N1. In the present embodiment, the fourth voltage V4 is the same as the second high level VH2. Specifically, this will be described in detail below with reference to FIG. 5.

[0047] The output circuit 500 is coupled with the second node N2, the second voltage terminal, the signal output terminal OUTPUT, the third node N3 and the fourth clock signal terminal, and is configured to provide the scan driving signal through the signal output terminal OUTPUT according to the voltage of the second node N2, the second voltage V2, the voltage of the third node N3 and the fourth clock signal CB1 from the fourth clock signal terminal. In the embodiments of the present disclosure, the output circuit 500 is coupled with the second voltage terminal to receive the second voltage V2. The output circuit 500 is coupled with the fourth clock signal terminal to receive the fourth clock signal CB1. The output circuit 500 provides the scan driving signal through the signal output terminal OUTPUT according to the voltage of the second node N2, the second voltage V2, the voltage of the third node N3 and the fourth clock signal CB1. In the embodiments of the present disclosure, the first clock signal CK1 and the fourth clock signal CB1 are a group of clock signals. Specifically, the first clock signal CK1 and the fourth clock signal CB1 have the first high level VH1 and the first low level VL1. The first clock signal CK1 and the fourth clock signal CB1 have the same frequency and a phase difference of 180 degrees. In the embodiments of the present disclosure, the first high level VH1 is greater than the second high level VH2. For example, the first high level VH1 is 14V. The first low level VL1 is the same as the second low level VL2. For example, the first low level VL1 is -6V.

[0048] In the embodiments of the present disclosure, the high level of the input signal STV is less than the first high level VH1 and greater than or equal to the second high level.

[0049] FIG. 3 shows an example circuit diagram of a shift register 30 according to an embodiment of the present application. As shown in FIG. 3, the shift register 30 includes first to eighth transistors T1-T8 and a capacitor C.

[0050] It should be noted that the transistors used in the embodiments of the present disclosure can be thin film transistors or field effect transistors (for example, Low Temperature Poly-Silicon transistors and oxide thin film transistors) or other switching devices with the same characteristics. The embodiments of the present disclosure are described by taking thin film transistors as an example. The source and drain of the transistor used herein can be symmetrical in structure, so the source and drain can be indistinguishable in structure. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is directly described as the first pole and the other is the second pole. The gate of the transistor can be referred to as the control pole. In addition, the transistor can be divided into N-type and P-type transistors according to the characteristics of the transistor. When the transistor is a P-type transistor, the on voltage is a low-level voltage and the off voltage is a high-level voltage. When the transistor is an N-type transistor, the on voltage is a high-level voltage and the off voltage is a low-level voltage.

[0051] In addition, it should be noted that the transistors used in the shift register provided in the embodiments of the present disclosure are described by taking N-type transistors as an example. The embodiments of the present disclosure include but are not limited to this, for example, at least part of the transistors in the shift register can also use P-type transistors.

[0052] The input circuit 100 includes a first transistor T1. The control pole of the first transistor T1 is coupled with the first clock signal end, the first pole of the first transistor T1 is coupled with the signal input end, and the second pole of the first transistor T1 is coupled with the first node N1.

[0053] The first control circuit 200 includes a second transistor T2 and a third transistor T3. The control pole of the second transistor T2 is coupled with the first node N1, the first pole of the second transistor T2 is coupled with the second clock signal end, and the second pole of the second transistor T2 is coupled with the second node N2. The control pole of the third transistor T3 is coupled with the second clock signal end, the first pole of the third transistor T3 is coupled with the first voltage end, and the second pole of the third transistor T3 is coupled with the second node N2.

[0054] The reset circuit 300 includes a fourth transistor T4 and a fifth transistor T5. The control pole of the fourth transistor T4 is coupled with the second node N2, the first pole of the fourth transistor T4 is coupled with the second voltage end, and the second pole of the fourth transistor T4 is coupled with the fourth node N4. The control pole of the fifth transistor T5 is coupled with the third clock signal end, the first pole of the fifth transistor T5 is coupled with the fourth node N4, and the second pole of the fifth transistor T5 is coupled with the first node N1.

[0055] The second control circuit 400 includes a sixth transistor T6. The control electrode of the sixth transistor T6 is coupled with the first voltage terminal, the first electrode of the sixth transistor T6 is coupled with the first node N1, and the second electrode of the sixth transistor T6 is coupled with the third node N3. In an embodiment of the present disclosure, the sixth transistor T6 can be a single-gate transistor.

[0056] The output circuit 500 includes a seventh transistor T7, an eighth transistor T8, and a capacitor C. The control electrode of the seventh transistor T7 is coupled with the third node N3, the first electrode of the seventh transistor T7 is coupled with the fourth clock signal terminal, and the second electrode of the seventh transistor T7 is coupled with the signal output terminal OUTPUT. The control electrode of the eighth transistor T8 is coupled with the second node N2, the first electrode of the eighth transistor T8 is coupled with the second voltage terminal, and the second electrode of the eighth transistor T8 is coupled with the signal output terminal OUTPUT. The first terminal of the capacitor C is coupled with the signal output terminal OUTPUT, and the second terminal of the capacitor C is coupled with the third node N3.

[0057] Figure 4 shows an example circuit diagram of a shift register 40 according to another embodiment of the present disclosure. The shift register 40 shown in Figure 4 is different from the shift register 30 shown in Figure 3 in that the eighth transistor T8 has a bottom control electrode. As shown in Figure 4, the eighth transistor T8 has a bottom control electrode. A transistor has a substrate and an active layer on the substrate. The active layer includes a channel region corresponding to the gate and a portion opposite to the channel region. The bottom control electrode is coupled with the portion. The bottom control electrode of the eighth transistor T8 is coupled with the third voltage terminal. The third voltage V3 from the third voltage terminal can be a low level. For example, the third voltage V3 is the same as the second low level VL2. The bottom control electrode can cause the eighth transistor T8 to increase the current passing capability of the transistor in the case of turning on the transistor without changing the voltage difference between the first electrode and the second electrode of the transistor. In addition, in implementation, the eighth transistor T8 can be an oxide thin film transistor. The threshold voltage of the oxide thin film transistor is prone to negative bias, which will cause the oxide thin film transistor in the circuit to leak. By adding the bottom control electrode, the output characteristic curve of the oxide thin film transistor can be adjusted to reduce or offset the effect of the negative bias threshold voltage, avoid the leakage of the transistor, and thus prevent the failure of the circuit.

[0058] The input circuit 100, the first control circuit 200, the reset circuit 300, and the second control circuit 400 in Figure 4 are similar to those in Figure 3, and will not be described here again.

[0059] Figure 5 shows an example circuit diagram of a shift register 50 according to another embodiment of the present disclosure. The shift register 50 shown in Figure 5 is different from the shift register 30 shown in Figure 3 in that the second control circuit 400 is coupled to the fourth voltage terminal V4 instead of the first voltage terminal V1. As shown in Figure 5, the second control circuit 400 includes a sixth transistor T6. The control terminal of the sixth transistor T6 is coupled to the fourth voltage terminal, the first terminal of the sixth transistor T6 is coupled to the first node N1, and the second terminal of the sixth transistor T6 is coupled to the third node N3. The input circuit 100, the first control circuit 200, the reset circuit 300, and the output circuit 500 in Figure 5 are similar to those in Figure 3 and will not be described again here.

[0060] The operation of the shift register 30 shown in Figure 3 will be described below in conjunction with the signal timing diagram in Figure 6. In an embodiment, the first voltage V1 is high at 14V and the second voltage is low at -6V. The first set of clock signals includes the first clock signal CK1 and the fourth clock signal CB1. The first high voltage VH1 of the first clock signal CK1 and the fourth clock signal CB1 is 14V and the first low voltage VL1 is -6V. The first clock signal CK1 and the fourth clock signal CB1 have the same frequency and a phase difference of 180 degrees. The second set of clock signals includes the second clock signal CK2 and the third clock signal CB2. The second high voltage VH2 of the second clock signal CK2 and the third clock signal CB2 is 10V and the second low voltage VL2 is -6V. The second clock signal CK2 and the third clock signal CB2 have the same frequency and a phase difference of 180 degrees. The first clock signal CK1 and the second clock signal CK2 have the same frequency and phase, and the third clock signal CB2 and the fourth clock signal CB1 have the same frequency and phase. In the present disclosure, a shift register with a set of clock signals is equivalent to the first clock signal CK1 and the second clock signal CK2 coupled to the shift register in Figure 2 being exactly the same, e.g., 14V, and the third clock signal CB2 and the fourth clock signal CB1 being exactly the same, e.g., -6V.

[0061] As shown in FIG. 6, in the first stage t1, the shift register 30 receives the input signal STV at a high level, the first clock signal CK1, the second clock signal CK2 and the first voltage V1, the third clock signal CB2, the fourth clock signal CB1 and the second voltage V2 at a low level. The first transistor T1 is turned on, and the received input signal STV at a high level is provided to the first node N1. The voltage of the N2 node is equal to the first voltage V1. The sixth transistor T6 is turned on, and the high level of the first node N1 is provided to the third node N3. The high level is saved by the capacitor C. The third transistor T3 is turned off. As previously described, in the embodiment of the present disclosure, the high level of the input signal STV is less than the first voltage V1, and thus the second transistor T2 is turned on, and the first voltage V1 is provided to the second node N2. Since the high level of the second clock signal CK2 is less than the first clock signal CK1, the fourth transistor T4 is turned on, and the high voltage of the second node N2 is provided to the fourth node N4. The eighth transistor T8 is turned on, and the second voltage V2 at a low level is provided to the signal output terminal OUTPUT as a scan signal. The seventh transistor T7 is turned off.

[0062] As shown in FIG. 6, in the first stage t1, the voltage of the second node N2 in the shift register 30 is lower than that in the shift register 10 having only one set of clock signals. Therefore, the working bias of the transistor whose control electrode is coupled to the second node N2 changes. In the embodiment of the present disclosure, the working bias of the transistor refers to the voltage difference VGS between the control electrode and the second electrode of the transistor. The working bias of the transistor of the shift register in the first stage t1 is described below with reference to FIG. 7A.

[0063] FIG. 7A is a diagram showing the bias of the transistors in the shift register having two sets of clock signals as shown in FIG. 3 in the first stage and the shift register having only one set of clock signals as shown in FIG. 1. As shown in FIG. 7A, the voltage difference VGS between the control electrode and the second electrode of the fourth transistor T4 and the eighth transistor T8 in the shift register 30 is less than the voltage difference VGS between the control electrode and the second electrode of the fourth transistor T4 and the eighth transistor T8 in the shift register 10 having only one set of clock signals. That is, in the first stage t1, the working bias VGS of the fourth transistor T4 and the eighth transistor T8 is reduced compared with the case of having only one set of clock signals. This can improve the reliability of the fourth transistor T4 and the eighth transistor T8 and thus prolong the service life thereof.

[0064] In the second phase t2, the shift register 30 receives the third clock signal CB2, the fourth clock signal CB2 and the first voltage VI at a high level, and the input signal STV, the first clock signal CK1, the second clock signal CK2 and the second voltage V2 at a low level. The second transistor T2 is turned on, and the second low level of the second clock signal CK2 is provided to the second node N2. The seventh transistor T7 is turned on, and the first high level VG1 of the fourth clock signal CB1 is provided to the signal output terminal OUTPUT. The voltage of the third node N3 is further increased due to the bootstrap effect of the capacitor C. The sixth transistor T6 is turned on, and the further increased voltage of the third node N3 is provided to the first node N1. That is, the voltage of the first node N1 is also further increased. The shift register 30 outputs the first high level VG1 as the scan signal via the signal output terminal OUTPUT. The fifth transistor T5 is turned on, and the high level of the first node N1 is provided to the fourth node N4. The first transistor T1, the third transistor T3, the fourth transistor T4 and the eighth transistor T8 are turned off. As shown in FIG. 6, the voltage of the fourth node N4 in the shift register 30 is decreased compared with the shift register 10 having only one set of clock signals. The working bias of the transistors of the shift register in the second phase t2 is described below with reference to FIG. 7B.

[0065] FIG. 7B shows a comparison of the bias of the transistors in the shift register having two sets of clock signals as shown in FIG. 3 and the shift register having only one set of clock signals as shown in FIG. 1 in the second phase. As mentioned before, there is no transistor whose control electrode is coupled to the fourth node N4, and thus the working bias of the transistor is not affected. As shown in FIG. 7B, the bias VGS between the control electrode and the second electrode of the turned-on second transistor T2 is not changed.

[0066] In the third phase t3, the shift register 30 receives the first clock signal CK1, the second clock signal CK2 and the first voltage VI at a high level, and the input signal STV, the third clock signal CB2, the fourth clock signal CB1 and the second voltage V2 at a low level. The first transistor T1 is turned on, and the received input signal STV at a low level is provided to the first node N1. The third transistor T3 is turned on, and the first voltage VI at a high level is provided to the second node N2. The fourth transistor T4 is turned on, and the second voltage V2 at a low level is provided to the fourth node. The eighth transistor T8 is turned on, and the received second voltage V2 at a low level is provided to the signal output terminal OUTPUT. The shift register 30 outputs the second voltage V2 at a low level as the scan signal via the signal output terminal OUTPUT. The sixth transistor T6 is turned on, and the low level of the first node N1 is provided to the third node N3. The second transistor T2, the fifth transistor T5 and the seventh transistor T7 are turned off.

[0067] As shown in FIG. 6, in the third stage t3, the voltage of the second node N2 of the shift register 30 is lower than that of the shift register 10 having only one set of clock signals. Therefore, the operating bias of the transistor whose control electrode is coupled to the second node N2 is changed. The operating bias of the transistor of the shift register in the third stage t3 is described below with reference to FIG. 7C.

[0068] FIG. 7C is a graph showing the bias of the transistors in the shift register having two sets of clock signals as shown in FIG. 3 in the third stage and the shift register having only one set of clock signals as shown in FIG. 1. As shown in FIG. 7C, the voltage difference VGS between the control electrode and the second electrode of the fourth transistor T4 and the eighth transistor T8 in the shift register 30 is smaller than that of the fourth transistor T4 and the eighth transistor T8 in the shift register 10 having only one set of clock signals. Similarly to FIG. 7A, in the first stage tl, the operating bias VGS of the fourth transistor T4 and the eighth transistor T8 is lowered. This can improve the reliability of the fourth transistor T4 and the eighth transistor T8 and thus prolong the life of the fourth transistor T4 and the eighth transistor T8 compared to the case of having only one set of clock signals.

[0069] In the fourth stage t4, the shift register 30 receives the third clock signal CB2, the fourth clock signal CB2, and the first voltage VI at a high level, and the input signal STV, the first clock signal CK1, the second clock signal CK2, and the second voltage V2 at a low level. The fourth transistor T4 and the fifth transistor T5 are turned on. The second voltage V2 at a low level is supplied to the fourth node N4 and the first node N1. The sixth transistor T6 is turned on, and the first node N1 at a low level is supplied to the third node N3. The eighth transistor T8 is turned on, and the received second voltage V2 at a low level is supplied to the signal output terminal OUTPUT. The shift register 30 outputs the second voltage V2 at a low level as a scan signal via the signal output terminal OUTPUT. The first transistor T1, the second transistor T2, the third transistor T3, and the seventh transistor T7 are turned off.

[0070] As shown in FIG. 6, in the fourth stage t4, the voltage of the second node N2 of the shift register 30 is lower than that of the shift register 10 having only one set of clock signals. Therefore, the operating bias of the transistor whose control electrode is coupled to the second node N2 is changed. The operating bias of the transistor of the shift register in the fourth stage t4 is described below with reference to FIG. 7D.

[0071] FIG. 7D shows a comparison of the bias voltage suffered by the transistors in the shift register with two sets of clock signals as shown in FIG. 3 and the shift register with only one set of clock signals as shown in FIG. 1 in the fourth stage. As shown in FIG. 7D, the voltage difference VGS between the control electrode and the second electrode of the fourth transistor T4, the fifth transistor T5 and the eighth transistor T8 in the shift register 30 is smaller than the voltage difference VGS between the control electrode and the second electrode of the fourth transistor T4, the fifth transistor T5 and the eighth transistor T8 in the shift register with only one set of clock signals. Similarly, in the fourth stage t4, the working bias VGS of the fourth transistor T4, the fifth transistor T5 and the eighth transistor T8 is reduced. This can improve the reliability of the fourth transistor T4, the fifth transistor T5 and the eighth transistor T8 and in turn prolong their service life compared with the case of only one set of clock signals.

[0072] In addition, in FIG. 7D, the voltage difference VDS between the first electrode and the second electrode of the second transistor T2 in the shift register 30 is reduced compared with the shift register 10 with only one set of clock signals. This can improve the stability of the second transistor T2 and prolong its service life.

[0073] Embodiments of the present disclosure also provide a gate drive circuit composed of shift registers. FIG. 8 shows a schematic diagram of a gate drive circuit 60 according to an embodiment of the present disclosure. As shown in FIG. 8, the gate drive circuit 60 can include a plurality of shift registers. Any one or more of the shift registers can adopt the structure of the shift register 20 or 30 provided by an embodiment of the present disclosure or a variant thereof. Only the first three shift registers, i.e., the first shift register SR_1 corresponding to the first row of pixels, the second shift register SR_2 corresponding to the second row of pixels, and the third shift register SR_3 corresponding to the third row of pixels, are shown in FIG. 8.

[0074] The signal output end of the Nth shift register is coupled to the input end of the N+1th shift register, where N is a positive integer. As shown in FIG. 8, the signal input end of the first shift register SR_1 receives an input signal STV_1 from an input signal line INPUT. The high level of the input signal STV_1 is smaller than the first high level VH1 and greater than or equal to the second high level VH2. The signal output end OUTPUT_1 of the first shift register SR_1 is coupled to the signal input end of the second shift register SR_2 to provide an input signal STV_2. The signal output end OUTPUT_2 of the second shift register SR_2 is coupled to the signal input end of the shift register SR_3 to provide an input signal STV_3. Based on the description above regarding FIG. 6, the high levels of the input signals STV_2 and STV_3 are equal to the second high level VH2.

[0075] In embodiments of the present disclosure, the gate drive circuit 60 further includes a first clock signal line CLK_A, a second clock signal line CLK_B, a third clock signal line CLK_C, and a fourth clock signal line CLK_D, a first voltage line VG, and a second voltage line VL. For odd row shift registers, the first clock signal line CLK_A is coupled to the first clock signal terminal of the shift register to provide the first clock signal CK1. The second clock signal line CLK_B is coupled to the second clock signal terminal of the shift register to provide the second clock signal CK2. The third clock signal line CLK_C is coupled to the third clock signal terminal of the shift register to provide the third clock signal CB2. The fourth clock signal line CLK_D is coupled to the fourth clock signal terminal of the shift register to provide the fourth clock signal CB1. For even row shift registers, the first clock signal line CLK_A is coupled to the fourth clock signal terminal of the shift register to provide the fourth clock signal CB1. The second clock signal line CLK_B is coupled to the third clock signal terminal of the shift register to provide the third clock signal CB2. The third clock signal line CLK_C is coupled to the second clock signal terminal of the shift register to provide the second clock signal CK2. The fourth clock signal line CLK_D is coupled to the first clock signal terminal of the shift register to provide the first clock signal CK1. It should be understood by those skilled in the art that the coupling relationship of the clock signal terminals of the odd row shift registers and the even row shift registers can be interchanged. In addition, the first voltage line VG1 is coupled to the first voltage terminal of all the shift registers to provide the first voltage V1. The second voltage line VL is coupled to the second voltage terminal of all the shift registers to provide the second voltage V2.

[0076] Alternatively, in other embodiments of the present disclosure, the gate drive circuit 60 includes a plurality of shift registers 40. The gate drive circuit further includes a third voltage line VL2 to provide a third voltage V3.

[0077] Alternatively, in another embodiment of the present disclosure, the gate drive circuit 60 includes a plurality of shift registers 50. The gate drive circuit further includes a fourth voltage line VG2 to provide a fourth voltage V4.

[0078] Embodiments of the present disclosure also provide a display device including the above-mentioned gate drive circuit. FIG. 9 shows a display device according to embodiments of the present disclosure. As shown in FIG. 9, the display device 70 includes the gate drive circuit 60. In embodiments, the display device can be a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function.

[0079] Furthermore, embodiments of the present disclosure also provide a method for driving a shift register. FIG. 10 shows a schematic flowchart of a method for driving a shift register according to an embodiment of the present disclosure. The shift register can be any applicable shift register based on embodiments of the present disclosure.

[0080] At step 1100, at the first stage t1, the input signal STV is provided to the first node N1 and the third node N3, the voltage difference between the third node N3 and the signal output terminal OUTPUT is stored and maintained, and the first voltage V1 is provided to the second node N2. In an embodiment, when driving of a certain row of pixels is required, the input circuit 100 provides the input signal STV to the first node N1 according to the first clock signal CK1. The second control circuit 200 provides the voltage of the first node N1 to the third node N3. The output circuit 500 stores and maintains the voltage difference between the third node N3 and the signal output terminal OUTPUT. In the present embodiment, the voltage output by the signal output terminal OUTPUT can be the second voltage. For example, the second voltage can be -6V.

[0081] At step 1200, at the second stage t2, the voltage difference is maintained so that the voltage of the signal output terminal OUTPUT varies with the fourth clock signal CB1, thereby outputting the fourth clock signal CB1 at the signal output terminal. In an embodiment, the output circuit 500 maintains the voltage difference, and the signal output terminal OUTPUT outputs the fourth clock signal CB1. In embodiments of the present disclosure, at the second stage t2, the fourth clock signal CB1 is high, the voltage difference is unchanged, and the voltage of the third node N3 is correspondingly raised. In an embodiment, the first clock signal CK1 and the fourth clock signal CB1 are a group of clock signals having a first high level VH1 and a first low level VL1. The first clock signal CK1 and the fourth clock signal CB1 have the same frequency and a phase difference of 180 degrees. In embodiments of the present disclosure, the first high level VH1 can be 14V, and the first low level VL1 can be -6V.

[0082] At step 1300, at the third stage t3, the first voltage V1 is provided to the second node N2 according to the second clock signal CK2, thereby outputting the second voltage at the signal output terminal. In an embodiment, the first control circuit 200 provides the first voltage V1 to the second node N2 according to the second clock signal CK2. The output circuit 500 outputs the second voltage V2 via the signal output terminal OUTPUT.

[0083] At step 1400, at the fourth stage t4, the second voltage V2 is provided to the first node N1 according to the third clock signal CB2, and the second voltage V2 is output at the signal output terminal OUTPUT. In an embodiment, the reset circuit 300 provides the second voltage V2 to the first node N1 according to the third clock signal CB2 to reset the first node N1. The output circuit 500 continuously outputs the second voltage V2 via the signal output terminal OUTPUT. The second clock signal CK2 and the third clock signal CB2 are a set of clock signals having a second high level VH2 and a second low level VL2. The second clock signal CK2 and the third clock signal CB2 have the same frequency and a phase difference of 180 degrees. The second high level VH2 is less than the first high level VH1. In an embodiment of the present disclosure, the second high level VH2 can be 10V, and the second low level VL2 can be -6V. Alternatively, in another embodiment of the present disclosure, the second high level VH2 can be 8V, and the second low level VL2 can be -6V.

[0084] It is understood by those skilled in the art that the above steps are described in sequence, but do not constitute a limitation on the sequence of the method, and embodiments of the present disclosure can also be implemented in any other suitable sequence.

[0085] The above describes several embodiments of the present disclosure in detail, but the protection scope of the present disclosure is not limited thereto. It is obvious that various modifications, replacements or variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.

Claims

1. A shift register comprising an input circuit, a first control circuit, a reset circuit, a second control circuit and an output circuit, wherein: the input circuit is coupled to a signal input terminal, a first clock signal terminal and a first node, and is configured to provide an input signal from the signal input terminal to the first node according to a first clock signal from the first clock signal terminal; the first control circuit is coupled to a first voltage terminal, a second clock signal terminal, the first node and a second node, and is configured to control a voltage of the second node according to a first voltage from the first voltage terminal, a second clock signal from the second clock signal terminal and a voltage of the second node; the reset circuit is coupled to the second node, a second voltage terminal, a third clock signal terminal and the first node, and is configured to reset the first node according to a voltage from the second node, a third clock signal from the third clock signal terminal and a second voltage from the second voltage terminal; the second control circuit is coupled to the first voltage terminal, the first node and a third node, and is configured to control a voltage of the third node according to the first voltage and a voltage of the first node; and the output circuit is coupled to the second node, the second voltage terminal, a signal output terminal, the third node and a fourth clock signal terminal, and is configured to provide a scan driving signal through the signal output terminal according to a voltage of the second node, the second voltage, a voltage of the third node and a fourth clock signal from the fourth clock signal terminal; wherein the first clock signal and the fourth clock signal have a first high level and a first low level, the first clock signal and the fourth clock signal have a same frequency and a phase difference of 180 degrees, the second clock signal and the third clock signal have a second high level and a second low level, the second clock signal and the third clock signal have a same frequency and a phase difference of 180 degrees, and the second high level is less than the first high level. The first clock signal and the second clock signal have a same frequency and a same phase, and the third clock signal and the fourth clock signal have a same frequency and a same phase. 3.The shift register of claim 2, wherein the first high level is the same as the first voltage, the first low level is the same as the second voltage, and the first low level is the same as the second low level. The first high level is 14V, the second high level is 8V, and the first low level and the second low level are -6V. The first high level is 14V, the second high level is 10V, and the first low level and the second low level are -6V. A high level of the input signal is less than the first high level and greater than or equal to the second high level. The input circuit comprises a first transistor, a control electrode of the first transistor is coupled to the first clock signal terminal, a first electrode of the first transistor is coupled to the signal input terminal, and a second electrode of the first transistor is coupled to the first node. ​ 2. The shift register of claim 1, wherein, ​ ​ 4. The shift register of claim 3, wherein, ​ 5. The shift register of claim 3, wherein, ​ 6. The shift register of claim 3, wherein, ​ 7. The shift register of claim 1, wherein, ​ 8. The shift register of claim 1, wherein, The first control circuit includes a second transistor and a third transistor, a control electrode of the second transistor is coupled with the first node, a first electrode of the second transistor is coupled with the second clock signal terminal, and a second electrode of the second transistor is coupled with the second node, a control electrode of the third transistor is coupled with the second clock signal terminal, a first electrode of the third transistor is coupled with the first voltage terminal, and a second electrode of the third transistor is coupled with the second node.

9. The shift register of claim 1, wherein, The reset circuit includes a fourth transistor and a fifth transistor, a control electrode of the fourth transistor is coupled with the second node, a first electrode of the fourth transistor is coupled with the second voltage terminal, a second electrode of the fourth transistor is coupled with a fourth node, a control electrode of the fifth transistor is coupled with the third clock signal terminal, a first electrode of the fifth transistor is coupled with the fourth node, and a second electrode of the fifth transistor is coupled with the first node.

10. The shift register of claim 1, wherein, The second control circuit includes a sixth transistor, a control electrode of the sixth transistor is coupled with the first voltage terminal, a first electrode of the sixth transistor is coupled with the first node, and a second electrode of the sixth transistor is coupled with the third node.

11. The shift register of claim 1, wherein, The output circuit includes a seventh transistor, an eighth transistor and a capacitor, a control electrode of the seventh transistor is coupled with the third node, a first electrode of the seventh transistor is coupled with the fourth clock signal terminal, a second electrode of the seventh transistor is coupled with the signal output terminal, a control electrode of the eighth transistor is coupled with the second node, a first electrode of the eighth transistor is coupled with the second voltage terminal, a second electrode of the eighth transistor is coupled with the signal output terminal, a first end of the capacitor is coupled with the signal output terminal, and a second end of the capacitor is coupled with the third node.

12. The shift register of claim 1, wherein: The input circuit includes a first transistor, a control electrode of the first transistor is coupled with the first clock signal terminal, a first electrode of the first transistor is coupled with the signal input terminal, and a second electrode of the first transistor is coupled with the first node; The first control circuit includes a second transistor and a third transistor, a control electrode of the second transistor is coupled with the first node, a first electrode of the second transistor is coupled with the second clock signal terminal, a second electrode of the second transistor is coupled with the second node, a control electrode of the third transistor is coupled with the second clock signal terminal, a first electrode of the third transistor is coupled with the first voltage terminal, and a second electrode of the third transistor is coupled with the second node; The reset circuit includes a fourth transistor and a fifth transistor, a control electrode of the fourth transistor is coupled with the second node, a first electrode of the fourth transistor is coupled with the second voltage terminal, a second electrode of the fourth transistor is coupled with a fourth node, a control electrode of the fifth transistor is coupled with the third clock signal terminal, a first electrode of the fifth transistor is coupled with the fourth node, and a second electrode of the fifth transistor is coupled with the first node; The second control circuit includes a sixth transistor, a control electrode of the sixth transistor is coupled with the first voltage terminal, a first electrode of the sixth transistor is coupled with the first node, and a second electrode of the sixth transistor is coupled with the third node. The second control circuit includes a sixth transistor, a control electrode of the sixth transistor is coupled with the first voltage terminal, a first electrode of the sixth transistor is coupled with the first node, and a second electrode of the sixth transistor is coupled with the third node; and The output circuit includes a seventh transistor, an eighth transistor, and a capacitor, a control electrode of the seventh transistor is coupled with the third node, a first electrode of the seventh transistor is coupled with the fourth clock signal terminal, a second electrode of the seventh transistor is coupled with the signal output terminal, a control electrode of the eighth transistor is coupled with the second node, a first electrode of the eighth transistor is coupled with the second voltage terminal, a second electrode of the eighth transistor is coupled with the signal output terminal, a first terminal of the capacitor is coupled with the signal output terminal, and a second terminal of the capacitor is coupled with the third node.

13. The shift register of claim 11 or 12, wherein, The eighth transistor has a bottom control electrode, and the bottom control electrode is coupled with a third voltage terminal.

14. The shift register of claim 13, wherein, A third voltage from the third voltage terminal is the same as the second low level.

15. The shift register of any one of claims 1 to 9 and 11, wherein, The second control circuit is alternatively coupled with a fourth voltage terminal, the first node, and the third node, and is configured to control a voltage of the third node according to a fourth voltage from the fourth voltage terminal and a voltage of the first node, wherein the fourth voltage is the same as the second high level.

16. The shift register of claim 15, wherein, The second control circuit includes a sixth transistor, a control electrode of the sixth transistor is coupled with the fourth voltage terminal, a first electrode of the sixth transistor is coupled with the first node, and a second electrode of the sixth transistor is coupled with the third node.

17. The shift register of claim 16, wherein, The seventh transistor has a bottom control electrode, and the bottom control electrode is coupled with a third voltage terminal, and a third voltage from the third voltage terminal is equal to the second low level.

18. A gate drive circuit comprising a plurality of cascaded shift registers as claimed in any one of claims 1 to 17, the signal output of an Nth shift register being coupled to the input of an (N+1)th shift register, wherein, N is a positive integer.

19. A display device comprising the gate driver circuit according to claim 18.

20. A method for driving the shift register according to any one of claims 1 to 17, comprising: in a first stage, providing an input signal to the first node and the third node, storing and maintaining a voltage difference between the third node and the signal output terminal, and providing a first voltage to the second node; in a second stage, maintaining the voltage difference to cause a voltage of the signal output terminal to change with a fourth clock signal, thereby outputting the fourth clock signal at the signal output terminal; in a third stage, providing the first voltage to the second node according to a second clock signal, thereby outputting a second voltage at the signal output terminal; in a fourth stage, providing the second voltage to the first node according to a third clock signal, and outputting the second voltage at the signal output terminal; and in a fifth stage, providing the second voltage to the second node according to a fourth clock signal, and outputting the second voltage at the signal output terminal. The first clock signal and the fourth clock signal have a first high level and a first low level, the first clock signal and the fourth clock signal have the same frequency and a phase difference of 180 degrees, the second clock signal and the third clock signal have a second high level and a second low level, the second clock signal and the third clock signal have the same frequency and a phase difference of 180 degrees, and the second high level is less than the first high level.

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