High-resistance silicon-based germanium spads sensor and manufacturing method therefor

Abstract

The present application relates to the technical field of semiconductors, and discloses a high-resistance silicon-based germanium SPADs sensor and a manufacturing method therefor. The high-resistance silicon-based germanium SPADs sensor comprises a high-resistance silicon-based germanium wafer, a sensing layer, a germanium-silicon layer, an avalanche layer, a second germanium layer, a silicon oxide layer, a sensing interconnection layer, a readout interconnection layer, and a readout circuit which are stacked in sequence; the high-resistance silicon-based germanium wafer comprises a high-resistance acceptor silicon substrate, a high-resistance silicon bonding layer, and a first germanium layer which are stacked in sequence; and the high-resistance acceptor silicon substrate is made of silicon carbide, diamond, or aluminum nitride. The present application can ensure that the high-resistance silicon-based germanium wafer has excellent heat dissipation characteristics and good working performance.

Description

A high-resistivity silicon-based germanium SPAD sensor and its fabrication method Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a high-resistivity silicon-based germanium SPADs sensor and its fabrication method. Background Technology

[0002] Conventional GOI wafers contain a buried oxide layer, which has low thermal conductivity. In particular, the high operating voltage of germanium SPADs sensors leads to severe self-heating effects in germanium SPADs sensors formed on GOI wafers, affecting key performance indicators such as dark current, dark count rate, and single-photon detection efficiency. In addition, pixel size, pixel pitch, and array specifications are usually defined by the readout circuit, but traditional hybrid integration processes use flip-chip technology to connect to the readout circuit, resulting in low yield and high cost of germanium SPADs sensors.

[0003] Summary of the Invention

[0004] This application provides a high-resistivity silicon-based germanium SPADs sensor and its fabrication method, which can ensure that the high-resistivity silicon-based germanium wafer has excellent heat dissipation characteristics and better working performance.

[0005] In a first aspect, this application provides a high-resistivity silicon-based germanium SPADs sensor, comprising a high-resistivity silicon-based germanium wafer, a sensing layer, a germanium-silicon layer, an avalanche layer, a second germanium layer, a silicon oxide layer, a sensing interconnect layer, a readout interconnect layer, and a readout circuit, which are stacked sequentially; the high-resistivity silicon-based germanium wafer comprises a high-resistivity acceptor silicon substrate, a high-resistivity silicon bonding layer, and a first germanium layer, which are stacked sequentially.

[0006] The high-resistivity acceptor silicon substrate is made of silicon carbide, diamond, or aluminum nitride.

[0007] Furthermore, the germanium SPADs sensor also includes multiple P-type heavily doped germanium regions distributed at a first preset interval; the P-type heavily doped germanium regions are L-type or U-type; the horizontal portion of the P-type heavily doped germanium region is embedded in the first germanium layer and has the same thickness as the first germanium layer; the vertical portion sequentially penetrates the sensing layer, the germanium-silicon layer, the avalanche layer, and the second germanium layer, and is connected to the silicon oxide layer.

[0008] Furthermore, the germanium SPADs sensor also includes multiple N-type heavily doped germanium regions embedded in the second germanium layer at a second preset interval, and the thickness is the same as that of the second germanium layer.

[0009] Furthermore, the sensing layer includes a germanium quantum well sensing layer and a germanium sensing layer; the germanium quantum well sensing layer is superimposed on the germanium sensing layer.

[0010] Furthermore, the sensing interconnect layer includes multiple N-type electrodes and multiple P-type electrodes; the N-type electrodes penetrate the silicon oxide layer and are connected to the N-type germanium heavily doped region; the P-type electrodes penetrate the silicon oxide layer and are connected to the vertical portion of the P-type germanium heavily doped region.

[0011] Furthermore, the readout interconnect layer and the sensing interconnect layer have the same structure and are placed symmetrically;

[0012] Both the N-type and P-type electrodes in the readout interconnect layer are connected to the readout circuit.

[0013] Furthermore, the thickness of the first germanium layer is between 100nm and 1000nm.

[0014] Furthermore, the thickness of both the sensing layer and the avalanche layer is between 500-3000 nm.

[0015] Furthermore, the thickness of the germanium-silicon layer is 100 nm; the thicknesses of the second germanium layer and the silicon oxide layer are both between 100 nm and 200 nm.

[0016] Furthermore, the high-resistivity acceptor silicon substrate is made of sapphire or glass.

[0017] Secondly, this application also provides a method for fabricating a high-resistivity silicon-based germanium SPADs sensor, comprising:

[0018] A donor silicon substrate, a germanium buffer layer, a first germanium layer, and a high-resistivity silicon bonding layer are sequentially stacked to obtain the donor substrate.

[0019] A high-resistivity acceptor silicon substrate and a high-resistivity silicon bonding layer are sequentially stacked to obtain the acceptor substrate;

[0020] Among them, the high-resistivity host silicon substrate is made of silicon carbide, diamond or aluminum nitride;

[0021] After bonding the donor and acceptor substrate wafers, the donor silicon substrate and germanium buffer layer are removed.

[0022] The first germanium layer was chemically and mechanically polished to obtain a high-resistivity silicon-based germanium wafer.

[0023] A high-resistivity silicon-based germanium SPAD sensor is obtained by sequentially stacking a sensing layer, a germanium-silicon layer, an avalanche layer, a second germanium layer, a silicon oxide layer, a sensing interconnect layer, a readout interconnect layer, and a readout circuit on a high-resistivity silicon-based germanium wafer.

[0024] Furthermore, the method also includes: after obtaining a high-resistivity silicon-based germanium wafer, forming multiple horizontal first P-type heavily doped germanium regions distributed at a first preset interval within the first germanium layer by ion implantation; after stacking the second germanium layer, forming multiple vertical second P-type heavily doped germanium regions that sequentially penetrate the second germanium layer, the avalanche layer, the germanium-silicon layer, and the sensing layer by ion implantation; the second P-type heavily doped germanium regions and the first P-type heavily doped germanium regions are connected one-to-one to form a P-type heavily doped germanium region.

[0025] Furthermore, the thickness of the high-resistivity silicon bonding layer is between 10nm and 100nm.

[0026] Furthermore, the thickness of the germanium buffer layer is between 100nm and 500nm.

[0027] Furthermore, the method also includes:

[0028] After obtaining the high-resistivity silicon-based germanium SPADs sensor, a predetermined percentage of the high-resistivity host silicon substrate is removed.

[0029] In summary, compared with the prior art, the beneficial effects of the technical solution provided in this application include at least the following:

[0030] This application provides a high-resistivity silicon-based germanium SPADs sensor. First, high-resistivity silicon material with high thermal conductivity is selected as the bonding layer, ensuring excellent heat dissipation characteristics of the high-resistivity silicon-based germanium wafer, preventing overheating damage to the germanium SPADs sensor, and ensuring stable operation at higher temperatures. Second, a high-resistivity silicon substrate is used as the acceptor substrate, which has the characteristics of low substrate capacitance and low doping concentration, resulting in better performance of the germanium SPADs sensor. Finally, it is connected to the readout circuit through an interconnect layer, achieving high integration, eliminating the need for flip-chip technology, and achieving high yield of the germanium SPADs sensor, providing a low-cost solution for high-resolution germanium SPADs sensor technology. Attached Figure Description

[0031] Figure 1 is a structural diagram of a high-resistivity silicon-based germanium SPADs sensor provided in one embodiment of this application.

[0032] Figure 2 is a structural diagram of a high-resistivity silicon-based germanium SPADs sensor provided in another embodiment of this application.

[0033] Figure 3 is a flowchart of a method for fabricating a high-resistivity silicon-based germanium SPADs sensor according to an embodiment of this application.

[0034] Figure 4 is a schematic diagram of generating a P-type germanium heavily doped region on a high-resistivity silicon-based germanium wafer according to an embodiment of this application.

[0035] Figure 5 is a schematic diagram of generating an N-type heavily doped germanium region on a germanium-silicon layer according to an embodiment of this application.

[0036] Figure 6 is a schematic diagram of an avalanche layer and a second germanium layer superimposed on a germanium-silicon layer according to an embodiment of this application.

[0037] Figure 7 is a schematic diagram of the generation of L-type and P-type germanium heavily doped regions according to an embodiment of this application.

[0038] Figure 8 is a schematic diagram of a silicon oxide layer superimposed on a second germanium layer according to an embodiment of this application.

[0039] Figure 9 is a schematic diagram of forming an N-type electrode and a P-type electrode according to an embodiment of this application.

[0040] Figure 10 is a schematic diagram of forming a sensing interconnect layer according to an embodiment of this application.

[0041] Figure label:

[0042] 101. High-resistivity acceptor silicon substrate; 102. High-resistivity silicon bonding layer; 103. First germanium layer; 104. Sensing layer; 105. Germanium-silicon layer; 106. Avalanche layer; 107. Second germanium layer; 108. Silicon oxide layer; 201. First interconnect layer; 202. Second interconnect layer; 203. Fourth interconnect layer; 204. Third interconnect layer; 205. Readout circuit; 301. P-type heavily doped germanium region; 302. P-type lightly doped charge layer; 303. N-type heavily doped germanium region. Detailed Implementation

[0043] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0044] Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0045] Please refer to Figures 1 and 2. This application embodiment provides a high-resistivity silicon-based germanium SPADs sensor, including a high-resistivity silicon-based germanium wafer, a sensing layer 104, a germanium-silicon layer 105, an avalanche layer 106, a second germanium layer 107, a silicon oxide layer 108, a sensing interconnect layer, a readout interconnect layer, and a readout circuit 205 stacked sequentially. The high-resistivity silicon-based germanium wafer includes a high-resistivity acceptor silicon substrate 101, a high-resistivity silicon bonding layer 102, and a first germanium layer 103 stacked sequentially.

[0046] The high-resistivity acceptor silicon substrate 101 is made of silicon carbide, diamond, or aluminum nitride, and can also be sapphire or glass.

[0047] The high-resistivity silicon bonding layer 102 and the high-resistivity acceptor silicon substrate 101 have a resistance greater than 10 kΩ·cm, which is considered high resistance.

[0048] The above embodiments use a high-resistivity silicon substrate as the acceptor substrate to form a high-resistivity silicon-based germanium wafer. It features low substrate capacitance and low doping concentration, which not only removes the lattice mismatch defects at the germanium-silicon interface but also ensures that the high-resistivity silicon-based germanium wafer has excellent heat dissipation characteristics (using high-resistivity silicon material with high thermal conductivity as the bonding layer). The hybrid structure of the high-resistivity acceptor silicon substrate 101 and the high-resistivity silicon bonding layer 102 serves as an effective heat conduction structure for the germanium SPADs sensor, preventing overheating damage and ensuring that the high-resistivity silicon-based germanium SPADs sensor can operate stably at higher temperatures. At the same time, because the high-resistivity silicon substrate has a smaller substrate capacitance and lower doping concentration, the high-resistivity silicon-based germanium SPADs sensor still has the performance advantages of fast operating speed, high reliability, strong anti-interference ability, and extremely strong voltage resistance without reducing the dark current, dark count rate, and single-photon detection efficiency of the germanium SPADs sensor. It can be argued that although GOI wafers inherit the advantages of SOI technology, such as high integration, high-speed transmission, low power consumption, and strong radiation resistance, these advantages are all attributed to the buried oxide layer. Although the substrate structure formed in this application does not have a buried oxide layer, it still exhibits significant performance advantages.

[0049] In some embodiments, the germanium SPADs sensor further includes a plurality of P-type heavily doped germanium regions 301 distributed at a first preset interval; the P-type heavily doped germanium regions 301 are L-shaped or U-shaped; the horizontal portion of the P-type heavily doped germanium regions 301 is embedded in the first germanium layer 103 and has the same thickness as the first germanium layer 103; the vertical portion sequentially penetrates the sensing layer 104, the germanium-silicon layer 105, the avalanche layer 106, and the second germanium layer 107, and is connected to the silicon oxide layer 108. Further, the germanium SPADs sensor of this application also includes a plurality of N-type heavily doped germanium regions 303 embedded in the second germanium layer 107 at a second preset interval and has the same thickness as the second germanium layer 107.

[0050] The thickness of the first germanium layer 103 is between 100nm and 1000nm, preferably 200nm; the thickness of the germanium-silicon layer 105 is 100nm; and the thicknesses of the second germanium layer 107 and the silicon oxide layer 108 are both between 100nm and 200nm.

[0051] Furthermore, this application also includes a plurality of lightly doped P-type charge layers 302 embedded in the germanium-silicon layer 105 at a third predetermined interval.

[0052] Specifically, the lengths of the N-type germanium heavily doped region 303 and the P-type lightly doped charge layer 302 are both less than the horizontal portion of the P-type germanium heavily doped region 301. In terms of distribution position, the N-type germanium heavily doped region 303, the P-type lightly doped charge layer 302, and the P-type germanium heavily doped region 301 are in one-to-one correspondence. When the P-type germanium heavily doped region 301 is U-shaped, the N-type germanium heavily doped region 303 and the P-type lightly doped charge layer 302 correspond exactly to the recess of the U-shaped P-type germanium heavily doped region 301. Therefore, it can be considered that the first preset interval is less than the second preset interval and also less than the third preset interval.

[0053] The above embodiment sets up an embedded P-type germanium heavily doped region 301 and an N-type germanium heavily doped region 303, which constitute a planar high-resistivity silicon-based germanium SPADs sensor structure. The planar structure can effectively bury the entire SPADs device in the layer structure, avoiding a large number of surface states and sidewall leakage currents caused by sidewall etching damage.

[0054] In some embodiments, the sensing layer 104 includes a germanium quantum well sensing layer 104 and a germanium sensing layer 104; the germanium quantum well sensing layer 104 is superimposed on the germanium sensing layer 104. Additionally, the avalanche layer 106 may employ a germanium / germanium-silicon superlattice layer or an aperiodic composite structure composed of germanium / germanium-silicon materials.

[0055] The thickness of both the sensing layer 104 and the avalanche layer 106 is between 500-3000 nm, and the silicon content is less than 30%.

[0056] The germanium / germanium-silicon multi-quantum-well layer and the avalanche layer 106 with a germanium / germanium-silicon multilayer structure in the above embodiments enable the sensor of this application to have a strong carrier avalanche multiplication effect, solving the problem of low ionization coefficient of germanium semiconductor materials.

[0057] In addition, this application achieves high lattice matching of the germanium / germanium-silicon multilayer avalanche layer 106, germanium-silicon layer 105, and germanium-based sensing layer 104, resulting in a smaller lattice mismatch and thermal mismatch in the entire device layer structure. The heterogeneous material interface has good quality and excellent electrical performance, reducing the dark current, dark count rate, and avalanche breakdown voltage of the germanium SPADs sensor.

[0058] In some embodiments, the sensing interconnect layer includes a plurality of N-type electrodes and a plurality of P-type electrodes; the N-type electrodes penetrate the silicon oxide layer 108 and are connected to the N-type heavily doped germanium region 303; the P-type electrodes penetrate the silicon oxide layer 108 and are connected to the vertical portion of the P-type heavily doped germanium region 301. The readout interconnect layer has the same structure as the sensing interconnect layer and is symmetrically placed. Both the N-type and P-type electrodes in the readout interconnect layer are connected to the readout circuit 205.

[0059] Please refer to Figures 1 and 2, where the sensing interconnect layer includes a first interconnect layer 201 and a second interconnect layer 202 stacked in sequence, and the readout interconnect layer includes a fourth interconnect layer 203 and a third interconnect layer 204 stacked in sequence. The first interconnect layer 201 and the third interconnect layer 204 are symmetrical, and the second interconnect layer 202 and the fourth interconnect layer 203 are symmetrical.

[0060] The P-type and N-type electrodes are the gray parts in the interconnect layer. The P-type electrode occupies only the first interconnect layer 201 and the third interconnect layer 204, while the N-type electrode runs through the entire interconnect layer and is connected to the readout circuit 205 and the N-type germanium heavily doped region 303.

[0061] The above embodiments enable the high-resistivity silicon-based germanium SPADs focal plane array to be connected to the readout circuit 205 through an interconnect layer, resulting in high integration. The pixel size, pixel pitch, and array specifications are defined by the readout circuit 205, rather than being limited by the level of hybrid integration process. Flip-chip technology is not required, resulting in high yield and low cost for germanium SPADs sensors.

[0062] Please refer to Figures 3-10. An embodiment of this application also provides a method for fabricating a high-resistivity silicon-based germanium SPADs sensor, specifically including the following steps:

[0063] Step S1: A donor silicon substrate, a germanium buffer layer, a first germanium layer 103, and a high-resistivity silicon bonding layer 102 are sequentially stacked to obtain the donor substrate. The thickness of the high-resistivity silicon bonding layer 102 is between 10 nm and 100 nm, preferably 200 nm; the thickness of the germanium buffer layer is between 100 nm and 500 nm.

[0064] Step S2: A high-resistivity acceptor silicon substrate 101 and a high-resistivity silicon bonding layer 102 are sequentially stacked to obtain the acceptor substrate.

[0065] The high-resistivity acceptor silicon substrate 101 is made of silicon carbide, diamond, or aluminum nitride, and can also be sapphire or glass. The resistance of the high-resistivity silicon bonding layer 102 and the high-resistivity acceptor silicon substrate 101 is greater than 10 kΩ·cm.

[0066] Step S3: After bonding the donor substrate and acceptor substrate wafers, remove the donor silicon substrate and germanium buffer layer. Specifically, wafer bonding involves flipping the donor substrate and stacking it on top of the acceptor substrate, with the following order from top to bottom: donor silicon substrate, germanium buffer layer, first germanium layer 103, high-resistivity silicon bonding layer 102, high-resistivity silicon bonding layer 102, and high-resistivity acceptor silicon substrate 101; then remove the donor substrate and germanium buffer layer, leaving the first germanium layer 103, high-resistivity silicon bonding layer 102, and high-resistivity acceptor silicon substrate 101.

[0067] Step S4: Perform chemical mechanical polishing on the first germanium layer 103 to obtain a high-resistivity silicon-based germanium wafer.

[0068] Step S5: A sensing layer 104, a germanium-silicon layer 105, an avalanche layer 106, a second germanium layer 107, a silicon oxide layer 108, a sensing interconnect layer, a readout interconnect layer, and a readout circuit 205 are sequentially stacked on a high-resistivity silicon-based germanium SPADs sensor. The structures and parameters of the sensing layer 104, germanium-silicon layer 105, avalanche layer 106, second germanium layer 107, silicon oxide layer 108, sensing interconnect layer, and readout interconnect layer have been described in detail in the above embodiments and will not be repeated here.

[0069] Since the sensing layer 104 specifically includes a germanium quantum well sensing layer 104 and a germanium sensing layer 104, the avalanche layer 106 uses germanium / germanium silicon material, and the second germanium layer 107 and the germanium silicon layer 105 also contain germanium, they can all be formed by homoepitaxially stacking them sequentially on the first germanium layer 103.

[0070] The above embodiments propose a technical solution for forming a high-quality germanium layer on a high-resistivity silicon substrate using a bonding method. This not only removes the lattice mismatch defects at the germanium-silicon interface but also ensures that the high-resistivity silicon-based germanium wafer has excellent heat dissipation characteristics. Furthermore, it solves the problems of overheating damage, high-temperature operating stability, reliability, anti-interference, voltage resistance, integration density, and yield of germanium SPADs sensors on insulators, while maintaining key performance indicators such as dark current, dark count rate, single-photon detection efficiency, and avalanche breakdown voltage. The fabrication method of this application is simple to construct, easy to implement in terms of process flow, highly compatible with standard CMOS manufacturing processes, and easy for mass production.

[0071] Furthermore, the method also includes: after obtaining a high-resistivity silicon-based germanium wafer, forming multiple horizontal first P-type heavily doped germanium regions 301 distributed at a first preset interval within the first germanium layer 103 by ion implantation; after stacking the second germanium layer 107, forming multiple vertical second P-type heavily doped germanium regions 301 that sequentially penetrate the second germanium layer 107, the avalanche layer 106, the germanium-silicon layer 105, and the sensing layer 104 by ion implantation; the second P-type heavily doped germanium regions 301 and the first P-type heavily doped germanium regions 301 are connected one-to-one to form the P-type heavily doped germanium regions 301.

[0072] Furthermore, after stacking the germanium-silicon layer 105 in step S5 above, multiple P-type lightly doped charge layers 302 distributed at a third preset interval can be formed in the germanium-silicon layer 105 by ion implantation.

[0073] The above embodiments propose a method for fabricating high-resistivity silicon-based germanium SPADs sensors with a planar structure. The planar structure can effectively embed the entire SPADs device in the layer structure, avoiding a large number of surface states and sidewall leakage currents caused by sidewall etching damage.

[0074] Furthermore, the method also includes:

[0075] After obtaining the high-resistivity silicon-based germanium SPADs sensor, a predetermined percentage of the high-resistivity host silicon substrate 101 is removed.

[0076] The preset percentage can be 30%-70%.

[0077] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0078] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A high-resistivity silicon-based germanium SPADs sensor, characterized in that, It includes a high-resistivity silicon-based germanium wafer, a sensing layer, a germanium-silicon layer, an avalanche layer, a second germanium layer, a silicon oxide layer, a sensing interconnect layer, a readout interconnect layer, and a readout circuit, which are stacked sequentially. The high-resistivity silicon-based germanium wafer comprises a high-resistivity acceptor silicon substrate, a high-resistivity silicon bonding layer, and a first germanium layer stacked sequentially. The high-resistivity host silicon substrate is made of silicon carbide, diamond, or aluminum nitride.

2. The high-resistivity silicon-based germanium SPADs sensor according to claim 1, characterized in that, It also includes multiple P-type germanium heavily doped regions distributed at a first preset interval; the P-type germanium heavily doped regions are L-type or U-type. The horizontal portion of the P-type germanium heavily doped region is embedded in the first germanium layer and has the same thickness as the first germanium layer; the vertical portion sequentially penetrates the sensing layer, the germanium-silicon layer, the avalanche layer and the second germanium layer, and is connected to the silicon oxide layer.

3. The high-resistivity silicon-based germanium SPADs sensor according to claim 2, characterized in that, It also includes multiple N-type germanium heavily doped regions embedded in the second germanium layer at a second preset interval, and the thickness is the same as that of the second germanium layer.

4. The high-resistivity silicon-based germanium SPADs sensor according to claim 1, characterized in that, The sensing layer includes a germanium quantum well sensing layer and a germanium sensing layer; the germanium quantum well sensing layer is superimposed on the germanium sensing layer.

5. The high-resistivity silicon-based germanium SPADs sensor according to claim 3, characterized in that, The sensing interconnect layer includes multiple N-type electrodes and multiple P-type electrodes; the N-type electrodes penetrate the silicon oxide layer and are connected to the N-type germanium heavily doped region; the P-type electrodes penetrate the silicon oxide layer and are connected to the vertical portion of the P-type germanium heavily doped region.

6. The high-resistivity silicon-based germanium SPADs sensor according to claim 5, characterized in that, The readout interconnect layer has the same structure as the sensing interconnect layer and is placed symmetrically. Both the N-type electrode and the P-type electrode in the readout interconnect layer are connected to the readout circuit.

7. The high-resistivity silicon-based germanium SPADs sensor according to claim 1, characterized in that, The thickness of the first germanium layer is between 100nm and 1000nm.

8. The high-resistivity silicon-based germanium SPADs sensor according to claim 1, characterized in that, The thickness of both the sensing layer and the avalanche layer is between 500-3000 nm.

9. The high-resistivity silicon-based germanium SPADs sensor according to claim 1, characterized in that, The thickness of the germanium-silicon layer is 100 nm; the thicknesses of the second germanium layer and the silicon oxide layer are both between 100 nm and 200 nm.

10. The high-resistivity silicon-based germanium SPADs sensor according to claim 1, characterized in that, The high-resistivity host silicon substrate is made of sapphire or glass.

11. A method for fabricating a high-resistivity silicon-based germanium SPADs sensor, characterized in that, include: A donor silicon substrate, a germanium buffer layer, a first germanium layer, and a high-resistivity silicon bonding layer are sequentially stacked to obtain the donor substrate. A high-resistivity acceptor silicon substrate and the high-resistivity silicon bonding layer are sequentially stacked to obtain the acceptor substrate; The high-resistivity host silicon substrate is made of silicon carbide, diamond, or aluminum nitride. After bonding the donor substrate and the acceptor substrate wafers, the donor silicon substrate and the germanium buffer layer are removed; The first germanium layer was subjected to chemical mechanical polishing to obtain a high-resistivity silicon-based germanium wafer. A high-resistivity silicon-based germanium SPAD sensor is obtained by sequentially stacking a sensing layer, a germanium-silicon layer, an avalanche layer, a second germanium layer, a silicon oxide layer, a sensing interconnect layer, a readout interconnect layer, and a readout circuit on the high-resistivity silicon-based germanium wafer.

12. The method for fabricating a high-resistivity silicon-based germanium SPADs sensor according to claim 11, characterized in that, Also includes: After obtaining the high-resistivity silicon-based germanium wafer, multiple horizontal first P-type germanium heavily doped regions distributed at a first preset interval are formed in the first germanium layer by ion implantation. After the second germanium layer is stacked, multiple second P-type heavily doped germanium regions are formed by ion implantation, which are vertical and sequentially penetrate the second germanium layer, the avalanche layer, the germanium-silicon layer and the sensing layer. The second P-type heavily doped germanium regions and the first P-type heavily doped germanium regions are connected one-to-one to form a P-type heavily doped germanium region.

13. The method for fabricating a high-resistivity silicon-based germanium SPADs sensor according to claim 11, characterized in that, The thickness of the high-resistivity silicon bonding layer is between 10nm and 100nm.

14. The method for fabricating a high-resistivity silicon-based germanium SPADs sensor according to claim 11, characterized in that, The thickness of the germanium buffer layer is between 100nm and 500nm.

15. The method for fabricating a high-resistivity silicon-based germanium SPADs sensor according to claim 11, characterized in that, Also includes: After obtaining the high-resistivity silicon-based germanium SPADs sensor, a predetermined percentage of the high-resistivity acceptor silicon substrate is removed.

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