Processor chip, chip system and access method

Abstract

The embodiments of the present application relate to the technical field of processors. Provided are a processor chip, a chip system and an access method, which improve the efficiency of the processor chip processing an access request, and improve the read-write performance of a power-down non-volatile memory. The specific solution is as follows: a processor chip comprises a processor and a controller, wherein the processor is used for generating an access request for a power-down non-volatile memory, and the access request carries a target logical address; and the controller is used for acquiring the access request, converting the target logical address into a target physical address in the power-down non-volatile memory on the basis of a flash translation layer (FTL) address mapping relationship, and sending the target physical address to the power-down non-volatile memory so as to access the target physical address. The embodiments of the present application are used for the process of a processor chip accessing a power-down non-volatile memory.

Description

Processor chip, chip system and access method

[0001] This application claims priority to Chinese patent application filed on June 21, 2024, with application number 202410817071.4 and entitled "Processor Chip, Chip System and Access Method", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of processor technology, and in particular to a processor chip, a chip system, and an access method. Background Technology

[0003] Currently, the development of multimedia technology has led to increasing storage demands on mobile devices, making the design of high-speed and durable storage systems a crucial issue. In the field of terminal devices, universal flash storage (UFS) is primarily used to build storage systems.

[0004] In commonly used UFS storage systems, the application processor (AP) connects to the UFS storage chip via a UFS interface. The mapping table between the logical addresses of the AP's central processing unit (CPU) and the physical addresses of the flash memory is stored partly in the UFS storage chip's static random access memory (SRAM) and partly in the UFS storage chip's flash memory. When the logical address of a UFS command issued by the AP does not match the mapping table in the SRAM, the UFS storage chip's storage controller needs to read the remaining mapping table in the flash memory to look up the physical address.

[0005] Because flash memory has a slow read speed, the processing efficiency of UFS commands is reduced, resulting in a decrease in the read and write performance of UFS storage chips. Summary of the Invention

[0006] This application provides a processor chip, a chip system, and an access method, which improves the efficiency of the processor chip in processing access requests and improves the read and write performance of power-down non-volatile memory.

[0007] To achieve the above objectives, the embodiments of this application adopt the following technical solutions.

[0008] In a first aspect, embodiments of this application provide a processor chip, which includes a processor and a controller. The processor generates an access request for a non-volatile memory (NVMemory), the access request carrying a target logical address. The controller acquires the access request, converts the target logical address into a target physical address in the NVMemory according to the Flash Translation Layer (FTL) address mapping relationship, and sends the target physical address to the NVMemory to access the target physical address.

[0009] Therefore, the processor chip provided in this application embodiment stores an FTL address mapping relationship. When the processor chip accesses the power-down non-volatile memory, the FTL can be implemented on the processor chip side to obtain the target physical address of the access request. In other words, the processor chip and the power-down non-volatile memory interact through physical addresses. Since the processor chip stores a complete FTL address mapping relationship, there is no need to implement the FTL address mapping on the power-down non-volatile memory side, which can improve the hit range of the target logical address of the access request, that is, only one lookup is needed instead of multiple lookups, thereby improving the processing efficiency of the access request and improving the read and write performance of the power-down non-volatile memory.

[0010] In one possible design, the controller includes a memory controller and a memory processor. The memory controller acquires access requests and parses them to obtain the target logical address. The memory processor translates the target logical address into a target physical address based on the FTL address mapping. The memory controller also sends the target physical address to the non-volatile memory (NVM) for access. Thus, the processor chip and the NVM interact via physical addresses, improving the efficiency of access request processing.

[0011] In one possible design, the controller is also used to establish FTL address mappings.

[0012] In one possible design, the controller is also used to update the FTL address mapping to perform at least one of the following operations on the power-down non-volatile memory: wear leveling, garbage collection, or bad block management. Thus, when the physical address of data changes due to operations such as wear leveling, garbage collection, or bad block management, the controller updates the FTL address mapping, ensuring the correctness of data access without needing to perform the relevant operations on the power-down non-volatile memory side.

[0013] In one possible design, the size of any physical address in the FTL address mapping is an integer multiple of the size of a page in the non-volatile memory (NDM). Therefore, when an access request requests access the NDM, the number of refreshes to the NDM can be reduced, increasing the lifespan of the NDM and improving its read / write performance.

[0014] In one possible design, the controller is also used to transfer redundant data to a power-down non-volatile memory, and this redundant data is used to reconstruct the FTL address mapping. Therefore, if the FTL address mapping is lost or erroneous on the processor chip side, it can be reconstructed, improving the reliability of the processor chip.

[0015] In one possible design, the controller is specifically used to transmit redundant data via the extra data field or write data field in the header of the Universal Flash Memory Protocol Information Unit (UPIU). This method of transmitting redundant data via the extra data field or write data field in the UPIU minimizes format variations, simplifies hardware processing, and increases processing efficiency.

[0016] Secondly, embodiments of this application provide a chip system, which includes a power-down non-volatile memory and a processor chip according to the first aspect.

[0017] In one possible design, the chip system also includes power-down volatile memory. The power-down volatile memory is used to retrieve and store access requests from the processor, and the controller is used to retrieve access requests from the power-down volatile memory.

[0018] Thirdly, embodiments of this application provide an access method applied to a processor chip. The access method includes: a processor in the processor chip generating an access request for a power-down non-volatile memory, the access request carrying a target logical address; a controller in the processor chip acquiring the access request, converting the target logical address into a target physical address in the power-down non-volatile memory according to an FTL address mapping relationship, and sending the target physical address to the power-down non-volatile memory to access the target physical address.

[0019] In one possible design, the controller in the processor chip obtains an access request, converts the target logical address into a target physical address in the power-down non-volatile memory according to the FTL address mapping relationship, and sends the target physical address to the power-down non-volatile memory to access the target physical address. This includes: the memory controller in the controller obtains the access request and parses the access request to obtain the target logical address; the memory processor in the controller converts the target logical address into a target physical address according to the FTL address mapping relationship; and the memory controller also sends the target physical address to the power-down non-volatile memory to access the target physical address.

[0020] In one possible design, the access method also includes: the controller establishing an FTL address mapping relationship.

[0021] In one possible design, the access method further includes: the controller updating the FTL address mapping to perform at least one of the following operations on the power-down non-volatile memory: wear leveling, garbage collection, or bad block management.

[0022] In one possible design, the access method further includes: the controller transferring redundant data to a power-down non-volatile memory, the redundant data being used to reconstruct the FTL address mapping.

[0023] In one possible design, the controller transmits redundant data to power-down non-volatile memory, including by transmitting redundant data via an additional data header field or a write data field in the UPIU.

[0024] For the beneficial effects of the third aspect, please refer to the explanation of the first aspect.

[0025] Fourthly, embodiments of this application provide a computer-readable storage medium including computer instructions that, when executed on a processor chip, cause the processor chip to perform the access method in any of the possible design embodiments of the third aspect described above.

[0026] Fifthly, embodiments of this application provide a computer program product that, when run on a computer or processor chip, causes the computer or processor to execute the access method in any of the possible design embodiments of the third aspect described above.

[0027] It is understood that any of the processor chips, chip systems, computer-readable storage media or computer program products provided above can be applied to the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects in the corresponding methods, and will not be repeated here.

[0028] These or other aspects of this application will become more readily apparent in the following description. Attached Figure Description

[0029] Figure 1 is a schematic diagram of a storage system provided in an embodiment of this application;

[0030] Figure 2 is a schematic diagram of another storage system provided in an embodiment of this application;

[0031] Figure 3 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0032] Figure 4 is a schematic diagram of the structure of another electronic device provided in an embodiment of this application;

[0033] Figure 5 is a schematic diagram of the structure of a processor chip provided in an embodiment of this application;

[0034] Figure 6 is a schematic diagram of an FTL address mapping relationship provided in an embodiment of this application;

[0035] Figure 7 is a schematic diagram of another processor chip provided in an embodiment of this application;

[0036] Figure 8 is a flowchart of an access method provided in an embodiment of this application. Detailed Implementation

[0037] For ease of understanding, the examples provide explanations of some concepts related to the embodiments of this application for reference. As shown below:

[0038] 1. Wear leveling (WL) is the process of evenly utilizing each flash memory block in a flash memory device to prevent certain "specific" blocks from becoming overused and turning into bad blocks. Because flash memory devices have a limited number of erase / write cycles, repeatedly erasing or writing to the same single flash memory block will slow down the read / write speed or even damage the device, rendering it unusable. Wear leveling algorithms control uneven "wear" across the flash memory devices by distributing written data across multiple sectors. For example, hot data is allocated to younger flash memory blocks (those with fewer erase / write cycles), and cold data is allocated to older flash memory blocks (those with more erase / write cycles).

[0039] 2. Garbage collection (GC) involves moving valid data from several flash memory blocks to a new flash memory block, then erasing the old blocks to obtain several usable flash memory blocks.

[0040] Because flash memory requires erasure before writing, it does not allow repeated writing to a single page; each erase operation allows only one write operation. This means that when writing new data, you cannot directly modify the existing data location; you must first write it to a new location. Consequently, writing data to a new location invalidates the existing data, which becomes garbage data. This garbage data consumes flash memory space, and when the available space in the flash memory is insufficient, garbage collection is required.

[0041] The steps of garbage collection may include: (1) identifying the source flash memory block, which can be the flash memory block with the least amount of valid data; (2) identifying valid data from the source flash memory block; and (3) writing the valid data to the target flash memory block, which can be a new flash memory block. Thus, flash memory devices can reclaim fragmented space and improve utilization through garbage collection.

[0042] 3. Bad block management (BBM) refers to the process by which flash memory devices identify and discontinue the use of damaged flash memory blocks (i.e., bad blocks). A bad block is a block containing one or more invalid bits. Bad blocks can be factory-original bad blocks present at the time of manufacture, or they can be accumulated bad blocks that accumulate during the use of the flash memory device.

[0043] Bad block management can be implemented through skipping or replacement strategies. Specifically, a skipping strategy, based on a created bad block table, stores data in the next good block when the target physical address corresponds to the address of a bad block, thus skipping the bad block. A replacement strategy redirects the FTL to a known free good block to replace the bad block. This strategy creates two areas in the flash memory device: a user-addressable block area and a reserved block area. The FTL can use the user-addressable block area to store data, while the reserved block area is only used for bad block replacement and maintaining the bad block table. Therefore, bad block management can improve the reliability of flash memory devices.

[0044] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B; "and / or" in this text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the description of the embodiments of this application, "multiple" refers to two or more than two.

[0045] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this embodiment, unless otherwise stated, "a plurality of" means two or more.

[0046] In storage systems, taking UFS storage chips as an example of flash memory devices, the unique data read / write characteristics of UFS storage chips prevent APs from directly managing them. Therefore, a flash translation layer (FTL) is placed between the AP and the UFS storage chip. When a user accesses data in the UFS storage chip, the AP, upon receiving the access request, first queries the FTL to determine the data storage location and then retrieves the data from the corresponding storage location to respond to the user's access request.

[0047] As shown in Figure 1, the storage system may include an access point (AP), a UFS (Ultra-Flash Memory) chip, and double-data-rate synchronous dynamic random access memory (DDR SDRAM). The AP may include a central processing unit (CPU), SRAM, a DDR SDRAM controller, and a UFS controller. The UFS chip may include a memory controller and NAND flash memory. The AP is connected to the UFS chip via the UFS controller, and the AP is connected to the DDR SDRAM via the DDR SDRAM controller.

[0048] Specifically, the CPU generates UFS commands via software and stores them in DDR SDRAM. The UFS controller reads the UFS commands from the DDR SDRAM and sends them to the UFS storage chip. The storage controller in the UFS storage chip executes the UFS commands and completes read and write operations on the NAND flash memory. In addition, the storage controller also implements the flash translation layer, handling tasks such as mapping the CPU's logical addresses to the physical addresses of the NAND flash memory, wear leveling, garbage collection, and bad block management.

[0049] In one possible implementation, as shown in Figure 2, the storage controller of the UFS storage chip may include a UFS processor, SRAM, and a flash controller. The UFS processor is used on the UFS storage chip side to implement FTL (Flash Flow Translation) for managing the NAND flash memory. The application processor and the UFS storage chip can transfer data via a high-speed serial interface (e.g., a multi-physical layer (MPHY) interface).

[0050] Because the SRAM space on the UFS storage chip side is limited, a portion of the mapping table between the logical addresses of the AP-side CPU and the physical addresses of the NAND flash memory is stored in the SRAM on the UFS storage chip side, and the other portion is stored in the NAND flash memory. When the logical address of a UFS command issued by the AP does not match the mapping table in the SRAM on the UFS storage chip side, the storage controller needs to read the remaining mapping table in the NAND flash memory to look up the physical address. Since the read speed of NAND flash memory is relatively slow, this leads to a decrease in the efficiency of UFS command processing and a decline in the read and write performance of the UFS storage chip.

[0051] Furthermore, UFS commands interacting between the AP side and the UFS storage chip side are executed in 4KB units, while read / write operations on the NAND flash memory of the UFS storage chip side are performed in NAND flash memory pages. When the amount of data read / written by a UFS command is less than the amount of data in a NAND flash memory page, the NAND flash memory page needs to be refreshed. Multiple refreshes will reduce the lifespan of the NAND flash memory.

[0052] In addition, the AP side uses the file system to organize fragmented files and release storage space, while the UFS storage chip side also organizes fragmented files in the NAND flash memory and releases NAND flash memory storage space. The efficiency of fragmented file consolidation is relatively low.

[0053] Therefore, this application provides a processor chip, which includes a processor and a controller. The processor chip stores an FTL address mapping relationship. When the processor chip accesses the power-down non-volatile memory, the FTL can be implemented on the processor chip side to obtain the target physical address of the access request. That is, the processor chip and the power-down non-volatile memory interact through physical addresses. Since the processor chip stores a complete FTL address mapping relationship, it is not necessary to implement the FTL address mapping on the power-down non-volatile memory side, which can improve the hit range of the target logical address of the access request, improve the processing efficiency of the access request, and improve the read and write performance of the power-down non-volatile memory.

[0054] In the above scenarios, the processor chip provided in this application embodiment can be applied to electronic devices, including but not limited to: mobile phones, tablets, personal computers, handheld computers, mobile internet devices (MIDs), cameras, wearable devices (such as smartwatches, smart bracelets, pedometers, etc.), audio equipment, audio and video players, set-top boxes, game consoles, printers, mice, keyboards, in-vehicle equipment (such as equipment on vehicles like cars, airplanes, ships, trains, and high-speed trains), virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, smart home devices (such as refrigerators, televisions, air conditioners, electricity meters, etc.), smart robots, workshop equipment, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, or smart homes. Wireless terminals and flying equipment (e.g., intelligent robots, hot air balloons, drones, airplanes) in the home.

[0055] The following example uses a mobile phone as an example to illustrate the structure of this electronic device. As shown in Figure 3, this electronic device may include: an application processor, a touch module, a display module, a camera module, a Bluetooth module, a wireless fidelity (Wi-Fi) module, a speaker, DDR SDRAM, a sensor, storage, and a modem, etc.

[0056] Continuing with the example of a personal computer, the structure of this electronic device is illustrated in Figure 4. This electronic device may include a CPU, mouse, keyboard, camera, monitor, Wi-Fi module, graphics processing unit (GPU), DDR SDRAM, memory, Ethernet, and universal serial bus (USB), etc.

[0057] Although not shown, the electronic device may also include other modules. Those skilled in the art will understand that the electronic device structure shown in Figures 3 and 4 does not constitute a limitation on the electronic device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0058] The processor chip provided in the embodiments of this application will be described in detail below.

[0059] This application provides a processor chip, which can also be understood as a system-on-a-chip (SoC). As shown in Figure 5 and referring to Figure 7, the processor chip includes a processor and a controller. The processor and the controller can be connected via a bus. The controller can be connected via a high-speed serial interface (e.g., an MPHY interface) and at least one power-down non-volatile memory.

[0060] For example, the processor may include a central processing unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0061] For example, the power-loss non-volatile memory can be one of UFS storage chips, solid state drives (SSDs), embedded multimedia cards (eMMCs), phase change memory, magnetic change memory, and resistive random access memory.

[0062] The processor generates access requests for power-down non-volatile memory, and the access requests carry the target logical address.

[0063] For example, the processor can generate an access request for the non-volatile memory, which may be to read data from the non-volatile memory or to write data to the non-volatile memory.

[0064] For example, the access request generated by the processor can be stored in memory, such as in DDR SDRAM as shown in Figure 7. The access request can carry a target logical address; specifically, the logical address is a virtual address used in the program. The logical address is an abstract representation of memory within the program and is independent of the actual physical storage location. The logical address is defined by the programmer or operating system and is used to access data in memory. The processor uses logical addresses to decouple access requests from actual physical storage locations and to isolate different programs or process batches.

[0065] In addition, access requests can also carry the size of the data to be accessed.

[0066] The controller is used to obtain access requests, convert the target logical address into the target physical address in the power-down non-volatile memory according to the FTL address mapping relationship, and send the target physical address to the power-down non-volatile memory to access the target physical address.

[0067] For example, a physical address is the actual address of a storage cell in memory, also known as a real address. A physical address is a unique identifier for each storage cell; it's an address at the hardware level, used for the actual data storage and access. In one possible example, memory can be divided into multiple storage cells, and each cell can be assigned a number, known as a memory address. For example, a 4GB memory cell could have physical addresses ranging from 0 to 0xFFFFFFFF.

[0068] The controller is also used to establish FTL address mapping relationships. Specifically, the controller can establish a mapping between logical addresses and physical addresses to obtain the FTL address mapping relationship. This FTL address mapping relationship can be a table, also called an address mapping table, which can be stored in volatile memory (VRAM), as shown in Figure 7. Of course, to prevent data loss due to power failure, multiple backups of this address mapping table can also be maintained.

[0069] Taking page mapping as an example, as shown in Figure 6, Figure 6 illustrates the mapping relationship between user space (i.e., logical address) and memory pages (i.e., physical addresses) in non-volatile memory. The user space can include spaces _0, _1, _2, _3, _4, and _5, etc., and the memory pages in non-volatile memory can include memory pages _0, _1, _2, _3, _4, and _5, etc. Specifically, the logical address corresponding to space _0 is mapped to the physical address corresponding to memory page _2, the logical address corresponding to space _2 is mapped to the physical address corresponding to memory page _0, the logical address corresponding to space _3 is mapped to the physical address corresponding to memory page _5, and the logical address corresponding to space _4 is mapped to the physical address corresponding to memory page _1.

[0070] It is understood that the FTL address mapping relationship in this embodiment is not stored in the power-loss volatile memory, which avoids the FTL address mapping relationship being frequently refreshed to the power-loss volatile memory and improves the service life of the power-loss non-volatile memory.

[0071] For example, the controller can read the access request from the power-down volatile memory and execute the FTL program to obtain the target physical address. The target physical address is the address of the power-down non-volatile memory, which is the actual address of the data corresponding to the access request.

[0072] Optionally, the controller is also used to update the FTL address mapping to perform at least one of the following operations on the power-down non-volatile memory: wear leveling, garbage collection, or bad block management.

[0073] For example, during wear leveling, garbage collection, or bad block management operations, the physical address of data may change. In this case, the controller needs to update the FTL address mapping to ensure the correctness of data access.

[0074] For example, when the processor generates an access request to write to or update a specific logical address, the controller actually writes the data to a different free physical address and updates the FTL address mapping relationship, establishing a mapping relationship between the specific logical address and the new free physical address.

[0075] In a possible example, suppose data is written to page 0 (corresponding to physical address n). If the data in page 0 needs to be updated, due to the characteristics of non-volatile memory, the updated data does not directly overwrite the original data in page 0. Specifically, the controller first writes the updated data to page 1 (corresponding to physical address n+1), then marks physical address n as "invalid," and updates the FTL address mapping to ensure that the processor can access the "valid" data.

[0076] Optionally, the size of any physical address in the FTL address mapping is an integer multiple of the size of a page in the power-down non-volatile memory.

[0077] For example, each access request accesses at least one page of storage data. Taking a storage page size of 16k as an example, the size of the physical address in the FTL address mapping relationship can be twice 16k, that is, the size of the physical address is 16k; the size of the physical address in the FTL address mapping relationship can also be twice 16k, that is, the size of the physical address is 32k; the size of the physical address in the FTL address mapping relationship can also be other multiples, and this application embodiment does not limit this.

[0078] Therefore, when the processor chip executes such access requests, it can reduce the number of refreshes of the non-volatile memory, thereby increasing the lifespan of the non-volatile memory and improving its read and write performance.

[0079] In addition, the processor chip's processor can also perform file system-level defragmentation and garbage collection based on the size of the non-volatile memory (NVMemory) pages. This avoids multiple garbage collections, improves the efficiency of defragmentation, reduces the number of NVOMemory refreshes, and extends the lifespan of the NVOMemory.

[0080] Optionally, referring to Figures 5 and 7, the controller includes a storage controller and a storage processor. The storage controller is used to acquire access requests and parse them to obtain the target logical address. The storage processor is used to convert the target logical address into a target physical address according to the FTL address mapping relationship. The storage controller is also used to send the target physical address to the power-down non-volatile memory to access the target physical address.

[0081] For example, the power-loss volatile memory can be one of DDR SDRAM, SRAM, random access memory (RAM), synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0082] For example, referring to Figure 7, taking DDR SDRAM as the volatile memory, the processor can generate an access request for the non-volatile memory and store the access request in the DDR SDRAM. The memory controller in the controller can read the access request stored in the DDR SDRAM and parse the access request to obtain the target logical address. The memory processor in the controller can query the FTL address mapping relationship in the DDR SDRAM to obtain the target physical address corresponding to the target logical address, that is, the actual physical address in the non-volatile memory corresponding to the access request. The memory controller can also send the access request carrying the target physical address to the non-volatile memory through the MPHY interface to access the data corresponding to the target physical address in the non-volatile memory.

[0083] For example, the processor chip and the non-volatile memory (NVM) interact via physical addresses, meaning the File Transfer Layer (FTL) is implemented on the processor chip side. Since the processor chip stores the complete FTL address mapping, there's no need to implement FTL address mapping on the NVM side. This improves the hit range of the target logical address for access requests, requiring only one lookup instead of multiple lookups, thus improving access request processing efficiency and enhancing the read / write performance of the NVM.

[0084] Optionally, as shown in Figure 7, the processor chip may include a processor and a controller, with the controller including a memory controller and a memory processor. Here, to distinguish it from the memory controller in the non-volatile memory, the memory controller in the controller is referred to as the first memory controller. The processor chip may also include a first SRAM and a DDR SDRAM controller, with the DDR SDRAM controller and DDR SDRAM coupled. The first SRAM can be used as a cache, storing temporary data generated during the operation of the processor chip or data with a high probability of access. The processor can read the FTL address mapping relationship stored in the DDR SDRAM through the DDR SDRAM controller, and the processor can also read access requests stored in the DDR SDRAM through the DDR SDRAM controller. The processor chip can also transmit data to the non-volatile memory through the MPHY interface, and can also receive data sent by the non-volatile memory through the MPHY interface.

[0085] Referring again to Figure 7, the non-volatile memory (NVH) may include a memory controller and NAND flash memory. To distinguish it from the memory controller mentioned earlier, the memory controller in the NDH is referred to as the second memory controller. The second memory controller may include a second SRAM and a flash controller. The second SRAM can be used as a cache, storing temporary data generated during the operation of the NDH or data to be written to the NAND flash memory. The second memory controller can perform write, read, or erase operations on the NAND flash memory through the flash controller.

[0086] Specifically, the process of a processor chip accessing non-volatile memory (NDM) can include: the processor in the processor chip generates an access request for the NDM and stores it in DDR SDRAM. The controller in the processor chip also accesses the DDR SDRAM through the DDR SDRAM controller to obtain the access request and the FTL address mapping relationship, and converts the target logical address in the access request into the target physical address in the NDM according to the FTL address mapping relationship. The target physical address is then sent to the NDM through the MPHY interface to access the target physical address. When the NDM receives the access request carrying the target physical address, it accesses the data corresponding to the target physical address in the NAND flash memory through the storage controller.

[0087] Optionally, the controller is also used to transfer redundant (out-of-band, OOB) data to power-down non-volatile memory, whereby the redundant data is used to reconstruct the address mapping.

[0088] For example, since the storage system in this embodiment implements FTL on the processor chip side, in order to rebuild the FTL address mapping relationship when it is lost or erroneous in the DDR SRAM, the controller can transfer redundant data to the power-down non-volatile memory for backup. Therefore, when the FTL address mapping relationship in the DDR SRAM is lost or erroneous, the processor can read the redundant data stored in the power-down non-volatile memory to rebuild the FTL address mapping relationship.

[0089] Optionally, the controller is specifically used to transmit redundant data via the extra data field or write data field in the header of the Universal Flash Storage Protocol Information Unit (UPIU).

[0090] For example, a UPIU may include a data out UPIU and a command UPIU.

[0091] In a possible example, the output UPIU may include a header segment, an extra header segment (EHS), and a write data field, as shown in Table 1. Specifically, the header segment may include flags, logical unit number (LUN), task tag, interface identifier (IID), reserved bits, extra interface identifier (EXT-IID), total EHS length, data segment length, data buffer offset, and data transfer count. Taking the data segment length as an example, the 10th bit of the header segment is the most significant bit (MSB), and the 11th bit is the least significant bit (LSB).

[0092] In addition, the EHS carries redundant data, such as OOB data 1 carried in the kth to k+3rd bits of the EHS, and OOB data N carried in the jth to j+3rd bits of the EHS.

[0093] In addition, the write data field carries multiple write data, such as data[0], data[1], data[2] and data[3] from the kth to the k+3rd position of the write data field, and data[length-4], data[length-3], data[length-2] and data[length-1] from the k+length-4th to the k+length-1th position of the write data field.

[0094] Table 1

[0095] For example, the output UPIU may include a header field and a write data field, where EHS can be 0. In this case, as shown in Table 2, the write data field carries redundant data.

[0096] The header fields of Table 2 are the same as those of Table 1, so they will not be described again here.

[0097] For example, the write data field carries redundant data, such as the kth to k+3rd bits of the write data field carrying OOB data 1, and the jth to j+3rd bits of the write data field carrying OOB data N.

[0098] Table 2

[0099] Therefore, redundant data can be transmitted through the extra fields of the data header or the write data field of the UPIU output data. The format of the UPIU changes little, and the write data and the redundant data correspond one-to-one. The write data and the corresponding redundant data are directly written into the non-volatile memory after power loss, which simplifies the hardware processing and increases the processing efficiency.

[0100] In another possible example, the command UPIU may include header fields and EHS, as shown in Table 3. Specifically, the header fields may include flags, LUN, task tag, IID, command set type, reserved, EXT-IID, total EHS length, data segment length, expected data transfer length, and CDB[0] to CDB

[0015] .

[0101] For example, the EHS carries redundant data, such as OOB data 1 carried in the kth to k+3rd bits of the EHS, and OOB data N carried in the jth to j+3rd bits of the EHS.

[0102] Table 3

[0103] Therefore, redundant data can be transmitted through the extra fields of the UPIU data header or the write data field, which simplifies hardware processing and increases processing efficiency.

[0104] This application also provides a chip system, which includes a power-down non-volatile memory and a processor chip.

[0105] In addition, the chip system includes power-loss volatile memory. This volatile memory is used to retrieve access requests from the processor and store those requests. The controller is used to retrieve access requests from the volatile memory.

[0106] For example, a processor in a processor chip can initiate an access to non-volatile memory (NVMemory) and store the generated access request in the NVMemory. On the processor chip side, the controller retrieves the access request from the NVMemory, converts the target logical address to the target physical address of the NVMemory according to the FTL address mapping relationship, and sends the target physical address to the NVMemory to access the target physical address. On the NVMemory side, the NVMemory may also include a memory controller and memory (e.g., NAND flash memory). The memory controller of the NVMemory retrieves the access request carrying the target physical address from the processor chip side and accesses the memory based on the target physical address.

[0107] Applied to the aforementioned processor chip, this application embodiment also provides an access method, as shown in FIG8, which includes the following process.

[0108] S801, The processor in the processor chip generates an access request for the power-down non-volatile memory.

[0109] The access request carries the target logical address.

[0110] S802: The controller in the processor chip obtains the access request, converts the target logical address into the target physical address in the power-down non-volatile memory according to the FTL address mapping relationship, and sends the target physical address to the power-down non-volatile memory to access the target physical address.

[0111] Optionally, S802 may include: a storage controller in the controller acquiring an access request and parsing the access request to obtain a target logical address; a storage processor in the controller converting the target logical address into a target physical address according to the FTL address mapping relationship; and the storage controller also sending the target physical address to the power-off non-volatile memory to access the target physical address.

[0112] Optionally, the access method may also include: the controller establishing an FTL address mapping relationship.

[0113] Optionally, the access method further includes: the controller updating the FTL address mapping to perform at least one of the following operations on the power-down non-volatile memory: wear leveling, garbage collection, or bad block management.

[0114] Optionally, the access method further includes: the controller transferring redundant data to a power-down non-volatile memory, the redundant data being used to reconstruct the FTL address mapping.

[0115] Optionally, the controller may transfer redundant data to power-down non-volatile memory, including by the controller transferring redundant data via an additional field in the header or a write data field in the UPIU.

[0116] Embodiments of this application also provide a computer storage medium storing computer instructions. When the computer instructions are executed on a processor chip, the processor chip performs the aforementioned related method steps to implement the access method in the above embodiments.

[0117] Embodiments of this application also provide a computer program product that, when run on a computer, causes the computer to perform the aforementioned related steps to implement the access method executed by the processor chip in the above embodiments.

[0118] In addition, embodiments of this application also provide an apparatus, which may specifically be a chip, component, or module. The apparatus may include a connected processor and a memory. The memory is used to store computer execution instructions. When the apparatus is running, the processor can execute the computer execution instructions stored in the memory to cause the chip to execute the access methods executed by the electronic devices in the above-described method embodiments.

[0119] In this embodiment, the processor chip, chip system, computer storage medium, computer program product or chip are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0120] Through the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0121] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0122] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0123] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0124] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, essentially or in other words, the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0125] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A processor chip, characterized by The processor is configured to generate an access request for the power-off nonvolatile memory, and the access request carries a target logical address. The controller is configured to obtain the access request, convert the target logical address into a target physical address in the power-off nonvolatile memory according to a flash translation layer (FTL) address mapping relationship, and send the target physical address to the power-off nonvolatile memory to access the target physical address. The controller comprises:

2. The processor chip of claim 1, wherein, The storage controller is configured to obtain the access request, and parse the access request to obtain the target logical address. The storage processor is configured to convert the target logical address into the target physical address according to the FTL address mapping relationship. The storage controller is further configured to send the target physical address to the power-off nonvolatile memory to access the target physical address.

3. The processor chip according to any one of claims 1 or 2, wherein the controller is further configured to establish the FTL address mapping relationship.

4. The processor chip according to any one of claims 1 to 3, wherein the controller is further configured to update the FTL address mapping relationship to perform at least one of the following operations on the power-off nonvolatile memory: wear leveling, garbage collection, or bad block management. Any physical address in the FTL address mapping relationship has a size that is an integer multiple of a size of a storage page of the power-off nonvolatile memory.

6. The processor chip according to any one of claims 1 to 5, wherein the controller is further configured to transmit redundant data to the power-off nonvolatile memory, and the redundant data is used to reconstruct the FTL address mapping relationship.

7. The processor chip according to claim 6, wherein the controller is specifically configured to transmit the redundant data through a data header additional field or a write data field in a universal flash storage protocol information unit (UPIU).

5. The processor chip of any of claims 1-4, wherein, The chip system comprises the power-off nonvolatile memory and the processor chip according to any one of claims 1 to 7. The chip system further comprises a power-off volatile memory. The power-off volatile memory is configured to obtain the access request from the processor, and store the access request. The controller is configured to obtain the access request from the power-off volatile memory. The method is applied to a processor chip, and the method comprises:

8. A chip system, characterized by A processor in the processor chip generates an access request for a power-off nonvolatile memory, and the access request carries a target logical address. A controller in the processor chip obtains the access request, converts the target logical address into a target physical address in the power-off nonvolatile memory according to a flash translation layer (FTL) address mapping relationship, and sends the target physical address to the power-off nonvolatile memory to access the target physical address.

9. The chip system according to claim 8, characterized by ​ ​ ​ 10. An access method, characterized by, ​ ​ ​ 11. The access method of claim 10, wherein, The controller in the processor chip acquires the access request, converts the target logical address into a target physical address in the power-off non-volatile memory according to a flash translation layer (FTL) address mapping relationship, and sends the target physical address to the power-off non-volatile memory to access the target physical address, including: The storage controller in the controller acquires the access request and parses the access request to obtain the target logical address; The storage processor in the controller converts the target logical address into the target physical address according to the FTL address mapping relationship; The storage controller also sends the target physical address to the power-off non-volatile memory to access the target physical address.

12. The access method according to claim 10 or 11, characterized in that, The method further includes: The controller establishes the FTL address mapping relationship.

13. The access method according to any of claims 10-12, characterized by, The method further includes: The controller updates the FTL address mapping relationship to perform at least one of the following operations on the power-off non-volatile memory: wear leveling, garbage collection, or bad block management.

14. The access method according to any of claims 10-13, characterized by, The method further includes: The controller transmits redundant data to the power-off non-volatile memory, and the redundant data is used to reconstruct the FTL address mapping relationship.

15. The access method of claim 14, wherein, The controller transmits redundant data to the power-off non-volatile memory, including: The controller transmits the redundant data through a data header extra field or a write data field in the UPIU.

16. A computer-readable storage medium, characterized in that, The computer instructions, when executed on the processor chip, cause the processor chip to perform the method of any one of claims 10-15.

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