Microdisplay device having cathode wiring area and manufacturing method therefor

Abstract

The present invention relates to the technical field of semiconductors. Disclosed in the present invention are a microdisplay device having a cathode wiring area and a manufacturing method therefor. The microdisplay device comprises: a driver wafer, the surface of the driver wafer comprising a pixel array AA area, each pixel area in the pixel array AA area comprising an anode contact and a cathode wiring area which are insulated from each other, and the cathode wiring areas of adjacent pixel areas being communicated with each other; and a display module, the display module being provided on the driver wafer, the display module comprising a light-emitting unit corresponding to the pixel areas respectively, and the light-emitting unit being communicated with the anode contacts in the corresponding pixel areas and having bottoms not in contact with the cathode wiring areas in the corresponding pixel areas, wherein the top of the cathode wiring area of each pixel area and the top of the light-emitting unit are coated with a continuous common cathode layer. The solution can prevent the light-emitting unit and a cathode metal grid from contending for horizontal space, thereby implementing optical enhancement and electrical enhancement to the maximum extent.

Description

Micro display device with cathode wiring area and preparation method thereof

[0001] Priority information: This application claims priority to the Chinese patent application with the application number 202410971674X and the invention name "Micro display device with cathode wiring area and preparation method thereof", which was filed on July 19, 2024, and the entire content of which is incorporated herein by reference.

[0002] This application claims priority to the Chinese patent application with the application number 2024213980933 and the invention name "Display device", which was filed on June 19, 2024, and the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the field of semiconductor technology, in particular to a micro display device with a cathode wiring area and a preparation method thereof. BACKGROUND

[0004] In the field of micro display and micro projection, silicon-based CMOS driving backplane is generally used, including Micro-OLED, Micro-LED, etc., and basically a common cathode structure is adopted, as shown in FIG. 1, the design of the driving backplane is a pixel array AA area (Active Area) containing a pixel matrix, a peripheral common cathode CC area (Common Cathode), and a signal and electrode pad IO interface area (Input / Output).

[0005] Taking Micro-OLED as an example, in the electrical connection of the pixel photoelectric device in the AA area, there is an anode electrode corresponding to the light emitting unit in the pixel array AA area, and a common cathode layer on the top of the light emitting unit, which extends to the peripheral common cathode CC area, and forms a loop with the common cathode layer. When the light emitting unit develops into Micro-LED, high brightness needs to be implemented under high current density, so the demand for current expansion is greatly increased, and the simple transparent conductive common cathode cannot meet the bearing of large current and the current expansion of large area display area, so the metal mesh grid between the light emitting units is increased as a cathode electrical enhancement structure to realize the current bearing and expansion of the cathode.

[0006] The metal mesh grid on the side of the light emitting unit will compete with the light emitting unit for horizontal space, causing conflicts in optics and electricity: when the light emitting unit is increased to enhance optical performance, the width of the metal mesh grid of the cathode will be compressed, resulting in a decrease in electrical performance; conversely, when the electrical capability is enhanced and the metal mesh grid is widened, the light emitting unit needs to be reduced, resulting in a loss of optical performance. Therefore, a new common cathode photoelectric device structure scheme is needed to solve the conflict between the light emitting unit and the cathode electrical enhancement structure in optics and electricity. SUMMARY

[0007] The present application aims to provide a micro display device with a cathode wiring area and a preparation method thereof, which can solve the contradiction between the light emitting unit and the cathode electrical enhancement structure in optical and electrical aspects.

[0008] To achieve the above-mentioned application purposes, the present application proposes the following technical solutions:

[0009] In one aspect, a micro display device with a cathode wiring area is provided, comprising:

[0010] A driving wafer, a surface of the driving wafer comprising a pixel array AA area, each pixel area in the pixel array AA area comprising: an anode contact and a cathode wiring area which are insulated from each other, and the cathode wiring areas between adjacent pixel areas are connected;

[0011] A display module, the display module being arranged on the driving wafer, the display module comprising a light emitting unit corresponding to each pixel area respectively, the light emitting unit being in conduction with the anode contact in the corresponding pixel area, and the bottom of the light emitting unit not being in contact with the cathode wiring area in the corresponding pixel area;

[0012] Wherein, the top of the cathode wiring area of each pixel area, and the top of the light emitting unit are covered with a continuous common cathode layer.

[0013] In one possible implementation, the surface of the driving wafer further comprises a peripheral common cathode CC area;

[0014] The cathode wiring area of the peripheral part in the pixel array AA area is connected with the peripheral common cathode CC area, and the common cathode layer extends to the peripheral common cathode CC area, so that the cathode wiring area, the common cathode layer and the peripheral common cathode CC area form a loop.

[0015] In one possible implementation, in each pixel area, the anode contact is in the middle region of the pixel area, the cathode wiring area is in the edge region of the pixel area, and the anode contact and the cathode wiring area are insulated.

[0016] In one possible implementation, the cathode wiring area comprises a first layer of cathode wiring area in a groove pattern.

[0017] In one possible implementation, the cathode wiring area further comprises a second layer of cathode wiring area in a hole pattern, the second layer of cathode wiring area being arranged on the first layer of cathode wiring area, and a projection of the second layer of cathode wiring area on the driving wafer being located within a projection of the first layer of cathode wiring area on the driving wafer.

[0018] In a possible implementation, a plurality of the pixel regions share one of the cathode wiring regions;

[0019] Or,

[0020] One of the pixel regions shares a plurality of the cathode wiring regions.

[0021] In a possible implementation, the size of the cathode wiring region is 0.1 um to 30 um, the size of the anode contact is 0.1 um to 100 um, and the size of the insulating region is not less than 0.1 um.

[0022] In a possible implementation, the cathode wiring region is a composite laminated structure, and the composite laminated structure comprises: a composite metal layer, a current transmission layer.

[0023] The composite metal layer comprises at least one of an adhesion layer, a barrier layer, and a seed layer.

[0024] In a possible implementation, the display module further comprises:

[0025] A microlens structure aligned with the light emitting unit and arranged on the common cathode layer.

[0026] In a possible implementation, the radius of the microlens structure in the horizontal direction is greater than 55% of the size of the light emitting unit.

[0027] In a possible implementation, a passivation layer is arranged between the sidewall of the light emitting unit and the common cathode layer, and between the region of the pixel array AA region other than the cathode wiring region and the region in contact with the bottom of the light emitting unit and the common cathode layer.

[0028] On the other hand, a preparation method of a micro display device is also provided, and the method is used for preparing the micro display device as shown in the above aspects, and the method comprises:

[0029] Preparation of a driving wafer, wherein the surface of the driving wafer comprises a pixel array AA region;

[0030] Preparation of an anode contact and a cathode wiring region in each pixel region of the pixel array AA region, and the cathode wiring regions of adjacent pixel regions are connected;

[0031] Integration of a light emitting unit on the driving wafer, wherein each light emitting unit is in conductive connection with the anode contact in the corresponding pixel region, and the bottom is not in contact with the cathode wiring region in the corresponding pixel region;

[0032] Arrangement of a continuous common cathode layer on the top of the cathode wiring region of each pixel region and the top of the light emitting unit.

[0033] In a possible implementation, the preparation of the anode contact and the cathode wiring area in each pixel area of the pixel array AA area includes:

[0034] The first cathode wiring is performed on the pixel array AA area to form the anode contact and the first layer of the cathode wiring area in a trench pattern, and the anode contact and the first layer of the cathode wiring area are separated by an insulation area.

[0035] In a possible implementation, the preparation of the anode contact and the cathode wiring area in each pixel area of the pixel array AA area includes:

[0036] The second cathode wiring is performed on the basis of the first cathode wiring to form the second layer of the cathode wiring area in a hole pattern, the second layer of the cathode wiring area is arranged on the first layer of the cathode wiring area, and a projection of the second layer of the cathode wiring area on the driving wafer is located within a projection of the first layer of the cathode wiring area on the driving wafer.

[0037] In a possible implementation, the first cathode wiring or the second cathode wiring includes:

[0038] The pixel array AA area is subjected to a patterned metal plating to form the anode contact and the cathode wiring area in each pixel area.

[0039] The pixel array AA area is subjected to deposition of an insulating medium to form an insulating layer, and a top of the insulating layer is higher than a top of the anode contact and the cathode wiring area.

[0040] The insulating layer is subjected to thinning and polishing until the anode contact and the cathode wiring area are exposed, and the insulation area is formed between the anode contact and the cathode wiring area.

[0041] In a possible implementation, the first cathode wiring or the second cathode wiring includes:

[0042] The insulating layer is deposited on the pixel array AA area.

[0043] The insulating layer is subjected to patterned etching to form a filling space for the anode contact and the cathode wiring area, and to form the insulation area.

[0044] The filling space is subjected to metal filling to form the anode contact and the cathode wiring area.

[0045] In a possible implementation, the continuous common cathode layer is arranged on a top of the cathode wiring area and a top of the light emitting unit in each pixel area.

[0046] A passivation layer is prepared on the surface of the driving wafer in the periphery of the light emitting unit;

[0047] The N-type ohmic contact layer and the cathode wiring region of the light emitting unit are exposed by plasma etching;

[0048] The common cathode layer is prepared in the periphery of the display module.

[0049] In a possible implementation, after the preparation of the common cathode layer, the method further comprises:

[0050] A microlens structure is prepared in alignment with the light emitting unit and on the common cathode layer.

[0051] Compared with the prior art, the present application has the following beneficial effects:

[0052] The cathode wiring is performed on the driving wafer, for each pixel region in the common pixel array AA region of the surface of the driving wafer, the pixel region is divided into an anode contact and a cathode wiring region, and the anode contact and the cathode wiring region are insulated from each other, and the light emitting unit corresponding to each pixel region is in electrical conduction with the anode contact in the corresponding pixel region, the bottom is not in contact with the cathode wiring region in the corresponding pixel region, and a common cathode layer is arranged on the top of the cathode wiring region of each pixel region and the top of the light emitting unit, and the 2D horizontal layout between the light emitting unit and the cathode electrical enhancement structure is converted into a 3D vertical layout through the lower cathode wiring, thereby solving the problem of competition for horizontal space between the light emitting unit and the cathode electrical enhancement structure, maximizing the realization of optical enhancement and electrical enhancement, and through the large-area metal cathode wiring at the bottom, the heat dissipation capacity of the chip is improved. BRIEF DESCRIPTION OF DRAWINGS

[0053] FIG. 1 is a top view of a driving wafer provided in the related art;

[0054] FIG. 2 is a cross-sectional view of a micro display device with a cathode wiring region provided in an embodiment of the present application;

[0055] FIG. 3 is a top view of a driving wafer with a cathode wiring region provided in an embodiment of the present application;

[0056] FIG. 4 is a top view of a pixel array AA region with a cathode wiring region provided in an embodiment of the present application;

[0057] FIG. 5 is a cross-sectional view of a driving wafer with a cathode wiring region provided in an embodiment of the present application;

[0058] FIG. 6 is a cross-sectional view of a driving wafer with a cathode wiring region provided in an embodiment of the present application;

[0059] Figure 7 is a top view of a pixel array AA region with cathode wiring region according to an embodiment of the present application;

[0060] Figure 8 is a cross-sectional view of a micro display device with a microlens structure according to an embodiment of the present application;

[0061] Figure 9 is a flow chart of a method for fabricating a micro display device according to an embodiment of the present application;

[0062] Figure 10 is a schematic diagram of a process for cathode wiring in a pixel array AA region according to an embodiment of the present application;

[0063] Figure 11 is a cross-sectional view of a compound epitaxy with a P-type ohmic contact layer according to an embodiment of the present application;

[0064] Figure 12 is a top view of a drive wafer with a patterned bonding metal layer according to an embodiment of the present application;

[0065] Figure 13 is a cross-sectional view of a compound epitaxy and drive wafer integrated bonding structure according to an embodiment of the present application;

[0066] Figure 14 is a cross-sectional view of a compound epitaxy and drive wafer integrated bonding structure according to an embodiment of the present application;

[0067] Figure 15 is a cross-sectional view of a micro display device in substrate removal according to an embodiment of the present application;

[0068] Figure 16 is a cross-sectional view of a micro display device after substrate removal according to an embodiment of the present application;

[0069] Figure 17 is a cross-sectional view of a micro display device after N-type ohmic contact fabrication according to an embodiment of the present application;

[0070] Figure 18 is a cross-sectional view of a micro display device after N-type layer roughening according to an embodiment of the present application;

[0071] Figure 19 is a cross-sectional view of a micro display device after N-type ohmic contact fabrication according to an embodiment of the present application;

[0072] Figure 20 is a cross-sectional view of a micro display device after pixel fabrication according to an embodiment of the present application;

[0073] Figure 21 is a schematic diagram of a process for opto-electronic functional fabrication of a light emitting unit according to an embodiment of the present application;

[0074] Figure 22 is a schematic diagram of a process for opto-electronic functional fabrication of a light emitting unit according to an embodiment of the present application;

[0075] FIG. 23 is a schematic diagram of a process for optoelectronic functional preparation of a light emitting unit according to an embodiment of the present application.

[0076] Reference numerals: 100 - driving wafer, 200 - display module, 10 - anode contact, 20 - cathode wiring area, 21 - first layer of cathode wiring area, 22 - second layer of cathode wiring area, 30 - light emitting unit, 31 - bonding metal layer, 32 - P-type ohmic contact layer, 33 - active layer, 34 - N-type ohmic contact layer, 35 - substrate, 40 - common cathode layer, 50 - microlens structure, 60 - passivation layer, 61 - sidewall dielectric layer, 62 - sidewall metal layer. DETAILED DESCRIPTION

[0077] In order to make the objects, technical solutions and advantages of the present application clearer, the following will be combined with the accompanying drawings for the embodiments of the present application to make a clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0078] In the description of the present application, it should be understood that the terms "vertical", "upper", "lower", "top", "side", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features limited by "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0079] In the description of the present application, it should be noted that, unless otherwise specified and limited, the terms "mounting", "connecting", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or the communication between the two elements inside. For those of ordinary skill in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0080] In the related art, the method of preparing a metal mesh grid between the light emitting units after completing the transparent conductive common cathode film layer is used to carry out current bearing and expansion.

[0081] Since both the metal mesh and the light emitting unit need to occupy horizontal space, the metal mesh current is in conflict in electrical and optical performance. A wider metal mesh has better electrical performance, but it needs to occupy more horizontal space, which leads to the size of the light emitting unit being unable to effectively increase, thereby sacrificing the aperture ratio of the pixel and limiting the further miniaturization of the pixel size, while in the micro display field, the horizontal space is limited, and when compromising optical enhancement, the width of the metal mesh is also limited, and a too narrow metal mesh cannot effectively carry current or expand when the screen size is large. In addition, the active region of the compound material (such as GaN) used by the Micro-LED is generally close to the anode, and accordingly, when the size of the metal mesh or the light emitting unit is large, the metal will be on the sidewall of the light emitting unit, shielding the light emitting unit and causing brightness loss. At the same time, the thickness and width of the metal film are limited by the patterning deposition process, and the aspect ratio of depth (thickness) to width generally cannot exceed 2:1.

[0082] In order to avoid the above problems, in the embodiments of the present application, a vertical chip structure of a cathode wiring area with wiring underneath is proposed, which solves the horizontal space conflict of the metal mesh in electrical and optical aspects through the lower metal layout, and at the same time, combined with the vertical structure light emitting unit, avoids the loss of the light emitting area, and can realize the best light emitting unit size and pixel density.

[0083] Next, the device structure proposed in the present application will be described.

[0084] First, the present application provides a micro display device with a cathode wiring area, as shown in FIG. 2, which includes:

[0085] A driving wafer 100, the surface of the driving wafer 100 includes a pixel array AA area, each pixel area in the pixel array AA area includes: an anode contact 10 and a cathode wiring area 20 which are insulated from each other, and the cathode wiring areas 20 between adjacent pixel areas are connected; a display module 200, the display module 200 is arranged on the driving wafer 100, the display module 200 includes a light emitting unit 30 corresponding to each pixel area, the light emitting unit 30 is in conduction with the anode contact 10 in the corresponding pixel area, and the bottom is not in contact with the cathode wiring area 20 in the corresponding pixel area; wherein the top of the cathode wiring area 20 of each pixel area, the top of the light emitting unit 30 is covered with a continuous common cathode layer 40.

[0086] In the embodiment of the present application, the surface of the driving wafer 100 is provided with a cathode wiring, specifically, the surface of the driving wafer 100 comprises a pixel array AA region composed of at least one pixel region, each pixel region is divided into an anode contact 10 and a cathode wiring region 20, and the anode contact 10 and the cathode wiring region 20 are insulated from each other. The driving wafer 100 is provided with a display module 200, and each light emitting unit 30 in the display module 200 corresponds to each pixel region respectively. Here, the one-to-one correspondence is described. The bottom of the light emitting unit 30 is in contact with the anode contact 10 in the corresponding pixel region, and the bottom is not in contact with the cathode wiring region 20 in the corresponding pixel region. The top of the cathode wiring region 20 of each pixel region and the top of the light emitting unit 30 are covered with a continuous common cathode layer 40, so that the cathode wiring region 20 realizes the functions of current bearing and expansion.

[0087] The anode contact 10 in each pixel region can be a single or multiple contacts, and can be circular or polygonal in shape. The anode contact 10 can specifically adopt a composite laminated structure, which comprises a composite metal layer and a current transmission layer. The composite metal layer comprises at least one of an adhesion layer, a barrier layer and a seed layer. The adhesion layer and the barrier layer can comprise Cr, Ti, Ta, Pt, Ni and nitrides such as TiN and TaN. The seed layer and the current transmission layer can comprise Al, Cu, W, Au and their alloys such as AlNi and AlCu. Generally, the metal thickness of the adhesion layer or the barrier layer is 1 nm to 200 nm, and the metal thickness of the current transmission layer is 100 nm to 5 um.

[0088] The cathode wiring region 20 in each pixel region can be a continuous region or a plurality of non-continuous regions. The cathode wiring region 20 can specifically adopt a composite laminated structure, which comprises a composite metal layer and a current transmission layer. The composite metal layer comprises at least one of an adhesion layer, a barrier layer and a seed layer. The adhesion layer and the barrier layer can comprise Cr, Ti, Ta, Pt, Ni and nitrides such as TiN and TaN. The seed layer and the current transmission layer can comprise Al, Cu, W, Au and their alloys such as AlNi and AlCu. Generally, the metal thickness of the adhesion layer or the barrier layer is 1 nm to 200 nm, and the metal thickness of the current transmission layer is 100 nm to 5 um.

[0089] It can be understood that the materials of the anode contact 10 and the cathode wiring region 20 can be the same or different, which is not limited in the present application.

[0090] The light emitting unit 30 can comprise, stacked in a direction away from the driving wafer 100, a bonding metal layer, a P-type ohmic contact layer, an active layer and an N-type ohmic contact layer.

[0091] The common cathode layer 40 can be a transparent conductive film layer such as indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), aluminum-doped indium tin oxide, silver-doped indium tin oxide, gold-doped indium tin oxide, etc. The thickness of the common cathode layer 40 is 50-500 nm.

[0092] In one possible implementation, as shown in FIG. 3, the surface of the driving wafer 100 further comprises a peripheral common cathode CC region; the cathode wiring region 20 of the peripheral part in the pixel array AA region is connected to the peripheral common cathode CC region, and the common cathode layer 40 extends to the peripheral common cathode CC region, so that the cathode wiring region 20, the common cathode layer 40, and the peripheral common cathode CC region form a loop.

[0093] In the present implementation, the cathode wiring region 20 is connected to the peripheral common cathode CC region on the surface of the driving wafer 100, and the common cathode layer 40 in the display module 200 is connected to the peripheral common cathode CC region, so as to realize a closed-loop optoelectronic device.

[0094] In one possible implementation, in each pixel region, the anode contact 10 is located in the middle region of the pixel region, the cathode wiring region 20 is located in the edge region of the pixel region, and the anode contact 10 and the cathode wiring region 20 are insulated by an insulating region.

[0095] In the present implementation, each pixel region comprises at least one anode contact 10, and the anode contact 10 is located in the middle region of the pixel region, the cathode wiring region 20 is located in the edge region of the pixel region, and the anode contact 10 and the cathode wiring region 20 are insulated by an insulating region. The insulating region material can include silicon oxide, silicon nitride, silicon carbide, etc., which is not limited in the present application.

[0096] In one example, the cathode wiring region 20 comprises a first layer of cathode wiring region 21 in a trench pattern, which can be considered as a cathode mesh, and the first layer of cathode wiring region 21 is directly connected to the surface of the driving wafer 100.

[0097] For example, the top view of the pixel region cathode wiring of the pixel array AA region is shown in FIG. 4, and the cross-sectional view is shown in FIG. 5. The anode contact 10 is located in the middle region of the pixel region, the first layer of cathode wiring region 21 is located in the edge region of the pixel region, the diagonal hatched region is the insulating region, and the common cathode wiring in the pixel region can be circular, rectangular, hexagonal, octagonal, etc., which is not limited in the present application.

[0098] In one example, the cathode wiring region 20 is a hole pattern, and a sectional view of the pixel region cathode wiring of the pixel array AA region is shown in FIG. 6. The cathode wiring region 20 further includes a hole pattern second layer cathode wiring region 22 on the basis of the first layer cathode wiring region 21. The second layer cathode wiring region 22 is disposed above the first layer cathode wiring region 21, and a projection of the second layer cathode wiring region 22 on the driving wafer 100 is within a projection of the first layer cathode wiring region 21 on the driving wafer 100. The cathode wiring region 20 can be considered as a cathode contact, which can be distributed in the middle of adjacent pixel regions or the four corners of the pixel region. The hole pattern cathode wiring region 20 can increase the size of the insulating region, i.e., increase the alignment and etching distance of the subsequent process and the cathode wiring region 20, and increase the process window.

[0099] It can be understood that, on the basis of the second layer cathode wiring region 22, a second layer anode contact and a second layer insulating region are further included in the horizontal direction of the second layer cathode wiring region 22. The second layer anode contact is stacked on the first layer anode contact in the same layer as the first layer cathode wiring region 21, and the size of the second layer insulating region is greater than the size of the first layer insulating region in the same layer as the first layer cathode wiring region 21. Further, the size of the second layer anode contact can be the same as the size of the first layer anode, and the center axis of the second layer anode contact can be aligned with the center axis of the second layer anode contact, thereby ensuring the contact effect between the two and ensuring the anode conduction performance.

[0100] Further, a plurality of pixel regions share one cathode wiring region 20, which can be the first layer cathode wiring region 21 or the second layer cathode wiring region 22; or, as shown in (b) and (c) of FIG. 7, one pixel region shares a plurality of cathode wiring regions 20, which can be the first layer cathode wiring region 21 or the second layer cathode wiring region 22. For example, a top view of the pixel region cathode wiring of the pixel array AA region is shown in FIG. 7. Specifically, as shown in (a) of FIG. 7, a plurality of pixel regions share one second layer cathode wiring region 22, and as shown in (b) and (c) of FIG. 7, one pixel region shares a plurality of second layer cathode wiring regions 22.

[0101] Further, as shown in FIG. 5, the size d1 of the cathode wiring region 20 (the first layer cathode wiring region 21, the second layer cathode wiring region 22) is 0.1 um to 30 um, the size d2 of the anode contact 10 is 0.1 um to 100 um, and the size d3 of the insulating region is not less than 0.1 um.

[0102] In a possible implementation, as shown in FIG. 2, a passivation layer 60 is arranged between the sidewall of the light emitting unit 30 and the common cathode layer 40, and between the area in the pixel array AA region except the cathode wiring region 20 and the area in contact with the bottom of the light emitting unit 30 and the common cathode layer 40.

[0103] The passivation layer 60 is used for passivation and insulation of the sidewall of the light emitting unit 30, and can be a single layer or multiple layers of a medium such as silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, etc., and the thickness of the passivation layer 60 is in the range of 50A-1.5um.

[0104] In a possible implementation, as shown in FIG. 8, the display module 200 further includes a microlens structure 50 aligned with the light emitting unit 30 and arranged on the common cathode layer 40.

[0105] In the present implementation, the microlens structure 50 is arranged on the light emitting unit 30, and is a spherical structure or a conical structure, which is convex as a whole in a direction away from the driving wafer 100. Optical collimation is achieved by the microlens or the metasurface, and convergence of the light emitting angle is achieved. The microlens material includes inorganic medium layers such as silicon oxide, silicon nitride, aluminum oxide, etc., or organic medium layers such as SU8, silicone, polyimide, etc., and the microlens can be smooth in curvature or a combination of multiple curvatures, which is not limited in the present application.

[0106] Further, the radius of the microlens structure 50 in the horizontal direction is greater than 55% of the size of the light emitting unit 30. The microlens structure 50 is centered on the P-type ohmic contact layer in the light emitting unit 30, the height from the bottom to the top is denoted as R, and the radius in the horizontal direction is denoted as r, the size of R and r is in the range of 0.5um-200um, r is greater than 55% of the size of the light emitting unit 30, 1≤R:r≤10, and the common cathode layer 40 at the bottom of the adjacent microlens structure 50 can be exposed and can be covered by the microlens material.

[0107] In summary, the embodiment of the present application provides a micro display device with a cathode wiring area, which performs cathode wiring on a driving wafer, and for each common pixel area in a pixel array AA area on the surface of the driving wafer, the pixel area is divided into an anode contact and a cathode wiring area, and the anode contact and the cathode wiring area are insulated from each other, and the light emitting unit corresponding to each pixel area is in electrical conduction with the anode contact in the corresponding pixel area, the bottom of the light emitting unit does not contact the cathode wiring area in the corresponding pixel area, and a common cathode layer is arranged on the top of the cathode wiring area and the top of the light emitting unit in each pixel area, and the 2D horizontal layout between the light emitting unit and the cathode electrical enhancement structure is converted into a 3D vertical layout through the lower cathode wiring, thereby solving the problem of competition for horizontal space between the light emitting unit and the cathode electrical enhancement structure, and maximizing the realization of optical enhancement and electrical enhancement, and through the large-area metal cathode wiring at the bottom, the heat dissipation capacity of the chip is improved.

[0108] Next, a preparation method of the micro display device corresponding to the structure in the above embodiment is described. As shown in FIG. 9, the preparation method of the micro display device can include the following steps:

[0109] Step S1: preparing a driving wafer, and the surface of the driving wafer includes a pixel array AA area.

[0110] Step S2: preparing an anode contact and a cathode wiring area that are insulated from each other in each pixel area of the pixel array AA area, and the cathode wiring areas between adjacent pixel areas are connected.

[0111] It can be understood that, if necessary, the metal of the IO electrode can be completed at the same time when the common cathode metal wiring is formed in step S2, or part of the common cathode is connected to related electrical IO interfaces, such as VCOM (cathode) or GND (ground) interfaces.

[0112] In a possible implementation, step S2 includes: performing first cathode wiring on the pixel array AA area to form an anode contact and a first layer of cathode wiring area in a trench pattern, and the anode contact and the first layer of cathode wiring area are insulated.

[0113] Further, step S2 further includes: performing second cathode wiring on the basis of the first cathode wiring to form a second layer of cathode wiring area in a hole pattern, and the second layer of cathode wiring area is arranged on the first layer of cathode wiring area, and the projection of the second layer of cathode wiring area on the driving wafer is located within the projection of the first layer of cathode wiring area on the driving wafer. That is, two times of cathode wiring are performed, and the anode and the cathode are all converted into hole type contact by the second wiring.

[0114] The process of the first cathode wiring or the second cathode wiring can be:

[0115] (1) The pixel array AA region is subjected to patterned metal plating to form an anode contact and a cathode wiring region in each pixel region.

[0116] The patterned metal plating can be specifically implemented by evaporation, sputtering, etc., which is not limited in the present application.

[0117] (2) The pixel array AA region is subjected to insulating medium deposition to form an insulating layer, and the top of the insulating layer is higher than the top of the anode contact and the cathode wiring region.

[0118] (3) The insulating layer is subjected to thinning and polishing until the anode contact and the cathode wiring region are exposed, and an insulating region is formed between the anode contact and the cathode wiring region.

[0119] In an embodiment, the common cathode wiring of a sandwich structure of Ti 5 nm, Au 500 nm, and Ti 10 nm is completed by patterned evaporation, the periphery of the cathode wiring region is connected to the peripheral common cathode CC region, the metal in the overlapping area connected to the peripheral common cathode CC region can be a mesh or a full surface, the anode contact and the cathode wiring region are arranged in the pixel array AA region at the same time, then silicon oxide is deposited, and the surface is thinned and polished to the metal Ti by chemical mechanical polishing (CMP) after the silicon oxide deposition.

[0120] The process of the first cathode wiring or the second cathode wiring can also be:

[0121] (1) The pixel array AA region is subjected to insulating medium deposition to form an insulating layer.

[0122] (2) The insulating layer is subjected to patterned etching to form a filling space for the anode contact and the cathode wiring region, and an insulating region.

[0123] Further, before the patterned etching, the insulating layer can be subjected to surface planarization treatment by CMP.

[0124] (3) The filling space is subjected to metal filling to form the anode contact and the cathode wiring region.

[0125] The metal filling can be specifically implemented by sputtering, vapor deposition, electroplating, etc., which is not limited in the present application.

[0126] In an embodiment, as shown in FIG. 10, after the insulating layer is deposited on the surface of the driving wafer, the trench corresponding to the cathode wiring region and the hole corresponding to the anode contact are etched, then the sputtering plating of the metal adhesion layer and the barrier layer is performed, and then the filling of the current transmission layer metal is performed by electroplating or chemical plating, and after the filling, the insulating layer is thinned and exposed by metal CMP, and the anode contact 10 and the cathode wiring region 20 are formed.

[0127] Step S3: integrating light-emitting units on the driving wafer, each light-emitting unit being in conduction with the anode contact in the corresponding pixel region and not in contact with the cathode wiring region in the corresponding pixel region.

[0128] In one possible implementation, step S3 specifically includes the following steps:

[0129] (1) As shown in FIG. 11, a patterned P-type ohmic contact layer 32 is prepared by compound epitaxy.

[0130] The P-type ohmic contact layer can be a transparent conductive thin film such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), aluminum-doped indium tin oxide, silver-doped indium tin oxide, gold-doped indium tin oxide, etc., or a metal with certain reflection function such as a single layer or a stack of Pt, Au, Be, Mg, Zn, Ag, Al, Ni, etc. The P-type ohmic contact layer has an area of 100 um to 1000 um expanded outside the overall cathode wiring region in the pixel array AA region. If necessary, the transparent conductive thin film and the metal with reflection function can be stacked with an adhesive layer in between.

[0131] Some compound materials are as shown in the following table. In some practical applications, the film layer of the compound can be more complex, or there can be cross-use of materials. Typically, the main components include a P-type ohmic contact layer, an N-type ohmic contact layer, and an MQW active quantum well (i.e., an active region) sandwiched between the two layers, and other functional layers.

[0132] (2) A bonding metal layer is prepared on the compound epitaxy and the driving wafer.

[0133] The bonding metal layer can be a single element such as Al, Au, Cu, etc., or a stack structure of Ni, Au, Cu, etc. and Sn, or a bonding stack of Au and In, Ge, or Si. If necessary, an adhesive layer and a barrier layer can be introduced between the bonding metal layer and the P-type ohmic layer.

[0134] In an embodiment, as shown in FIG. 12, the patterning of the bonding metal layer is to drive the area after the peripheral common cathode CC area of the wafer surface is expanded, and the width of the bonding metal layer is in the range of 50um-500um compared to the expansion distance D of the peripheral common cathode CC area. The bonding metal layer is prepared in this area, and the peripheral can be filled with a dielectric layer or left blank. By patterning the P-type ohmic contact layer and the bonding metal layer, stress control during film layer and bonding process is achieved, and excessive warping is avoided. At the same time, compared with full-area metal, the metal on the wafer after patterning is less, especially the noble metal can be recycled, and the cost is lower. At the same time, the non-full-area metal can use the metal-free area to arrange the alignment marks required for the bonding and exposure processes on the driving wafer in advance, which is not blocked by metal, and the process is easier to implement. Compared with pixel-level alignment bonding, this expansion area can be coarsely aligned or have lower alignment accuracy requirements, and is not limited by pixel size, and is easier to implement engineering.

[0135] In an embodiment, a Si-based GaN compound wafer is selected, and the P-type ohmic contact layer is 110nm ITO+2nm adhesion layer metal Cr+50nm reflective layer metal Pt. The bonding metal layer on the compound epitaxial and driving wafer can specifically include an adhesion layer of 10nm metal Ti, a barrier layer of 20nm metal Pt, a bonding metal layer of 40nm Ni and 100nm Sn, and a surface covered with 10nm Au as an oxidation barrier layer. The P-type ohmic contact layer and the bonding metal layer are expanded by D=200um compared to the peripheral common cathode CC area, and there is a filled dielectric layer in the periphery of the bonding metal layer. The dielectric layer can be inorganic substances such as silicon oxide and silicon carbide, or organic substances such as SU8 and polyimide.

[0136] (3) Perform wafer-level heterogeneous integration bonding.

[0137] Specifically, after the surface of the compound epitaxial and driving wafer is activated by Ar or N2 plasma, the wafer profile is coarsely aligned and hot-pressed, for example, the bonding temperature is 310℃, and the pressure is 5000Kg. The bonding metal layer and the dielectric layer (if any) are respectively integrated together by bonding. FIG. 13 is a schematic diagram of a wafer after corresponding integrated bonding of the bonding metal layer 31 using full-area design, and FIG. 14 is a schematic diagram of a wafer after corresponding integrated bonding of the bonding metal layer 31 using patterning design.

[0138] (4) Perform N-type ohmic contact preparation.

[0139] Specifically, as shown in FIG. 15, the substrate 35 is removed by laser ablation, fluorine-based plasma dry etching, fluorine-based or ammonia-based wet etching, etc. In an embodiment, the Si substrate is removed by using a chemical such as HF. After the substrate is removed, the compound epitaxy is exposed to the N-type ohmic contact layer 34 by plasma etching, to obtain the structure shown in FIG. 16. A transparent conductive film layer of N-type ohmic contact is prepared on the N-type ohmic contact layer 34, to obtain the structure shown in FIG. 17. The transparent conductive film layer includes indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), aluminum-doped indium tin oxide, silver-doped indium tin oxide, gold-doped indium tin oxide, etc.

[0140] In an embodiment, as shown in FIG. 18, the N-type ohmic contact layer 34 is first roughened, and then a transparent conductive film layer of N-type ohmic contact is prepared on the N-type ohmic contact layer 34, to obtain the structure shown in FIG. 19. The roughening can be obtained by plasma dry etching, acid or alkali etching, etc. For example, the N-type GaN surface can be roughened by using KOH solution to obtain a hexagonal pyramid roughened surface, or by using phosphorus solution to obtain a dodecahedral pyramid roughened surface.

[0141] (5) Pixel preparation.

[0142] Specifically, as shown in FIG. 20, the preparation of the light emitting unit 30 is completed by patterning etching the compound and the bonding metal layer corresponding to the anode contact 10. The patterning etching can be plasma etching, ion beam etching, wet etching, etc. The etching angles A and B can be different, and the angle range is within 90°±45°. The distance between the compound and the bonding metal layer 31 in the light emitting unit 30 is 0≤L1≤25um, and the distance between the bonding metal layer 31 and the cathode wiring area 20 is 0.2um≤L2≤40um. The size of the light emitting unit 30 ranges from 1um to 200um.

[0143] Step S4: A continuous common cathode layer is coated on the top of the cathode wiring area and the top of the light emitting unit.

[0144] In a possible implementation, step S3 specifically includes the following steps:

[0145] (1) A passivation layer is prepared on the surface of the driving wafer and the periphery of the light emitting unit.

[0146] Specifically, after the etching of the light emitting unit is completed, an insulating medium is coated on the periphery of the light emitting unit, to form a passivation layer on the surface of the driving wafer and the periphery of the light emitting unit.

[0147] (2) The N-type ohmic contact layer of the light emitting unit and the cathode wiring area are exposed by plasma etching.

[0148] Specifically, the part of the passivation layer on the top of the light emitting unit and the top of the cathode wiring area is etched by plasma to expose the N-type ohmic contact layer of the light emitting unit and the cathode wiring area.

[0149] (3) A common cathode layer is prepared on the periphery of the display module.

[0150] Specifically, the common cathode layer is prepared on the periphery of the display module by transparent conductive film deposition, so that the common cathode layer is arranged on the top of the cathode wiring area and the top of the light emitting unit.

[0151] Further, after the common cathode layer is prepared by step S4, the following step is further included: preparing a microlens structure aligned with the light emitting unit and arranged on the common cathode layer. The scheme for forming the microlens structure can be in-situ growth, or patterning etching, etc., which is not limited in the present application.

[0152] In an embodiment, as shown in FIG. 21, a metal is prepared on the cathode wiring area 20, which can be a reserved part of the bonding metal layer, or prepared on the cathode wiring area by metal plating, which is used to prevent the exposed cathode wiring area 20 from oxidation or migration, etc. The size of the metal belongs to L3, which is greater than or equal to the size of the exposed cathode wiring area 20 below, and then the passivation layer 60, the common cathode layer 40 and the microlens structure 50 are prepared.

[0153] In an embodiment, as shown in FIG. 22, the distance between the compound in the light emitting unit 30 and the bonding metal layer 31 is designed as 0. After the passivation layer 60 is deposited, only the passivation layer 60 on the sidewall of the light emitting unit 30 is reserved by in-situ etching, which maximally exposes the related N contact area (N-type ohmic contact layer and cathode wiring area), and then the common cathode layer 40 and the microlens structure 50 are prepared.

[0154] In an embodiment, as shown in FIG. 23, only the compound is etched when the light emitting unit 30 is prepared, and the bonding metal layer 31 is reserved. Then, after the dielectric layer and the metal layer are deposited, in-situ etching is performed to reserve the dielectric layer and the metal layer on the sidewall of the light emitting unit to form a sidewall dielectric layer 61 and a sidewall metal layer 62. The metal layer can be a single layer or multiple layers of high reflectivity metal such as Al, Au, Pt, etc. The sidewall dielectric layer 61 and the sidewall metal layer 62 constitute a total reflection, which enhances the cross talk between the light emitting units 30 and the light extraction of the pixels. After the sidewall dielectric layer 61 and the sidewall metal layer 62 are prepared, the insulating dielectric is deposited to form the passivation layer 60, and the N contact area (N-type ohmic contact layer and cathode wiring area) is exposed by patterning etching, and then the common cathode layer 40 and the microlens structure 50 are prepared.

[0155] In summary, the preparation method of the micro display device provided by the embodiments of the present application performs cathode wiring on the driving wafer, divides each common pixel area in the pixel array AA area on the surface of the driving wafer into an anode contact and a cathode wiring area, and insulates the anode contact and the cathode wiring area from each other, and the corresponding light emitting unit of each pixel area is in conduction with the anode contact in the corresponding pixel area, the bottom is not in contact with the cathode wiring area in the corresponding pixel area, and a common cathode layer is arranged on the top of the cathode wiring area and the top of the light emitting unit in each pixel area, and the 2D horizontal layout between the light emitting unit and the cathode electrical enhancement structure is converted into a 3D vertical layout through the lower cathode wiring, solving the problem of the competition for horizontal space between the light emitting unit and the cathode electrical enhancement structure, and maximizing the realization of optical enhancement and electrical enhancement, and through the large-area metal cathode wiring at the bottom, the heat dissipation capacity of the chip can be improved.

[0156] All the optional technical solutions described above can be combined in any way to form optional embodiments of the present application, that is, any number of embodiments can be combined to meet the needs of different application scenarios, which are all within the protection scope of the present application, and will not be described one by one here.

[0157] It should be noted that the above description is only a preferred embodiment of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A microdisplay device having a cathode wiring area, characterized in that, The microdisplay device includes: A driving wafer, the surface of which includes a pixel array AA region, each pixel region in the pixel array AA region including: mutually insulated anode contacts and cathode wiring regions, and the cathode wiring regions between adjacent pixel regions are interconnected; The display module is disposed on the driving wafer. The display module includes light-emitting units corresponding to each pixel area. The light-emitting units are connected to the anode contacts in the corresponding pixel area, and their bottoms are not in contact with the cathode wiring areas in the corresponding pixel area. In this embodiment, a continuous common cathode layer is provided on the top of the cathode wiring area of ​​each pixel region and on the top of the light-emitting unit.

2. The microdisplay device according to claim 1, characterized in that, The surface of the driving wafer also includes: a peripheral common cathode (CC) region; The cathode wiring area in the outer portion of the pixel array AA region is connected to the outer common cathode CC region, and the common cathode layer extends to the outer common cathode CC region, so that the cathode wiring area, the common cathode layer, and the outer common cathode CC region form a loop.

3. The microdisplay device according to claim 1, characterized in that, In each pixel region, the anode contact is located in the middle region of the pixel region, the cathode wiring region is located in the edge region of the pixel region, and there is an insulating region between the anode contact and the cathode wiring region.

4. The microdisplay device according to claim 3, characterized in that, The cathode wiring area includes a first layer of cathode wiring area with a trench pattern.

5. The microdisplay device according to claim 4, characterized in that, The cathode wiring area also includes a second cathode wiring area with a hole pattern. The second cathode wiring area is disposed above the first cathode wiring area, and the projection of the second cathode wiring area on the driving wafer is located within the projection of the first cathode wiring area on the driving wafer.

6. The microdisplay device according to claim 1, characterized in that, Multiple pixel regions share one cathode wiring region; or, One of the pixel regions shares multiple of the cathode wiring regions.

7. The microdisplay device according to claim 3, characterized in that, The size of the cathode wiring area is between 0.1um and 30um, the size of the anode contact is between 0.1um and 100um, and the size of the insulating area is not less than 0.1um.

8. The microdisplay device according to claim 1, characterized in that, The cathode wiring area is a composite stacked structure, which includes: a composite metal layer and a current transmission layer; The composite metal layer includes at least one of an adhesive layer, a barrier layer, and a seed layer.

9. The microdisplay device according to claim 1, characterized in that, The display module also includes: A microlens structure is aligned with the light-emitting unit and is disposed on the common cathode layer.

10. The microdisplay device according to claim 9, characterized in that, The radius of the microlens structure in the horizontal direction is greater than 55% of the size of the light-emitting unit.

11. The microdisplay device according to claim 1, characterized in that, A passivation layer is provided between the sidewall of the light-emitting unit and the common cathode layer, and between the area of ​​the pixel array AA region other than the cathode wiring area and the area in contact with the bottom of the light-emitting unit and the common cathode layer.

12. A method for fabricating a microdisplay device, characterized in that, The method is used to prepare the microdisplay device as described in any one of claims 1 to 11, the method comprising: Prepare a driver wafer, the surface of which includes a pixel array AA region; In each pixel region of the pixel array AA region, mutually insulated anode contacts and cathode wiring regions are prepared, and the cathode wiring regions between adjacent pixel regions are interconnected. Light-emitting units are integrated on the driving wafer. Each light-emitting unit is connected to the anode contact in the corresponding pixel area, and its bottom does not contact the cathode wiring area in the corresponding pixel area. A continuous common cathode layer is applied to the top of the cathode wiring area of ​​each pixel region and the top of the light-emitting unit.

13. The method according to claim 12, characterized in that, The process of fabricating mutually insulated anode contacts and cathode wiring areas in each pixel region of the pixel array AA region includes: The pixel array AA area is subjected to the first cathode wiring to form mutually insulated anode contacts and a first layer of cathode wiring area in the form of a trench pattern. The anode contacts and the first layer of cathode wiring area are insulated from each other.

14. The method according to claim 13, characterized in that, The step of fabricating mutually insulated anode contacts and cathode wiring areas in each pixel region of the pixel array AA region further includes: A second cathode wiring is performed based on the first cathode wiring to form a second cathode wiring area with a hole pattern. The second cathode wiring area is disposed above the first cathode wiring area, and the projection of the second cathode wiring area on the driving wafer is located within the projection of the first cathode wiring area on the driving wafer.

15. The method according to claim 13 or 14, characterized in that, The process of the first cathode wiring or the second cathode wiring includes: A patterned metal coating is applied to the pixel array AA region to form the anode contact and the cathode wiring region in each pixel region; An insulating dielectric is deposited on the AA region of the pixel array to form an insulating layer, the top height of which is higher than the top height of the anode contact and the cathode wiring area. The insulating layer is thinned and polished until the anode contact and the cathode wiring area are exposed, and the insulating area is formed between the anode contact and the cathode wiring area.

16. The method according to claim 13 or 14, characterized in that, The process of the first cathode wiring or the second cathode wiring includes: An insulating dielectric is deposited in the AA region of the pixel array to form an insulating layer; The insulating layer is patterned and etched to form filling spaces for the anode contacts and the cathode wiring area, as well as to form an insulating area; The filling space is filled with metal to form the anode contact and the cathode wiring area.

17. The method according to claim 12, characterized in that, The provision of a continuous common cathode layer covering the top of the cathode wiring area of ​​each pixel region and the top of the light-emitting unit includes: A passivation layer is prepared on the surface of the driving wafer surrounding the light-emitting unit; The N-type ohmic contact layer of the light-emitting unit and the cathode wiring area are exposed by plasma etching. The common cathode layer is fabricated around the display module.

18. The method according to claim 12, characterized in that, After the common cathode layer is prepared, the method further includes: A microlens structure is prepared that is aligned with the light-emitting unit and disposed on the common cathode layer.

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