Impedance circuit self-matching optimization method and system, and related device

Abstract

The present invention relates to the technical field of wireless communications. Provided are an impedance circuit self-matching optimization method and system, and a related device. The method comprises the following steps: S1, reading an SNP file of a filter and generating corresponding port networks and operating frequency bands; S2, performing circuit pre-estimation optimization on each port network, and recording optimization results of all the port networks; S3, perform screening on each port network on the basis of a preset rule, so as to obtain a plurality of screening results; S4, assembling overall matching circuits on the basis of the plurality of screening results, and obtaining a plurality of circuit optimization results; and S5, screening the plurality of circuit optimization results to obtain an optimal matching circuit. The impedance circuit self-matching optimization method in the present invention can improve the optimization efficiency of a SAW matching circuit and the operating electrical performance of a SAW.

Description

Impedance circuit self-matching optimization methods, systems and related equipment Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to an impedance circuit self-matching optimization method, system, and related equipment. Background Technology

[0002] For surface acoustic wave (SAW) filters, a proper matching circuit is just as important as an appropriate interpolation geometry design. For SAW devices, constructing a suitable matching circuit can significantly improve the electrical performance, including insertion loss, return frequency, and VSWR within the passband.

[0003] Most current circuit design tools support filter matching circuit optimization. This involves the designer loading the SNP file representing the electrical performance of the SAW filter into the tool. Based on their observations and design experience, the designer manually builds the matching circuit and assigns initial values ​​to the added electronic components (commonly capacitors and inductors). Then, the designer manually specifies the optimization target for insertion loss or VSWR and uses the built-in optimization algorithm of the circuit design tool to numerically optimize the physical quantities of each electronic component in the matching circuit.

[0004] Existing circuit design tools generally require the initial construction of the basic matching circuit structure, such as determining whether each port of the filter is connected to the output via one or more capacitors or inductors in series or parallel. For a single port, even considering matching circuit structures with a maximum of two electronic components, there are 2*2 + 4*4 theoretically feasible matching circuit structures. For an n-port SAW filter, there are 20^n theoretically feasible matching circuit structures.

[0005] Therefore, when dealing with an n-port SAW filter, designers need to fully utilize their design experience to select one of the 20^n matching circuit structures, model it in a circuit design tool, and then optimize the physical quantities of the electronic components using optimization algorithms to obtain the specific physical quantities of the electronic components in the matching circuit. When the optimization results are unsatisfactory, designers need to conduct in-depth analysis of the electrical performance of the SAW filter, repeatedly adjusting the structure of the matching circuit to ultimately select a suitable circuit structure and obtain the physical quantities of the electronic components.

[0006] However, the drawback of the existing technology is that the structure of the matching circuit needs to be preset when optimizing the matching circuit. When the structure of the matching circuit is not designed reasonably or is not good enough, it is impossible to achieve the purpose of regulating the electrical performance of the SAW filter through the matching circuit, and the self-matching optimization efficiency of the impedance circuit is low. Summary of the Invention

[0007] This invention provides an impedance circuit self-matching optimization method to solve the problem of low efficiency in existing impedance circuit self-matching optimization methods.

[0008] In a first aspect, embodiments of the present invention provide an impedance circuit self-matching optimization method, the method comprising the following steps:

[0009] S1. Read the SNP file of the filter and generate the corresponding port network and operating frequency band;

[0010] S2. Perform circuit pre-estimation optimization on each of the port networks and record the optimization results for all the port networks;

[0011] S3. Filter each of the port networks according to preset rules to obtain multiple filtering results;

[0012] S4. Assemble a matching circuit for the various screening results to obtain various circuit optimization results;

[0013] S5. Filter the various circuit optimization results to obtain the optimal matching circuit.

[0014] Preferably, step S2 specifically includes the following sub-steps:

[0015] S21. The port network is presumably set to have N ports, and the i-th port is selected; where 0 < i ≤ N, and i and N are both positive integers;

[0016] S22. Traverse all feasible circuit structures and optimize the physical quantities of electronic components in each circuit structure to obtain the target optimization result;

[0017] S23. Record the optimization results of the target;

[0018] S24. Complete the optimization processing of the N ports and record the optimization results of all ports.

[0019] Preferably, in step S22, the physical quantities of electronic components in each circuit structure are optimized using the gradient descent method to obtain the target optimization result.

[0020] Preferably, step S3 specifically includes the following sub-steps:

[0021] S31. Extract the optimization results obtained from the circuit pre-estimation of the i-th port;

[0022] S32. Sort the optimization results according to passband flatness;

[0023] S33. The sorted optimization results are filtered according to the first decimal place of the passband flatness to obtain the filtering results; wherein, the first decimal place represents all the filtering results that are less than the minimum value of passband flatness + (maximum value of passband flatness - minimum value of passband flatness) / 10 after sorting multiple VSWR values.

[0024] S34. Complete the result filtering for all N ports.

[0025] Preferably, step S4 specifically includes the following sub-steps:

[0026] S41. Use Cartesian product traversal to obtain all feasible results for the overall matched circuit;

[0027] S42. Select any feasible result of the overall matching circuit, perform pre-optimization processing, and obtain the pre-optimization result;

[0028] S43. Use the pre-optimization result as the initial value of the physical quantity of the electronic component, and use the gradient optimization algorithm to optimize each port;

[0029] S44. Complete the optimization process for all the overall matching circuits.

[0030] Preferably, in step S41, the Cartesian product is specifically represented as:

[0031] Defined, the feasible result of the overall matching circuit is K, K i The i-th result for each port.

[0032] Preferably, in step S5, the first quartile is used to filter the various circuit optimization results, and the filtered result is taken as the optimal matching circuit.

[0033] In a second aspect, embodiments of the present invention provide an impedance circuit self-matching optimization system, the impedance circuit self-matching optimization system comprising:

[0034] The reading module is used to read the SNP file of the filter and generate the corresponding port network and operating frequency band;

[0035] The pre-estimation module is used to perform circuit pre-estimation for each of the port networks and record the optimization results of all the port networks;

[0036] The filtering module is used to filter each of the port networks according to preset rules to obtain multiple filtering results;

[0037] An assembly module is used to perform overall matching circuit assembly on various screening results and obtain various circuit optimization results;

[0038] The recommendation module is used to filter the various circuit optimization results to obtain the optimal matching circuit.

[0039] Thirdly, embodiments of the present invention provide a computer device, including: a memory, a processor, and an impedance circuit self-matching optimization program stored in the memory and executable on the processor. When the processor executes the impedance circuit self-matching optimization program, it implements the steps in the impedance circuit self-matching optimization method described above.

[0040] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing an impedance circuit self-matching optimization program, wherein the impedance circuit self-matching optimization program, when executed by a processor, implements the steps in the above-described impedance circuit self-matching optimization method.

[0041] Compared with existing technologies, the impedance circuit self-matching optimization method in this invention reads the SNP file of the filter and generates corresponding port networks and operating frequency bands; performs circuit pre-estimation optimization on each port network and records the optimization results of all port networks; filters each port network according to preset rules to obtain multiple filtering results; assembles the overall matching circuit of the multiple filtering results and obtains multiple circuit optimization results; filters the multiple circuit optimization results to obtain the optimal matching circuit. This eliminates the need for users to preset circuit structures, and the optimization method can try all feasible matching circuits. Through the pre-optimization step, feasible circuits are initially screened using the voltage standing wave ratio (VSWR) performance of each single port, thereby improving the efficiency of overall analysis of all SAW ports. Screening multiple circuit optimization results ensures that the SAW matching circuit provides superior electrical performance, while allowing users to choose a more suitable solution from the results according to their actual needs, thus improving the optimization efficiency of the impedance matching circuit. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 is a flowchart of the impedance circuit self-matching optimization method provided in an embodiment of the present invention;

[0044] Figure 2 is a flowchart illustrating step S2 provided in an embodiment of the present invention;

[0045] Figure 3 is a flowchart illustrating step S3 provided in an embodiment of the present invention;

[0046] Figure 4 is a flowchart illustrating step S4 provided in an embodiment of the present invention;

[0047] Figure 5 is a comparison diagram of the original SAW electrical performance and the electrical performance after loading the matching circuit provided in the embodiment of the present invention.

[0048] Figure 6 is a block diagram of the impedance circuit self-matching optimization system provided in an embodiment of the present invention;

[0049] Figure 7 is a block diagram of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0050] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, every other embodiment of the present invention obtained by those of ordinary skill in the art without creative effort is within the scope of protection of the present invention.

[0051] Example 1

[0052] Referring to Figures 1-5, this embodiment of the invention provides an impedance circuit self-matching optimization method, the method comprising the following steps:

[0053] S1. Read the SNP file of the filter and generate the corresponding port network and operating frequency band.

[0054] Here, "port network" stands for "Network"; "SNP file" is an SNP file format used to store parameters of the port network or passive connections of a filter, which describe the network's behavior at a specific frequency.

[0055] S2. Perform circuit pre-estimation optimization on each of the port networks and record the optimization results for all the port networks.

[0056] The port network includes the circuit structure, physical quantities of electronic components, and optimization results for each feasible circuit.

[0057] Conventional matching circuit optimization requires applying matching elements to each port and considering the electrical performance of each port. Matching circuit prediction, however, only considers one port in a multi-port device. That is, no matching elements are applied to other ports, and their electrical performance is not considered, thus improving matching efficiency.

[0058] S3. Each port network is filtered according to preset rules to obtain multiple filtering results.

[0059] Since the first step requires pre-estimation of each port, there will be multiple feasible results for each port.

[0060] S4. Assemble an overall matching circuit for the various screening results and obtain various circuit optimization results.

[0061] In this process, all the results obtained in step S3 are combined to obtain the complete set of screening results. For example, there are 3 matching circuits after screening at port 1 [a, b, c], and 2 matching circuits after screening at port 2 [d, e]. Therefore, through the Cartesian product, there are a total of 6 matching circuits for this device [ad, ae, bd, be, cd, ce].

[0062] S5. Filter the various circuit optimization results to obtain the optimal matching circuit.

[0063] Specifically, the process involves reading the filter's SNP file and generating corresponding port networks and operating frequency bands; performing circuit pre-estimation optimization on each port network and recording the optimization results for all port networks; filtering each port network according to preset rules to obtain multiple filtering results; assembling an overall matching circuit from the multiple filtering results to obtain multiple circuit optimization results; and filtering the multiple circuit optimization results to obtain the optimal matching circuit. This eliminates the need for users to preset circuit structures, and the optimization method can try all feasible matching circuits. Through the pre-optimization step, feasible circuits are initially screened using the voltage standing wave ratio (VSWR) performance of each single port, thereby improving the efficiency of overall analysis of all SAW ports. Filtering multiple circuit optimization results ensures that the SAW matching circuit provides superior electrical performance, while allowing users to select a suitable solution from the results based on actual needs, thus improving the optimization efficiency of the impedance matching circuit.

[0064] In this embodiment, step S2 specifically includes the following sub-steps:

[0065] S21. Preset that the port network has N ports, and select the i-th port; where 0 < i ≤ N, and i and N are both positive integers.

[0066] S22. Traverse all feasible circuit structures and optimize the physical quantities of electronic components in each circuit structure to obtain the target optimization result.

[0067] In this embodiment, in step S22, the physical quantities of electronic components in each circuit structure are optimized using the gradient descent method to obtain the target optimization result.

[0068] Among them, gradient descent moves a certain step size along the direction of the negative gradient (i.e. the direction of the fastest descent) in each iteration until the minimum value of the loss function is reached, which has high optimization efficiency.

[0069] Specifically, there are approximately 20 feasible circuit structures. By iterating through these 20 feasible circuit structures, the physical quantities of the electronic components in each circuit structure are optimized using the gradient descent method. The optimization objective is the estimated passband flatness (ILMIN-ILMAX).

[0070] S23. Record the optimization results of the target. Record the optimization results of 20 feasible circuit structures.

[0071] S24. Complete the optimization processing of the N ports and record the optimization results of all ports. Complete the circuit pre-estimation of all N ports and record 20*N optimization results for all N ports.

[0072] The so-called pre-estimation involves applying a matching element only to a specific port to optimize its electrical performance. This pre-estimation is relative to the final goal, which is to obtain the matching circuit for the entire N-port device. In other words, before obtaining the final matching circuit, unsuitable circuit elements in each port are eliminated in advance through pre-estimation. Thus, the pre-estimation for a specific port is performed through feasible circuit optimization.

[0073] In this embodiment, step S3 specifically includes the following sub-steps:

[0074] S31. Extract the optimization results obtained from the circuit pre-estimation of the i-th port.

[0075] Specifically, the i-th port is selected, and the recorded circuit structure, physical quantities of electronic components, and pre-optimization results are obtained.

[0076] S32. Sort the optimization results according to passband flatness.

[0077] The pre-optimization results are sorted from smallest to largest to obtain a sorted result, which facilitates further filtering of the results.

[0078] S33. The sorted optimization results are filtered according to the first decimal place of the passband flatness to obtain the filtering results; wherein, the first decimal place represents all the filtering results that are less than the minimum passband flatness + (maximum passband flatness - minimum passband flatness) / 10 after sorting multiple VSWR values.

[0079] The first decimal place represents numbers from 0 to 10, selecting numbers before 1. By filtering the data within the first decimal place, this data includes the physical quantities of circuit structures and electronic components.

[0080] Optionally, 20 feasible circuit structures can be pre-screened, as shown in Table 1 below.

[0081] Table 1-6 Feasible Circuit Structures

[0082] As shown in Table 1 above, 20 feasible circuit structures can be pre-selected based on user needs. If the user wishes to use only inductors, the 20 feasible circuit structures can be reduced to 6, which can further improve optimization efficiency.

[0083] S34. Complete the result filtering for all N ports. The VSWR performance of each individual port is used to initially filter feasible circuits, thereby greatly improving the efficiency of overall SAW port analysis.

[0084] In this embodiment, step S4 specifically includes the following sub-steps:

[0085] S41. Use Cartesian product traversal to obtain all feasible results for the overall matched circuit and perform pre-optimization.

[0086] The Cartesian product is used to obtain all K feasible results, where K represents all the filtering results for each port i.

[0087] S42. Select any feasible result of the overall matching circuit, perform pre-optimization processing, and obtain the pre-optimization result.

[0088] Among them, the feasible result of selecting the j-th overall matching circuit of K types is used to obtain the pre-optimization result; where 0 < j < K.

[0089] S43. Use the pre-optimization result as the initial value of the physical quantity of the electronic component, and use the gradient optimization algorithm to optimize each port.

[0090] The gradient optimization algorithm is used to optimize each port, with test specifications (optional) as constraints and the target indicators (such as insertion loss, voltage standing wave ratio, ripple, etc.) within the passband as objectives.

[0091] S44. Complete the optimization process for all the overall matching circuits. This completes the optimization of K types of overall matching circuits and improves the optimization efficiency of the matching circuits.

[0092] Optionally, users can intervene in the optimization process at each step to achieve various customized requirements, such as requiring that only inductors exist in the circuit, or requiring that the physical quantity of the inductor not exceed 10nH (this upper and lower limit can be added in the gradient optimization of Step 3.2 and Step 4.3). The objective function formula in step S43 can be modified during the optimization process to adjust the weights according to actual needs. For example, if the goal is to focus on optimizing VSWR, the objective can be set to Sum(X*VSWR+Abs(IL_MAX)), where X can be any value greater than 1.

[0093] In this embodiment, in step S41, the Cartesian product is specifically represented as:

[0094] Defined, the feasible result of the overall matching circuit is K, K i The i-th result for each port. Optional, since K i It is the result of the screening of the decimal place, therefore K i Much less than 20, therefore This achieves the goal of screening feasible matching circuit structures.

[0095] In this embodiment, in step S5, the first quartile is used to filter the various circuit optimization results, and the filtered result is taken as the optimal matching circuit.

[0096] The optimization results are filtered using the first quartile, ensuring that the SAW matching circuit provides better electrical performance while allowing users to choose the most suitable solution from the results based on their actual needs.

[0097] In this embodiment, as shown in Figure 5, the impedance circuit self-matching optimization method is used to obtain a comparison chart of the electrical performance of the matching circuit and the original SAW circuit. The matching circuit is Port 1: 2.0nH in parallel, 2.0pF in series (power factor); the matching circuit is Port 2: 3.7nH in series, 1.4pF in parallel. The electrical performance is: passband insertion loss -2.2dB, return -12.1dB.

[0098] Example 2

[0099] As shown in Figure 6, this embodiment of the invention provides an impedance circuit self-matching optimization system 200, the impedance circuit self-matching optimization system 200 comprising:

[0100] The reading module 201 is used to read the SNP file of the filter and generate the corresponding port network and operating frequency band;

[0101] The pre-estimation module 202 is used to perform circuit pre-estimation optimization for each of the port networks and record the optimization results of all the port networks;

[0102] The filtering module 203 is used to filter each of the port networks according to preset rules to obtain multiple filtering results;

[0103] Assembly module 204 is used to perform overall matching circuit assembly on multiple screening results and obtain multiple circuit optimization results by traversal;

[0104] The recommendation module 205 is used to filter the various circuit optimization results to obtain the optimal matching circuit.

[0105] The optimization method involves several steps: First, the filter's SNP file is read by module 201, generating the corresponding port network and operating frequency band. Second, the circuit pre-estimation module 202 performs circuit pre-estimation optimization on each port network and records the optimization results for all port networks. Third, the filtering module 203 filters each port network according to preset rules, obtaining multiple filtering results. Fourth, the assembly module 204 assembles the overall matching circuit from the multiple filtering results and obtains multiple circuit optimization results through iteration. Fifth, the recommendation module 205 filters the multiple circuit optimization results to obtain the optimal matching circuit. This eliminates the need for users to preset the circuit structure, and the optimization method can try all feasible matching circuits. The pre-optimization step utilizes the VSWR performance of each single port to initially filter feasible circuits, greatly improving the efficiency of overall analysis of all SAW ports. By filtering the optimization results, while ensuring that the SAW matching circuit provides superior electrical performance, users can choose the most suitable solution from the results based on their actual needs.

[0106] In this embodiment, the pre-estimation module 202 is further configured to: preset that the port network has N ports, and select the i-th port; where 0 < i ≤ N, and i and N are both positive integers. All feasible circuit structures are traversed, and the physical quantities of electronic components in each circuit structure are optimized to obtain the target optimization result.

[0107] In this embodiment, the physical quantities of electronic components in each circuit structure are optimized using the gradient descent method to obtain the target optimization result.

[0108] The optimization results for the stated objective are recorded. This is achieved by recording the optimization results for 20 feasible circuit structures.

[0109] Complete the circuit pre-estimation for all N ports and record the optimization results for all ports. Complete the circuit pre-estimation for all N ports and record 20*N optimization results for all N ports.

[0110] In this embodiment, the filtering module 203 is further used to extract the optimization results obtained from the circuit pre-estimation of the i-th port.

[0111] Specifically, the i-th port is selected, and the recorded circuit structure, physical quantities of electronic components, and pre-optimization results are obtained.

[0112] The optimization results are sorted according to passband flatness.

[0113] The pre-optimization results are sorted from smallest to largest to obtain a sorted result, which facilitates further filtering of the results.

[0114] The sorted optimization results are filtered according to the first decimal place of the passband flatness to obtain the filtering results; wherein, the first decimal place represents all filtering results that are less than the minimum passband flatness + (maximum passband flatness - minimum passband flatness) / 10 after sorting multiple VSWR values.

[0115] The results for all N ports are filtered. The VSWR performance of each individual port is used to initially screen feasible circuits, thus greatly improving the efficiency of overall SAW port analysis.

[0116] In this embodiment, the assembly module 204 is further configured to use Cartesian product traversal to obtain all feasible results of the overall matching circuit.

[0117] The Cartesian product is used to obtain all K feasible results, where K represents all the filtering results for each port i.

[0118] Select any feasible result of the overall matching circuit, perform pre-optimization processing, and obtain the pre-optimized result.

[0119] Among them, the feasible result of selecting the j-th overall matching circuit of K types is used to obtain the pre-optimization result; where 0 < j < K.

[0120] The pre-optimization results are used as initial values ​​for the physical quantities of the electronic components, and a gradient optimization algorithm is used to optimize each port.

[0121] The gradient optimization algorithm is used to optimize each port, with test specifications (optional) as constraints and the target indicators (such as insertion loss, voltage standing wave ratio, ripple, etc.) within the passband as objectives.

[0122] The optimization process for all the aforementioned overall matching circuits is completed. This achieves the optimization of K types of overall matching circuits, improving the optimization efficiency of the matching circuits.

[0123] The impedance circuit self-matching optimization system 200 performs the same function as the impedance circuit self-matching optimization method described above, and produces the same technical effect, so it will not be described again here.

[0124] Example 3

[0125] As shown in Figure 7, this embodiment of the invention provides a computer device 300, including: a memory 301, a processor 302, and an impedance circuit self-matching optimization program stored in the memory 301 and executable on the processor 302. When the processor 302 executes the impedance circuit self-matching optimization program, it implements the steps in the impedance circuit self-matching optimization method described above.

[0126] S1. Read the SNP file and generate the corresponding port network and operating frequency band;

[0127] S2. Perform circuit pre-estimation for each of the port networks and record the optimization results for all the port networks;

[0128] S3. Filter each of the port networks according to preset rules to obtain multiple filtering results;

[0129] S4. Assemble an overall matching circuit for the various screening results and obtain various circuit optimization results;

[0130] S5. Filter the various circuit optimization results to obtain the recommended matching circuit.

[0131] Example 4

[0132] This invention provides a computer-readable storage medium storing an impedance circuit self-matching optimization program. When the impedance circuit self-matching optimization program is executed by a processor, it implements the steps in the impedance circuit self-matching optimization method described above.

[0133] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0134] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0135] The above description discloses only preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. An impedance circuit self-matching optimization method, characterized by, The method comprises the following steps: S1, reading the SNP file of the filter and generating the corresponding port network and working frequency band; S2, performing circuit pre-estimation optimization on each port network, and recording the optimization results of all port networks; S3, screening each port network according to a preset rule to obtain multiple screening results; S4, performing overall matching circuit assembly on the multiple screening results to obtain multiple circuit optimization results; S5, screening the multiple circuit optimization results to obtain the optimal matching circuit.

2. The impedance circuit self-matching optimization method of claim 1, wherein, Step S2 specifically comprises the following sub-steps: S21, presetting that the port network has N ports, and selecting the i-th port; wherein 0 S22, traversing all feasible circuit structures, and optimizing the physical quantity of each electronic element in each circuit structure to obtain a target optimization result; S23, recording the target optimization result; S24, completing the optimization processing of the N ports, and recording the optimization results of all ports.

3. The impedance circuit self-matching optimization method of claim 2, wherein, In step S22, the physical quantity of each electronic element in each circuit structure is optimized by the gradient descent method to obtain the target optimization result.

4. The impedance circuit self-matching optimization method of claim 2, wherein, Step S3 specifically comprises the following sub-steps: S31, extracting the optimization result obtained by circuit pre-estimation of the i-th port; S32, sorting the optimization result according to the passband flatness; S33, screening the sorted optimization result according to the first tenth of the passband flatness to obtain a screening result; wherein the first tenth represents all screening results after sorting multiple standing wave ratio values, which are less than the minimum value of the passband flatness + (the maximum value of the passband flatness - the minimum value of the passband flatness) / 10; S34, completing the result screening of all N ports.

5. The impedance circuit self-matching optimization method of claim 4, wherein, Step S4 specifically comprises the following sub-steps: S41, using Cartesian product traversal to obtain all feasible results of overall matching circuits; S42, selecting any one of the feasible results of overall matching circuits for pre-optimization processing to obtain a pre-optimization result; S43, using the pre-optimization result as the initial value of the physical quantity of the electronic element, and optimizing each port using a gradient optimization algorithm; S44, completing the optimization processing of all overall matching circuits.

6. The impedance circuit self-matching optimization method of claim 5, wherein, In step S41, the Cartesian product is specifically represented as: By definition, the overall match circuit can work for results K, K i for each port for the i-th result.

7. The impedance circuit self-matching optimization method of claim 1, wherein, In step S5, the first quartile is used to screen the multiple circuit optimization results, and the screening result is used as the optimal matching circuit.

8. An impedance circuit self-matching optimization system, comprising: The impedance circuit self-matching optimization system comprises: A reading module for reading the SNP file of the filter and generating the corresponding port network and working frequency band; A pre-estimation module for performing circuit pre-estimation optimization on each port network, and recording the optimization results of all port networks; A screening module for screening each port network according to a preset rule to obtain multiple screening results; An assembly module for performing overall matching circuit assembly on the multiple screening results to obtain multiple circuit optimization results; A recommendation module for screening the multiple circuit optimization results to obtain the optimal matching circuit.

9. A computer device, comprising: It comprises: A memory, a processor and an impedance circuit self-matching optimization program stored on the memory and executable on the processor, the processor implementing the steps of the impedance circuit self-matching optimization method according to any one of claims 1-7 when executing the impedance circuit self-matching optimization program.

10. A computer-readable storage medium, characterized in that, A computer readable storage medium having stored thereon an impedance circuit self-matching optimization program, the impedance circuit self-matching optimization program implementing the steps of the impedance circuit self-matching optimization method according to any one of claims 1-7 when executed by a processor.

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