Tiled display panel and driving method therefor, and display device

Abstract

A tiled display panel and a driving method therefor, and a display device. The tiled display panel comprises a first sub-panel and a second sub-panel. The first sub-panel comprises M display areas, and the second sub-panel comprises N display areas. In the tiling direction of the first sub-panel and the second sub-panel, scanning is performed in the M display areas of the first sub-panel in a first scanning sequence, scanning is performed in the N display areas of the second sub-panel in a second scanning sequence, and scanning directions of at least two display areas on two sides of a tiling seam between the first sub-panel and the second sub-panel are the same, wherein the direction of the first scanning sequence is opposite to the direction of the second scanning sequence.

Description

Spliced display panel, driving method thereof and display device

[0001] The present application claims priority to the Chinese patent application No. 202410781589.7, filed on June 17, 2024, to the Chinese Patent Office, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the field of display technology, for example, to a spliced display panel, a driving method thereof and a display device. BACKGROUND

[0003] With the continuous development of display technology, micro light emitting diodes (Micro-LED) and mini light emitting diodes (Mini-LED) have been widely used in the display field due to their wide color gamut, fast response speed, high brightness, long service life and other advantages.

[0004] Large screens or super large screens are usually spliced by multiple panels, however, the existing spliced display panel has the problem of poor display effect. SUMMARY

[0005] Embodiments of the present application provide a spliced display panel, a driving method thereof and a display device to improve the display effect of the spliced display panel.

[0006] Embodiments of the present application provide a spliced display panel, comprising at least one first sub-panel and at least one second sub-panel, the first sub-panel comprising M display areas, and the second sub-panel comprising N display areas; wherein M≥2, N≥2, and M and N are integers.

[0007] In the splicing direction of the first sub-panel and the second sub-panel, the M display areas in the first sub-panel are scanned in a first scanning order, and the N display areas in the second sub-panel are scanned in a second scanning order, and the scanning directions of at least two display areas on both sides of the splicing seam of the first sub-panel and the second sub-panel are the same; wherein the direction of the first scanning order is opposite to the direction of the second scanning order, one of the two display areas on both sides of the splicing seam is one display area in the first sub-panel, and the other is one display area in the second sub-panel.

[0008] The embodiment of the present application provides a driving method of a spliced display panel, the spliced display panel comprising at least one first sub-panel and at least one second sub-panel, the first sub-panel comprising M display areas, and the second sub-panel comprising N display areas; wherein M is greater than or equal to 2, N is greater than or equal to 2, and M and N are both integers;

[0009] The driving method of the spliced display panel comprises:

[0010] controlling the M display areas in the first sub-panel to scan in a first scanning order;

[0011] controlling the N display areas in the second sub-panel to scan in a second scanning order;

[0012] wherein the scanning directions of at least two display areas on both sides of a splicing seam of the first sub-panel and the second sub-panel are the same, the direction of the first scanning order is opposite to the direction of the second scanning order, and one of the two display areas on both sides of the splicing seam is a display area in the first sub-panel, and the other is a display area in the second sub-panel.

[0013] The embodiment of the present application provides a display device, which comprises the spliced display panel provided in any of the embodiments of the present application.

[0014] The technical scheme provided by the embodiment of the present application comprises at least one first sub-panel and at least one second sub-panel, the first sub-panel in the spliced display panel is divided into M display areas, the second sub-panel is divided into N display areas, and the M and N display areas are scanned respectively. In the splicing direction of the first sub-panel and the second sub-panel, the M display areas in the first sub-panel are scanned in a first scanning order, the N display areas in the second sub-panel are scanned in a second scanning order, and the scanning directions of at least two display areas on both sides of a splicing seam of the first sub-panel and the second sub-panel are the same; wherein the direction of the first scanning order is opposite to the direction of the second scanning order. The technical scheme provided by the embodiment of the present application controls the directions of the scanning orders of the display areas in the adjacent two sub-panels to be opposite, so that at least two display areas on both sides of the splicing seam in the adjacent two sub-panels are scanned simultaneously, the difference in the number of frames between the two display areas at the splicing seam of the adjacent two sub-panels is reduced, the difference in the light-emitting time of the two is shortened, the phenomenon of image tearing at the splicing seam is improved, and the display effect is improved. Moreover, the display areas on both sides of the splicing seam in the adjacent two sub-panels are scanned simultaneously in the same direction, so that the display areas on both sides of the splicing seam do not need to introduce a forward and reverse scanning mode, and the display effect at the splicing seam is further improved. BRIEF DESCRIPTION OF DRAWINGS

[0015] FIG. 1 is a structural schematic diagram of a spliced display panel according to an embodiment of the present application;

[0016] FIG. 2 is a structural schematic diagram of another spliced display panel according to an embodiment of the present application;

[0017] FIG. 3 is a structural schematic diagram of a first gate drive circuit according to an embodiment of the present application;

[0018] FIG. 4 is a structural schematic diagram of a second gate drive circuit according to an embodiment of the present application;

[0019] FIG. 5 is a structural schematic diagram of another spliced display panel according to an embodiment of the present application;

[0020] FIG. 6 is a driving timing schematic diagram of a first gate drive circuit according to an embodiment of the present application;

[0021] FIG. 7 is a driving timing schematic diagram of a second gate drive circuit according to an embodiment of the present application;

[0022] FIG. 8 is a structural schematic diagram of another spliced display panel according to an embodiment of the present application;

[0023] FIG. 9 is a structural schematic diagram of a pixel circuit according to an embodiment of the present application;

[0024] FIG. 10 is a driving timing schematic diagram of a pixel circuit according to an embodiment of the present application;

[0025] FIG. 11 is a structural schematic diagram of another spliced display panel according to an embodiment of the present application;

[0026] FIG. 12 is a flow chart of a driving method of a spliced display panel according to an embodiment of the present application. DETAILED DESCRIPTION

[0027] The terms "first", "second", and the like in the description and in the claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a particular order or a sequence. It should be understood that the data thus used can be interchanged, where appropriate, so that the embodiments of the present application described herein can be carried out in other than the order shown or described herein. Furthermore, the terms "comprise" and "have", and any variations thereof, are intended to cover non-exclusive inclusion, for example, processes, methods, systems, products, or devices that comprise a series of steps or units not only include those listed in the embodiments of the present application, but also include other processes, methods, systems, products, and devices not clearly listed, or other steps or units inherent to these processes, methods, systems, products, or devices.

[0028] In a spliced display panel, each display panel is turned on at the same time and performs line-by-line scanning, which causes a difference in display period (frame number) at the splicing joint of two adjacent display panels. For example, in two adjacent display panels, the refresh time of the pixel in the last row of the display panel on the top and the pixel in the first row of the display panel on the bottom differ by one display period, so that the light-emitting time of the pixels at the splicing joint of the two display panels differs, thereby causing a "picture tearing" and reducing the display effect. In the related art, the positive and negative scanning modes are usually used for the two adjacent display panels, that is, one display panel uses forward scanning and the other display panel uses reverse scanning, to eliminate the "picture tearing" at the splicing joint. However, the positive and negative scanning mode limits one pixel circuit to have only one gate line, so that the pixel circuit cannot be initialized before the data voltage is written, which is not conducive to improving the display effect.

[0029] The present application provides the following solutions:

[0030] Embodiments of the present application provide a spliced display panel. FIG. 1 is a structural schematic diagram of a spliced display panel according to an embodiment of the present application. Referring to FIG. 1, the spliced display panel provided by the embodiment includes at least one first sub-panel 11 and at least one second sub-panel 12. The first sub-panel 11 includes M display areas, and the second sub-panel 12 includes N display areas. M≥2 and N≥2, and M and N are integers.

[0031] In the splicing direction of the first sub-panel 11 and the second sub-panel 12, the M display areas in the first sub-panel 11 are scanned according to a first scanning order, and the N display areas in the second sub-panel 12 are scanned according to a second scanning order. The scanning directions of at least two display areas on both sides of the splicing joint of the first sub-panel 11 and the second sub-panel 12 are the same. The direction of the first scanning order is opposite to the direction of the second scanning order. One of the two display areas on both sides of the splicing joint is a display area in the first sub-panel 11, and the other is a display area in the second sub-panel 12.

[0032] The splicing direction of the first sub-panel 11 and the second sub-panel 12 refers to the connection arrangement direction when the first sub-panel 11 and the second sub-panel 12 are spliced. For example, if the first sub-panel 11 and the second sub-panel 12 are spliced vertically, the splicing direction is the vertical direction. If the first sub-panel 11 and the second sub-panel 12 are spliced horizontally, the splicing direction is the horizontal direction.

[0033] The first sub-panel 11 is divided into M display areas, and the second sub-panel 12 is divided into N display areas, wherein 1 / M represents a first display area in the first sub-panel 11, 2 / M represents a second display area in the first sub-panel 11, …, M / M represents an Mth display area in the first sub-panel 11, 1 / N represents a first display area in the second sub-panel 12, 2 / N represents a second display area in the second sub-panel 12, …, and N / N represents an Nth display area in the second sub-panel 12. Taking the first sub-panel 11 and the second sub-panel 12 as an example, the Mth display area of the first sub-panel 11 is adjacent to the first display area of the second sub-panel 12, and there is a splicing seam between the two.

[0034] The scanning order of the M display areas in the first sub-panel 11 and the N display areas in the second sub-panel 12 is opposite. Here, the scanning order refers to the opening order of each display area. Exemplarily, the first sub-panel 11 first scans the Mth display area according to a first scanning order, and the second sub-panel 12 first scans the first display area according to a second scanning order, that is, by controlling the first sub-panel 11 and the second sub-panel 12 to scan according to different scanning orders, at least two display areas at the splicing seam of the first sub-panel 11 and the second sub-panel 12 are scanned at the same time, greatly shortening the scanning time difference of the two display areas at the splicing seam of the two adjacent sub-panels, thereby shortening the difference in light-emitting time of the two display areas, thereby being beneficial to improving the image tearing phenomenon at the splicing seam. In addition, since the scanning directions of the two display areas on both sides of the splicing seam of the first sub-panel 11 and the second sub-panel 12 are the same, that is, the Mth display area in the first sub-panel 11 is scanned according to the scanning direction from the first row of pixels to the last row of pixels, and the first display area in the second sub-panel 12 is also scanned according to the scanning direction from the first row of pixels to the last row of pixels, therefore, the display areas on both sides of the splicing seam do not need to introduce a forward and reverse scanning mode, so that the pixels of the corresponding display area do not have the problem of being unable to initialize, which is beneficial to improving the display effect, especially the display effect at the splicing seam.

[0035] The technical scheme provided in the embodiments of the present application comprises at least one first sub-panel 11 and at least one second sub-panel 12, the first sub-panel 11 in the spliced display panel is divided into M display areas, the second sub-panel 12 is divided into N display areas, and the M and N display areas are scanned respectively. In the splicing direction of the first sub-panel 11 and the second sub-panel 12, the M display areas in the first sub-panel 11 are scanned according to a first scanning sequence, the N display areas in the second sub-panel 12 are scanned according to a second scanning sequence, and the scanning directions of the display areas on both sides of the splicing seam of the first sub-panel 11 and the second sub-panel 12 are the same; wherein the direction of the first scanning sequence is opposite to the direction of the second scanning sequence. The technical scheme provided in the embodiments controls the directions of the scanning sequences of the plurality of display areas in the adjacent two sub-panels to be opposite, so that the two display areas on both sides of the splicing seam in the adjacent two sub-panels are scanned simultaneously, the frame number difference between the two display areas at the splicing seam of the adjacent two sub-panels is reduced, the difference in light-emitting time between the two is shortened, which is beneficial to improve the image tearing phenomenon at the splicing seam, and thus the display effect is improved. Moreover, the display areas on both sides of the splicing seam in the adjacent two sub-panels are scanned simultaneously according to the same direction, so that the two display areas on both sides of the splicing seam do not need to introduce a forward and reverse scanning mode, which is beneficial to further improve the display effect at the splicing seam.

[0036] Of course, in other embodiments, the scanning directions of the M display areas in the first sub-panel 11 and the N display areas in the second sub-panel 12 are the same, so that the entire sub-panel does not need to introduce a forward and reverse scanning mode, which can improve the full-screen display effect, and is beneficial to reduce the control difficulty and reduce the design cost.

[0037] Optionally, the number of partitions of the first sub-panel 11 and the number of partitions of the second sub-panel 12 can be equal or not equal, that is, M=N or M≠N, which can be partitioned according to actual conditions. By dividing the first sub-panel 11 and the second sub-panel 12 into the same number of partitions, the control difficulty of the panel is reduced.

[0038] Optionally, in the present embodiment, the first scanning sequence is the opening sequence of the M display areas in the first sub-panel 11, for example, in the first sub-panel 11, the display areas are sequentially opened in the order of the Mth display area, the M-1th display area,..., and the first display area. The second scanning sequence is the opening sequence of the N display areas in the second sub-panel 12, for example, in the second sub-panel 12, the display areas are sequentially opened in the order of the first display area,..., the N-1th display area, and the Nth display area.

[0039] Optionally, the opening sequence of the display area can be controlled by the corresponding gate driving circuit. FIG. 2 is a structural schematic diagram of another spliced display panel provided by an embodiment of the present application. Referring to FIG. 2, on the basis of the above embodiment, the first sub-panel 11 includes a first gate driving circuit, the first gate driving circuit includes M first sub-circuits, each first sub-circuit corresponds to a display area of the first sub-panel 11, the trigger signals corresponding to different first sub-circuits are different, and the first sub-circuit is configured to scan the corresponding display area in response to the trigger signal.

[0040] The second sub-panel 12 includes a second gate driving circuit, the second gate driving circuit includes N second sub-circuits, each second sub-circuit corresponds to a display area of the second sub-panel 12, the trigger signals corresponding to different second sub-circuits are different, and the second sub-circuit is configured to scan the corresponding display area in response to the trigger signal.

[0041] The first gate driving circuit includes M first sub-circuits, which are respectively a first first sub-circuit 21-1, a second first sub-circuit 21-2, and an Mth first sub-circuit 21-M. The first first sub-circuit 21-1 corresponds to a first display area 1 / M in the first sub-panel 11, the second first sub-circuit 21-2 corresponds to a second display area 2 / M in the first sub-panel 11, and the Mth first sub-circuit 21-M corresponds to an Mth display area M / M in the first sub-panel 11. The second gate driving circuit includes N second sub-circuits, which are respectively a first second sub-circuit 22-1, a second second sub-circuit 22-2, and an Nth second sub-circuit 22-N. The first second sub-circuit 22-1 corresponds to a first display area 1 / N in the second sub-panel 12, the second second sub-circuit 22-2 corresponds to a second display area 2 / N in the second sub-panel 12, and the Nth second sub-circuit 22-N corresponds to an Nth display area N / N in the second sub-panel 12. Each sub-circuit corresponds to a trigger signal, and the trigger signals corresponding to different sub-circuits in the same sub-panel are different.

[0042] FIG. 3 is a structural schematic diagram of a first gate drive circuit provided by an embodiment of the present application, and FIG. 4 is a structural schematic diagram of a second gate drive circuit provided by an embodiment of the present application. In combination with FIGS. 2, 3 and 4, the first sub-panel 11 includes a plurality of first gate lines G1, each first sub-circuit includes a plurality of cascaded first shift registers 100, each first shift register 100 is connected with a first gate line G1, and the arrangement direction of the plurality of first gate lines G1 is opposite to the direction of the first scanning order of the M display areas in the first sub-panel 11. The second sub-panel 12 includes a plurality of second gate lines G2, each second sub-circuit includes a plurality of cascaded second shift registers 200, each second shift register 200 is connected with a second gate line G2, and the arrangement direction of the plurality of second gate lines G2 is the same as the direction of the second scanning order of the N display areas in the second sub-panel 12.

[0043] The first shift register 100 and the second shift register 200 each include a first clock signal end SCK1, a second clock signal end SCK2, an input end IN and an output end OUT, wherein the input end IN is configured to access a trigger signal, the first clock signal end SCK1 is connected with a first clock signal line CLK1 and configured to access a first clock signal transmitted on the first clock signal line CLK1, the second clock signal end SCK2 is connected with a second clock signal line CLK2 and configured to access a second clock signal transmitted on the second clock signal line CLK2, and the output end OUT is configured to output a scanning signal.

[0044] The trigger signal corresponding to the first sub-circuit is different from the trigger signal corresponding to the second sub-circuit. The first stage first shift register 100 of the first first sub-circuit 21-1 accesses a first sub-signal STV1-1 of a first trigger signal, the first stage first shift register 100 of the second first sub-circuit 21-2 accesses a second sub-signal STV1-2 of the first trigger signal, and the first stage first shift register 100 of the Mth first sub-circuit 21-M accesses an Mth sub-signal STV1-M of the first trigger signal. The multiple stages of first shift registers 100 output scanning signals row by row according to the sub-signals of the corresponding first trigger signals.

[0045] The first stage second shift register 200 of the first second sub-circuit 22-1 accesses a first sub-signal STV2-1 of a second trigger signal, the first stage second shift register 200 of the second second sub-circuit 22-2 accesses a second sub-signal STV2-2 of the second trigger signal, and the first stage second shift register 200 of the Nth second sub-circuit 22-N accesses an Nth sub-signal STV2-N of the second trigger signal. The multiple stages of second shift registers 200 output scanning signals row by row according to the sub-signals of the corresponding second trigger signals.

[0046] Optionally, the first shift register 100 and the second shift register 200 can adopt the architecture and control mode in the related art. The trigger signals (trigger signal sub-signals) corresponding to the sub-circuits of different segments are used to open the first stage shift register in the corresponding segment sub-circuit in time. The first shift register 100 and the second shift register 200 can have the same architecture to reduce the difficulty of circuit design.

[0047] The first sub-panel 11 and the second sub-panel 12 each include pixel circuits PX arranged in an array, and pixel circuits PX in the same row are connected to the same gate line. For example, in the first sub-panel 11, multiple rows of pixel circuits PX in the M display areas are respectively connected to different first gate lines G1, and the first gate lines G1 are configured to transmit the scan signals output by the corresponding first shift register 100 to the pixel circuits PX in the corresponding row, so that the pixel circuits PX write data voltages, and data refresh of the first sub-panel 11 is realized. In the second sub-panel 12, multiple rows of pixel circuits PX in the N display areas are respectively connected to different second gate lines G2, and the second gate lines G2 are configured to transmit the scan signals output by the corresponding second shift register 200 to the pixel circuits PX in the corresponding row, so that the pixel circuits PX write data voltages, and data refresh of the second sub-panel 12 is realized.

[0048] In this embodiment, the first sub-panel 11 and the second sub-panel 12 are scanned at the same time, the opening sequence of the M first sub-circuits is the same as the first scanning sequence, and the opening sequence of the N second sub-circuits is the same as the second scanning sequence.

[0049] For example, the first display area, the second display area, …, and the Mth display area in the first sub-panel 11 are arranged in the direction of the first scanning sequence in turn, the first display area, the second display area, …, and the Nth display area in the second sub-panel 12 are arranged in the direction of the second scanning sequence in turn, and the Mth display area in the first sub-panel 11 is adjacent to the first display area in the second sub-panel 12.

[0050] The first segment first sub-circuit 21-1 is connected to the first gate line G1 in the first display area in the first sub-panel 11 in correspondence, the second segment first sub-circuit 21-2 is connected to the first gate line G1 in the second display area in the first sub-panel 11 in correspondence, …, and the Mth segment first sub-circuit 21-M is connected to the first gate line G1 in the Mth display area in the first sub-panel in correspondence; in the first sub-panel 11, the first gate drive circuit is configured to open the Mth segment first sub-circuit 21-M, …, the second segment first sub-circuit 21-2, and the first segment first sub-circuit 21-1 in turn, so as to scan the Mth display area, …, the second display area, and the first display area in the first sub-panel 11 in turn.

[0051] The first sub-circuit 22-1 of the first segment is connected to the second gate line G2 in the first display area of the second sub-panel 12, the second sub-circuit 22-2 of the second segment is connected to the second gate line G2 in the second display area of the second sub-panel 12, and the second sub-circuit 22-N of the Nth segment is connected to the second gate line G2 in the Nth display area of the second sub-panel 12. In the second sub-panel 12, the second gate driving circuit is configured to sequentially turn on the first sub-circuit 22-1 of the first segment, the second sub-circuit 22-2 of the second segment, and the second sub-circuit 22-N of the Nth segment, so as to sequentially scan the first display area, the second display area, and the Nth display area of the second sub-panel 12.

[0052] When a segment of the first sub-circuit is turned on in response to the corresponding first trigger signal, the multi-stage first shift register 100 in the segment of the first sub-circuit outputs the scanning signal row by row. At the same time, when a segment of the second sub-circuit is turned on in response to the corresponding second trigger signal, the multi-stage second shift register 200 in the segment of the second sub-circuit outputs the scanning signal row by row.

[0053] Fig. 5 is a structural schematic diagram of another spliced display panel provided by an embodiment of the present application, Fig. 6 is a driving timing schematic diagram of a first gate driving circuit provided by an embodiment of the present application, Fig. 7 is a driving timing schematic diagram of a second gate driving circuit provided by an embodiment of the present application, and the timing shown in Figs. 6 and 7 can be applicable to the spliced display panel shown in Fig. 5. Referring to Figs. 5-7, taking M=N=4 as an example, the starting time of the effective level of the fourth sub-signal STV1-4 of the first trigger signal is located before the starting time of the effective level of the third sub-signal STV1-3 of the first trigger signal, the starting time of the effective level of the third sub-signal STV1-3 of the first trigger signal is located before the starting time of the effective level of the second sub-signal STV1-2 of the first trigger signal, the starting time of the effective level of the second sub-signal STV1-2 of the first trigger signal is located before the starting time of the effective level of the first sub-signal STV1-1 of the first trigger signal, and the ending time of the effective level of each sub-signal does not overlap with the starting time of the effective level of the next sub-signal. Therefore, the fourth segment of the first sub-circuit 21-4, the third segment of the first sub-circuit 21-3, the second segment of the first sub-circuit 21-2, and the first segment of the first sub-circuit 21-1 are sequentially turned on. The effective level refers to the conduction level of the sub-signal.

[0054] The starting moment of the active level of the first sub-signal STV2-1 of the second trigger signal is before the starting moment of the active level of the second sub-signal STV2-2 of the second trigger signal, the starting moment of the active level of the second sub-signal STV2-2 of the second trigger signal is before the starting moment of the active level of the third sub-signal STV2-3 of the second trigger signal, the starting moment of the active level of the third sub-signal STV2-3 of the second trigger signal is before the starting moment of the active level of the fourth sub-signal STV2-4 of the second trigger signal, and the ending moment of the active level of each sub-signal does not overlap with the starting moment of the active level of the next sub-signal. Therefore, the first segment second sub-circuit 22-1, the second segment second sub-circuit 22-2, the third segment second sub-circuit 22-3, and the fourth segment second sub-circuit 22-4 are sequentially turned on.

[0055] Optionally, the first clock signal transmitted on the first clock signal line CLK1 in the first sub-panel 11 and the second sub-panel 12 is the same, and the second clock signal transmitted on the second clock signal line CLK2 is the same. The starting moment of the active level of the first sub-signal STV2-1 of the second trigger signal is the same as the starting moment of the active level of the first sub-signal STV1-1 of the first trigger signal, so that the first sub-panel 11 and the second sub-panel 12 are simultaneously turned on for scanning.

[0056] FIG. 8 is a structural schematic diagram of another spliced display panel provided by the embodiment of the present application. Referring to FIG. 8, on the basis of the above-mentioned multiple technical solutions, optionally, the first sub-panel 11 includes a plurality of first data lines DL1, the extension direction of the plurality of first data lines DL1 is opposite to the direction of the first scanning order of the M display areas in the first sub-panel 11, and the arrangement direction of the plurality of first data lines DL1 intersects the direction of the first scanning order of the M display areas in the first sub-panel 11. For example, the scanning direction of the M display areas in the first sub-panel 11 is the second direction Y (the direction of the first scanning order is the opposite direction Y’ of the second direction Y), the extension direction of the plurality of first data lines DL1 is the second direction Y, and the arrangement direction of the plurality of first data lines DL1 is the first direction X. The first direction X intersects the second direction Y, and both the first direction X and the second direction Y are perpendicular to the thickness direction of the spliced display panel. The first data line DL1 is configured to transmit a data voltage to a pixel circuit PX in the first sub-panel 11.

[0057] The second sub-panel 12 includes a plurality of second data lines DL2, the extension direction of the plurality of second data lines DL2 is the same as the direction of the second scanning sequence of the N display areas in the second sub-panel 12, and the arrangement direction of the plurality of second data lines DL2 intersects with the direction of the second scanning sequence of the N display areas in the second sub-panel 12. For example, the scanning direction of the N display areas in the second sub-panel 12 is the second direction Y (the direction of the second scanning sequence is also the second direction Y), the extension direction of the plurality of second data lines DL2 is the second direction Y, and the arrangement direction of the plurality of second data lines DL2 is the first direction X. The second data line DL2 is configured to transmit a data voltage to the pixel circuit PX in the second sub-panel 12.

[0058] The data refresh direction of the M display areas in the first sub-panel 11 is the same as the direction of the first scanning sequence, and the data refresh direction of the N display areas in the second sub-panel 12 is the same as the direction of the second scanning sequence.

[0059] The data refresh direction refers to the direction in which the plurality of display areas write a data voltage. Since the M display areas in the first sub-panel 11 are scanned in turn according to the first scanning sequence, the first scanning sequence is opposite to the scanning direction, when the Mth display area of the first sub-panel 11 is scanned, the data voltage transmitted on the first data line DL1 is the data voltage corresponding to the Mth display area, rather than the data voltage corresponding to the first display area, thereby preventing the display image from being misaligned. The N display areas in the second sub-panel 12 are scanned in turn according to the second scanning sequence, the second scanning sequence is the same as the scanning direction, so the data voltage transmitted on the second data line DL2 can be normally transmitted according to the data voltage corresponding to the first display area to the Nth display area.

[0060] The technical scheme provided in the embodiment controls the data refresh direction to cooperate with the direction of the scanning sequence of the plurality of display areas, which can reduce the frame number difference between the two display areas at the splicing joint of the adjacent two sub-panels, thereby shortening the difference in light-emitting time, which is beneficial to improve the image tearing phenomenon at the splicing joint, and further improve the display effect. The display areas at the splicing joint of the adjacent two sub-panels are scanned in the same direction at the same time, so there is no need to introduce a forward and reverse scanning mode, which is beneficial to further improve the display effect.

[0061] FIG. 9 is a structural schematic diagram of a pixel circuit provided in an embodiment of the present application. Referring to FIG. 9, on the basis of the above-mentioned embodiments, the pixel circuit PX is optionally connected with the light-emitting element 30, and the pixel circuit PX is configured to drive the light-emitting element 30 to emit light in a display period.

[0062] The pixel circuit PX comprises a time control module 10 and a current control module 20, the current control module 20 and the light emitting element 30 are connected between the first power supply line L1 and the second power supply line L2, the current control module 20 is configured to drive the light emitting element 30 to emit light according to the first data voltage Vdata_I in the light emitting stage; the time control module 10 is configured to output a time control signal to the control end of the current control module 20 according to the Vdata_t and the sweep signal SWEEP, so as to control the light emitting time of the light emitting element 30.

[0063] The first power supply line L1 is configured to provide a first power supply voltage VDDA, the second power supply line L2 is configured to provide a second power supply voltage VSS, and the current control module 20 can drive the light emitting element 30 to emit light in the light emitting stage in the display period. The size of the driving current is related to the size of the first data voltage Vdata_I accessed by the current control module 20. The time control module 10 outputs a time control signal according to the second data voltage Vdata_t and the sweep signal SWEEP, so as to control the potential of the control end of the current control module 20, thereby controlling the light emitting time of the light emitting element 30.

[0064] Optionally, in this embodiment, taking M=N as an example, one display period comprises N data writing stages and at least N light emitting stages, the data writing stages and the light emitting stages are arranged alternately, in the first sub-panel 11 or the second sub-panel 12, each data writing stage corresponds to data refreshing of one display area, and different data writing stages correspond to data refreshing of different display areas. In the data writing stage, the second data voltage Vdata_t is written to the time control module, and the first data voltage Vdata_I is written to the current control module.

[0065] Exemplarily, in the first sub-panel 11, since the scanning order of the M display areas in the first sub-panel 11 is the reverse direction Y' of the second direction Y, that is, scanning from bottom to top of the first sub-panel 11, in the first data writing stage, the N(M)th display area of the first sub-panel and the first display area of the second sub-panel are refreshed, and then the full screen emits light (the data voltage of the display area which is not refreshed is the data voltage of the last display period); in the second data writing stage, the N-1(M-1)th display area of the first sub-panel and the second display area of the second sub-panel are refreshed, and then the full screen emits light; …… in the Nth data writing stage, the first display area of the first sub-panel and the Nth display area of the second sub-panel are refreshed, and then the full screen emits light.

[0066] For the scheme of setting multiple light-emitting stages in a display period, a blank stage is usually set between adjacent light-emitting stages. In this embodiment, at least part of the blank stage is multiplexed as a data writing stage, so as to write data voltage to the corresponding display area in the blank stage. FIG. 10 is a schematic diagram of a driving timing of a pixel circuit provided in this embodiment. In combination with FIG. 9 and FIG. 10, in the related art, in the data writing stage, full-screen data writing is performed, and then light emission is performed. A blank stage is set between multiple light-emitting stages. The time of the blank stage is equal to the time of the data writing stage, i.e., T1=T3. In this embodiment, by partitioning the full screen, each data writing stage only writes data voltage to one display area, i.e., 1 / N screen writing is performed. Compared with full-screen writing, the time of 1 / N screen writing is smaller, in other words, T1’<T1, so that the light-emitting time of the light-emitting stage can be increased, i.e., T2’>T2. Wherein, T1’=T3’.

[0067] In this embodiment, by setting the 1 / N screen data writing stage in the blank stage, the 1 / N screen writing mode is adopted. Compared with the full-screen writing mode of writing data voltage in the related art, the technical scheme provided in this embodiment can effectively increase the light-emitting time duty cycle. In the light-emitting stage of a display period, the sweep signal SWEEP includes multiple sub-signals, each sub-signal corresponds to a light-emitting stage, and each sub-signal of the sweep signal SWEEP repeats the corresponding driving process, so as to increase the slope of the sweep signal SWEEP and improve the switching speed of the light-emitting element 30 between bright state and dark state, which is beneficial to improve the display problem caused by the slow switching speed of the light-emitting element 30 from bright state to dark state in low gray scale, and is beneficial to improve the display effect. The sweep signal SWEEP can be a sawtooth wave, a triangular wave or other ramp signal.

[0068] The sweep signal SWEEP is a global signal, and the light-emitting time of the light-emitting element 30 in at least N light-emitting stages is equal, i.e., the light-emitting time of multiple light-emitting stages in the same display period (1 frame) is the same. Therefore, the number of light-emitting stages is at least equal to the number of partitions of the sub-panel, so as to ensure that each display area can write corresponding data voltage.

[0069] The technical scheme provided by the embodiment is that a plurality of sub-panels are partitioned, and partitioned data voltage is written, the data refresh direction is controlled to match the direction of the scanning sequence of the plurality of display areas, the display areas at the splicing joint of the two adjacent sub-panels are simultaneously scanned, the frame number difference between the two display areas at the splicing joint of the two adjacent sub-panels is reduced, the difference in the light-emitting time of the two is shortened, the phenomenon of image tearing at the splicing joint is improved, the light-emitting duty ratio is increased, the light-emitting time of the light-emitting element 30 is increased, and the display areas at the splicing joint of the two adjacent sub-panels are simultaneously scanned in the same direction, so that the forward and reverse scanning mode does not need to be introduced, and the display effect is further improved.

[0070] Alternatively, the light-emitting element 30 can be a Micro-LED or a Mini-LED. In other embodiments, the light-emitting element 30 can also be an organic light-emitting diode (OLED) or a light-emitting diode (LED).

[0071] The above plurality of embodiments are described by taking one first sub-panel 11 and one second sub-panel 12 as an example. Alternatively, the splicing display panel provided by the embodiment can also be spliced by a plurality of first sub-panels 11 and a plurality of second sub-panels 12. FIG. 11 is a structural schematic diagram of another splicing display panel provided by the embodiment of the application. Based on the above plurality of embodiments, referring to FIG. 11, the first sub-panels 11 and the second sub-panels 12 are alternately arranged along the second direction Y, the plurality of first sub-panels 11 are sequentially arranged along the first direction X, the plurality of second sub-panels 12 are sequentially arranged along the first direction X, the first direction X and the second direction Y intersect, and both are perpendicular to the thickness direction of the splicing display panel.

[0072] The scanning mode and the data refresh mode of the first sub-panel 11 and the second sub-panel 12 can refer to the related description in the above embodiments, which will not be described here.

[0073] Of course, in other embodiments, the first sub-panels 11 and the second sub-panels 12 can also be alternately arranged along the first direction X. At this time, the architecture layout of the first sub-panels 11 and the second sub-panels 12 can be appropriately adjusted, but the scanning mode and the data refresh mode are the same as the technical scheme in the above plurality of embodiments.

[0074] Alternatively, the embodiment of the application further provides a driving method of a splicing display panel. The driving method can be applied to the splicing display panel provided by any embodiment of the application. FIG. 12 is a flow chart of a driving method of a splicing display panel provided by the embodiment of the application. Referring to FIG. 12, the driving method comprises the following steps.

[0075] S110, control the M display areas in the first sub-panel to scan according to a first scanning sequence.

[0076] S120, control the N display areas in the second sub-panel to scan according to a second scanning sequence; wherein, the scanning directions of the two display areas at least on both sides of the splicing seam of the first sub-panel and the second sub-panel are same, the direction of the first scanning sequence is opposite to the direction of the second scanning sequence, one of the two display areas on both sides of the splicing seam is a display area in the first sub-panel, and the other is a display area in the second sub-panel.

[0077] The technical scheme provided by the embodiments of the present application, the splicing display panel includes at least one first sub-panel and at least one second sub-panel, by dividing the first sub-panel in the splicing display panel into M display areas, and dividing the second sub-panel into N display areas, respectively partitioning and scanning the M and N display areas. In the splicing direction of the first sub-panel and the second sub-panel, the M display areas in the first sub-panel are scanned according to a first scanning sequence, and the N display areas in the second sub-panel are scanned according to a second scanning sequence, and the scanning directions of the display areas at least on both sides of the splicing seam of the first sub-panel and the second sub-panel are same; wherein, the direction of the first scanning sequence is opposite to the direction of the second scanning sequence. The technical scheme provided by the present embodiment controls the directions of the scanning sequences of the multiple display areas in the adjacent two sub-panels to be opposite, so that the two display areas on both sides of the splicing seam in the adjacent two sub-panels are scanned at the same time, which can reduce the frame number difference between the two display areas at the splicing seam of the adjacent two sub-panels, thereby shortening the difference in light-emitting time, which is conducive to improving the image tearing phenomenon at the splicing seam, and further improving the display effect. And the display areas at least on both sides of the splicing seam of the adjacent two sub-panels are scanned at the same time according to the same direction, so that the two display areas at least on both sides of the splicing seam do not need to introduce a forward and reverse scanning mode, which is conducive to further improving the display effect at the splicing seam.

[0078] Optionally, the embodiments of the present application also provide a display device, which includes the splicing display panel provided by any of the embodiments of the present application. The display device may, for example, be a television, a tablet, and a large-size electronic device such as a vehicle display and a conference display.

[0079] It should be understood that the steps shown above can be reordered, added, or deleted. For example, the steps described in the present application can be executed in parallel, sequentially, or in different orders, as long as the desired results of the technical scheme of the present application can be achieved, which is not limited herein.

Claims

1. A tiled display panel, comprising at least one first sub-panel and at least one second sub-panel, the first sub-panel comprising M display areas, and the second sub-panel comprising N display areas; wherein, M≥2, N≥2, and M and N are integers; In a splicing direction of the first sub-panel and the second sub-panel, the M display areas in the first sub-panel are scanned in a first scanning order, and the N display areas in the second sub-panel are scanned in a second scanning order, and the scanning directions of the two display areas on both sides of the splicing joint of the first sub-panel and the second sub-panel are the same; wherein the direction of the first scanning order is opposite to the direction of the second scanning order, one of the two display areas on both sides of the splicing joint is one display area in the first sub-panel, and the other is one display area in the second sub-panel. 2.The tiled display panel of claim 1, wherein, The scanning directions of the M display areas in the first sub-panel are the same, and the scanning directions of the N display areas in the second sub-panel are the same. 3.The tiled display panel of claim 1, wherein, The first scanning order is the opening order of the M display areas in the first sub-panel, and the second scanning order is the opening order of the N display areas in the second sub-panel.

4. The tiled display panel of claim 3, wherein, In the first sub-panel, the M display areas are sequentially opened in the order of the Mth display area, the M-1th display area,..., and the first display area; in the second sub-panel, the N display areas are sequentially opened in the order of the first display area,..., the N-1th display area, and the Nth display area. 5.The tiled display panel of claim 1, wherein, The first sub-panel includes a first gate drive circuit, the first gate drive circuit includes M first sub-circuits, each first sub-circuit corresponds to a display area of the first sub-panel, the trigger signals corresponding to different first sub-circuits are different, and the first sub-circuit is configured to scan the corresponding display area in response to the trigger signal; The second sub-panel includes a second gate drive circuit, the second gate drive circuit includes N second sub-circuits, each second sub-circuit corresponds to a display area of the second sub-panel, the trigger signals corresponding to different second sub-circuits are different, and the first sub-circuit is configured to scan the corresponding display area in response to the trigger signal.

6. The tiled display panel of claim 5, wherein, The opening order of the M first sub-circuits is the same as the first scanning order, and the opening order of the N second sub-circuits is the same as the second scanning order.

7. The tiled display panel of claim 5, wherein, The trigger signal corresponding to the first sub-circuit is different from the trigger signal corresponding to the second sub-circuit.

8. The tiled display panel of claim 5, wherein, The first sub-panel and the second sub-panel are scanned simultaneously.

9. The tiled display panel of claim 5, wherein, The first sub-panel includes a plurality of first gate lines, each first sub-circuit includes a plurality of cascaded first shift registers, each first shift register is connected with a first gate line, and the arrangement direction of the plurality of first gate lines is opposite to the direction of the first scanning order of the M display areas in the first sub-panel; The second sub-panel comprises a plurality of second gate lines, each of the second sub-circuits comprises a plurality of cascaded second shift registers, each of the second shift registers is connected with one of the second gate lines, and the arrangement direction of the plurality of second gate lines is the same as the direction of the second scanning sequence of the N display areas in the second sub-panel.

10. The tiled display panel of claim 9, wherein, The first display area, the second display area, and the Mth display area in the first sub-panel are arranged in the reverse direction of the first scanning sequence in sequence, the first display area, the second display area, and the Nth display area in the second sub-panel are arranged in the direction of the second scanning sequence in sequence, and the Mth display area in the first sub-panel is adjacent to the first display area in the second sub-panel; The first sub-circuit is connected with the first gate line in the first display area in the first sub-panel in correspondence, the second sub-circuit is connected with the first gate line in the second display area in the first sub-panel in correspondence, and the Mth sub-circuit is connected with the first gate line in the Mth display area in the first sub-panel in correspondence; in the first sub-panel, the first gate drive circuit is configured to sequentially turn on the Mth sub-circuit, the second sub-circuit, and the first sub-circuit to sequentially scan the Mth display area, the second display area, and the first display area in the first sub-panel; The first sub-circuit is connected with the first gate line in the first display area in the first sub-panel in correspondence, the second sub-circuit is connected with the first gate line in the second display area in the first sub-panel in correspondence, and the Mth sub-circuit is connected with the first gate line in the Mth display area in the first sub-panel in correspondence; in the first sub-panel, the first gate drive circuit is configured to sequentially turn on the Mth sub-circuit, the second sub-circuit, and the first sub-circuit to sequentially scan the Mth display area, the second display area, and the first display area in the first sub-panel; 11. The tiled display panel of claim 1, wherein, The first sub-panel comprises a plurality of first data lines, the extension direction of the plurality of first data lines is opposite to the direction of the first scanning sequence of the M display areas in the first sub-panel, the arrangement direction of the plurality of first data lines intersects with the direction of the first scanning sequence of the M display areas in the first sub-panel, and the first data line is configured to transmit a data voltage to a pixel circuit in the first sub-panel. The second sub-panel comprises a plurality of second data lines, the extension direction of the plurality of second data lines is the same as the direction of the second scanning sequence of the N display areas in the second sub-panel, the arrangement direction of the plurality of second data lines intersects with the direction of the second scanning sequence of the N display areas in the second sub-panel, and the second data line is configured to transmit a data voltage to a pixel circuit in the second sub-panel.

12. The tiled display panel of claim 11, wherein, Data refresh directions of the M display areas in the first sub-panel are the same as a direction of the first scanning sequence, and data refresh directions of the N display areas in the second sub-panel are the same as a direction of the second scanning sequence.

13. The tiled display panel of claim 11, wherein, The first sub-panels and the second sub-panels are arranged alternately along a second direction, the first sub-panels are arranged sequentially along a first direction, the second sub-panels are arranged sequentially along the first direction, the first direction intersects with the second direction, and both are perpendicular to a thickness direction of the tiled display panel.

14. The tiled display panel of claim 13, wherein, The direction of the first scanning sequence is a reverse direction of the second direction, and the direction of the second scanning sequence is the second direction.

15. The tiled display panel of claim 1, wherein, The first sub-panels and the second sub-panels each include arrayed pixel circuits and light emitting elements, the pixel circuits are connected to the light emitting elements correspondingly, and the pixel circuits are configured to drive the light emitting elements to emit light in a display period. M = N, one display period includes N data writing stages and at least N light emitting stages, the data writing stages and the light emitting stages are arranged alternately, in the first sub-panel or the second sub-panel, each data writing stage corresponds to data refresh of one display area, and different data writing stages correspond to data refresh of different display areas.

16. The tiled display panel of claim 15, wherein, The pixel circuit includes a time control module and a current control module, the current control module and the light emitting element are connected between a first power supply line and a second power supply line, and the current control module is configured to drive the light emitting element to emit light according to a first data voltage in the light emitting stage. The time control module is configured to output a time control signal to a control end of the current control module according to a second data voltage and a sweep signal, so as to control light emitting time of the light emitting element.

17. The tiled display panel of any of claims 15 or 16, wherein, Blank stages are arranged between adjacent light emitting stages, and at least part of the blank stages are multiplexed as the data writing stages, so as to write data voltages to corresponding display areas in the blank stages.

18. The tiled display panel of claim 17, wherein, Light emitting time of the light emitting element in the at least N light emitting stages is equal.

19. A driving method of a tiled display panel, the tiled display panel comprising at least one first sub-panel and at least one second sub-panel, the first sub-panel comprising M display areas, the second sub-panel comprising N display areas; wherein, M ≥ 2, N ≥ 2, and M and N are integers; The driving method of the tiled display panel includes: controlling M display areas in the first sub-panel to scan according to a first scanning sequence; controlling N display areas in the second sub-panel to scan according to a second scanning sequence; At least scanning directions of two display areas on both sides of a splicing seam of the first sub-panel and the second sub-panel are the same, a direction of the first scanning sequence is opposite to a direction of the second scanning sequence, one of the two display areas on both sides of the splicing seam is one display area in the first sub-panel, and the other is one display area in the second sub-panel.

20. A display device including the tiled display panel of any one of claims 1-18.

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