Analog-to-digital conversion circuit, chip, and electronic device

Abstract

The present application provides an analog-to-digital conversion circuit, a chip, and an electronic device. The analog-to-digital conversion circuit comprises: a plurality of stages of analog-to-digital conversion modules, wherein each stage of analog-to-digital conversion module is used for outputting a conversion code value and a residual voltage on the basis of an input voltage; at least one inter-stage amplification module, wherein the inter-stage amplification module is used for amplifying the residual voltage outputted by a previous-stage analog-to-digital conversion module to obtain a residual amplified voltage, and the residual amplified voltage is used as the input voltage of a next-stage analog-to-digital conversion module; and an inter-stage adjustment module, wherein the inter-stage adjustment module is used for monitoring the magnitude of the input voltage of at least one stage of analog-to-digital conversion module. In the present application, when the detected input voltage of an analog-to-digital conversion module exceeds a set threshold, the inter-stage adjustment module can change the amplification factor of at least one inter-stage amplification module to ensure that the voltage outputted by the inter-stage amplification module returns to within the set threshold, thereby finally avoiding the phenomenon that the voltage outputted by the inter-stage amplification module goes beyond an optimal working range thereof.

Description

Analog-to-digital converter circuits, chips and electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202410795081.2, filed on June 19, 2024, entitled “Analog-to-Digital Conversion Circuit, Chip and Electronic Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of integrated circuit technology, specifically to an analog-to-digital conversion circuit, a chip, and an electronic device. Background Technology

[0003] A pipelined analog-to-digital converter (ADC) or pipelined successive approximation ADC (SAR ADC) is a type of ADC that implements pipelined analog-to-digital conversion. It consists of multiple stages of ADCs, with an interstage amplifier between adjacent stages. This interstage amplifier amplifies the quantization margin of the previous stage before outputting it to the next stage for further quantization. After all stages of ADCs have completed the analog-to-digital conversion of the same measured analog voltage signal, the code values ​​output from all stages are concatenated to obtain the digital signal corresponding to the measured analog voltage signal.

[0004] However, when the measured analog voltage signal exceeds the full scale, the residual voltage output of the first-stage analog-to-digital converter may increase, leading to abnormal saturation of the interstage amplifier output. This will reduce the accuracy of the interstage amplifier output voltage and ultimately cause a sharp drop in the overall analog-to-digital conversion accuracy. Technical solutions

[0005] In view of the above problems, embodiments of this application provide an analog-to-digital conversion circuit, a chip, and an electronic device to solve the above technical problems.

[0006] In a first aspect, embodiments of this application provide an analog-to-digital conversion circuit, including:

[0007] A multi-stage analog-to-digital converter module, each stage of which outputs a conversion code value and residual voltage based on the input voltage;

[0008] At least one interstage amplification module is provided, which is used to amplify the residual voltage output by the previous stage analog-to-digital converter module to obtain a residual amplified voltage, and the residual amplified voltage is used as the input voltage of the next stage analog-to-digital converter module.

[0009] Interstage adjustment module, used to monitor the input voltage of at least one analog-to-digital converter module;

[0010] When the input voltage of the monitored analog-to-digital converter exceeds a set threshold, the interstage adjustment module changes the amplification factor of at least one interstage amplification module.

[0011] Secondly, embodiments of this application also provide a chip including the analog-to-digital conversion circuit described above.

[0012] Thirdly, embodiments of this application also provide an electronic device, including the aforementioned chip or analog-to-digital conversion circuit. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 shows a schematic diagram of a pipelined analog-to-digital converter in related technologies.

[0015] Figure 2 shows a schematic diagram of a pipelined successive approximation analog-to-digital converter in related technologies.

[0016] Figure 3 shows a schematic diagram of a successive approximation analog-to-digital converter in related technologies.

[0017] Figure 4 shows a schematic diagram of an analog-to-digital conversion circuit in an embodiment of this application.

[0018] Figure 5 shows another schematic diagram of the analog-to-digital conversion circuit in an embodiment of this application.

[0019] Figure 6 shows another schematic diagram of the analog-to-digital conversion circuit in an embodiment of this application.

[0020] Figure 7 shows another schematic diagram of the analog-to-digital conversion circuit in an embodiment of this application.

[0021] Figure 8 shows another schematic diagram of the analog-to-digital conversion circuit in an embodiment of this application.

[0022] Figure 9 shows another schematic diagram of the analog-to-digital conversion circuit in an embodiment of this application.

[0023] Figure 10 shows another schematic diagram of the analog-to-digital conversion circuit in an embodiment of this application.

[0024] Figure 11 shows another schematic diagram of the analog-to-digital conversion circuit in an embodiment of this application.

[0025] Figure 12 shows another schematic diagram of the analog-to-digital conversion circuit in an embodiment of this application.

[0026] Figure 13 shows another schematic diagram of the analog-to-digital conversion circuit in an embodiment of this application.

[0027] Figure 14 shows another schematic diagram of the analog-to-digital conversion circuit in an embodiment of this application.

[0028] Figure 15 shows another schematic diagram of the analog-to-digital conversion circuit in an embodiment of this application.

[0029] Figure 16 shows another schematic diagram of the analog-to-digital conversion circuit in an embodiment of this application.

[0030] Figure 17 shows another schematic diagram of the analog-to-digital conversion circuit in an embodiment of this application.

[0031] Figure 18 shows another schematic diagram of the analog-to-digital conversion circuit in an embodiment of this application.

[0032] Figure 19 shows another schematic diagram of the analog-to-digital conversion circuit in an embodiment of this application.

[0033] Figure 20 shows another schematic diagram of the analog-to-digital conversion circuit in an embodiment of this application.

[0034] Among them, 10 is an analog-to-digital converter module, 11 is a first sub-analog-to-digital converter, 12 is a first sub-digital-to-analog converter, 101 is a second sub-digital-to-analog converter, 102 is a second comparator, 103 is a successive approximation logic module, 20 is an inter-stage amplification module, 30 is an inter-stage adjustment module, and 40 is a reference voltage module.

[0035] Reference voltage Vref, sampling capacitor Cs, first operational amplifier OP1, first capacitor C1, first switch S1, first resistor R1, second switch S2, first reference voltage V1, second reference voltage V2, first comparator COMP11, second comparator COMP2.

[0036] Implementation methods of this application

[0037] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0038] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0039] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0040] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0041] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0042] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0043] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0044] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after it are in an "or" relationship.

[0045] Currently, pipelined analog-to-digital converters (ADCs) or pipelined successive approximation ADCs are a type of ADC that implements pipelined ADC conversion. Due to their high conversion speed and accuracy, they are increasingly widely used. Referring to Figure 1, which illustrates a schematic diagram of a pipelined ADC in related technologies, the pipelined ADC includes multiple stages of ADCs and digital-to-analog converters (DACs). Each stage of the ADC and the DACs have an amplifier between them. The DAC outputs an analog voltage corresponding to the conversion code value of the ADC. Then, an adder subtracts the input voltage from the analog voltage to obtain the residual voltage. This residual voltage is then amplified and input to the next stage for ADC conversion, and so on. Once all stages of the ADC have obtained their corresponding conversion code values ​​D1, D2, and DN, the code value conversion module concatenates the conversion code values ​​output from all stages to obtain the digital signal corresponding to the input voltage Vin.

[0046] Referring again to Figure 2, which illustrates a schematic diagram of a pipelined successive approximation analog-to-digital converter (ADC) in the related art, the pipelined successive approximation ADC includes multiple stages of SAR ADCs (Successive Approximation Register ADCs), with an amplifier positioned between adjacent SAR ADCs. Compared to conventional pipelined ADCs, because SAR ADCs can directly output code values ​​and also output residual voltages, the pipelined successive approximation ADC eliminates the need for digital-to-analog converters and adders, thus reducing the area of ​​the analog-to-digital conversion circuit.

[0047] For example, referring to Figure 3, which illustrates a schematic diagram of a successive approximation analog-to-digital converter (ADC) in related technologies, the SAR ADC mainly includes a digital-to-analog converter (DAC), a comparator, and a successive approximation logic module. During the sampling phase of the successive approximation DAC, switch SW is closed, and the lower plates of sampling capacitors C1, C2…Cn are connected to the analog input voltage Vin, while the upper plates are connected to the common-mode voltage Vcm through switch SW. After sampling is fully established, Vdac = Vcm, and the voltage difference across sampling capacitors C1, C2…Cn is Vcm - Vin. During the conversion phase, switch SW is synchronously opened, and the lower plates of sampling capacitors C1, C2…Cn are no longer connected to the analog input voltage. Instead, the reference voltage Vref or ground gnd is selected based on the control of the successive approximation logic module. At this time, the voltage at the inverting input of the comparator is the common-mode voltage Vcm, and the voltage Vdac at the non-inverting input of the comparator is: Vdac = Vref * Ceq / Ctotal - VIN + Vcm

[0048] Where Ceq is the capacitance value of the sampling capacitor connected to the reference voltage Vref at the lower plate, and Ctotal is the total capacitance of the entire sampling capacitor array C1, C2...Cn.

[0049] During the comparison process, the Vcm term, representing the common-mode voltage, is eliminated during the transcoding comparison. The comparator essentially determines the sign of Vref*Ceq / Ctotal-VIN. Based on the comparator's output, the logic module determines the output code value for the next comparison cycle, controlling the size of the sampling capacitor Ceq. This causes the voltage Vdac at the non-inverting input of the comparator to successively approach the common-mode voltage Vcm until the analog output voltage Vdac is approximately equal to the common-mode voltage Vcm. Finally, the logic module obtains the digital signal converted from the analog input voltage VIN. Simultaneously, since Vref*Ceq / Ctotal-VIN represents the difference between the analog voltage corresponding to the digital signal and the analog input voltage VIN, it can be directly amplified as a residual voltage and input to the next stage of the SAR ADC.

[0050] The working principle of a pipelined analog-to-digital converter (ADC) or a pipelined successive approximation ADC is similar. Taking a two-stage pipelined ADC, with each stage being 4-bit and having an input range of 8V, a measured voltage of 6.3V, and an amplifier gain of 8 as an example, the first-stage ADC converts the measured voltage of 6.3V into a binary value of 1100 (corresponding to the decimal value 12 = [6.3 / (8 / 2)]). 4 The first-stage digital-to-analog converter outputs an analog voltage of 6V based on the binary code value of 1100. The residual voltage input to the first-stage amplifier after passing through the adder is 0.3V. Therefore, the first-stage amplifier, with an amplification factor of 8, outputs a voltage of 2.4V. The second-stage analog-to-digital converter converts this 2.4V voltage to a binary code value of 0100 (corresponding to the decimal code value 4 = [2.4 / (8 / 2)]). 4 The final code value output by the code conversion module is 1100100, which corresponds to the decimal value of 100. Therefore, the measured voltage value corresponding to the code value output by the code conversion module is 100*8 / 2. 7 =6.25V.

[0051] It can be seen that the binary code value obtained by a single first-stage digital-to-analog converter is 1100, corresponding to a 6V voltage, while the binary code value obtained by a two-stage pipelined analog-to-digital converter is 1100100, corresponding to a 6.25V voltage. Therefore, the more stages a pipelined analog-to-digital converter or a pipelined successive approximation analog-to-digital converter has, the higher the analog-to-digital conversion accuracy. Furthermore, during the measurement process, after the previous stage of the analog-to-digital converter completes the conversion of the previous input signal, it can directly start converting the next input signal. This allows multi-stage analog-to-digital converters to complete the pipelined analog-to-digital conversion process. Therefore, pipelined analog-to-digital converters or pipelined successive approximation analog-to-digital converters have both high accuracy and high speed.

[0052] However, when the measured analog voltage signal exceeds its full scale, the residual voltage output by the first-stage analog-to-digital converter (ADC) increases. For example, in the above case, if the voltage to be measured is changed to 9V, the first-stage ADC obtains a binary code value of 11110 based on the 9V voltage. The first-stage digital-to-analog converter (DAC) outputs an analog voltage of 8V based on the binary code value of 11110. The residual voltage input to the first-stage amplifier after passing through the adder is 1V. At this time, the voltage amplified and output by the first-stage amplifier is 8V. If the optimal voltage amplification range of the first-stage amplifier is 2V to 6V, it will cause the first-stage amplifier to malfunction. Furthermore, the interstage amplifier will require tens of additional cycles to recover to normal operation, which severely affects its conversion accuracy during the period of interstage amplifier malfunction.

[0053] Therefore, this application provides an analog-to-digital conversion circuit, a chip, and a voltage device, which are described in detail below.

[0054] First, referring to Figure 4, Figure 4 shows a schematic diagram of an analog-to-digital conversion circuit in an embodiment of this application, wherein the analog-to-digital conversion circuit includes a multi-stage analog-to-digital conversion module 10, at least one interstage amplification module 20, and at least one interstage adjustment module 30.

[0055] Specifically, each stage of the analog-to-digital converter (ADC) 10 outputs conversion code values ​​(D1, D2, D3...DN) and residual voltages (Vs1, Vs2, Vs3...) based on the input voltage. The residual voltage is equal to the difference between the analog voltage corresponding to the conversion code value and the input voltage. For example, if the input voltage Vin connected to the first-stage ADC 10 is 5.2V, and the conversion code value D1 of the first-stage ADC 10 is 1010, corresponding to an analog voltage of 5V, then the residual voltage Vs1 is 0.2V. As another example, if the input voltage Vb1 connected to the second-stage ADC 10 is 1.6V, and the conversion code value D2 of the second-stage ADC 10 is 0011, corresponding to an analog voltage of 1.5V, then the residual voltage Vs2 is 0.1V.

[0056] In some embodiments of this application, the analog-to-digital conversion module 10 can simultaneously output the conversion code value and the residual voltage. For example, each stage of the analog-to-digital conversion module 10 may include a progressive analog-to-digital converter to directly utilize the progressive analog-to-digital converter to output the conversion code value and the residual voltage.

[0057] In some embodiments of this application, each stage of analog-to-digital conversion module 10 can output a conversion code value and a residual voltage respectively. For example, each stage of analog-to-digital conversion module 10 includes an analog-to-digital converter and a digital-to-analog converter, so as to use the analog-to-digital converter to convert the input voltage into a code value, and use the digital-to-analog converter to output the corresponding analog voltage according to the code value, thereby using the analog voltage and the input voltage to obtain the residual voltage through an adder.

[0058] For example, the analog-to-digital converter (ADC) can be, but is not limited to, a Sigma-Delta ADC, a Ramp-compare ADC, a Flash ADC, etc. The digital-to-analog converter (DAC) can be, but is not limited to, a resistive DAC, a voltage-mode DAC, or a current-mode DAC, etc.

[0059] The interstage amplification module 20 amplifies the residual voltage output from the previous stage analog-to-digital converter module 10 to obtain a residual amplified voltage, which is then used as the input voltage for the next stage analog-to-digital converter module 10. For example, referring to Figure 4, the first-stage analog-to-digital converter module 10 receives the voltage to be measured Vin as its input voltage and outputs a residual voltage Vs1 to the first-stage interstage amplification module 20. After amplification, the first-stage interstage amplification module 20 outputs a residual amplified voltage Vb1. The second-stage analog-to-digital converter module 10 uses the residual amplified voltage Vb1 as its input voltage and outputs a residual voltage Vs2 to the second-stage interstage amplification module 20. After amplification, the second-stage interstage amplification module 20 outputs a residual amplified voltage Vb2. The third-stage analog-to-digital converter module 10 uses the residual amplified voltage Vb2 as its input voltage, and so on.

[0060] If the measured voltage Vin input to the first-stage analog-to-digital converter (ADC) module 10 is 6.8V, the analog voltage corresponding to the D1 conversion code value 1101 output by the first-stage ADC module 10 is 6.5V, and the residual voltage Vs1 output by the first-stage ADC module 10 is 0.3V, then if the amplification factor of the first-stage interstage amplifier module 20 is 8, a residual amplified voltage Vb1 of 2.4V can be obtained, and this 2.4V residual amplified voltage Vb1 can be used as the input voltage of the second-stage ADC module 10. For example, if the second-stage ADC module 10 outputs the analog voltage corresponding to the D2 conversion code value 0100 for the 2.4V residual amplified voltage Vb1, and the residual voltage Vs2 output by the second-stage ADC module 10 is 0.4V, then if the amplification factor of the second-stage interstage amplifier module 20 is 8, a residual amplified voltage Vb2 of 3.2V can be obtained, and this 3.2V residual amplified voltage can be used as the input voltage of the third-stage ADC module 10.

[0061] For example, the interstage amplification module 20 may include, but is not limited to, a differential amplifier circuit, a common-emitter amplifier circuit, or a common-base amplifier circuit.

[0062] Understandably, there can be one or more interstage amplification modules 20. For example, when the multi-stage analog-to-digital converter module 10 has two stages, one interstage amplification module 20 can be set between the first-stage analog-to-digital converter module 10 and the second-stage analog-to-digital converter module 10. When the multi-stage analog-to-digital converter module 10 has more than two stages, there can be multiple interstage amplification modules 20 so that one interstage amplification module 20 can be set between any two adjacent analog-to-digital converter modules 10.

[0063] The interstage adjustment module 30 is used to monitor the input voltage of at least one analog-to-digital converter module 10 to determine whether the input voltage exceeds a set threshold. When the monitored input voltage of the analog-to-digital converter module 10 exceeds the set threshold, the interstage adjustment module 30 can change the amplification factor of at least one interstage amplification module 20 to prevent the output voltage of the interstage amplification module 20 from exceeding its optimal operating range.

[0064] For example, taking Figure 4 as an example, the interstage adjustment module 30 monitors the input voltage of the second-stage analog-to-digital converter module 10 and can control the amplification factor of the first-stage interstage amplifier module 20. Taking a set threshold of 2V to 6V as an example, when the input voltage of the second-stage analog-to-digital converter module 10 is 7V, the interstage adjustment module 30 can control the amplification factor of the interstage amplifier module 20 to decrease from 8 to 4, so that the residual amplified voltage Vb1 output by the interstage amplifier module 20 is reduced to 3.5V, thereby making the output voltage of the interstage amplifier module 20 return to the set threshold, and ultimately avoiding the phenomenon that the output voltage of the interstage amplifier module 20 exceeds its optimal operating range.

[0065] For example, the interstage adjustment module 30 may include one or more voltage comparison circuits such as comparators, threshold comparators or hysteresis comparators, to monitor the input voltage of the analog-to-digital conversion module 10 and output a control signal that changes the amplification factor of the interstage amplification module 20.

[0066] In this embodiment, the interstage adjustment module 30 monitors the input voltage of at least one analog-to-digital converter module 10. When the monitored input voltage of the analog-to-digital converter module 10 exceeds a set threshold, it indicates that the residual amplified voltage output by the interstage adjustment module exceeds the set threshold. Therefore, the interstage adjustment module 30 can change the amplification factor of at least one interstage amplification module 20, thereby ensuring that the output voltage of the interstage amplification module 20 returns to within the set threshold, and ultimately avoiding the phenomenon that the output voltage of the interstage amplification module 20 exceeds its optimal operating range.

[0067] In some embodiments of this application, when the input voltage of the (N+1)th analog-to-digital converter module 10 exceeds a set threshold, the interstage adjustment module 30 changes the amplification factor of the Nth interstage amplification module 20; where N is an integer greater than or equal to 1. For example, referring to FIG4, the interstage adjustment module 30 can monitor the input voltage of the second-stage analog-to-digital converter module 10 and the input voltage of the third-stage analog-to-digital converter module 10. When the input voltage of the second-stage analog-to-digital converter module 10 is detected to exceed the set threshold, the interstage adjustment module 30 changes the amplification factor of the first-stage interstage amplification module 20 to prevent the output voltage of the first-stage interstage amplification module 20 from exceeding its optimal operating range. Similarly, when the input voltage of the third-stage analog-to-digital converter module 10 is detected to exceed the set threshold, the interstage adjustment module 30 changes the amplification factor of the first-stage interstage amplification module 20 to prevent the output voltage of the first-stage interstage amplification module 20 from exceeding its optimal operating range.

[0068] Understandably, the interstage adjustment module 30 can also monitor the input voltage of the Nth stage analog-to-digital converter module 10 and control the amplification factor of the Nth stage interstage amplification module 20. For example, referring to FIG5, FIG5 shows another schematic diagram of the analog-to-digital converter circuit in the embodiment of this application. The interstage adjustment module 30 can also monitor the input voltage of the first stage analog-to-digital converter module 10 and control the amplification factor of the interstage amplification module 20 between the first stage analog-to-digital converter module 10 and the second stage analog-to-digital converter module 10.

[0069] In some embodiments of this application, when the input voltage of the (N+1)th stage analog-to-digital converter (ADC) module 10 exceeds a set threshold, the inter-stage adjustment module 30 also changes the input range of the (N+1)th stage ADC module 10 to ensure that the overall resolution of the ADC circuit remains unchanged. For example, referring to FIG6, FIG6 shows another schematic diagram of the ADC circuit in an embodiment of this application, wherein the inter-stage adjustment module 30 can monitor the input voltage of the second stage ADC module 10 and the input voltage of the third stage ADC module 10. When the input voltage of the second stage ADC module 10 is detected to exceed the set threshold, the inter-stage adjustment module 30 can not only change the amplification factor of the first stage inter-stage amplification module 20, but also change the input range of the second stage ADC module 10; when the input voltage of the third stage ADC module 10 is detected to exceed the set threshold, the inter-stage adjustment module 30 can not only change the amplification factor of the second stage inter-stage amplification module 20, but also change the input range of the third stage ADC module 10.

[0070] It should be noted that when the input voltage of the (N+1)th stage analog-to-digital converter (ADC) 10 exceeds the set threshold, if only the amplification factor of the Nth stage interstage amplifier 20 is changed without changing the input range of the (N+1)th stage ADC 10, it may cause abnormal conversion of other normal input voltages. For example, assuming the input range of each ADC 10 is 8V and the amplification factor of each interstage amplifier 20 is 8, when the amplification factor of the Nth stage interstage amplifier 20 is changed to 4 and the residual voltage output by the Nth stage ADC 10 is 0.4V, the (N+1)th stage ADC 10 measures a voltage of 4*0.4 = 1.6V and obtains a conversion code value of 0011. However, under normal circumstances, the (N+1)th stage ADC 10 measures 8*0.4 = 3.2V and obtains a conversion code value of 0110. After changing the amplification factor of the Nth stage interstage amplifier 20, the normal signal exhibits an abnormal conversion code value at the (N+1)th stage ADC 10.

[0071] In the above embodiment, if the input range of the N+1th stage analog-to-digital converter module 10 is changed to 4V, then for the interstage amplifier module 20, whose amplification factor is changed to 4 and outputs a voltage of 1.6V, the conversion code value of the N+1th stage analog-to-digital converter module 10 is 0110. This is the same as the conversion code of the N+1th stage analog-to-digital converter module 10 under normal circumstances, thus ensuring that the overall resolution of the analog-to-digital converter circuit remains unchanged and avoiding the phenomenon of abnormal analog-to-digital conversion caused by only changing the amplification factor of the interstage amplifier module 20.

[0072] In some embodiments of this application, when the input voltage of the (N+1)th stage analog-to-digital converter module 10 is greater than a first preset value, the interstage adjustment module 30 reduces the amplification factor of the Nth stage interstage amplifier module 20 and reduces the input range of the (N+1)th stage analog-to-digital converter module 10. For example, taking Figure 6 as an example, the first preset value is 6V. When the input voltage of the second stage analog-to-digital converter module 10 is 7.2V, the first interstage adjustment module 30 can reduce the amplification factor of the first stage interstage amplifier module 20 to half of the original amplification factor and reduce the input range of the second stage analog-to-digital converter module 10 to half of the original input range. Ultimately, this reduces the residual amplified voltage output by the first stage interstage amplifier module 20 to 3.6V, thereby preventing the output voltage of the first stage interstage amplifier module 20 from being too high.

[0073] In some embodiments of this application, when the input voltage of the (N+1)th stage analog-to-digital converter module 10 is less than a second preset value, the interstage adjustment module 30 increases the amplification factor of the Nth stage interstage amplifier module 20 and increases the input range of the (N+1)th stage analog-to-digital converter module 10. For example, taking Figure 6 as an example, the second preset value is 2V. When the input voltage of the third stage analog-to-digital converter module 10 is 1.8V, the interstage adjustment module 30 can increase the amplification factor of the second stage interstage amplifier module 20 by twice the original amplification factor and increase the input range of the third stage analog-to-digital converter module 10 by twice the original input range, ultimately changing the output voltage of the second stage interstage amplifier module 20 to 3.6V, thereby preventing the output voltage of the first stage interstage amplifier module 20 from being too small.

[0074] It should be noted that the preset threshold, first preset value, and second preset value in the above embodiments are only illustrative examples. Those skilled in the art can make adaptive settings according to actual needs, and this application does not impose any specific limitations.

[0075] In some embodiments of this application, referring to FIG7, FIG7 shows another schematic diagram of the analog-to-digital conversion circuit in an embodiment of this application, wherein the interstage adjustment module 30 is used to monitor the magnitude of the input voltage of the second-stage analog-to-digital conversion module 10; when the input voltage of the second-stage analog-to-digital conversion module 10 exceeds a set threshold, the interstage adjustment module 30 changes the amplification coefficient of the first-stage interstage amplification module 20 and changes the input range of the second-stage analog-to-digital conversion module 10.

[0076] It should be noted that when the voltage to be measured exceeds the measurement range of the analog-to-digital converter circuit, it usually causes the first-stage interstage amplifier module 20 to malfunction, which may then lead to malfunctions in subsequent interstage amplifier modules 20 (such as the second-stage interstage amplifier module 20). Therefore, the interstage adjustment module 30 directly monitors the input voltage of the second-stage analog-to-digital converter module 10 and changes the amplification factor of the first-stage interstage amplifier module 20 and the input range of the second-stage analog-to-digital converter module 10. This not only prevents malfunctions in the first-stage interstage amplifier module 20 but also prevents malfunctions in subsequent interstage amplifier modules 20.

[0077] Those skilled in the art will understand that the implementation of the interstage adjustment module 30 is not limited thereto. For example, referring to FIG8, FIG8 shows another schematic diagram of the analog-to-digital conversion circuit in the embodiment of the present application. The interstage adjustment module 30 can also monitor the input voltage of the first-stage analog-to-digital conversion module 10 and control the amplification factor of the first-stage interstage amplification module 20 and the input range of the second-stage analog-to-digital conversion module 10.

[0078] In some embodiments of this application, referring to FIG9, FIG9 shows another schematic diagram of the analog-to-digital conversion circuit in an embodiment of this application, wherein the interstage amplification module 20 includes a first operational amplifier OP1, a plurality of first capacitors C1 and a plurality of first switches S1; the first capacitors C1 and the first switches S1 correspond one-to-one, the first plate of the first capacitors C1 is connected to the input terminal of the first operational amplifier OP1; the second plate of the first capacitors C1 is connected to the first terminal of the first switches S1, and the second terminal of the first switches S1 is connected to the output terminal of the first operational amplifier OP1.

[0079] It should be noted that the first operational amplifier OP1, multiple first capacitors C1, and multiple first switches S1 form a capacitor-type voltage amplifier circuit. The more first switches S1 are closed, the larger the total capacitance of the multiple first capacitors C1, which in turn increases the gain coefficient of the interstage amplifier module 20. Conversely, the fewer first switches S1 are closed, the smaller the total capacitance of the multiple first capacitors C1, which in turn decreases the gain coefficient of the interstage amplifier module 20. Therefore, when the input voltage of the monitored analog-to-digital converter module 10 exceeds the set threshold, the interstage adjustment module 30 can change the amplification coefficient of the interstage amplifier module 20 by controlling the number of first switches S1 that are closed.

[0080] Understandably, the implementation of the interstage amplification module 20 is not limited to this. For example, the interstage amplification module 20 can also adopt a boost circuit or a buck circuit, and the amplification factor of the interstage amplification module 20 can be changed by controlling the size of the electronic components in the boost circuit or buck circuit; or, for example, the first capacitor C1 can be replaced with a resistor to form a resistive voltage amplifier circuit.

[0081] In some embodiments of this application, such as an embodiment where the interstage adjustment module 30 can change the input range of the analog-to-digital converter module 10, referring to FIG10, FIG10 shows another schematic diagram of the analog-to-digital converter circuit in an embodiment of this application, wherein the analog-to-digital converter module 10 is connected to a reference voltage Vref. When the input voltage of the N+1th stage analog-to-digital converter module 10 exceeds a set threshold, the interstage adjustment module 30 changes the magnitude of the reference voltage Vref connected to the N+1th stage analog-to-digital converter module 10 to change the input range of the N+1th stage analog-to-digital converter module 10.

[0082] It should be noted that the reference voltage Vref is the reference voltage for the digital signal output by the analog-to-digital converter (ADC) module 10. Changing the value of the reference voltage Vref changes the input range of the ADC module 10. For example, taking an ADC module 10 that includes a successive approximation ADC module as an example, when the input voltage of the (N+1)th stage ADC module 10 is greater than a first preset value, the inter-stage adjustment module 30 reduces the reference voltage Vref. According to the formula for the output analog voltage of a successive approximation ADC: Vdac = Vref * Ceq / Ctotal - Vin + Vcm, the above process actually reduces the parameter Vref in the formula, thus reducing the input range of the ADC module 10. Therefore, when the input voltage of the (N+1)th stage ADC module 10 exceeds a set threshold, the inter-stage adjustment module 30 can change the value of the reference voltage Vref connected to the (N+1)th stage ADC module 10, thereby changing the input range of the (N+1)th stage ADC module 10 to ensure that the resolution of the ADC circuit remains unchanged.

[0083] As an example, referring to FIG11, FIG11 shows another schematic diagram of the analog-to-digital conversion circuit in an embodiment of the present application, wherein the analog-to-digital conversion circuit further includes a reference voltage module 40, the reference voltage module 40 including a plurality of first resistors R1 connected in series and a plurality of second switches S2; the first resistor R1 located at the beginning of the series is connected to a first reference voltage V1, and the first resistor R1 located at the end of the series is connected to a second reference voltage V2; the second switches S2 correspond one-to-one with the first resistors R1, and the first end of each second switch S2 is connected to the first resistor R1; the second ends of the plurality of second switches S2 are connected to each other, and the second ends of the plurality of second switches S2 are connected to the analog-to-digital conversion module 10 to provide a reference voltage Vref to the analog-to-digital conversion module 10.

[0084] Specifically, at most one of the multiple second switches S2 is closed. When the closed second switch S2 corresponds to different first resistors R1, the reference voltage Vref output by the reference voltage module 40 is different. In other words, by controlling the closure of different second switches S2 through the principle of voltage division by series resistors, the magnitude of the reference voltage Vref can be changed, ultimately achieving the purpose of changing the input range of the corresponding analog-to-digital converter module 10.

[0085] It is understood that Figure 11 is only an exemplary embodiment of changing the magnitude of the reference voltage Vref, and the embodiments of changing the magnitude of the reference voltage Vref are not limited thereto. For example, boost voltage and / or buck voltage can also be used to change the magnitude of the reference voltage Vref.

[0086] In some embodiments of this application, such as an embodiment where the interstage adjustment module 30 can change the input range of the analog-to-digital converter module 10, referring to FIG12, FIG12 shows another schematic diagram of the analog-to-digital converter circuit in an embodiment of this application, wherein the analog-to-digital converter module 10 includes a plurality of sampling capacitors Cs; when the input voltage of the N+1th stage analog-to-digital converter module 10 exceeds a set threshold, the interstage adjustment module 30 changes the number of working samples Cs of the N+1th stage analog-to-digital converter module 10 to change the input range of the N+1th stage analog-to-digital converter module 10.

[0087] For example, taking the N+1 stage analog-to-digital converter module 10, which includes a successive approximation analog-to-digital converter, if under normal circumstances all B sampling capacitors Cs work in the sampling and conversion stages of the successive approximation analog-to-digital converter to sample and convert voltage, when the input voltage of the N+1 stage analog-to-digital converter module 10 exceeds a set threshold, the inter-stage adjustment module 30 makes the successive approximation analog-to-digital converter work in the sampling and conversion stages with A sampling capacitors Cs to sample and convert voltage. A is greater than B. According to the formula for the output analog voltage of the successive approximation analog-to-digital converter: Vdac=Vref*Ceq / Ctotal-VIN+Vcm, the above process actually increases the parameter Ctotal, the total capacitance value of the sampling capacitors Cs in the formula, thus reducing the input range of the analog-to-digital converter module 10.

[0088] For example, under normal circumstances, all A sampling capacitors Cs of the successive approximation analog-to-digital converter (ADC) are working to sample and convert voltage during the sampling and conversion phases. When the input voltage of the N+1 stage ADC module 10 exceeds a set threshold, the inter-stage adjustment module 30 causes the successive approximation ADC to work with B sampling capacitors Cs during the sampling and conversion phases to sample and convert voltage. Since A is greater than B, according to the formula for the output analog voltage of the successive approximation ADC: Vdac=Vref*Ceq / Ctotal-VIN+Vcm, the above process actually reduces the parameter Ctotal, the total capacitance value of the sampling capacitors Cs in the formula, thus increasing the input range of the ADC module 10.

[0089] Understandably, the implementation of changing the input range of the analog-to-digital converter module 10 is not limited to this. For example, referring to FIG13, FIG13 shows another schematic diagram of the analog-to-digital converter circuit in an embodiment of the present application. The interstage adjustment module 30 can also simultaneously change the magnitude of the reference voltage Vref input to the analog-to-digital converter module 10 and the number of working samples Cs.

[0090] In some embodiments of this application, the analog-to-digital converter circuit can be a pipelined analog-to-digital converter. For example, referring to FIG14, FIG14 shows another schematic diagram of the analog-to-digital converter circuit in an embodiment of this application, wherein at least one stage of analog-to-digital converter module 10 includes a first sub-analog-to-digital converter 11 and a first sub-digital-to-analog converter 12; the first sub-analog-to-digital converter 11 converts the input voltage into a conversion code value; the first sub-digital-to-analog converter 12 is used to output a corresponding conversion voltage according to the conversion code value, so as to obtain the residual voltage according to the input voltage and the conversion voltage.

[0091] In some embodiments of this application, such as for embodiments where the analog-to-digital conversion circuit is a pipelined analog-to-digital converter, the first sub-analog-to-digital converter 11 includes at least one first comparator COMP1, through which analog voltage can be converted into digital signal.

[0092] For example, referring to Figure 15, which shows another schematic diagram of the analog-to-digital converter circuit in an embodiment of this application, each first sub-analog-to-digital converter 11 includes a first comparator COMP1, and each first sub-digital-to-analog converter 12 includes a switch Sx. The non-inverting input terminal of the first comparator COMP1 is connected to the input voltage, and the inverting input terminal of the first comparator COMP1 is connected to the reference voltage Vref. One end of the switch Sx is connected to the reference voltage Vref, and its output terminal is connected to the adder. The control terminal of the switch Sx is connected to the output terminal of the first comparator COMP1. Taking the reference voltage Vref0 in Figure 15 as 3.3V as an example, when the input voltage Vin is 3.5V, the output terminal of the first comparator COMP1 outputs the code value 1 and controls the switch Sx to close. The adder outputs a residual voltage of 0.2V based on the input voltage Vin and the reference voltage Vref0, so that the interstage amplification module 20 can amplify the 0.2V residual voltage.

[0093] In some embodiments of this application, at least one stage of analog-to-digital conversion module 10 includes a successive approximation analog-to-digital converter, that is, the analog-to-digital conversion circuit of this application can be a pipelined successive approximation analog-to-digital converter.

[0094] In some embodiments of this application, such as embodiments where the analog-to-digital conversion circuit is a pipelined successive approximation analog-to-digital converter, referring to FIG16, FIG16 shows another schematic diagram of the analog-to-digital conversion circuit in an embodiment of this application, wherein the successive approximation analog-to-digital converter includes a second sub-digital-to-analog converter 101, a second comparator 102, and a successive approximation logic module 103; the second sub-digital-to-analog converter 101 is used to output an analog voltage signal according to the digital signal output by the successive approximation logic module 103; the second comparator 102 is used to compare the analog voltage signal with the input signal and output a control signal; the successive approximation logic module 103 outputs a digital signal successively approximatingly according to the control signal.

[0095] As an example, Figure 16 illustrates the embodiment process of this application. When the input voltage of the (N+1)th stage analog-to-digital converter module 10 exceeds a set threshold, the interstage adjustment module 30 changes the gain coefficient of the Nth stage interstage amplifier module 20 by controlling the number of closures of the first switch S1, thereby preventing the output voltage of the Nth stage interstage amplifier module 20 from exceeding its optimal operating range. Simultaneously, the interstage adjustment module 30 changes the magnitude of the reference voltage Vref connected to the N+1th stage analog-to-digital converter module 10 by controlling the change in the closure of the second switch S2, ultimately altering the input range of the N+1th stage analog-to-digital converter module 10 to ensure that the overall resolution of the analog-to-digital converter circuit remains unchanged.

[0096] As another example, referring to FIG17 (the upper-level analog-to-digital converter module 10 is not shown), FIG17 shows another schematic diagram of the analog-to-digital converter circuit in an embodiment of the present application. The second sub-digital-to-analog converter 101 includes a switch array S11 to S1n and a sampling capacitor array C11 to C1n. Taking FIG17 as an example, the embodiment process of the present application is illustrated. When the input voltage of the N+1 stage analog-to-digital converter module 10 exceeds a set threshold, the inter-stage adjustment module 30 changes the gain coefficient of the Nth stage inter-stage amplification module 20 by controlling the number of closed first switches S1, thereby avoiding the phenomenon that the output voltage of the Nth stage inter-stage amplification module 20 exceeds the optimal operating range. At the same time, the inter-stage adjustment module 30 changes the input range of the N+1 stage analog-to-digital converter module 10 by controlling the number of working sampling capacitors C11 to C1n in the second sub-digital-to-analog converter 101, so as to ensure that the overall resolution of the analog-to-digital converter circuit remains unchanged.

[0097] It should be noted that Figures 16 and 17 are illustrated using single-ended signals as examples, but are not limited thereto. Those skilled in the art can modify Figures 16 and 17 to a fully differential circuit structure according to actual needs.

[0098] For example, referring to Figure 18, which shows another schematic diagram of the analog-to-digital converter circuit in an embodiment of this application, the second sub-digital-to-analog converter 101 includes switch arrays S11-S1n, sampling capacitor arrays C11-C1n, switch arrays S21-S2n, and sampling capacitor arrays C21-C2n. The first operational amplifier OP1 of the interstage amplification module 20 is a fully differential amplifier, and the interstage amplification module 20 includes two sets of first capacitors C1 and two sets of first switches S1. One set of switches controls the total capacitance value of one set of first capacitors C1, and the other set of switches controls the other set of first capacitors C1. The reference voltage module 40 includes two sets of second switches S2. One set of second switches S2 controls the output reference voltage Vrefp, and the other set of second switches S2 controls the output reference voltage Vrefn, so that the reference voltages Vrefp and Vrefn can be input into the fully differential second sub-digital-to-analog converter 101.

[0099] Using Figure 18 as an example, the embodiment process of this application is illustrated. When the input voltage of the (N+1)th stage analog-to-digital converter module 10 exceeds a set threshold, the interstage adjustment module 30 changes the gain coefficient of the Nth stage interstage amplifier module 20 by controlling the number of closures of the first switch S1, thereby preventing the output voltage of the Nth stage interstage amplifier module 20 from exceeding the optimal operating range. Simultaneously, the interstage adjustment module 30 changes the reference voltage Vrefp by controlling a set of second switches S2 and another set of second switches S2 to change the reference voltage Vrefn, thereby changing the magnitude of the reference voltage Vref connected to the (N+1)th stage analog-to-digital converter module 10, ultimately changing the input range of the (N+1)th stage analog-to-digital converter module 10 to ensure that the overall resolution of the analog-to-digital converter circuit remains unchanged.

[0100] For example, referring to Figure 19, which shows another schematic diagram of the analog-to-digital conversion circuit in an embodiment of this application, unlike Figure 18, the interstage adjustment module 30 can control the number of working samples in the sampling capacitor arrays C11-C1n and C21-C2n in the second sub-digital-to-analog converter 101. Using Figure 18 as an example, the embodiment process of this application is illustrated as follows: when the input voltage of the (N+1)th stage analog-to-digital converter module 10 exceeds a set threshold, the interstage adjustment module 30 changes the gain coefficient of the Nth stage interstage amplifier module 20 by controlling the number of closed first switches S1, thereby preventing the output voltage of the Nth stage interstage amplifier module 20 from exceeding its optimal operating range. Simultaneously, the interstage adjustment module 30, by controlling the number of working capacitor arrays C11-C1n and C21-C2n, ultimately changes the input range of the (N+1)th stage analog-to-digital converter module 10 to ensure that the overall resolution of the analog-to-digital conversion circuit remains unchanged.

[0101] It is worth noting that the above description of the analog-to-digital conversion circuit is intended to clearly illustrate the implementation and verification process of this application. Those skilled in the art can also make equivalent modifications under the guidance of this application. For example, referring to Figure 20, Figure 20 shows another schematic diagram of the analog-to-digital conversion circuit in the embodiment of this application. While controlling the number of working capacitor arrays C11 to C1n and sampling capacitor arrays C21 to C2n, the reference voltage Vrefp and reference voltage Vrefn are changed to change the input range of the analog-to-digital conversion module 10.

[0102] This application also provides a chip that includes the analog-to-digital conversion circuit described above. A chip (Integrated Circuit, IC) is also called a chip, and this chip can be, but is not limited to, a System on Chip (SOC) chip or a System in Package (SIP) chip. Since the chip in this application embodiment has the analog-to-digital conversion circuit described above, it possesses all the beneficial effects of the aforementioned analog-to-digital conversion circuit, which will not be elaborated further here.

[0103] This application also provides an electronic device, which includes a device body and a chip as described above disposed within the device body. The electronic device may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car center console screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.

[0104] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An analog-to-digital converter circuit, characterized in that, include: A multi-stage analog-to-digital converter module, wherein each stage of the analog-to-digital converter module is used to output a conversion code value and a residual voltage based on the input voltage; At least one interstage amplification module is provided, wherein the interstage amplification module is used to amplify the residual voltage output by the previous stage analog-to-digital conversion module to obtain a residual amplified voltage, and the residual amplified voltage is used as the input voltage of the next stage analog-to-digital conversion module; An interstage adjustment module is used to monitor the magnitude of the input voltage of at least one stage of the analog-to-digital conversion module; When the input voltage of the monitored analog-to-digital conversion module exceeds a set threshold, the interstage adjustment module changes the amplification factor of at least one of the interstage amplification modules.

2. The analog-to-digital converter circuit as described in claim 1, characterized in that, When the input voltage of the (N+1)th analog-to-digital conversion module exceeds a set threshold, the interstage adjustment module changes the amplification factor of the Nth stage interstage amplification module; Where N is an integer greater than or equal to 1.

3. The analog-to-digital converter circuit as described in claim 2, characterized in that, When the input voltage of the analog-to-digital converter module of the (N+1)th stage exceeds a set threshold, the inter-stage adjustment module also changes the input range of the analog-to-digital converter module of the (N+1)th stage.

4. The analog-to-digital converter circuit as described in claim 3, characterized in that, When the input voltage of the N+1th stage analog-to-digital converter module is greater than the first preset value, the inter-stage adjustment module reduces the amplification factor of the Nth stage inter-stage amplification module and reduces the input range of the N+1th stage analog-to-digital converter module. When the input voltage of the N+1 stage analog-to-digital converter module is less than the second preset value, the inter-stage adjustment module increases the amplification factor of the Nth stage inter-stage amplification module and increases the input range of the N+1 stage analog-to-digital converter module.

5. The analog-to-digital converter circuit as described in claim 3, characterized in that, The interstage adjustment module is used to monitor the magnitude of the input voltage of the second-stage analog-to-digital conversion module; When the input voltage of the second-stage analog-to-digital converter exceeds a set threshold, the inter-stage adjustment module changes the amplification factor of the first-stage inter-stage amplification module and changes the input range of the second-stage analog-to-digital converter.

6. The analog-to-digital converter circuit as described in claim 3, characterized in that, The analog-to-digital conversion module is connected to a reference voltage; When the input voltage of the N+1 stage analog-to-digital converter module exceeds a set threshold, the inter-stage adjustment module changes the magnitude of the reference voltage connected to the N+1 stage analog-to-digital converter module to change the input range of the N+1 stage analog-to-digital converter module.

7. The analog-to-digital converter circuit as described in claim 6, characterized in that, The analog-to-digital conversion circuit also includes a reference voltage module, which includes multiple first resistors connected in series and multiple second switches. The first resistor at the beginning of the series connection is connected to a first reference voltage, and the first resistor at the end of the series connection is connected to a second reference voltage. The second switch corresponds one-to-one with the first resistor, and the first terminal of each second switch is connected to the first resistor. The second terminals of the plurality of second switches are interconnected, and the second terminals of the plurality of second switches are connected to the analog-to-digital conversion module to provide a reference voltage to the analog-to-digital conversion module.

8. The analog-to-digital converter circuit as described in claim 3, characterized in that, The analog-to-digital conversion module includes multiple sampling capacitors; When the input voltage of the N+1 stage analog-to-digital converter module exceeds a set threshold, the inter-stage adjustment module changes the number of working samples of the N+1 stage analog-to-digital converter module to change the input range of the N+1 stage analog-to-digital converter module.

9. The analog-to-digital converter circuit as described in claim 1, characterized in that, The interstage amplification module includes a first operational amplifier, multiple first capacitors, and multiple first switches; The first capacitor corresponds one-to-one with the first switch, and the first plate of the first capacitor is connected to the input terminal of the first operational amplifier. The second plate of the first capacitor is connected to the first terminal of the first switch, and the second terminal of the first switch is connected to the output terminal of the first operational amplifier. When the input voltage of the monitored analog-to-digital converter module exceeds a set threshold, the interstage adjustment module changes the number of times the first switch is closed.

10. The analog-to-digital converter circuit as described in claim 1, characterized in that, At least one level of the analog-to-digital conversion module includes a first sub-analog-to-digital converter and a first sub-digital-to-analog converter; The first sub-analog-to-digital converter converts the input voltage into the conversion code value; The first sub-digital-to-analog converter is used to output the corresponding conversion voltage according to the conversion code value.

11. The analog-to-digital converter circuit as described in claim 10, characterized in that, The first sub-analog-to-digital converter includes at least one first comparator.

12. The analog-to-digital converter circuit as described in claim 1, characterized in that, At least one of the analog-to-digital conversion modules includes a progressive approximation analog-to-digital converter.

13. The analog-to-digital converter circuit as described in claim 12, characterized in that, The successive approximation analog-to-digital converter includes a second sub-digital-to-analog converter, a second comparator, and a successive approximation logic module; The second sub-digital-to-analog converter is used to output an analog voltage signal based on the digital signal output by the successive approximation logic module; The second comparator is used to compare the analog voltage signal with the input signal and output a control signal; The successive approximation logic module outputs the digital signal in successive approximations according to the control signal.

14. A chip, characterized in that, Includes the analog-to-digital conversion circuit as described in any one of claims 1 to 13.

15. An electronic device, characterized in that, Includes the chip as described in claim 14.

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