Processor, instruction processing apparatus, electronic device and instruction processing method

Abstract

A processor, an instruction processing apparatus, an electronic device and an instruction processing method. The processor comprises: an instruction fetching unit, an instruction parsing unit, a DQ instruction execution unit and a CA instruction execution unit, wherein the instruction fetching unit, the instruction parsing unit and a first target unit form a first instruction pipeline; the instruction fetching unit, the instruction parsing unit and a second target unit form a second instruction pipeline; when a target condition is met, the first instruction pipeline and the second instruction pipeline are executed in parallel; and the first target unit comprises the DQ instruction execution unit, and the second target unit comprises the CA instruction execution unit.

Description

Processor, instruction processing device, electronic device and instruction processing method Cross-reference to related applications

[0001] This application claims priority to the Chinese Patent Application No. 202410782583.1, filed on June 18, 2024, and entitled "Processor, Instruction Processing Device, Electronic Device and Instruction Processing Method", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application belongs to the field of computers, and particularly relates to a processor, an instruction processing device, an electronic device and an instruction processing method. BACKGROUND

[0003] To meet the requirement of data storage, flash memory technology emerges as the times require. With the increasing demand of flash memory grain interface bandwidth, the data transmission rate of flash memory interface is continuously improved, while the command / address transmission rate of flash memory interface does not change. In the traditional flash memory interface transmission protocol (ONFi or Toggle), the command / address and data are transmitted on the same group of transmission lines. With the increase of data transmission rate, the command / address transmission time proportion increases, which becomes the bottleneck of flash memory grain interface bandwidth. In order to solve the problem of flash memory interface bandwidth improvement, a new flash memory grain protocol, such as separate command data (Separate Command Address, SCA) protocol, separates the transmission of command / address and data and puts them on two different transmission buses. The command / address is transmitted on the command and address (Command and Address, CA) bus, and the data is transmitted on the data (DATA, also called DQ) bus, which realizes the transmission of command / address on the CA bus while the transmission of data on the DQ bus.

[0004] In the related art, in the process of processing the instructions of the flash memory grain chip, the SCA protocol is usually implemented by a dedicated state machine, which has the problem of low efficiency of processing instructions. SUMMARY

[0005] Embodiments of the present application provide a processor, an instruction processing device, an electronic device and an instruction processing method, which can solve the problem of low efficiency of processing instructions caused by the implementation of SCA protocol by a state machine in the related art.

[0006] In a first aspect, embodiments of the present application provide a processor, comprising:

[0007] An instruction fetching unit is configured to fetch a target instruction and send the target instruction to an instruction parsing unit, the target instruction being an instruction adapted to a flash memory grain chip.

[0008] The instruction parsing unit is configured to determine an instruction type of the target instruction by performing parsing processing on the target instruction, the instruction type including a command / address (CA) operation instruction or a data (DQ) operation instruction.

[0009] The DQ instruction execution unit is configured to send target data to a flash memory chip through a DQ bus in a case where the instruction type is the DQ operation instruction.

[0010] The CA instruction execution unit is configured to send CA information or CA-related configuration information to the flash memory chip through a CA bus in a case where the instruction type is the CA operation instruction.

[0011] The instruction fetching unit, the instruction parsing unit, and the first target unit form a first instruction pipeline, and the instruction fetching unit, the instruction parsing unit, and the second target unit form a second instruction pipeline.

[0012] The first instruction pipeline and the second instruction pipeline are executed in parallel in a case where a target condition is met, the first target unit including the DQ instruction execution unit, and the second target unit including the CA instruction execution unit.

[0013] In a second aspect, an embodiment of the present application provides a device for processing instructions, including a flash memory chip and the processor of the first aspect, the processor being connected to the flash memory chip through a CA bus, and the processor being connected to the flash memory chip through a DQ bus.

[0014] In a third aspect, an embodiment of the present application provides a storage device, including the device according to the second aspect.

[0015] In a fourth aspect, an embodiment of the present application provides an electronic device, including the storage device according to the third aspect.

[0016] In a fifth aspect, an embodiment of the present application provides a method for processing instructions, executed by a processor, including:

[0017] Obtaining a target instruction;

[0018] Performing parsing processing on the target instruction, and determining an instruction type of the target instruction, the instruction type including a command / address (CA) operation instruction or a data (DQ) operation instruction;

[0019] In a case where the instruction type is the DQ operation instruction, sending target data to a flash memory chip through a DQ bus;

[0020] in the case that the instruction type is the CA operation instruction, sending CA information or configuration information related to CA to the flash chip through the CA bus;

[0021] in the case that the DQ operation instruction needs write back, obtaining first information from the flash chip through the DQ bus and writing the first information into a data storage space in the processor;

[0022] in the case that the CA operation instruction needs write back, obtaining second information from the flash chip through the CA bus and writing the second information into the data storage space in the processor.

[0023] In a sixth aspect, an embodiment of the present application provides a storage medium, which stores a program, and the program, when executed, implements the method in the fifth aspect.

[0024] In an embodiment of the present application, a processor is provided, which includes: an instruction fetching unit configured to obtain a target instruction and send the target instruction to an instruction parsing unit, the target instruction being an instruction adapted to a flash chip; the instruction parsing unit configured to determine an instruction type of the target instruction by performing parsing processing on the target instruction, the instruction type including a CA operation instruction or a DQ operation instruction; a DQ instruction execution unit configured to, in the case that the instruction type is the DQ operation instruction, send target data to the flash chip through a DQ bus; and a CA instruction execution unit configured to, in the case that the instruction type is the CA operation instruction, send CA information or configuration information related to CA to the flash chip through a CA bus; wherein the instruction fetching unit, the instruction parsing unit and a first target unit form a first instruction pipeline; the instruction fetching unit, the instruction parsing unit and a second target unit form a second instruction pipeline; and the first instruction pipeline and the second instruction pipeline are executed in parallel in the case that a target condition is met, wherein the first target unit includes the DQ instruction execution unit, and the second target unit includes the CA instruction execution unit. In this way, the SCA protocol can be implemented in the process of processing the instruction of the flash chip by means of the processor, and the processing speed of the target instruction is improved. In the case that the target condition is met, the processor can flexibly process the instruction in parallel through the first instruction pipeline and the second instruction pipeline, and the efficiency of the instruction processing is further improved. In addition, in the processor provided in the embodiment of the present application, the first instruction pipeline and the second instruction pipeline share the instruction fetching unit and the instruction parsing unit, and the number of components and the hardware area on the processor can be reduced to a certain extent. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0026] Fig. 1 is a structural block diagram of a processor provided by an embodiment of the present application;

[0027] Fig. 2 is a structural block diagram of another processor provided by an embodiment of the present application;

[0028] Fig. 3 is an architecture diagram of a target format provided by an embodiment of the present application;

[0029] Fig. 4 is a structural block diagram of an instruction processing device provided by an embodiment of the present application;

[0030] Fig. 5 is a flowchart of an instruction processing method provided by an embodiment of the present application;

[0031] Fig. 6 is an external environment architecture diagram of a processor provided by an embodiment of the present application;

[0032] Fig. 7 is an architecture diagram of a processor provided by an embodiment of the present application;

[0033] Fig. 8 is an architecture diagram of a target instruction processing process provided by an embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clear, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0035] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be exchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than that illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of a kind and do not limit the number of objects, for example, the first object can be one or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally means that the objects before and after are in an "or" relationship.

[0036] The following detailed description of embodiments of the application in the drawings provided is not intended to limit the scope of the application claimed, but merely represents selected embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of protection of the application.

[0037] As described in the background, in the process of processing instructions of a flash memory chip, the related art usually implements the SCA protocol through a dedicated state machine, which has the problem of low efficiency in processing instructions.

[0038] In the embodiments of the present application, a processor is provided, comprising: an instruction fetching unit, an instruction parsing unit, a DQ instruction execution unit and a CA instruction execution unit; wherein the instruction fetching unit, the instruction parsing unit and a first target unit form a first instruction pipeline; the instruction fetching unit, the instruction parsing unit and a second target unit form a second instruction pipeline; the first instruction pipeline and the second instruction pipeline execute in parallel under the condition that a target condition is met, wherein the first target unit comprises the DQ instruction execution unit, and the second target unit comprises the CA instruction execution unit. In this way, the SCA protocol can be implemented in the process of processing instructions of a flash memory chip through the processor, and the processing speed of target instructions is improved. Under the condition that the target condition is met, the processor can flexibly process instructions in parallel through the first instruction pipeline and the second instruction pipeline, further improving the efficiency of instruction processing. In addition, on the processor provided in the embodiments of the present application, the first instruction pipeline and the second instruction pipeline share the instruction fetching unit and the instruction parsing unit, which can reduce the number of components and the hardware area on the processor to a certain extent.

[0039] In addition, in the related art, before transmission through two transmission buses, instructions are usually processed through a scalar pipeline design (one instruction pipeline). The processor provided in the embodiments of the present application can implement a super scalar design through the first instruction pipeline and / or the second instruction pipeline, and more flexibly and efficiently complete the processing of target instructions.

[0040] In the related art, in the case of considering the instructions adapted to multiple flash memory chip, a large amount of hardware circuits are often designed in advance. Even so, the new instructions not designed in advance cannot be compatible, and the problems of poor compatibility, large area and cost still exist. However, in the embodiments of the present application, the processor has an instruction storage space for storing various instructions adapted to flash memory chips, and the instruction storage space is used to store the target instruction. In this way, the processor can be adapted to different flash memory chips of different storage manufacturers by modifying the target instruction in the instruction storage space of the processor, so that the processor can be adapted to flash memory chips of more manufacturers. Compared with the related art, the processor provided in the embodiments of the present application has better compatibility and adaptability, and can also reduce the cost.

[0041] In the embodiments of the present application, the target instruction is an instruction conforming to a target format; and the target format includes a bus type field, a data field, a write-back indication field, a length field, a waveform indication field and a lock field. Through the target format, the processor can better control the execution behavior (waveform between the interfaces of the CA bus and / or the DQ bus, i.e., the signal behavior of the target instruction), data, parallel or exclusive operation, etc. between the CA bus and the DQ bus.

[0042] In the embodiments of the present application, the processor can further control the CA bus and / or the DQ bus by simultaneously controlling the first instruction pipeline and / or the second instruction pipeline. Moreover, since the processor controls the CA bus and / or the DQ bus simultaneously, the behavior of the other transmission bus can be reasonably arranged based on the behavior of any one transmission bus, so that the relationship between the instruction operations of the two transmission buses is more easily controlled.

[0043] It should be understood that the description of the same term or case in the embodiments of the present application can be referred to. That is, the description of a certain term or case in one embodiment can also be applied to the description of the term or case in other embodiments, as long as it is logically consistent.

[0044] The method provided in the embodiments of the present application will be described in detail in combination with the drawings and specific embodiments and application scenarios.

[0045] In the embodiments of the present application, the flash memory chip can be a NAND flash chip, and the processor provided in the embodiments of the present application can be used to control the behavior of the flash memory chip, such as implementing the read and write operations of the flash memory chip in the application layer, or implementing the configuration of the flash memory chip, etc.

[0046] Figure 1 is a structural block diagram of a processor according to an embodiment of the present application. As shown in Figure 1, the processor 100 according to an embodiment of the present application comprises:

[0047] An instruction fetching unit 110 is configured to fetch a target instruction, and send the target instruction to an instruction parsing unit, wherein the target instruction is an instruction adapted to a flash memory chip;

[0048] The instruction parsing unit 120 is configured to determine an instruction type of the target instruction by performing parsing processing on the target instruction, wherein the instruction type comprises a CA operation instruction or a DQ operation instruction;

[0049] The DQ instruction execution unit 130 is configured to send target data to the flash memory chip through a DQ bus in a case where the instruction type is the DQ operation instruction;

[0050] The CA instruction execution unit 140 is configured to send CA information or CA-related configuration information to the flash memory chip through a CA bus in a case where the instruction type is the CA operation instruction;

[0051] The instruction fetching unit, the instruction parsing unit and the first target unit form a first instruction pipeline, and the instruction fetching unit, the instruction parsing unit and the second target unit form a second instruction pipeline.

[0052] The first instruction pipeline and the second instruction pipeline are executed in parallel in a case where a target condition is met, wherein the first target unit comprises the DQ instruction execution unit, and the second target unit comprises the CA instruction execution unit.

[0053] In the embodiment of the present application, the processor 100 can be a hardware device, and each unit in the processor 100 can also have a corresponding hardware module. In the processor according to an embodiment of the present application, the corresponding hardware modules of each unit can be connected through a circuit, so that data can be transmitted between each unit.

[0054] In the embodiment of the present application, different flash chip manufacturers have different instruction expression modes for the same operation, for example, a "write operation". The target instruction in the embodiment of the present application can be any operation instruction for a flash chip, and can be an instruction that is adapted to a flash chip, for example, a read-write operation instruction for a flash chip, or a self-configuration operation instruction for a flash chip. The instruction fetch unit 110 in the processor 100 can obtain a target instruction from outside the processor 100, for example, from an application layer; the instruction fetch unit 110 can also obtain a target instruction from inside the processor 100, for example, from a place (hereinafter referred to as an instruction storage space) in the processor 100 where instructions are stored. The embodiment of the present application does not make specific limitations on the manner in which the instruction fetch unit 110 obtains a target instruction that is adapted to a flash chip.

[0055] In the embodiment of the present application, the target instruction can be one instruction or multiple instructions, and the embodiment of the present application does not make specific limitations on the number of target instructions. Further, the target instruction can be one instruction for one flash chip, multiple instructions for one flash chip, or multiple instructions for multiple flash chips, and the embodiment of the present application does not make specific limitations on the correspondence between the number of target instructions and the number of flash chips.

[0056] In the embodiment of the present application, the processor provided by the embodiment of the present application can process operation instructions for a flash chip based on an SCA protocol, and classify the operation instructions for the flash chip into CA operation instructions and DQ operation instructions. Specifically, the instruction analysis unit 120 analyzes and processes the target instruction, and determines the instruction type of the target instruction, which includes a CA operation instruction or a DQ operation instruction. The CA operation instruction can be an operation instruction related to the configuration of the flash chip itself, for example, an instruction for reading the state of the flash chip or an instruction for modifying the state of a register on the flash chip. The DQ operation instruction can be an instruction related to the data information stored on the flash chip, for example, a read-write operation instruction for the flash chip.

[0057] In the embodiment of the present application, the target instruction can include a field directly indicating the instruction type, and the instruction analysis unit 120 analyzes the target instruction and determines the instruction type of the target instruction according to the field directly indicating the instruction type included in the target instruction. The instruction analysis unit 120 can also analyze the target instruction and determine the instruction type of the target instruction based on the data proportion in the target instruction, and the embodiment of the present application does not make specific limitations on how the instruction analysis unit 120 determines the instruction type of the target instruction.

[0058] As shown in FIG. 1 provided by the embodiments of the present application, after the instruction analysis unit 120 determines the instruction type of the target instruction, the target instruction can be executed by different instruction execution units based on the instruction type. The processor 100 can control the flash memory chip by controlling the waveform behavior of the input / output (I / O) interface on the flash memory chip.

[0059] In the embodiments of the present application, when the instruction type of the target instruction is the DQ operation instruction, the DQ instruction execution unit 130 converts the operation content of the target instruction into the waveform behavior of the I / O interface on the processor, realizes the conversion of the digital signal of the target instruction into the analog signal, and transmits the waveform behavior of the I / O interface on the processor 100 to the I / O interface on the flash memory chip through the DQ bus, so that the flash memory chip obtains the target data based on the waveform behavior of the I / O interface on the flash memory chip.

[0060] In the embodiments of the present application, the target data can be any data that attempts to be stored on the flash memory chip. The target data can come from the target instruction itself, and can also be obtained from the internal storage space of the processor 100 based on the indication of the target instruction, for example, the data storage space described below. The target data can be obtained from the internal storage space of the processor 100 based on the indication of the target instruction.

[0061] Correspondingly, when the instruction type of the target instruction is the CA operation instruction, the CA instruction execution unit 140 converts the operation content of the target instruction into the waveform behavior of the I / O interface on the processor, realizes the conversion of the digital signal of the target instruction into the analog signal, and transmits the waveform behavior of the I / O interface on the processor 100 to the I / O interface on the flash memory chip through the CA bus, so that the flash memory chip obtains the CA information or the configuration information related to the CA based on the waveform behavior of the I / O interface on the flash memory chip, and completes the CA related command.

[0062] In the embodiments of the present application, the CA information can be the configuration information related to the flash memory chip itself, for example, the modified register information of the flash memory chip. After the flash memory chip obtains the CA information or the configuration information related to the CA through the waveform behavior of the I / O interface, the flash memory chip performs the operation corresponding to the CA instruction, for example, modifies the register information.

[0063] In the embodiments of the present application, the first target unit (DQ instruction execution unit 130) on the first instruction pipeline is associated with the DQ bus. Correspondingly, the second target unit of the second instruction pipeline is associated with the CA bus. The target condition can represent whether the DQ bus and the CA bus can process target instructions in parallel. Specifically, the target condition can be that the first instruction pipeline and the second instruction pipeline process target instructions of different flash grain chips, or the target condition can be that the instructions currently processed by the first instruction pipeline and the second instruction pipeline do not have an exclusive relationship, so that the first instruction pipeline can execute in parallel with the second instruction pipeline, thereby improving the efficiency of processing target instructions. In the embodiments of the present application, when the first instruction pipeline and the second instruction pipeline execute in parallel, the target instructions on the first instruction pipeline and the target instructions on the second instruction pipeline can be instructions of different flash grain chips or instructions of the same flash grain chip, and the embodiments of the present application do not make specific limitations.

[0064] In the embodiments of the present application, when the first instruction pipeline and the second instruction pipeline execute in parallel, it means that any unit (for example, the instruction fetching unit 110) on the first instruction pipeline can execute in parallel with any unit (for example, the instruction parsing unit 120 or the second target unit) on the second instruction pipeline which is different from the unit on the first instruction pipeline that is currently working. For example, while the instruction fetching unit on the first instruction pipeline acquires X target instructions, the second target unit (CA instruction execution unit 140) on the second instruction pipeline can execute Y target instructions. In the embodiments of the present application, any letter description of target instructions represents different target instructions, such as the aforementioned X target instructions and Y target instructions, and the following A target instructions and B target instructions.

[0065] In the embodiments of the present application, when the DQ instruction execution unit on the first instruction pipeline executes target instructions, if the instruction fetching unit and / or the instruction parsing unit are idle, the instruction fetching unit and / or the instruction parsing unit can execute other instructions in parallel. The target instructions and the other instructions can be instructions of the same flash grain chip or instructions of different flash grain chips. For example, after the instruction fetching unit sends A target instructions for an A flash grain chip to the instruction parsing unit, the instruction fetching unit can acquire B target instructions for the A flash grain chip again, so that the first instruction pipeline and the second instruction pipeline become two parallel instruction pipelines for heterogeneous processing. In addition, the instruction fetching unit can acquire A target instructions for a B flash grain chip in addition to acquiring B target instructions for the A flash grain chip, and the embodiments of the present application do not make specific limitations.

[0066] In the embodiment of the present application, the CA instruction execution unit on the second instruction pipeline executes the A target instruction when the target condition is met. Meanwhile, the DQ instruction execution unit on the first instruction pipeline receives the B target instruction for processing, so as to realize parallel execution of the first instruction pipeline and the second instruction pipeline.

[0067] In the embodiment of the present application, when the target condition is not met, it means that the DQ bus and the CA bus cannot process the target instruction in parallel, for example, the instruction currently processed by the first instruction pipeline (which can be regarded as the instruction corresponding to the target data currently transmitted by the DQ bus) is repelled by the instruction currently processed by the second instruction pipeline, and cannot be processed in parallel. The CA instruction execution unit in the second target unit on the second instruction pipeline can wait until the target instruction on the first instruction pipeline is completed.

[0068] For example, in the embodiment of the present application, the CA instruction execution unit executes the C target instruction. Because the target condition is not met, the DQ instruction execution unit cannot execute the D target instruction in parallel. The DQ instruction execution unit of the first instruction pipeline can execute the D target instruction after the C target instruction on the second instruction pipeline is executed.

[0069] In the embodiment of the present application, the SCA protocol can be realized in the process of processing the instructions of the flash memory particle chip by means of the processor, so as to improve the processing speed of the target instruction. When the target condition is met, the processor can realize the heterogeneous pipeline by means of the first instruction pipeline and the second instruction pipeline, so as to further improve the efficiency of instruction processing. In addition, the first instruction pipeline and the second instruction pipeline share the instruction fetching unit 110 and the instruction analysis unit 120 on the processor provided in the embodiment of the present application, which can reduce the number of components and the hardware area on the processor to a certain extent.

[0070] FIG. 2 is a structural block diagram of a processor provided in the embodiment of the present application. As shown in FIG. 2, the processor 100 provided in the embodiment of the present application further includes a DQ write-back unit 150 and a CA write-back unit 160. The DQ write-back unit 150 is configured to acquire first information from the flash memory particle chip through the DQ bus and write the first information into a data storage space in the processor when the DQ operation instruction needs to be written back. The CA write-back unit 160 is configured to acquire second information from the flash memory particle chip through the CA bus and write the second information into the data storage space in the processor when the CA operation instruction needs to be written back. The first target unit further includes the DQ write-back unit 150, and the second target unit further includes the CA write-back unit 160.

[0071] In the embodiment of the present application, the target instruction can further include a write-back operation, which is used to write back configuration information or data information of the flash memory chip to the processor 100 for further processing by the processor 100. For example, the processor 100 saves the configuration information written back by the flash memory chip, or sends the data information written back by the flash memory chip to a user. In the embodiment of the present application, if the DQ operation instruction needs to be written back, the DQ write-back unit 150 can be used to perform the write-back; if the CA operation instruction needs to be written back, the CA write-back unit 160 can be used to perform the write-back.

[0072] In the embodiment of the present application, in the case where the DQ operation instruction needs to be written back, the DQ write-back unit 150 can obtain first information from the flash memory chip through the DQ bus. The DQ write-back unit 150 converts the analog signal transmitted by the flash memory chip into a data signal of the first information through the DQ bus, thereby obtaining the first information. In the embodiment of the present application, the first information can be any data stored on the flash memory chip, for example, the first information can be valid data information stored on the flash memory chip by a user.

[0073] After the DQ write-back unit 150 obtains the first information, the first information can be written into a data storage space 170 in the processor 100. The data storage space 170 can be a space in the processor 100 specially used for storing data content, and any data in the processor can be stored in the data storage space 170. The data storage space 170 can not only be written with data information, but also can write data information out of the processor 100, for example, the processor 100 externally includes a transmission route specially used for processing data, a data path, etc., and the data storage space 170 writes data information irrelevant to the processor 100 out of the data path of the processor 100. Further, in the process in which the DQ instruction execution unit 130 sends target data to the flash memory chip through the DQ bus, the target data can come from the data storage space 170, and if the data storage space 170 cannot provide the target data, the target data can also obtain data information from outside the processor 100 through the data storage space 170.

[0074] Correspondingly, in the embodiment of the present application, in the case where the CA operation instruction needs to be written back, the CA write-back unit 160 can obtain second information from the flash memory chip through the CA bus. The CA write-back unit 160 converts the analog signal transmitted by the flash memory chip into a data signal of the second information through the CA bus, thereby obtaining the second information. In the embodiment of the present application, the second information can be configuration information related to the flash memory chip.

[0075] After the CA write back unit 160 acquires the second information, the second information can be written into the data storage space 170 in the processor 100. Since the data storage space 170 includes the second information related to the CA operation instruction, during the process of the instruction analysis unit 120 analyzing the target instruction, the instruction analysis unit 120 can also acquire data information from the data storage space 170, for example, the register information of the modified flash memory chip.

[0076] In the embodiments of the present application, through the DQ write back unit and the CA write back unit, the write back operation of the target instruction can be realized, so that the target instruction for the flash memory chip has a wider indication range, and the flash memory chip can perform more operations.

[0077] In the embodiments of the present application, as shown in FIG. 2, the instruction fetching unit 110, the instruction analysis unit 120, the DQ instruction execution unit 130 and the DQ write back unit 150 form a first instruction pipeline; the instruction fetching unit 110, the instruction analysis unit 120, the CA instruction execution unit 140 and the CA write back unit 160 form a second instruction pipeline. In the case of meeting the target condition, the first designated unit in the first target unit on the first instruction pipeline and the second designated unit in the second target unit on the second instruction pipeline are executed in parallel, wherein the first designated unit includes at least one of the DQ instruction execution unit 130 and the DQ write back unit 150, and the second designated unit includes at least one of the CA instruction execution unit 140 and the CA write back unit 160.

[0078] In the embodiments of the present application, in the case of meeting the target condition, in the first clock cycle, the CA write back unit on the second instruction pipeline executes the E target instruction. At the same time, the DQ instruction execution unit on the first instruction pipeline executes the F target instruction, which also includes a write back operation. In the second clock cycle, the CA write back unit on the second instruction pipeline still executes the E target instruction, and the DQ write back unit on the first instruction pipeline executes the F target instruction, so as to realize the parallel execution of the first designated unit in the first target unit on the first instruction pipeline and the second designated unit in the second target unit on the second instruction pipeline.

[0079] In the embodiment of the present application, when the target condition is not satisfied, during the execution of the target instruction by any one of the instruction pipelines (for example, the first instruction pipeline), the other instruction pipeline (for example, the second instruction pipeline) will not execute the instruction. For example, the DQ write-back unit of the first instruction pipeline executes the G target instruction. Because the target condition is not satisfied, the CA instruction execution unit in the second instruction pipeline cannot execute the H target instruction, and the CA instruction execution unit can execute the H target instruction after the execution of the G target instruction is completed.

[0080] In the embodiment of the present application, the first designated unit in the first target unit on the first instruction pipeline and the second designated unit in the second target unit on the second instruction pipeline are executed in parallel, which can make the processor process the target instruction more efficiently. In addition, because of the limitation of the target condition, the processor provided in the embodiment of the present application can reasonably arrange the processing logic sequence of the target instruction.

[0081] In the embodiment of the present application, the processor can further have an instruction storage space for storing various instructions adapted to the flash memory chip. The instruction storage space is used to store the target instruction. According to the instruction manual of the flash memory chip manufacturer, the logic of the instruction adapted to the flash memory chip can be preset in advance. For example, according to the instruction manual of the flash memory chip manufacturer, the code of the target instruction is written and assembled, and finally the target instruction corresponding to the instruction manual is obtained, that is, the target instruction adapted to the flash memory chip. The instruction storage space can store the target instructions adapted to multiple flash memory chip manufacturers, so as to adapt to more flash memory chips.

[0082] In the embodiment of the present application, the instruction of the application layer can be obtained from the instruction storage space, and the corresponding target instruction can be matched to obtain the target instruction. In the embodiment of the present application, the instruction of the application layer can also be obtained by the instruction fetching unit from the application layer, and the target instruction corresponding to the instruction of the application layer can be matched in the instruction storage space.

[0083] By modifying the target instruction stored in the instruction storage space in the processor, the processor can be more flexible to adapt to different flash memory chips of different storage manufacturers. Compared with the related art, the processor provided in the embodiment of the present application has better compatibility and adaptability, and can also reduce the cost.

[0084] In the embodiment of the present application, the target instruction is an instruction in a target format. FIG. 3 is an architecture diagram of a target format provided by an embodiment of the present application. As shown in FIG. 3, the target format of the target instruction provided by the embodiment of the present application includes a bus type field, a data field, a write back indication field, a length field, a wave indication field, and a lock field. The bus type field (BUS_type) is used to indicate whether the bus type used by the target instruction is a CA bus or a DQ bus. The data field (Data) indicates the data content to be sent, which is from the target instruction and / or a data storage space. The write back indication field (R / W) is used to indicate whether the target instruction has a write back operation. The length field (Length) is used to indicate the length of the current operation. The wave indication field (BUS_wave) is used to indicate the signal timing behavior of the target instruction. The lock field (Lock) indicates whether the target instruction is executed synchronously with the next instruction of a different bus.

[0085] In the embodiment of the present application, the instruction parsing unit of the processor can determine the instruction type of the target instruction according to the bus type field in the target format. If the bus type field indicates that the bus type used by the target instruction is a CA bus, the target instruction can be sent to the CA instruction execution unit. If the bus type field indicates that the bus type used by the target instruction is a DQ bus, the target instruction can be sent to the DQ instruction execution unit.

[0086] In the embodiment of the present application, the data field (Data) indicates the data content to be sent, which can also be from the data storage space according to the indication. If there is no data content to be sent by the target instruction in the data storage space, the instruction parsing unit can obtain the target data from outside the processor (for example, a data path) through the data storage space.

[0087] In the embodiment of the present application, the write back indication field (R / W) is used to indicate whether the target instruction has a write back operation. If the write back indication field (R / W) is used to indicate that the target instruction has a write back operation, after the execution of the instruction execution unit (the DQ instruction execution unit and / or the CA instruction execution unit), the write back unit (the DQ write back unit and / or the CA write back unit) obtains the to-be-written-back information (the first information and / or the second information) from the flash memory chip. If the write back indication field (R / W) is used to indicate that the target instruction does not need a write back operation, after the execution of the instruction execution unit, the target instruction can be considered to have been executed.

[0088] In the embodiment of the present application, the length field (Length) is used to indicate the length of the current operation. Further, the length field can indicate the length of the wave behavior of the I / O interface of the DQ bus and / or the CA bus at the processor end.

[0089] In the embodiment of the present application, the waveform indication field (BUS_wave) is used to indicate the signal timing behavior of the target instruction, control the transition of each physical line on the transmission bus connected with the flash memory particle, form different waveform behaviors by causing the transition of different physical lines, and further make the flash memory particle chip execute different target instructions.

[0090] In the embodiment of the present application, the waveform behavior of the I / O interface of the DQ bus and / or the CA bus at the processor end can be determined by at least one of the length field (Length) and the waveform indication field (BUS_wave).

[0091] In the embodiment of the present application, the lock field (Lock) indicates whether the target instruction is executed synchronously with the instruction of the next different bus, and the instruction of the next different bus can be the instruction of one flash memory particle chip or the instruction of different flash memory particle chips, which is not limited in the embodiment of the present application. If the lock field of the target instruction indicates that the target instruction is not executed synchronously with the instruction of the next different bus, it can be understood that the target instruction currently processed locks the transmission bus at the current time and does not allow the instructions of different transmission buses to be executed simultaneously.

[0092] In the embodiment of the present application, through the target format, the processor can better control the execution behavior (the waveform between the interfaces of the CA bus and / or the DQ bus, that is, the signal behavior of the target instruction), data, parallel or exclusive operation, etc. between the CA bus and the DQ bus.

[0093] In the embodiment of the present application, the target condition can be associated with the lock field, and the target condition can include that the lock field indicates the synchronous execution with the instruction of the next different bus. If the lock field indicates that the target instruction can be executed synchronously with the instruction of the next different bus, the first target unit on the first instruction pipeline and the second target unit on the second instruction pipeline provided in the embodiment of the present application can be executed in parallel, that is, the DQ bus and the CA bus can transmit data information at the same time, and the target instruction of the flash memory particle chip can be efficiently processed.

[0094] In the embodiment of the present application, the instruction analysis unit determines the instruction type, and further determines whether the target condition is met through the lock field (BUS_lock), so as to solve the exclusive problem between the instructions.

[0095] In the embodiments of the present application, the processor can further control the CA bus and / or the DQ bus by simultaneously controlling the first instruction pipeline and / or the second instruction pipeline. Moreover, since the processor simultaneously controls the CA bus and / or the DQ bus, the behavior of one transmission bus can be reasonably arranged based on the behavior of the other transmission bus, and the mutually exclusive relationship between the two transmission buses can be more easily controlled.

[0096] In the embodiments of the present application, each unit on the first instruction pipeline can execute a plurality of first target instructions in parallel, and the plurality of first target instructions are different instructions for different flash memory chip, for example, the CA instruction execution unit executes a first target instruction for a first flash memory chip, the instruction analysis unit executes a first target instruction for a second flash memory chip, and the instruction fetch unit executes a first target instruction for a third flash memory chip. Correspondingly, each unit on the second instruction pipeline can execute a plurality of second target instructions in parallel, and the plurality of second target instructions are different instructions for different flash memory chip, and the target instructions include the first target instructions and the second target instructions.

[0097] In the embodiments of the present application, each unit on the first instruction pipeline executes a plurality of third target instructions in sequence, and the plurality of third target instructions are different instructions for the same flash memory chip (i.e., the instructions of one die (DIE)). For example, for the same flash memory chip, the CA instruction for starting data read transmission, the DQ instruction for data read transmission, and the CA instruction for ending data read transmission can be included. In the first clock cycle, the instruction fetch unit obtains the CA instruction for starting data read transmission. In the second clock cycle, the instruction analysis unit analyzes the CA instruction for starting data read transmission, and the instruction fetch unit obtains the DQ instruction for data read transmission. In the third clock cycle, the CA instruction execution unit of the second instruction pipeline executes the CA instruction for starting data read transmission, the instruction analysis unit analyzes the DQ instruction for data read transmission, and the instruction fetch unit obtains the CA instruction for ending data read transmission. In this way, each unit on the first instruction pipeline executes a plurality of third target instructions in sequence, and the plurality of third target instructions are different instructions for the same flash memory chip; and correspondingly, each unit on the second instruction pipeline executes a plurality of fourth target instructions in sequence, and the plurality of fourth target instructions are different instructions for the same flash memory chip. In the embodiments of the present application, the heterogeneous processing of the first instruction pipeline and / or the second instruction pipeline in the processor can more efficiently process the target instructions.

[0098] Figure 4 is a structural block diagram of an instruction processing device provided in an embodiment of the present application. As shown in Figure 4, the instruction processing device 300 provided in the embodiment of the present application includes a flash grain chip 320 and a processor 310. The processor 310 is connected to the flash grain chip 320 through a CA bus, and is connected to the flash grain chip 320 through a DQ bus. The processor 310 in the instruction processing device 300 provided in the embodiment of the present application can be the processor 100 shown in any one of Figures 1 or 2, and thus the specific implementation of this embodiment can refer to the implementation of the corresponding processor described above, and the repeated description will not be repeated. In the embodiment of the present application, the instruction processing device can be a device including the hardware device of the processor shown in any one of Figures 1 or 2 and the hardware device of the flash grain chip.

[0099] In the instruction processing device provided in the embodiment of the present application and shown in Figure 4, the number of the flash grain chips is N, each of the N flash grain chips is connected to the processor through the CA bus, and each of the N flash grain chips is connected to the processor through the DQ bus, where N is a positive integer greater than or equal to 1. One flash grain chip corresponds to one die (DIE), and the target instruction for one flash grain chip can be executed in sequence. When the CA instruction of the first flash grain chip is executed on the CA bus, the DQ instruction of the second flash grain chip can be executed on the DQ bus, so as to realize parallel transmission and efficiently process the target instruction.

[0100] In the embodiment of the present application, the waveform indication field in the target instruction includes a chip select indication field, the chip select indication field is used for the processor to determine the target flash grain chip from the N flash grain chips, and the chip select indication field is used for indicating the target flash grain chip to execute the target instruction. The instruction analysis unit in the processor determines the chip select line of the target flash grain chip in the bus according to the chip select indication segment, and controls the chip select line to generate fluctuation so that the pin of the target flash grain chip can receive the signal, so as to realize that the processor determines the target flash grain chip from the N flash grain chips. When the target flash grain chip receives the waveform of the target instruction through the pin, the target instruction can be executed. The target flash grain chip is determined from the N flash grain chips through the chip select indication field, and the accuracy of determining the target flash grain chip is improved.

[0101] In the embodiment of the present application, the instruction processing device shown in Figure 4 can be a controller including the processor shown in any one of Figures 1 or 2 and the flash grain chip.

[0102] The embodiments of the present application also provide a storage device, which can be a solid state disk (SSD), a universal flash storage (UFS), or the like, including the controller described above.

[0103] In the embodiments of the present application, an electronic device is also provided, which includes the storage device described above. The electronic device can be a terminal device, such as a personal mobile computer or the like, or a server including the storage device described above.

[0104] In addition, in the embodiments of the present application, an instruction processing method is also provided, which is executed by a processor. The processor can be the processor provided in the embodiments of the present application shown in any one of FIG. 1 or FIG. 2, or any other processor capable of implementing the SCA protocol. FIG. 5 is a flowchart of the instruction processing method provided in the embodiments of the present application. As shown in FIG. 5, the instruction processing method provided in the embodiments of the present application includes the following steps:

[0105] In step 410, a target instruction is acquired.

[0106] In step 420, the target instruction is parsed and processed, and the instruction type of the target instruction is determined. The instruction type includes a CA operation instruction or a DQ operation instruction.

[0107] If the instruction type is the CA operation instruction, step 440 can be executed; if the instruction type is the DQ operation instruction, step 430 can be executed.

[0108] In step 420 provided in the embodiments of the present application, the target instruction is an instruction conforming to a target format. The target format includes a lock field indicating whether the target instruction is executed synchronously with the next instruction of a different bus. While determining the instruction type of the target instruction, it can also be determined whether steps 430 and 440 can be executed in parallel according to the lock field of the target instruction. If the lock field indicates locking, steps 430 and 440 cannot be executed in parallel; if the lock field indicates no locking, steps 430 and 440 can be executed in parallel.

[0109] In step 430, if the instruction type is the DQ operation instruction, target data is sent to a flash grain chip through a DQ bus.

[0110] In step 440, if the instruction type is the CA operation instruction, CA information or configuration information related to CA is sent to the flash grain chip through a CA bus.

[0111] If the CA operation instruction needs to be written back, step 460 can be performed; if the DQ operation needs to be written back, step 450 can be performed.

[0112] Step 450, in the case that the DQ operation instruction needs to be written back, first information is obtained from the flash memory chip through the DQ bus and written into the data storage space in the processor.

[0113] Step 460, in the case that the CA operation instruction needs to be written back, second information is obtained from the flash memory chip through the CA bus and written into the data storage space in the processor.

[0114] In the embodiments of the present application, the processor provided by the embodiments of the present application can be used to execute the above-mentioned method, improve the processing speed of the target instruction, control the repulsion relationship between the DQ bus and the CA bus, and solve the problem of repulsion between instructions.

[0115] In order to better understand the processor provided by the embodiments of the present application, examples are given, and it should be understood that the examples are not limiting.

[0116] FIG. 6 is an external environment architecture diagram of the processor provided by the embodiments of the present application, as shown in FIG. 6, in the embodiments of the present application, the SCA protocol processor as shown in any one of FIG. 1 or FIG. 2 converts the application layer operation into the operation behavior of the DQ bus and the CA bus after receiving the operation request of the application layer. The processor can realize the synchronous control of the CA bus and the DQ bus of the flash memory chip interface, and the transmission on the two buses can be performed in parallel. In the process of processing the target instruction by the SCA protocol processor as shown in any one of FIG. 1 or FIG. 2, the target data can be obtained from the data path. The SCA protocol processor obtains the digital signal after executing the target instruction, converts the digital signal into an analog signal through the physical layer bus (DQ bus and CA bus), and further enables the flash memory chip to read. Correspondingly, in the write-back process, the physical layer bus converts the analog signal fed back by the flash memory chip into a digital signal.

[0117] FIG. 7 is an architecture diagram of a processor provided by the embodiments of the present application, as shown in FIG. 7, in the processor provided by the embodiments of the present application (i.e., the SCA protocol processor shown in FIG. 7), a superscalar pipeline design method is used, including two different instruction pipeline controls. The division of labor of each unit of the processor as shown in FIG. 7 can include:

[0118]  The instruction fetching unit reads instructions from the instruction storage space;

[0119]  The instruction parsing unit processes the instructions, judges whether the instruction type is a CA operation instruction or a DQ operation instruction, and then sends the instructions to the CA instruction execution unit and the DQ instruction execution unit according to the instruction type;

[0120] The processor shown in FIG. 7 has two execution units that can execute in parallel, a DQ instruction execution unit that sends data to the flash particle through the DQ bus physical layer, and a CA instruction execution unit that sends configuration data of commands and addresses to the flash particle through the CA bus physical layer.

[0121] The processor shown in FIG. 7 has two write-back units that can execute in parallel, a DQ write-back unit that reads data from the flash particle through the DQ bus physical layer and writes the data into the internal storage space (i.e., the data storage space shown in FIG. 7) of the master chip, and a CA write-back unit that reads configuration and ID data information from the flash particle through the CA bus physical layer and writes the data into the internal space (i.e., the data storage space shown in FIG. 7) of the master chip.

[0122] The pipeline operation of instruction execution in the processor shown in FIG. 7 is as follows:

[0123] The operation of the application layer on the flash particle is performed according to the instruction execution in the SCA protocol processor shown in FIG. 7.

[0124] The instructions in the processor are executed according to the four-stage pipeline of instruction fetching> instruction parsing> instruction execution> write-back.

[0125] The instructions of the processor can be divided into two types, CA bus operation and DQ bus operation.

[0126] The instruction execution stage controls the CA bus and the DQ bus that interface with the flash particle, respectively.

[0127] The write-back operation reads the data or configuration information of the flash particle and writes the data into the data storage space of the master chip, and some instructions do not need to be written back.

[0128] In the processor provided in the embodiments of the present application, the instruction storage space interacts with the application layer control, and the data storage space interacts with the data path. The data saved in the data storage space does not involve the processor itself, and the data can be written back to the data path. In the process of DQ instruction execution, data can be read from the data storage space first, and if the data storage space cannot provide data, the data is read from the data path through the data storage space. The data storage space also saves the data information written back by the CA instruction, so that the instruction parsing unit can read the execution result of the previous instruction if needed.

[0129] In addition, in the processor provided in the embodiments of the present application, a general instruction architecture can be used, for example, the instruction architecture shown in FIG. 3. Based on the instruction format shown in FIG. 3, the processor can control whether the instructions on the DQ bus and the CA bus can be executed in parallel, that is, whether there is a repelling relationship between the instructions, and can also control the waveform behavior of each instruction on the IO interface, the data and behavior of sending / receiving.

[0130] In order to better understand the method for processing instructions provided by the embodiments of the present application, examples are given, and it should be understood that the examples are not limiting.

[0131] FIG. 8 is an architecture diagram of a processing procedure of a target instruction provided by the embodiments of the present application. As shown in FIG. 8, in the processing procedure of the target instruction provided by the embodiments of the present application, the processor shown in any of FIG. 1 or FIG. 2 executes the following instructions A-I in sequence according to the instruction order and the double instruction pipeline.

[0132] The instructions B and F are data transmission instructions (DQ instructions) and are transmitted on a DQ bus (BUS). The instruction B is a read data instruction and needs to write back DQ BUS data; the instruction F is a write data instruction and does not need to write back.

[0133] The instructions A, C, D, E, H and I are command and address related instructions (CA instructions) and are transmitted on a CA BUS. The instruction H is a read state instruction through the CA BUS and needs to write back CA BUS data; the other instructions only need to send CA signals and do not need to write back data.

[0134] Since the interface BUS resources required by the instruction B and the instruction C are not in conflict, the two instructions can be executed in parallel;

[0135] Since the interface BUS resources required by the instruction F and the instruction H are not in conflict, the two instructions can be executed in parallel;

[0136] The instructions A, B and D are instructions of a DIE 1 respectively; the three operations can be executed in sequence and cannot be executed in parallel. However, the instruction B can execute the CA BUS operation of a DIE 2 in the execution process of the DQ BUS.

[0137] The instructions E, F and I are instructions of a DIE n respectively; the three operations can be executed in sequence and cannot be executed in parallel. However, the instruction F can execute the CA BUS operation of a DIE m in the execution process of the DQ BUS.

[0138] Specifically, in a first clock cycle (which can be understood as one clock cycle within the upper and lower two dashed lines), the instruction fetching unit of the processor acquires the data transmission start instruction A of the DIE 1.

[0139] In a second clock cycle, the instruction fetching unit of the processor acquires the data read transmission instruction B of the DIE 1, and the instruction parsing unit of the processor acquires the instruction A acquired by the instruction fetching unit in the first clock cycle.

[0140] In the third clock cycle, the instruction fetch unit of the processor fetches the DIE 2 command+address C, the instruction resolving unit of the processor fetches the instruction B fetched by the instruction fetch unit in the second clock cycle, and the CA instruction execution unit of the second instruction pipeline executes the A instruction.

[0141] In the fourth clock cycle, the instruction fetch unit of the processor fetches the DIE 1 data transmission end instruction D, the instruction resolving unit of the processor fetches the instruction C fetched by the instruction fetch unit in the third clock cycle, the DQ instruction execution unit of the first instruction pipeline executes the instruction B, and the CA bus fetches the DIE 1 data transmission start instruction (i.e., SCE).

[0142] In this way, the SCA protocol control is realized through the heterogeneous pipeline superscalar processor design method, the synchronization control of the CA bus and the DQ bus of the flash memory particle interface is realized, and the transmission on the two buses can be performed in parallel.

[0143] In the embodiment of the application, the application layer control is converted into the SCA protocol waveform of the NAND chip IO interface through the processor mode; flexibility is increased, the standard protocol and various self-defined commands of the storage chip (Flash) of manufacturers can be adapted through the instruction storage space. Through the superscalar design method, two heterogeneous pipelines are provided to process the control of the CA bus and the DQ bus, and the parallel execution of the signal transmission on the two buses can be realized. Since the two pipelines share the instruction fetch and instruction resolving unit, the hardware area of the processor can be reduced. Meanwhile, the CA bus and the DQ bus are controlled by the same processor, and the mutual exclusive relationship of the instruction operation between the two buses can be more easily controlled. In the embodiment of the application, the general instruction architecture is used to control the execution behavior (waveform), data, parallel or exclusive operation of the CA bus and the DQ bus.

[0144] Through the processing of the target instruction provided in the embodiment of the application, the following advantages are also provided: 1. The DQ bus and the CA bus behavior can be synchronously controlled: whether the IO operations can be executed in parallel, and the exclusive relationship between the two buses; 2. The processor mode is used, the sequence and timing of the command / address and data transmission can be flexibly specified, and various flexible flash operations can be supported; the various operation commands of different manufacturers can be more flexibly adapted; 3. The superscalar design method is used, compared with the scheme of using two independent processors to control the CA bus and the DQ bus, only one execution unit and one write-back unit are added, and the resource area is relatively small.

[0145] The embodiment of the present application further provides a computer readable storage medium, wherein the readable storage medium stores a program or instructions, and the program or instructions are executed by a processor to realize each process of the above method embodiment and achieve the same technical effects. To avoid repetition, details are not described herein.

[0146] The readable storage medium includes a computer readable storage medium, such as a computer readable only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and the like.

[0147] The embodiment of the present application provides a computer program product stored in a storage medium, and the program product is executed by at least one processor to realize each process of the above method embodiment and achieve the same technical effects. To avoid repetition, details are not described herein.

[0148] It should be noted that in this document, the terms “comprising”, “including”, or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles or devices including a series of elements not only include those elements, but also include other elements not explicitly listed, or include elements inherent to such processes, methods, articles or devices. Without more limitations, the element defined by the statement “including a…” does not exclude the presence of additional identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to the order of performing functions as shown or discussed, but can also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method can be performed in an order different from the described order, and various steps can also be added, omitted or combined. In addition, the features described with reference to some examples can be combined in other examples.

[0149] From the above description of the embodiments, those skilled in the art can clearly understand that the above method embodiments can be realized by means of software and necessary general hardware platforms, of course, they can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a plurality of instructions for making a terminal (which can be a mobile phone, computer, server, or network equipment, etc.) execute the methods described in each embodiment of the present application.

[0150] The embodiments of the present application are described above with reference to the accompanying drawings, but the present application is not limited to the specific embodiments described above, and the specific embodiments described above are merely illustrative, but not restrictive, and a person of ordinary skill in the art can make many forms under the inspiration of the present application without departing from the purpose of the present application and the scope protected by the claims.

Claims

1. A processor, characterized in that, include: The instruction fetch unit is used to fetch the target instruction and send it to the instruction parsing unit; The instruction parsing unit is used to determine the instruction type of the target instruction by parsing the target instruction. The instruction type includes command / address (CA) operation instructions or data (DQ) operation instructions. The DQ instruction execution unit is used to send target data to the flash memory chip via the DQ bus when the instruction type is a DQ operation instruction. The CA instruction execution unit is used to send CA information or CA-related configuration information to the flash memory chip via the CA bus when the instruction type is a CA operation instruction. The instruction fetch unit, the instruction parsing unit, and the first target unit form a first instruction pipeline; the instruction fetch unit, the instruction parsing unit, and the second target unit form a second instruction pipeline. When the target conditions are met, the first instruction pipeline and the second instruction pipeline are executed in parallel, wherein the first target unit includes the DQ instruction execution unit and the second target unit includes the CA instruction execution unit.

2. The processor according to claim 1, characterized in that, The processor also includes: The DQ write-back unit is used to obtain first information from the flash memory chip via the DQ bus and write the first information into the data storage space in the processor when the DQ operation instruction requires write-back. The CA write-back unit is used to obtain second information from the flash memory chip via the CA bus and write the second information into the data storage space in the processor when the CA operation instruction requires write-back. The first target unit further includes the DQ write-back unit, and the second target unit further includes the CA write-back unit.

3. The processor according to claim 2, characterized in that, When the target conditions are met, the first designated unit in the first target unit of the first instruction pipeline and the second designated unit in the second target unit of the second instruction pipeline are executed in parallel. The first designated unit includes at least one of the DQ instruction execution unit and the DQ write-back unit, and the second designated unit includes at least one of the CA instruction execution unit and the CA write-back unit.

4. The processor according to any one of claims 1-3, characterized in that, The processor has an instruction storage space for storing various instructions adapted to flash memory chips, and the instruction storage space is used to store the target instructions.

5. The processor according to any one of claims 1-3, characterized in that, The target instruction is an instruction conforming to the target format; wherein, the target format includes: bus type field, data field, write-back indicator field, length field, waveform indicator field, and lock field; The bus type field is used to indicate whether the target instruction uses a CA bus or a DQ bus. The data field indicates the data content to be sent; The write-back indication field is used to indicate whether the target instruction has a write-back operation; The length field is used to indicate the length of the current operation; The waveform indication field is used to indicate the signal timing behavior of the target instruction; The locking field indicates whether the target instruction is executed synchronously with the next instruction on a different bus.

6. The processor according to claim 5, characterized in that, The target condition includes the locking field indicating that the target instruction is executed synchronously with the instruction on the next different bus.

7. The processor according to any one of claims 1-3, characterized in that, Each unit in the first instruction pipeline executes multiple first target instructions in parallel, the multiple first target instructions being different instructions for different flash memory chips; each unit in the second instruction pipeline executes multiple second target instructions in parallel, the multiple second target instructions being different instructions for different flash memory chips, the target instructions including first target instructions and second target instructions; or, Each unit in the first instruction pipeline executes a plurality of third target instructions in sequence, wherein the plurality of third target instructions are different instructions for the same flash memory chip; each unit in the second instruction pipeline executes a plurality of fourth target instructions in sequence, wherein the plurality of fourth target instructions are different instructions for the same flash memory chip, and the target instructions include third target instructions and fourth target instructions.

8. An instruction processing apparatus, characterized in that, It includes a flash memory chip and a processor according to any one of claims 1-7, wherein the processor is connected to the flash memory chip via a CA bus and the processor is connected to the flash memory chip via a DQ bus.

9. The apparatus according to claim 8, characterized in that, The number of flash memory chips is N. Each of the N flash memory chips is connected to the processor via a CA bus and also connected to the processor via a DQ bus, where N is a positive integer greater than or equal to 1.

10. The apparatus according to claim 9, characterized in that, The target instruction is an instruction conforming to the target format; wherein, the target format includes: bus type field, data field, write-back indicator field, length field, waveform indicator field, and lock field; The waveform indication field in the target instruction includes a chip select indication field, which is used by the processor to determine the target flash memory chip from N flash memory chips, and the chip select indication field is used to instruct the target flash memory chip to execute the target instruction.

11. The apparatus according to any one of claims 8-10, characterized in that, The device is a controller.

12. A storage device, characterized in that, The storage device includes the apparatus according to claim 11.

13. An electronic device, characterized in that, The electronic device includes the storage device according to claim 12.

14. An instruction processing method, characterized in that, Executed by a processor, the method includes: Obtain the target instruction; The target instruction is parsed and the instruction type of the target instruction is determined. The instruction type includes command / address (CA) operation instructions or data (DQ) operation instructions. When the instruction type is a DQ operation instruction, the target data is sent to the flash memory chip via the DQ bus; When the instruction type is a CA operation instruction, CA information or CA-related configuration information is sent to the flash memory chip via the CA bus; When the DQ operation instruction needs to be written back, the first information is obtained from the flash memory chip via the DQ bus and written into the data storage space within the processor; If the CA operation instruction needs to be written back, the second information is obtained from the flash memory chip via the CA bus and written into the data storage space within the processor.

15. A storage medium, characterized in that, The storage medium stores a program that, when executed, implements the method as described in claim 14.

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