Photovoltaic cell, module and system

Abstract

The present disclosure is applicable to the technical field of solar cells, and provides a photovoltaic cell, a module and a system. A first surface is divided into an edge region and a central region, and a third doping layer comprising three doping segments and having a polarity opposite to that of a silicon substrate is disposed in the edge region. The area of an emitter in the back contact cell can be increased, thereby improving the efficiency of the back contact cell.

Description

Photovoltaic cells, modules and systems

[0001] Priority information

[0002] This disclosure claims priority to Chinese patent application No. 202421443494.6, filed on June 21, 2024, with the China National Intellectual Property Administration, entitled “Back Contact Battery, Battery Module and Photovoltaic System”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of solar cell technology, and more particularly to a back-contact cell, a cell module, and a photovoltaic system. Background Technology

[0004] Solar cell power generation is a sustainable and clean energy source that utilizes the photovoltaic effect of a semiconductor pn junction to convert sunlight into electrical energy. In solar cells, back-contact solar cells are those where both the p-region and n-region are located on the back (non-light-receiving surface) of the cell. The light-receiving surface of this cell has no metal electrodes obstructing it, thus effectively increasing the short-circuit current of the cell.

[0005] In related technologies, in back-contact batteries, the doped layer and electrodes are designed on the back side, which needs to be designed as intersecting p-regions and N-regions. The p-regions and N-regions are evenly distributed along one direction. The area of ​​the back emitter region is relatively small, resulting in low battery conversion efficiency.

[0006] Utility Model Content

[0007] This disclosure provides a back-contact battery, a battery module, and a photovoltaic system.

[0008] This disclosure is implemented as follows: the back contact battery of the embodiments of this disclosure includes:

[0009] A silicon substrate having opposing first and second surfaces, the first surface having opposing first and second edges along a first direction, and opposing third and fourth edges along a second direction, the second direction intersecting the first direction; the first surface includes an edge region and an intermediate region, the edge region surrounding the intermediate region;

[0010] A plurality of first doped layers, a plurality of second doped layers, a plurality of first connecting layers, and a plurality of second connecting layers are disposed in the intermediate region. The first doped layers and second doped layers are arranged alternately along a first direction and both extend discontinuously along a second direction. The first connecting layers and second connecting layers are arranged alternately along the second direction and extend along the first direction. The first doped layers are connected to the first connecting layers and disconnected at the second connecting layers, and the second doped layers are connected to the second connecting layers and disconnected at the first connecting layers. The doping types of the first and second doped layers are opposite.

[0011] A third doped layer is disposed on the edge region. The doping type of the third doped layer is opposite to that of the silicon substrate, and the doping type of the third doped layer is the same as that of the first doped layer and the first interconnecting layer. The third doped layer includes a first doped segment, a second doped segment, and a third doped segment. The first doped segment is disposed at the first edge and extends continuously along the second direction. The second doped segment is disposed at the second edge and extends continuously along the second direction. The third doped segment is disposed at the third edge and extends continuously along the first direction. The first doped segment, the second doped segment, and the third doped segment are all insulated from the second doped layer.

[0012] Furthermore, when the silicon substrate is p-type doped, the first doped layer and the first interconnecting layer are n-type doped, the second doped layer and the second interconnecting layer are p-type doped, and the third doped layer is n-type doped.

[0013] When the silicon substrate is doped with n-type doping, the first doped layer and the first interconnecting layer are doped with p-type doping, the second doped layer and the second interconnecting layer are doped with n-type doping, and the third doped layer is doped with p-type doping.

[0014] Furthermore, the third doped segment satisfies at least one of the following: both ends of the third doped segment are connected to the first doped segment and the second doped segment, respectively; the third doped segment is connected to several first doped layers.

[0015] Furthermore, the first connecting layer satisfies at least one of the following: the first doped segment is connected to the end of the first connecting layer; the second doped segment is connected to the end of the first connecting layer.

[0016] Furthermore, a first sub-gate is provided on the first doped layer, and a second sub-gate is provided on the second doped layer, with both the first and second sub-gates extending along the second direction;

[0017] The first sub-gate is disconnected at the second connecting layer, and the second sub-gate is disconnected at the first connecting layer;

[0018] A third sub-gate is provided on the first doped section, a fourth sub-gate is provided on the second doped section, the third and fourth sub-gates extend continuously along the second direction, and a fifth sub-gate is provided on the third doped section, the fifth sub-gate extends continuously along the first direction.

[0019] Furthermore, a first main gate is provided on the first connection layer, the first main gate extends along a first direction and is electrically connected to a first sub-gate, a third sub-gate and a fourth sub-gate;

[0020] The second connection layer is provided with a second main gate, which extends along the first direction and is electrically connected to the second sub-gate, but the second main gate is not electrically connected to the first sub-gate, the third sub-gate and the fourth sub-gate.

[0021] Furthermore, the second main gate does not extend above the first and second doped sections; or

[0022] The second main gate extends above the first doped section and the second doped section and intersects with the third sub-gate and the fourth sub-gate. A first insulating layer is disposed at the position where the third sub-gate and the fourth sub-gate intersect with the second main gate, and the second main gate is located above the first insulating layer.

[0023] Furthermore, the fifth sub-gate is electrically connected to the third and fourth sub-gates, but not electrically connected to the second sub-gate.

[0024] Furthermore, the widths of the third and fourth sub-gates in the first direction are greater than the widths of the first and second sub-gates in the first direction.

[0025] Furthermore, the third doped section is further provided with a third main gate, which extends continuously along the first direction and is electrically connected to the fifth sub-gate, while the third main gate is not electrically connected to the second sub-gate; or, at least a portion of the fifth sub-gate has a width in the second direction that is greater than the widths of the first sub-gate and the second sub-gate in the first direction; or, the third doped section is further provided with a third main gate, which extends continuously along the first direction and is electrically connected to the fifth sub-gate, while the third main gate is not electrically connected to the second sub-gate, and at least a portion of the fifth sub-gate has a width in the second direction that is greater than the widths of the first sub-gate and the second sub-gate in the first direction.

[0026] Furthermore, the third doped layer also includes a fourth doped segment, which is disposed at the fourth edge and extends continuously along the first direction. The fourth doped segment is insulated from the second doped layer, and a sixth sub-gate is provided on the fourth doped segment, which extends continuously along the first direction.

[0027] Furthermore, the fourth doped segment satisfies at least one of the following: both ends of the fourth doped segment are connected to the first doped segment and the second doped segment, respectively; the fourth doped segment is connected to a plurality of first doped layers.

[0028] Furthermore, the sixth sub-gate is electrically connected to the third and fourth sub-gates, but not electrically connected to the second sub-gate; or, a fourth main gate is provided on the fourth doped section, the fourth main gate extends continuously along the first direction and is electrically connected to the sixth sub-gate, but not electrically connected to the second sub-gate; or, the sixth sub-gate is electrically connected to the third and fourth sub-gates, but not electrically connected to the second sub-gate, the fourth main gate is provided on the fourth doped section, the fourth main gate extends continuously along the first direction and is electrically connected to the sixth sub-gate, but not electrically connected to the second sub-gate.

[0029] Furthermore, a fourth doped layer is stacked on the edge region. The fourth doped layer is disposed at the fourth edge and extends continuously along the first direction. The doping type of the fourth doped layer is opposite to that of the third doped layer. The fourth doped layer is insulated from the first doped layer, the first doped segment, and the second doped segment.

[0030] A seventh sub-gate is provided on the fourth doped layer. The seventh sub-gate extends continuously along the first direction and is not electrically connected to the third and fourth sub-gates.

[0031] Furthermore, the fourth doped layer is connected to several second doped layers.

[0032] Furthermore, a fifth main gate is provided on the fourth doped layer, the fifth main gate extends continuously along the first direction and is electrically connected to the seventh sub-gate, and the fifth main gate is not electrically connected to the first sub-gate, the third sub-gate and the fourth sub-gate; or, at least a portion of the seventh sub-gate has a width in the second direction that is greater than the width of the first sub-gate and the second sub-gate in the first direction; or, a fifth main gate is provided on the fourth doped layer, the fifth main gate extends continuously along the first direction and is electrically connected to the seventh sub-gate, the fifth main gate is not electrically connected to the first sub-gate, the third sub-gate and the fourth sub-gate, and at least a portion of the seventh sub-gate has a width in the second direction that is greater than the width of the first sub-gate and the second sub-gate in the first direction.

[0033] Furthermore, the extension of the fourth doped layer along the first direction intersects with the first doped segment and the second doped segment;

[0034] In one configuration, the fifth main gate does not extend above the first doped section and the second doped section; or, the fifth main gate extends above the first doped section and the second doped section and intersects with the third sub-gate and the fourth sub-gate, and a second insulating layer is provided at the position where the third sub-gate and the fourth sub-gate intersect with the fifth main gate, and the fifth main gate is located above the second insulating layer.

[0035] Furthermore, a first sub-gate is provided on the first doped layer, and a second sub-gate is provided on the second doped layer. Both the first and second sub-gates extend along the second direction. The first sub-gate is disconnected at the second connecting layer, and the second sub-gate is disconnected at the first connecting layer. A third sub-gate is provided on the first doped section, and a fourth sub-gate is provided on the second doped section. The third and fourth sub-gates extend continuously along the second direction. No fifth sub-gate is provided on the third doped section. A third main gate is provided on the third doped section. The third main gate extends continuously along the first direction, and the third main gate is not electrically connected to the second sub-gate.

[0036] Furthermore, a first sub-gate is provided on the first doped layer, and a second sub-gate is provided on the second doped layer. Both the first and second sub-gates extend along the second direction. The first sub-gate is disconnected at the second connecting layer, and the second sub-gate is disconnected at the first connecting layer. The third doped layer also includes a fourth doped segment, which is disposed at the fourth edge and extends continuously along the first direction. The fourth doped segment is insulated from the second doped layer. No sixth sub-gate is provided on the fourth doped segment. A fourth main gate is provided on the fourth doped segment, which extends continuously along the first direction. The fourth main gate is not electrically connected to the second sub-gate.

[0037] This disclosure also provides a battery assembly including a plurality of back contact batteries of any of the above types.

[0038] This disclosure also provides a photovoltaic system, which includes the aforementioned battery module.

[0039] In the embodiments of the back-contact battery, battery module, and photovoltaic system disclosed herein, the first surface includes an edge region and a middle region, with the edge region surrounding the middle region. A first doped layer, a first connecting layer, a second doped layer, and a second connecting layer are disposed on the middle region. A third doped layer is disposed on the edge region. The third doped layer has the same doping type as the first doped layer but the opposite doping type to that of the silicon substrate. The third doped layer includes a first doped segment, a second doped segment, and a third doped segment located at the three edges of the first surface. Thus, compared to the conventional scheme of using doped layers of different polarities arranged alternately and uniformly in one direction, this disclosure, by dividing the first surface into an edge region and a middle region, and disposing of a third doped layer with three doped segments and an opposite polarity to that of the silicon substrate on the edge region, can increase the emitter area in the back-contact battery, thereby improving the efficiency of the back-contact battery.

[0040] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description

[0041] Figure 1 is a schematic diagram of the modules of the photovoltaic system provided in an embodiment of this disclosure;

[0042] Figure 2 is a schematic diagram of the planar structure of the silicon substrate of the back contact battery provided in an embodiment of this disclosure;

[0043] Figure 3 is a schematic diagram of the planar structure of the back contact battery provided in an embodiment of this disclosure;

[0044] Figure 4 is a schematic diagram of another planar structure of the back contact battery provided in an embodiment of this disclosure;

[0045] Figure 5 is another planar structural schematic diagram of the back contact battery provided in an embodiment of this disclosure;

[0046] Figure 6 is another planar structural schematic diagram of the back contact battery provided in the embodiment of this disclosure;

[0047] Figure 7 is another planar structural schematic diagram of the back contact battery provided in the embodiment of this disclosure;

[0048] Figure 8 is another planar structural schematic diagram of the back contact battery provided in the embodiment of this disclosure;

[0049] Figure 9 is another planar structural schematic diagram of the back contact battery provided in an embodiment of this disclosure.

[0050] Key component symbols: 1000, photovoltaic system; 200, battery module; 100, back contact cell; 10, silicon substrate; 11, first surface; 111, first edge; 112. Second edge; 113. Third edge; 114. Fourth edge; 115. Edge region; 116. Middle region; 20. First doped layer; 21. First sub-gate; 30. Second doped layer; 31. Second sub-gate; 40. First connecting layer; 50. Second connecting layer; 60. Third doped layer; 61. First doped segment; 611. Third sub-gate; 62. Second doped segment; 621. Fourth sub-gate; 63. Third doped segment; 631. Fifth sub-gate; 64. Fourth doped segment; 641. Sixth sub-gate; 70. First main gate; 80. Second main gate; 90. Third main gate; 110. First insulating layer; 120. Fourth main gate; 130. Fourth doped layer; 131. Seventh sub-gate; 140. Fifth main gate; 150. Second insulating layer. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. It should be noted that the embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this disclosure, and should not be construed as limiting this disclosure. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this disclosure and are not intended to limit this disclosure.

[0052] In the description of this disclosure, it should be understood that the terms "upper", "lower", "left", "right", "lateral", "longitudinal", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0053] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this disclosure, "several" means two or more, unless otherwise explicitly specified.

[0054] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0055] The following disclosure provides numerous different embodiments or examples for implementing various structures of this disclosure. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this disclosure. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this disclosure, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0056] Please refer to Figure 1. The photovoltaic system 1000 in this embodiment may include the battery module 200 in this embodiment. The battery module 200 in this embodiment may include a plurality of back contact batteries (not shown in the figure) in this embodiment. The plurality of back contact batteries can be connected together in series by soldering ribbon to form a plurality of battery strings. Each battery string can be connected in series, in parallel or in series-parallel manner to form the battery module 200.

[0057] Referring to Figures 2 and 3, the back contact battery 100 in this embodiment may include a silicon substrate 10, a plurality of first doped layers 20, a plurality of second doped layers 30, a plurality of first interconnect layers 40, a plurality of second interconnect layers 50 and a third doped layer 60.

[0058] As shown in Figure 2, the silicon substrate 10 has a first surface 11 and a second surface (not shown). The first surface 11 has a first edge 111 and a second edge 112 opposite to each other along a first direction, and a third edge 113 and a fourth edge 114 opposite to each other along a second direction, which intersects the first direction. The first surface 11 includes an edge region 115 and a middle region 116, with the edge region 115 surrounding the middle region 116.

[0059] Specifically, the first surface 11 can be the back surface of the silicon substrate 10 (i.e., the backlight surface of the back contact cell 100), the second surface can be the front surface of the silicon substrate 10, the first direction can be the longitudinal direction of the back contact cell 100, and the second direction can be the lateral direction of the back contact cell 100, which are perpendicular to each other. In the example shown in FIG2, the first edge 111 is the upper edge in the longitudinal direction, the second edge 112 is the lower edge in the longitudinal direction, the third edge 113 is the left edge in the lateral direction, and the fourth edge 114 is the right edge in the lateral direction. Exemplarily, the edge region 115 can be a region located at the four edges of the silicon substrate 10, which is approximately U-shaped, and the edge region 115 is disposed around the middle region 116.

[0060] Referring to Figures 2 and 3, several first doped layers 20, several second doped layers 30, several first connecting layers 40, and several second connecting layers 50 are all disposed on the central region 116. The first doped layers 20 and second doped layers 30 are arranged alternately along a first direction and extend discontinuously along a second direction. The first connecting layers 40 and second connecting layers 50 are arranged alternately along the second direction and extend along the first direction. The first doped layer 20 is connected to the first connecting layer 40 and disconnected at the second connecting layer 50; the second doped layer 30 is connected to the second connecting layer 50 and disconnected at the first connecting layer 40. The doping types of the first doped layers 20 and second doped layers 30 are opposite; the doping types of the first connecting layers 40 and second connecting layers 50 are opposite; the doping types of the first connecting layers 40 and first doped layers 20 are the same; and the doping types of the second connecting layers 50 and second doped layers 30 are the same.

[0061] The third doped layer 60 is disposed on the edge region 115. The doping type of the third doped layer 60 is opposite to that of the silicon substrate 10, and the doping type of the third doped layer 60 is the same as that of the first doped layer 20 and the first interconnecting layer 40. The third doped layer 60 includes a first doped segment 61, a second doped segment 62 and a third doped segment 63. The first doped segment 61 is disposed at the first edge 111 and extends continuously along the second direction. The second doped segment 62 is disposed at the second edge 112 and extends continuously along the second direction. The third doped segment 63 is disposed at the third edge 113 and extends continuously along the first direction. The first doped segment 61, the second doped segment 62 and the third doped segment 63 are all insulated from the second doped layer 30.

[0062] In other words, in the embodiments disclosed herein, the first doped layer 20, the first interconnecting layer 40, and the third doped layer 60 are all of the opposite doping type to the silicon substrate 10. All three are emitter doped layers of the back contact cell 100, while the second doped layer 30 is of the same doping type as the silicon substrate 10 and is the base region doped layer of the back contact cell 100.

[0063] It should be noted that in the embodiments of this disclosure, "discontinuous extension" can be understood as the structure being segmented in its extension direction, with several interrupted regions in between. That is, the phrase "the first doped layer 20 and the second doped layer 30 extend discontinuously along the second direction" in the text refers to the fact that from the third edge 113 to the fourth edge 114, the first doped layer 20 and the second doped layer 30 have several interrupted regions, and a first connecting layer 40 and a second connecting layer 50 are disposed at the locations of these interrupted regions (as shown in Figure 3). In other words, the first doped layer 20 is interrupted at the second connecting layer 50, and the second doped layer 30 is interrupted at the first connecting layer 40. In the following descriptions of "discontinuous extension," please refer to this document for clarification.

[0064] Furthermore, "continuous extension" can be understood as a structure that is continuous and uninterrupted in the extension direction, without any breaks in the middle. That is to say, in this paper, the first doped segment 61, the second doped segment 62, and the third doped segment 63 are continuous and uninterrupted structures in their respective extension directions. In the following text, if there is a description of "continuous extension," please refer to this section for clarification.

[0065] As shown in Figures 1 to 3, in the back contact battery 100, battery module 200 and photovoltaic system 1000 of this disclosure embodiment, the first surface 11 includes an edge region 115 and a middle region 116. The edge region 115 is disposed around the middle region 116. A first doped layer 20, a first connecting layer 40, a second doped layer 30 and a second connecting layer 50 are disposed on the middle region 116. A third doped layer 60 is disposed on the edge region 115. The third doped layer 60 has the same doping type as the first doped layer 20 and the opposite doping type to the silicon substrate 10. The third doped layer 60 includes a first doped segment 61, a second doped segment 62 and a third doped segment 63 respectively located at the three edges of the first surface 11. Thus, compared to the traditional scheme of using doped layers of different polarities arranged alternately and uniformly in one direction, this disclosure divides the first surface 11 into an edge region 115 and a middle region 116, and provides a third doped layer 60 with three doped segments and opposite polarity to the silicon substrate 10 on the edge region 115, which can increase the area of ​​the emitter in the back contact cell 100, thereby improving the efficiency of the back contact cell 100.

[0066] Specifically, in some embodiments, the first doped segment 61 may be located at the position of the first edge 111, where its upper edge coincides with the first edge 111, or there may be a preset distance between the upper edge of the first doped segment 61 and the first edge 111. This can be determined according to the specific manufacturing process and is not limited here. Similarly, the second doped segment 62 may be located at the position of the second edge 112, where its lower edge coincides with the second edge 112, or there may be a preset distance between the lower edge of the second doped segment 62 and the second edge 112. Similarly, the third doped segment 63 may be located at the position of the third edge 113, where its left edge coincides with the third edge 113, or there may be a preset distance between the left edge of the third doped segment 63 and the third edge 113. This is not limited here. The figures show that each doped segment has a preset distance from the edge, which is merely illustrative to clearly show the existence of the silicon substrate 10 and is not necessarily required.

[0067] For example, in the structure of the back contact battery 100, the structural features satisfy at least one of the following: the first doped segment 61 can extend from the third edge 113 to the fourth edge 114; the second doped segment 62 can extend from the third edge 113 to the fourth edge 114; and the third doped segment 63 can extend from the first edge 111 to the second edge 112.

[0068] Furthermore, in the intermediate region 116, the arrangement of each doped layer and connecting layer is shown in Figure 3. As shown in Figure 3, both the first doped layer 20 and the second doped layer 30 have several disconnected regions along the second direction. The disconnected regions of two adjacent first doped layers 20 are substantially aligned in the first direction, and the disconnected regions of two adjacent second doped layers 30 are also substantially aligned in the first direction. The first connecting layer 40 is disposed at the disconnected regions of the second doped layer 30, and is connected to the first doped layer 20 and insulated from the second doped layer 30. The second connecting layer 50 is disposed at the disconnected regions of the first doped layer 20, and is connected to the second doped layer 30 and insulated from the first doped layer 20.

[0069] In the embodiments of this disclosure, the silicon substrate 10 can be a p-type silicon substrate or an N-type silicon substrate, that is, the doping type of the silicon substrate 10 can be p-type doping or n-type doping.

[0070] For example, when the silicon substrate 10 is p-type doped, the first doped layer 20 and the first interconnecting layer 40 are n-type doped, the second doped layer 30 and the second interconnecting layer 50 are p-type doped, and the third doped layer 60 is n-type doped.

[0071] For example, when the silicon substrate 10 is doped with n-type doping, the first doped layer 20 and the first interconnecting layer 40 are doped with p-type doping, the second doped layer 30 and the second interconnecting layer 50 are doped with n-type doping, and the third doped layer 60 is doped with p-type doping.

[0072] In other words, regardless of the doping type of the silicon substrate 10, the first doped layer 20, the first interconnecting layer 40 in the middle region 116, and the third doped layer 60 in the edge region 115 are all emitter doped layers of the back contact cell 100, while the second doped layer 30 is a base region doped layer.

[0073] In this way, by providing a third doped layer 60 with the opposite doping type to that of the silicon substrate 10 at the three edges of the edge region 115, the area of ​​the emitter can be increased, thereby improving efficiency.

[0074] Furthermore, it should be noted that in the embodiments disclosed herein, "insulation isolation" refers to the absence of electrical conduction between the two. This can be achieved by directly forming a trench between the two, or by providing other insulating dielectric films between them. No specific limitations are imposed here.

[0075] Please refer to Figure 4. In some embodiments, the two ends of the third doped segment 63 may be connected to the first doped segment 61 and the second doped segment 62, respectively.

[0076] Thus, the first doped section 61, the second doped section 62, and the third doped section 63 can be treated as a whole, without the need to isolate the third doped section 63 from the first doped section 61, or the third doped section 63 from the second doped section 62. This reduces the area of ​​the ineffective region (i.e., the area not covered by the doped layer) of the entire silicon substrate 10, improving the efficiency of the back contact cell 100. Furthermore, when setting up a sub-gate for current collection or setting up a main gate, solder strip, or a combination of main gate and solder strip for current convergence, it is only necessary to turn on the sub-gates on the first doped section 61, the second doped section 62, and the third doped section 63 to collect the current from the third doped section 63, without needing to set up a main gate on the third doped section 63 to collect the current from the third doped section 63 located at the third edge 113.

[0077] Of course, in some embodiments, the two ends of the third doped segment 63 may not be connected to the first doped segment 61 and the second doped segment 62, and no specific restrictions are imposed here.

[0078] Please refer to Figures 3 and 4. In some embodiments, the third doped segment 63 may be connected to several first doped layers 20.

[0079] In this way, the third doped section 63 can be connected to the first doped layer 20 as a whole without isolating the two, and the area of ​​the ineffective region of the entire silicon substrate 10 (i.e. the area covered by the doped layer) can be reduced, thereby improving the efficiency of the back contact cell 100.

[0080] Meanwhile, as shown in Figures 3 and 4, when the second connection layer 50 is the connection layer adjacent to the third doped segment 63, the first doped layer 20 needs to be disconnected at the second connection layer 50. This results in a portion of the first doped layer 20 being isolated between the third doped segment 63 and the second connection layer 50 adjacent to the third doped segment 63. Consequently, the current in this portion of the doped layer cannot be collected. However, by connecting the third doped segment 63 and the first doped layer 20 together, these isolated first doped layers 20 can form a whole with the third doped segment 63, thereby achieving current collection.

[0081] Of course, it is understandable that in some embodiments, when the first connection layer 40 is the connection layer adjacent to the third doped segment 63, the third doped segment 63 may be disposed close to the first connection layer 40 or directly connected to the first connection layer 40 to form a whole.

[0082] Please refer to Figures 3 and 4. In some embodiments, the first doped segment 61 may be connected to the end of the first connection layer 40.

[0083] In this way, the first doped segment 61 and the first connecting layer 40, which belong to the same doping type, can be connected into a whole without isolating them. This can reduce the area of ​​the ineffective region of the entire silicon substrate 10 (i.e., the area covered by the doped layer) and improve the efficiency of the back contact cell 100.

[0084] Similarly, in some embodiments, the second doped segment 62 may be connected to the other end of the first connection layer 40. In this way, the second doped segment 62 and the first connection layer 40, which belong to the same doping type, can be connected into a whole without isolating them, which can reduce the area of ​​the ineffective region of the entire silicon substrate 10 (i.e., the area covered by the doped layer) and improve the efficiency of the back contact cell 100.

[0085] Referring to Figures 3 and 4, in some embodiments, a first sub-gate 21 is provided on the first doped layer 20, and a second sub-gate 31 is provided on the second doped layer 30. Both the first sub-gate 21 and the second sub-gate 31 extend along a second direction. The first sub-gate 21 is disconnected at the second connecting layer 50, and the second sub-gate 31 is disconnected at the first connecting layer 40. A third sub-gate 611 is provided on the first doped section 61, and a fourth sub-gate 621 is provided on the second doped section 62. The third sub-gate 611 and the fourth sub-gate 621 extend continuously along the second direction. A fifth sub-gate 631 is provided on the third doped section 63, and the fifth sub-gate 631 extends continuously along a first direction.

[0086] In this way, current can be collected by setting sub-gates on each doped layer and each doped segment, and then the current can be output through the main gate, solder strip, or both the main gate and solder strip.

[0087] Specifically, in this embodiment, the first sub-gate 21 is used to collect the current of the first doped layer 20, the second sub-gate 31 is used to collect the current of the second doped layer 30, the third sub-gate 611 is used to collect the current of the first doped segment 61, the fourth sub-gate 621 is used to collect the current of the second doped segment 62, and the fifth sub-gate 631 is used to collect the current of the third doped segment 63. It is easy to understand that in the back contact battery 100, the first surface 11 is covered with a passivation film layer. Each sub-gate can form an ohmic contact with the corresponding doped layer or doped segment by burning through the passivation film layer or by laser grooving, thereby achieving current collection.

[0088] Further, referring to FIG5, in some embodiments, the back contact battery 100 may be a back contact battery with a main grid. In such a case, a first main grid 70 is provided on the first connection layer 40. The first main grid 70 extends along a first direction and is electrically connected to the first sub-grid 21, the third sub-grid 611 and the fourth sub-grid 621.

[0089] The second connection layer 50 is provided with a second main gate 80, which extends along the first direction and is electrically connected to the second sub-gate 31. The second main gate 80 is not electrically connected to the first sub-gate 21, the third sub-gate 611 and the fourth sub-gate 621.

[0090] Thus, by setting a first main gate 70 and a second main gate 80 on the first connection layer 40 and the second connection layer 50, the first main gate 70 can combine the current collected by the first sub-gate 21, the third sub-gate 611 and the fourth sub-gate 621, and the second main gate 80 can combine the current collected by the second sub-gate 31.

[0091] Of course, in other embodiments, the back contact battery 100 may be a gridless back contact battery. In such cases, pads may be directly provided on the sub-grid for welding with the solder strip. No specific restrictions are imposed here.

[0092] Referring to Figure 4, in some embodiments, the fifth sub-gate 631 is electrically connected to the third sub-gate 611 and the fourth sub-gate 621, and the fifth sub-gate 631 is not electrically connected to the second sub-gate 31.

[0093] Thus, by connecting the fifth sub-gate 631 on the third doped section 63 to the third sub-gate 611 on the first doped section 61 and the fourth sub-gate 621 on the second doped section 62, the current collected by the fifth sub-gate 631 can be directly fed to the first main gate 70 through the third sub-gate 611 and the fourth sub-gate 621, without the need to set a main gate and solder strip on the third doped section 63 for current collection and output, and without the need to solder at the edge of the silicon substrate 10, thus avoiding stress concentration at the edge during soldering and causing wafer cracking.

[0094] Specifically, in such an embodiment, the portions at both ends of the third doped segment 63 can be connected to the first doped segment 61 and the second doped segment 62, respectively. In this case, when printing the sub-gate, a continuous sub-gate is formed on the first doped segment 61, the third doped segment 63 and the second doped segment 62. The continuous sub-gate is in contact with the doped segment below. The third sub-gate 611, the fifth sub-gate 631 and the fourth sub-gate 621 can be connected in sequence.

[0095] Furthermore, in some embodiments, the widths of the third sub-gate 611 and the fourth sub-gate 621 in the first direction are greater than the widths of the first sub-gate 21 and the second sub-gate 31 in the first direction.

[0096] Thus, when no main gate and solder strip are provided on the third doped section 63, the third sub-gate 611 and the fourth sub-gate 621, in addition to collecting the current from the first doped section 61 and the second doped section 62, also undertake the transmission of the current collected by the fifth sub-gate 631. Setting the width of the third sub-gate 611 and the fourth sub-gate 621 to be wider can reduce the loss in the transmission process, thereby ensuring the reliability of collection and current collection.

[0097] As shown in Figure 5, in some embodiments, a third main gate 90 may also be provided on the third doped section 63. The third main gate 90 extends continuously along the first direction and is electrically connected to the fifth sub-gate 631, and the third main gate 90 is not electrically connected to the second sub-gate 31.

[0098] In such an embodiment, the third main gate 90 can be used to weld with the solder strip to achieve a bus output, and the third main gate 90 can cover the fifth sub-gate 631 and form an integral part of the fifth sub-gate 631.

[0099] In some embodiments, the width of the fifth sub-gate 631 in the second direction is greater than the widths of the first sub-gate 21 and the second sub-gate 31 in the first direction.

[0100] In this way, it is not necessary to set a main gate on the fifth sub-gate 631. Instead, a pad can be set directly on the fifth sub-gate 631 for soldering with the solder strip. Making the fifth sub-gate 631 wider can increase the soldering area between the solder strip and the fifth sub-gate 631, thereby improving the reliability and stability of the soldering. That is to say, in the embodiments of this disclosure, the third main gate 90 may not be set on the third doped section 63.

[0101] In some embodiments, the width of a portion of the fifth sub-gate 631 (e.g., the position where it is welded to the solder strip) in the second direction may be greater than the width of the first sub-gate 21 and the second sub-gate 31 in the first direction.

[0102] That is to say, in the embodiments of this disclosure, at least a portion of the fifth sub-gate 631 may have a width in the second direction that is greater than the widths of the first sub-gate 21 and the second sub-gate 31 in the first direction.

[0103] Referring to Figure 5, in some embodiments, the second main gate 80 does not extend over the first doped section 61 and the second doped section 62.

[0104] In this way, leakage can be avoided due to contact between the second main gate 80, the third sub-gate 611, and the fourth sub-gate 621.

[0105] Of course, referring to Figure 6, in some embodiments, the second main gate 80 may also extend above the first doped section 61 and the second doped section 62 and intersect with the third sub-gate 611 and the fourth sub-gate 621. In this case, a first insulating layer 110 is provided at the location where the third sub-gate 611 and the fourth sub-gate 621 intersect with the second main gate 80, and the second main gate 80 is located above the first insulating layer 110. Thus, even if the second main gate 80 extends above the first doped section 61 and the second doped section 62, it can still achieve insulation between itself and the third sub-gate 611 and the fourth sub-gate 621 through the first insulating layer 110 to avoid leakage.

[0106] Referring to Figures 3-6, in some embodiments, the third doped layer 60 may further include a fourth doped segment 64. The fourth doped segment 64 is disposed at the fourth edge 114 and extends continuously along the first direction. The fourth doped segment 64 is insulated from the second doped layer 30. A sixth sub-gate 641 is provided on the fourth doped segment 64, and the sixth sub-gate 641 extends continuously along the first direction. The location of the fourth doped segment 64 at the fourth edge 114 may be such that the right edge of the fourth doped segment 64 coincides with the fourth edge 114, or there may be a predetermined distance between the upper edge of the fourth doped segment 64 and the fourth edge 114. This distance can be determined according to the specific manufacturing process and is not limited here. For example, the fourth doped segment 64 may extend from the first edge 111 to the second edge 112.

[0107] Thus, by providing a fourth doped segment 64 at the position of the fourth edge 114 with a doping type opposite to that of the silicon substrate 10, the area ratio of the emitter of the back contact cell 100 can be further increased, thereby improving efficiency.

[0108] Please refer to Figure 4. In some embodiments, the two ends of the fourth doped segment 64 are connected to the first doped segment 61 and the second doped segment 62, respectively.

[0109] Thus, the first doped section 61, the second doped section 62, and the fourth doped section 64 can be treated as a whole, without the need to isolate the fourth doped section 64 from the first doped section 61 or from the second doped section 62. This reduces the area of ​​the ineffective region (i.e., the area covered by the doped layer) of the entire silicon substrate 10, improving the efficiency of the back contact cell 100. Furthermore, when setting up a sub-gate for current collection or setting up a main gate, solder strip, or a combination of main gate and solder strip for current convergence, it is only necessary to turn on the sub-gates on the first doped section 61, the second doped section 62, and the fourth doped section 64 to collect current from the fourth doped section 64, without needing to set up a main gate on the fourth doped section 64.

[0110] Specifically, as shown in Figure 4, in such an embodiment, the first doped segment 61, the third doped segment 63, the second doped segment 62, and the fourth doped segment 64 can be connected end to end in a square shape.

[0111] Of course, it is understood that, as shown in Figures 5 and 6, in some other embodiments, the two ends of the fourth doped segment 64 may not be connected to the first doped segment 61 and the second doped segment 62, and no specific restrictions are imposed here.

[0112] Please refer to Figures 3-6. In some embodiments, the fourth doped segment 64 may be connected to several first doped layers 20.

[0113] In this way, the fourth doped segment 64 can be connected to the first doped layer 20 as a whole without isolating the two, and the area of ​​the ineffective region of the entire silicon substrate 10 (i.e. the area covered by the doped layer) can be reduced, thereby improving the efficiency of the back contact cell 100.

[0114] Meanwhile, when the second connection layer 50 is the connection layer adjacent to the fourth doped segment 64, the first doped layer 20 needs to be disconnected at the second connection layer 50. This results in a portion of the first doped layer 20 being isolated between the fourth doped segment 64 and the second connection layer 50 adjacent to the fourth doped segment 64. This prevents the circuit of this part of the doped layer from being collected. However, by connecting the fourth doped segment 64 and the first doped layer 20 together, these isolated first doped layers 20 can be integrated with the fourth doped segment 64 to form a whole, thereby achieving current collection.

[0115] Of course, it is understandable that in some embodiments, when the first connection layer 40 is the connection layer adjacent to the fourth doped segment 64, the fourth doped segment 64 may be disposed close to the first connection layer 40 or directly connected to the first connection layer 40 to form a whole.

[0116] Referring to Figure 4, in some embodiments, the sixth sub-gate 641 is electrically connected to the third sub-gate 611 and the fourth sub-gate 621, and the sixth sub-gate 641 is not electrically connected to the second sub-gate 31.

[0117] Thus, by connecting the sixth sub-gate 641 on the fourth doped section 64 with the third sub-gate 611 on the first doped section 61 and the fourth sub-gate 621 on the second doped section 62, the current collected by the sixth sub-gate 641 can be directly fed to the first main gate 70 through the third sub-gate 611 and the fourth sub-gate 621, without the need to set a main gate and solder strip on the fourth doped section 64 for current collection and output, and without the need to solder at the edge of the silicon substrate 10, thus avoiding stress concentration at the edge during soldering and causing wafer cracking.

[0118] Specifically, in such an embodiment, the portions of the fourth doped segment 64 at both ends can be connected to the first doped segment 61 and the second doped segment 62, respectively. In this case, when printing the sub-gate, a continuous sub-gate is formed on the first doped segment 61, the fourth doped segment 64 and the second doped segment 62. The continuous sub-gate is in contact with the doped segment below, that is, the third sub-gate 611, the sixth sub-gate 641 and the fourth sub-gate 621 are connected in sequence.

[0119] As shown in Figure 4, in some embodiments, the first doped segment 61, the third doped segment 63, the second doped segment 62 and the fourth doped segment 64 are connected end to end in a square shape, and the third sub-gate 611, the fifth sub-gate 631, the fourth sub-gate 621 and the sixth sub-gate 641 are also connected end to end in a square shape.

[0120] As shown in Figure 5, in some embodiments, a fourth main gate 120 may also be provided on the fourth doped section 64. The fourth main gate 120 extends continuously along the first direction and is electrically connected to the fifth sub-gate 631, and the fourth main gate 120 is not electrically connected to the second sub-gate 31.

[0121] In such an embodiment, the fourth main gate 120 can be used to weld with a solder strip to achieve a bus output, and the fourth main gate 120 can cover the sixth sub-gate 641 and form an integral part with the fifth sub-gate 631.

[0122] In some embodiments, the width of the sixth sub-gate 641 in the second direction is greater than the widths of the first sub-gate 21 and the second sub-gate 31 in the first direction.

[0123] In this way, it is not necessary to set a main gate on the sixth sub-gate 641. Instead, a pad can be set directly on the sixth sub-gate 641 for soldering with the solder strip. Making the sixth sub-gate 641 wider can increase the soldering area between the solder strip and the sixth sub-gate 641, thereby improving the reliability and stability of the soldering. That is to say, in the embodiments of this disclosure, the fourth main gate 120 may not be set on the fourth doped section 64.

[0124] In some embodiments, the width of a portion of the sixth sub-gate 641 (e.g., the position where it is welded to the solder strip) in the second direction may be greater than the width of the first sub-gate 21 and the second sub-gate 31 in the first direction.

[0125] That is to say, in the embodiments of this disclosure, at least a portion of the sixth sub-gate 641 may have a width in the second direction that is greater than the widths of the first sub-gate 21 and the second sub-gate 31 in the first direction.

[0126] Please refer to Figures 7-9. In some embodiments, the fourth edge 114 may not be a fourth doped segment 64 with the opposite doping type to the silicon substrate 10, but a doped layer with the same doping type as the silicon substrate 10.

[0127] Specifically, in this case, please refer to Figures 1 and 7-9. A fourth doped layer 130 may be stacked on the edge region 115. The fourth doped layer 130 is disposed at the fourth edge 114 and extends continuously along the first direction. The doping type of the fourth doped layer 130 is opposite to that of the third doped layer 60 and the same as that of the silicon substrate 10. The fourth doped layer 130 is insulated from the first doped layer 20, the first doped segment 61 and the second doped segment 62. A seventh sub-gate 131 is provided on the fourth doped layer 130. The seventh sub-gate 131 extends continuously along the first direction and is not electrically connected to the third sub-gate 611 and the fourth sub-gate 621.

[0128] Furthermore, as shown in FIG7, in some embodiments, when the connection layer closest to the fourth doped layer 130 is a first connection layer 40 and there is a first doped layer 20 and a second doped layer 30 between the first connection layer 40 and the fourth doped layer 130, the fourth doped layer 130 can be connected to a plurality of second doped layers 30. In this way, the fourth doped layer 130 and the second doped layers 30 can be connected into a whole without isolating them, which can also reduce the area of ​​the ineffective region of the entire silicon substrate 10 (i.e., the area covered by the doped layer) and improve the efficiency of the back contact cell 100.

[0129] Meanwhile, when the first connection layer 40 is the connection layer adjacent to the fourth doped layer 130, the second doped layer 30 needs to be disconnected at the first connection layer 40. This results in a portion of the second doped layer 30 being isolated between the fourth doped layer 130 and the second connection layer 50 adjacent to the fourth doped layer 130. This prevents the circuit of this part of the doped layer from being collected. However, by connecting the fourth doped layer 130 and the second doped layer 30 together, these isolated second doped layers 30 can be integrated with the fourth doped layer 130 to form a whole, thereby achieving current collection.

[0130] Of course, as shown in Figures 8 and 9, in some embodiments, when the connection layer closest to the fourth doped layer 130 is the first connection layer 40 and there is no first doped layer 20 and second doped layer 30 between the first connection layer 40 and the fourth doped layer 130, the fourth doped layer 130 may be spaced apart from the first connection layer 40.

[0131] Please refer to Figures 7-9. In some embodiments, a fifth main gate 140 is provided on the fourth doped layer 130. The fifth main gate 140 extends continuously along the first direction and is electrically connected to the seventh sub-gate 131. The fifth main gate 140 is not electrically connected to the first sub-gate 21, the third sub-gate 611 and the fourth sub-gate 621.

[0132] Thus, by setting the fifth main gate 140 on the fourth doped layer 130, current collection and output can be achieved.

[0133] In some embodiments, the width of the seventh sub-gate 131 in the second direction is greater than the widths of the first sub-gate 21 and the second sub-gate 31 in the first direction. Thus, it is not necessary to provide a main gate on the seventh sub-gate 131; instead, pads can be directly provided on the seventh sub-gate 131 for soldering with the solder ribbon. Making the seventh sub-gate 131 wider increases the soldering area between the solder ribbon and the seventh sub-gate 131, improving the reliability and stability of the soldering. That is to say, in embodiments of this disclosure, the fifth main gate 140 may not be provided on the fourth doped layer 130.

[0134] In some embodiments, the width of a portion of the seventh sub-gate 131 (e.g., the position where it is welded to the solder strip) in the second direction may be greater than the width of the first sub-gate 21 and the second sub-gate 31 in the first direction.

[0135] That is to say, in the embodiments of this disclosure, at least a portion of the seventh sub-gate 131 may have a width in the second direction that is greater than the widths of the first sub-gate 21 and the second sub-gate 31 in the first direction.

[0136] Referring to Figures 7 and 8, in some embodiments, the extension of the fourth doped layer 130 along the first direction intersects the first doped segment 61 and the second doped segment 62. The fifth main gate 140 does not extend above the first doped segment 61 and the second doped segment 62.

[0137] In this way, leakage can be avoided due to contact between the fifth main gate 140, the third sub-gate 611, and the fourth sub-gate 621.

[0138] Of course, referring to Figure 9, in some embodiments, the fifth main gate 140 may also extend above the first doped section 61 and the second doped section 62 and intersect with the third sub-gate 611 and the fourth sub-gate 621. In this case, a second insulating layer 150 is provided at the location where the third sub-gate 611 and the fourth sub-gate 621 intersect with the fifth main gate 140, and the fifth main gate 140 is located above the second insulating layer 150. Thus, even if the fifth main gate 140 extends above the first doped section 61 and the second doped section 62, it can still achieve insulation between itself and the third sub-gate 611 and the fourth sub-gate 621 through the second insulating layer 150 to avoid leakage.

[0139] In some embodiments, as shown in FIG5, a first sub-gate 21 is provided on the first doped layer 20, and a second sub-gate 31 is provided on the second doped layer 30. Both the first sub-gate 21 and the second sub-gate 31 extend along a second direction. The first sub-gate 21 is disconnected at the second connecting layer 50, and the second sub-gate 31 is disconnected at the first connecting layer 40. A third sub-gate 611 is provided on the first doped section 61, and a fourth sub-gate 621 is provided on the second doped section 62. The third sub-gate 611 and the fourth sub-gate 621 extend continuously along the second direction. A fifth sub-gate 631 is not provided on the third doped section 63, but a third main gate 90 is provided on the third doped section 63. The third main gate 90 extends continuously along the first direction, and the third main gate 90 is not electrically connected to the second sub-gate 31. This reduces the need to print the fifth sub-gate, thus reducing paste consumption.

[0140] In some embodiments, as shown in FIG5, a first sub-gate 21 is provided on the first doped layer 20, and a second sub-gate 31 is provided on the second doped layer 30. Both the first sub-gate 21 and the second sub-gate 31 extend along a second direction. The first sub-gate 21 is disconnected at the second connecting layer 50, and the second sub-gate 31 is disconnected at the first connecting layer 40. The third doped layer 60 further includes a fourth doped segment 64, which is disposed at the fourth edge 114 and extends continuously along the first direction. The fourth doped segment 64 is insulated from the second doped layer 30. The fourth doped segment 64 does not have a sixth sub-gate 641, but it has a fourth main gate 120, which extends continuously along the first direction and is not electrically connected to the second sub-gate 31. This reduces the need to print a sixth sub-gate, thus reducing paste consumption.

[0141] As an example, the main grid can use either a non-burn-through slurry or a burn-through slurry, and those skilled in the art can make the setting according to actual needs.

[0142] In the description of this specification, references to terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with the described embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0143] Furthermore, the above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A back-contact battery, wherein, include: A silicon substrate having opposing first and second surfaces, the first surface having opposing first and second edges along a first direction, and opposing third and fourth edges along a second direction, the second direction intersecting the first direction; the first surface including an edge region and a middle region, the edge region surrounding the middle region; A plurality of first doped layers, a plurality of second doped layers, a plurality of first connecting layers, and a plurality of second connecting layers are disposed on the intermediate region. The first doped layers and the second doped layers are arranged alternately along the first direction and extend intermittently along the second direction. The first connecting layers and the second connecting layers are arranged alternately along the second direction and extend along the first direction. The first doped layer is connected to the first connecting layer and disconnected at the second connecting layer. The second doped layer is connected to the second connecting layer and disconnected at the first connecting layer. The doping types of the first doped layer and the second doped layer are opposite. and A third doped layer is disposed on the edge region. The doping type of the third doped layer is opposite to that of the silicon substrate, and the doping type of the third doped layer is the same as that of the first doped layer and the first interconnecting layer. The third doped layer includes a first doped segment, a second doped segment, and a third doped segment. The first doped segment is disposed at the first edge and extends continuously along the second direction. The second doped segment is disposed at the second edge and extends continuously along the second direction. The third doped segment is disposed at the third edge and extends continuously along the first direction. The first doped segment, the second doped segment, and the third doped segment are all insulated from the second doped layer.

2. The back contact battery according to claim 1, wherein, When the silicon substrate is p-type doped, the first doped layer and the first interconnecting layer are n-type doped, the second doped layer and the second interconnecting layer are p-type doped, and the third doped layer is n-type doped. When the silicon substrate is doped with n-type doping, the first doped layer and the first connecting layer are doped with p-type doping, the second doped layer and the second connecting layer are doped with n-type doping, and the third doped layer is doped with p-type doping.

3. The back contact battery according to claim 1, wherein, The third doped segment satisfies at least one of the following: both ends of the third doped segment are respectively connected to the first doped segment and the second doped segment; the third doped segment is connected to a plurality of the first doped layers.

4. The back contact battery according to claim 1, wherein, The first connection layer satisfies at least one of the following: the first doped segment is connected to the end of the first connection layer; the second doped segment is connected to the end of the first connection layer.

5. The back contact battery according to claim 1, wherein, A first sub-gate is provided on the first doped layer, and a second sub-gate is provided on the second doped layer. Both the first sub-gate and the second sub-gate extend along the second direction. The first subgate is disconnected at the second connection layer, and the second subgate is disconnected at the first connection layer; The first doped section has a third sub-gate, the second doped section has a fourth sub-gate, the third sub-gate and the fourth sub-gate extend continuously along the second direction, and the third doped section has a fifth sub-gate, the fifth sub-gate extends continuously along the first direction.

6. The back contact battery according to claim 5, wherein, The first connection layer is provided with a first main gate, which extends along the first direction and is electrically connected to the first sub-gate, the third sub-gate and the fourth sub-gate; The second connection layer is provided with a second main gate, which extends along the first direction and is electrically connected to the second sub-gate, and the second main gate is not electrically connected to the first sub-gate, the third sub-gate and the fourth sub-gate.

7. The back contact battery according to claim 6, wherein, The second main gate does not extend above the first doped section and the second doped section; or The second main gate extends above the first doped section and the second doped section and intersects with the third sub-gate and the fourth sub-gate. A first insulating layer is provided at the position where the third sub-gate and the fourth sub-gate intersect with the second main gate, and the second main gate is located above the first insulating layer.

8. The back contact battery according to claim 5, wherein, The fifth sub-gate is electrically connected to the third and fourth sub-gates, but is not electrically connected to the second sub-gate.

9. The back contact battery according to claim 5, wherein, The widths of the third and fourth sub-gates in the first direction are greater than the widths of the first and second sub-gates in the first direction.

10. The back contact battery according to claim 5, wherein, The third doped section is further provided with a third main gate, which extends continuously along the first direction and is electrically connected to the fifth sub-gate, and the third main gate is not electrically connected to the second sub-gate; Alternatively, at least a portion of the fifth sub-gate has a width in the second direction that is greater than the widths of the first sub-gate and the second sub-gate in the first direction; or, the third doped section is further provided with a third main gate, the third main gate extending continuously along the first direction and electrically connected to the fifth sub-gate, and the third main gate not electrically connected to the second sub-gate, wherein at least a portion of the fifth sub-gate has a width in the second direction that is greater than the widths of the first sub-gate and the second sub-gate in the first direction.

11. The back contact battery according to claim 5, wherein, The third doped layer further includes a fourth doped segment, which is disposed at the fourth edge and extends continuously along the first direction. The fourth doped segment is insulated from the second doped layer. A sixth sub-gate is provided on the fourth doped segment, which extends continuously along the first direction.

12. The back contact battery according to claim 11, wherein, The fourth doped segment satisfies at least one of the following: both ends of the fourth doped segment are connected to the first doped segment and the second doped segment, respectively; the fourth doped segment is connected to a plurality of the first doped layers.

13. The back contact battery according to claim 12, wherein, The sixth sub-gate is electrically connected to the third and fourth sub-gates, but is not electrically connected to the second sub-gate; Alternatively, a fourth main gate is provided on the fourth doped section, the fourth main gate extends continuously along the first direction and is electrically connected to the sixth sub-gate, and the fourth main gate is not electrically connected to the second sub-gate; or, the sixth sub-gate is electrically connected to the third sub-gate and the fourth sub-gate, and the sixth sub-gate is not electrically connected to the second sub-gate, the fourth main gate is provided on the fourth doped section, the fourth main gate extends continuously along the first direction and is electrically connected to the sixth sub-gate, and the fourth main gate is not electrically connected to the second sub-gate.

14. The back contact battery according to claim 5, wherein, A fourth doped layer is also stacked on the edge region. The fourth doped layer is disposed at the fourth edge and extends continuously along the first direction. The doping type of the fourth doped layer is opposite to that of the third doped layer. The fourth doped layer is insulated from the first doped layer, the first doped segment, and the second doped segment. The fourth doped layer has a seventh sub-gate, which extends continuously along the first direction and is not electrically connected to the third sub-gate and the fourth sub-gate.

15. The back contact battery according to claim 14, wherein, The fourth doped layer is connected to several second doped layers.

16. The back contact battery according to claim 14, wherein, A fifth main gate is provided on the fourth doped layer. The fifth main gate extends continuously along the first direction and is electrically connected to the seventh sub-gate. The fifth main gate is not electrically connected to the first sub-gate, the third sub-gate, and the fourth sub-gate. Alternatively, at least a portion of the seventh sub-gate has a width in the second direction that is greater than the widths of the first sub-gate and the second sub-gate in the first direction. Or, a fifth main gate is provided on the fourth doped layer. The fifth main gate extends continuously along the first direction and is electrically connected to the seventh sub-gate. The fifth main gate is not electrically connected to the first sub-gate, the third sub-gate, and the fourth sub-gate. At least a portion of the seventh sub-gate has a width in the second direction that is greater than the widths of the first sub-gate and the second sub-gate in the first direction.

17. The back contact battery according to claim 16, wherein, The extension line of the fourth doped layer along the first direction intersects the first doped segment and the second doped segment; Wherein, the fifth main gate does not extend above the first doped section and the second doped section; or, the fifth main gate extends above the first doped section and the second doped section and intersects with the third sub-gate and the fourth sub-gate, a second insulating layer is provided at the position where the third sub-gate and the fourth sub-gate intersect with the fifth main gate, and the fifth main gate is located above the second insulating layer.

18. The back contact battery according to claim 1, wherein, A first sub-gate is provided on the first doped layer, and a second sub-gate is provided on the second doped layer. Both the first sub-gate and the second sub-gate extend along the second direction. The first subgate is disconnected at the second connection layer, and the second subgate is disconnected at the first connection layer; The first doped section has a third sub-gate, the second doped section has a fourth sub-gate, the third sub-gate and the fourth sub-gate extend continuously along the second direction, the third doped section does not have a fifth sub-gate, the third doped section has a third main gate, the third main gate extends continuously along the first direction, and the third main gate is not electrically connected to the second sub-gate.

19. The back contact battery according to claim 1, wherein, A first sub-gate is provided on the first doped layer, and a second sub-gate is provided on the second doped layer. Both the first sub-gate and the second sub-gate extend along the second direction. The first subgate is disconnected at the second connection layer, and the second subgate is disconnected at the first connection layer; The third doped layer further includes a fourth doped segment, which is disposed at the fourth edge and extends continuously along the first direction. The fourth doped segment is insulated from the second doped layer. The fourth doped segment does not have a sixth sub-gate but has a fourth main gate, which extends continuously along the first direction and is not electrically connected to the second sub-gate.

20. A battery assembly, wherein, Includes the back contact battery as described in any one of claims 1-19.

21. A photovoltaic system, wherein, Includes the battery assembly as described in claim 20.

Images