Semiconductor element having a resistive region in the source region

Abstract

The invention relates to a semiconductor component, preferably a power semiconductor component, preferably a power semiconductor component based on a wide-band gap material, which is made of silicon carbide (SiC) in particular, comprising an active region consisting of at least one active half-cell, having a source region (9) in at least one half-cell, preferably in all half-cells, said source region being provided in a p-doped region (8) and having a resistive region (9c, 9d) for generating a voltage drop in the event of a short circuit.

Description

[0001] Description

[0002] Semiconductor element with a resistive region in the source area

[0003] Technical field

[0004] The invention relates to a semiconductor device, in particular a power semiconductor device, preferably based on silicon carbide (SiC) with a resistive region in the source region.

[0005] State of the art

[0006] A challenge with semiconductor devices such as trench-gate power MISFETs (metal-insulator-semiconductor field-effect transistors), especially those based on silicon carbide (SiC), is achieving good conduction characteristics, particularly a low area-specific RDSon*A, while maintaining good short-circuit withstand capability. Typically, the current flowing from drain to source through the device during a short circuit is significantly higher than during forward conduction. One approach to achieving good short-circuit withstand capability is to limit the current density during a short circuit to the lowest possible values. This limits the power dissipation density and the heating rate of the device, and allows for timely shutdown of the device before it is damaged or destroyed.

[0007] Generally, measures to reduce the current in the event of a short circuit lead to an increase in the area-specific RDSon*A, so a good compromise between these two requirements must be found. A known method for reducing the current density, especially in the event of a short circuit, is to introduce a resistive region in the source or source region of each cell of the device's active region, which consists of a multitude of parallel-connected cells, as described, for example, in US 9,825,126 B2. In the event of a short circuit, the current flowing from a drain metal through the substrate, the drift region, the inversion channel formed in the p-body region at the boundary with the gate oxide under the gate electrode, and the source region to the source contact results in a higher voltage drop in the source region than the smaller current in the forward-biased state. This leads to a reduction in the short-circuit current through a kind of negative feedback.

[0008] Disclosure of the invention

[0009] The invention relates to a semiconductor device, preferably a power semiconductor device, preferably based on a wide-bandgap material, in particular silicon carbide (SiC) or gallium nitride (GaN), more preferably 4H-SiC, with an active region comprising at least one active half-cell, having in at least one, preferably in all half-cells, a source region which is arranged in a p-doped region and has a resistive region for generating a voltage drop in the event of a short circuit, wherein the resistive region is realized as a section comprising several segments, having inner, n-doped segments and outer, p-doped segments which at least partially surround these in cross-sectional view, and which are arranged such that in the event of a short circuit a geometric constriction of an electron current through the section occurs from at least two sides.

[0010] The design according to the invention allows the electrical resistance acting in the direction of electron flow in the section to change and, in particular, increase with increasing temperature. This results in an increase in resistance due to geometric narrowing of the current path and, with increasing current density, increasing negative feedback. In contrast to the prior art, the narrowing of the current path occurs not only from one side, but from at least two sides. This achieves a very good compromise between low Ron*A and short-circuit withstand capability, since the current density is considerably higher in the case of a short circuit than in the forward-biased case of normal operation. In a preferred embodiment, the inner segments are arranged such that an electron current can flow through them substantially perpendicular to the cross-section.The outermost segments of the section are advantageously connected to the source potential or a potential of the same order of magnitude.

[0011] In a preferred embodiment, the inner segments comprise first inner segments and second inner segments adjacent to each of these. The outer segments advantageously comprise first outer segments adjacent to each of the second inner segments and second outer segments adjacent to each of these. The respective inner and outer segments are advantageously arranged in a cross-sectional view, preferably radially outward from a center or central area of ​​the source region, in a layered arrangement. In a preferred embodiment, the individual segments can be substantially parallel to each other in a cross-sectional view or arranged in a layered arrangement. The first and second inner segments, as well as the first and second outer segments, advantageously each comprise at least two segments, more advantageously at least three segments, and even more advantageously at least four segments.

[0012] In a preferred embodiment, the inner and outer segments of the section are arranged such that in the event of a short circuit and / or with increasing temperature, a geometric constriction of the electron current through the section occurs from at least three sides, more preferably from four sides.

[0013] The geometric constriction of the current path is caused by a space charge region that forms between the n- and p-regions and expands further along a path opposite to the current flow as the current flow increases and the voltage drop increases in the opposite direction. The extent of the space charge region in each segment encompassed by the space charge region is smaller the higher the doping concentration of the respective segment. Furthermore, a balanced charge distribution is established within a space charge region between exposed donors (i.e., those encompassed by the space charge region) in the n-doped region and exposed acceptors in the p-doped region.Therefore, the constriction of the cross-sectional area of ​​the current path lying outside the space charge region in an n-region is stronger if the constriction occurs from at least two sides than if it occurs from only one side, with the resistance modulation based on this geometric effect also being higher between conduction and short-circuit conditions.

[0014] In a preferred embodiment, the net doping of the inner, n-doped segments is less intense than that of the adjacent outer, preferably highly p-doped segments. The doping of the second outer p-doped segment is arbitrary and can be selected according to device-specific considerations. In this embodiment, the space charge regions extend substantially into the n-doped segments. The extent is small in the conduction state and large in the short-circuit state, depending on the choice of n-doping. In the limiting case, pinch-off preferably occurs.

[0015] In a preferred embodiment, the net doping of the first, inner n-doped segments is less dense than that of the second, inner segments arranged between them and the p-doped segments, wherein the p-doped segments adjacent to these are highly p-doped. Depending on the net doping level and thickness of these segments, this allows the space charge region to extend less into the n-doped segments during conduction than in the previously described preferred embodiment, because it encompasses the n-doped second, inner segments entirely or partially. As a result, the Ron*A remains small during conduction, and a noticeable geometric resistance modulation then occurs during a short circuit. In the limiting case, pinch-off preferably occurs.

[0016] In a further preferred embodiment, the net doping of the inner, n-doped segments is substantially equal to or higher than that of the adjacent first outer, p-doped segments, wherein the second outer segments adjacent to these are highly p-doped. Depending on the net doping level and the thickness of the adjacent p-doped segments, the space charge region can be designed to extend predominantly into the p-doped segments during conduction. Only during short-circuit conditions do the space charge regions extend to the highly p-doped second outer segments, and above this current density, the space charge regions extend almost exclusively into the inner n-doped segments. This keeps the Ron*A small during conduction and results in a noticeable geometric resistance modulation during short-circuit conditions. In the limiting case, pinch-off is preferably achieved.

[0017] The semiconductor device can be configured as an n-channel trench MISFET. This preferably comprises a substrate, a drift region arranged above it, an n-doped spreading region arranged above it, a highly doped pPIus region, a p-doped pBody region laterally adjacent to a trench, a highly doped pPIus lid, a source contact region, and an adjacent n-doped region which is at least partially covered by the pPIus lid, wherein the source region is formed from parts of the pPIus lid that are arranged adjacently above the n-doped region, the n-doped region, and parts of the pBody region that are arranged adjacently below the n-doped region.

[0018] The semiconductor device can be advantageously designed as an n-channel trench MISFET with a V-shaped trench.

[0019] The semiconductor device can further advantageously be configured as an n-channel trench FinFET. This preferably comprises a substrate, a drift region arranged above it, an n-doped spreading region arranged above it, a highly doped pPIus region, a p-doped pBody region laterally adjacent to a trench, a deep pPIus contact region connecting the pBody region to a source metal, and a pPIus lid consisting of several segments with an intervening n-doped region, wherein the portion of the source region is arranged vertically and is formed from parts of the pPIus lid that are arranged laterally adjacent to the n-doped region and the intervening n-doped region.

[0020] The application of the invention is not limited to n-channel FinFETs with a p-body region, but can also be applied to p-channel FinFETs with an n-body region. Further advantages, features, and details of the invention will become apparent from the following description of preferred embodiments of the invention and from the drawings.

[0021] Brief description of the drawings

[0022] Figs. 1a-c each show a section through a layer structure of a planar MOSFET, a trench MISFET and a trench MISFET with a vertically arranged source region according to the prior art, each as half-cell 01 of the device;

[0023] Figs. 2 and 3 show preferred embodiments of the inventive section of the source region of the semiconductor device;

[0024] Figures 4a-7c each show a section through a layer structure of a half-cell of a semiconductor device according to the invention, in particular a trench MISFET; and

[0025] Figs. 8a-d each show a section through a layer structure of a half-cell of a semiconductor device according to the invention, in particular a FinFET;

[0026] Embodiments of the invention

[0027] Identical elements or elements with the same function are designated with the same reference numerals in the figures. The invention is described below, in particular, for a unit cell of a transistor.

[0028] Fig. 1a shows a half-cell 01 of a prior art planar MOSFET, comprising a substrate 13, a drift region 15 above it, a pBody region 8 with a Source region 9 arranged therein, and an associated gate oxide 6 with a gate electrode 4. The pBody region 8 is connected to the Source potential via a pPIus region 10. The Source 9 consists of a series connection of a highly doped contact region 9a to achieve a low-resistance contact with the Source metal 2, a resistive region 9c, 9d to generate a voltage drop, especially in the event of a short circuit, and a highly doped expansion region 9b to reduce the sensitivity of the short-circuit current to lateral adjustment tolerances from the Gate electrode 4 to the Source 9.

[0029] In the event of a short circuit, the current flowing from the drain metal 3 through the substrate 13, the drift region 15, the inversion channel formed in the p-body region 8 at the boundary with the gate oxide 6 under the gate electrode 4, and the source region 9 to the source contact 2, results in a higher voltage drop in the source region 9 than the smaller current in the forward-biased state. This leads to a reduction in the short-circuit current through a kind of negative feedback. A space charge region present between the source and p-body regions 9, 8, which expands as a result of a voltage drop, can extend into the resistive source region 9c, d and increase its resistance by constricting the current path. This geometrically constricts the current path from one side, leading to an increase in the resistance of the source region 9.

[0030] Fig. 1b shows a half-cell 02 of a prior art trench MOSFET. Here, the gate electrode 4 is arranged in a trench 5 lined with gate oxide 6. The basic operating principle corresponds to the embodiment according to Fig. 1a, wherein the trench MOSFET advantageously has a lower pitch compared to the planar MOSFET.

[0031] Fig. 1c shows a half-cell 03 of another trench MOSFET according to the prior art. In contrast to the embodiment according to Fig. 1b, this has a vertically arranged source region 9 in order to achieve a reduced pitch.

[0032] Figures 2 and 3 describe the basic structure of a source region 9 of a semiconductor device according to the invention. This is arranged in a p-doped region of the semiconductor device and comprises at least one section 1 as described below.

[0033] Section 1 has, in a cross-section as shown in Fig. 2, any number of segments of any cross-sectional shape and not necessarily constant doping. In cross-section AA' in Fig. 2, 4x4 segments are shown, of which inner segments 9c_1, 9c_2, 9c_3, 9c_4 and 9d_1, 9d_2, 9d_3, 9d_4 are n-doped and can be traversed by an electron current substantially perpendicular to the cross-section or perpendicular to the plane of the drawing in section AA', and outer segments 9e_1, 9e_2, 9e_3, 9e_4 and 9f_1, 9f_2, 9f_3, 9f_4 are p-doped, with the outermost segments 9f_1, 9f_2, 9f_3, 9f_4 being connected to source potential or a potential of the same order of magnitude.

[0034] These are arranged in the semiconductor device such that the electrical resistance acting in the direction of electron flow changes with increasing temperature, and in particular can increase. This increase in resistance occurs through geometric constriction of the current path from at least two sides, in this case four sides in Fig. 2, due to the space charge region that forms between the n- and p-doped regions and expands further along a path opposite to the current flow with increasing current flow and thus increasing voltage drop against the current direction. Space charge regions form between the n- and p-doped segments.If the outermost segments 9f_1, 9f_2, 9f_3, 9f_4 are connected to the reference potential and the n-doped segments 9c_1, 9c_2, 9c_3, 9c_4 and 9d_1, 9d_2, 9d_3, 9d_4 are brought to a positive potential in contrast, in particular by a current flow along the segment 1 into the cross-sectional area AA', the space charge regions expand.

[0035] A preferred embodiment of section 1 results when the net doping of the n-doped segments 9c_1, 9c_2, 9c_3, 9c_4 and 9d_1, 9d_2, 9d_3, 9d_4 is less than that of the adjacent, in this case very highly p-doped segments 9e_1, 9e_2, 9e_3, 9e_4. In this embodiment, the space charge region extends substantially into the n-doped segments 9c_1, 9c_2, 9c_3, 9c_4 and 9d_1, 9d_2, 9d_3, 9d_4. The extent is small in the conduction state and, in the short-circuit state, is large for the reasons mentioned above, provided the n-doping is chosen appropriately.

[0036] Another preferred embodiment of section 1 is obtained when the net doping of the innermost n-doped segments 9c_1, 9c_2, 9c_3, 9c_4 is less than that of the segments 9d_1, 9d_2, 9_3, 9d_4 arranged between them and the p-doped segments, and when, furthermore, the segments 9e_1, 9e_2, 9e_3, 9e_4 adjacent to these segments 9d_1, 9d_2, 9d_3, 9d_4 are highly p-doped. In this case, depending on the level of net doping and the thickness of these segments, it can be achieved that the space charge zone in the case of transmission extends less strongly into the n-doped segments 9c_1, 9c_2, 9c_3, 9c_4 than in the previously described preferred embodiment, because it encompasses the n-doped segments 9d_1, 9d_2, 9d_3, 9d_4 completely or partially.

[0037] Another preferred embodiment of section 1 is obtained when the net doping of the n-doped segments 9c_1, 9c_2, 9c_3, 9c_4 and 9d_1, 9d_2, 9d_3, 9d_4 is on the order of magnitude or higher than that of the adjacent p-doped segments 9e_1, 9e_2, 9e_3, 9e_4 and when, furthermore, the segments 9f_1, 9f_2, 9f_3, 9f_4 adjacent to the segments 9e_1, 9e_2, 9e_3, 9e_4 are highly p-doped. In this case, depending on the net doping level and the thickness of the adjacent p-doped segments 9e_1, 9e_2, 9e_3, 9e_4, the space charge region can be arranged so that, under conduction conditions, it extends predominantly into the p-doped segments 9e_1, 9e_2, 9e_3, 9e_4. Only under short-circuit conditions do the space charge regions extend to the highly p-doped segments 9f_1, 9f_2, 9f_3, 9f_4, and above this current density, the space charge region extends almost exclusively into the n-doped segments 9c_1, 9c_2, 9c_3, 9c_4 and 9d_1, 9d_2, 9d_3, 9d_4.

[0038] Corresponding further preferred embodiments of section 1 result from removing segments on one or more sides, e.g., in Fig. 2, segments 9d_3, 9e_3, 9f_3 or 9d_3, 9e_3, 9f_3 as well as 9d_1, 9e_1, 9f_1, and arranging the remaining segments, as shown in Fig. 3, essentially in layers. The fundamental possibilities of net doping and layer thickness geometry described in the preceding preferred embodiments are retained; however, the geometric constriction of the current path here only occurs from two sides.

[0039] Preferred embodiments of cells or half-cells in the active region of devices using the invention are described below. These embodiments utilize the previously described preferred embodiments of the section 1 in the source region 9 as shown. Unless otherwise described, cells are obtained from the half-cells by mirroring them across their lateral boundary planes. For clarity, the respective source metallization 2 is shown only schematically in the form of its ohmic contact region 20 with the semiconductor. An intermediate oxide that electrically insulates the source metal 2 is also omitted for clarity. Doping regions may exhibit locally non-constant doping. The buffer shown is optional. The gate dielectric 4 may be thicker at the bottom of the trench 5 than at other locations.The boundaries of areas shown should not be considered restrictive with regard to a type or sequence of production.

[0040] Fig. 4a shows a first preferred embodiment of the half-cell 100 of the semiconductor device and in particular of an n-channel SiC trench MISFET using the inventive sub-region 1 in a source region 9.The device comprises a highly n-doped substrate 13 contacted with a drain metallization 3, an n-doped buffer 14 arranged above it, a drift region 15 arranged above it, an n-doped spreading region 11 arranged above it, which is created epitaxially and / or by means of additional implantation and has a higher doping concentration than the drift region 15, a highly doped pPIus region 10 which extends vertically at least into or penetrates the spreading region 11, and a moderately p-doped pBody region 8 which is arranged on the spreading region 11 and laterally adjoins a trench 5 which extends from the semiconductor surface at least into the spreading region 11 and is lined with a gate dielectric 6, which is a highly n-doped material, typically consisting of polysilicon or another highly conductive material. Gate electrode 4 at least partially encloses.

[0041] The gate electrode 4 is separated by the gate dielectric 6 from at least an n-doped portion of the source region 9. The pBody region 8 is connected to the source metal 2 (see also Fig. 1a-c) via at least one pPIus region 10. A highly doped pPIus cover 30 borders the pPIus region 10 laterally and has openings for the island-shaped, highly n-doped source contact regions 9a. The pPIus cover 30 at least partially covers the n-doped region 31, which borders the source contact regions 9a and is connected to the source metal 2 via these. The source contact regions 9a can extend vertically to a greater depth than the n-doped area 31. The source area optionally includes a source extension region 9b, which can extend vertically to a greater depth than the n-doped area 31. This depth can also differ from that of areas 9a.Optionally, the source extension region 9b can extend vertically into the pPIus cover 30, or even reach the semiconductor surface, and optionally be overdoped in each case. The optional source extension region 9b enables only low sensitivity of the short-circuit current to lateral tolerances of the distance between the source contact region and the trench 5 with gate electrode 4. The source Meta II (see contact area 20) contacts at least the source contact regions 9a and the pPIus region 10, and optionally also the pPIus cover 30, but must not contact the optional source extension region 9b if it extends to the semiconductor surface. In this case, a smaller lateral distance between the source metal 2 and the trench 5 and the gate electrode 4 is possible than in the prior art according to Fig. 1b, since the pPIus cover 30 prevents a complete or partial short-circuiting of the area 31.

[0042] The inventive subregion 1 of the source region 9 is formed in the present case from parts of the pPIus cover 30, where it is arranged adjacently above region 31 and corresponds to segments 9f_2, 9e_2 of subregion 1, and from region 31, which there corresponds to segments 9d_2, 9c_2, 9c_4, 9d_4 of subregion 1, and the corresponding parts of the pBody region 8, where it is arranged adjacently below region 31 and corresponds to segment 9e_4 of subregion 1. A current path constriction in the source region 31, particularly in the case of a short circuit, occurs here essentially from two sides: from above, starting from the pPIus cover 30, and from below, starting from the Body region 8.

[0043] If the pPIus lid 30, the source region 9, and the regions located below it are created by implantation, the pn transition between the pPIus lid 30 and the source region 9 can generally be implemented more abruptly than between the source region 9 and the regions located below it, because the implantation profiles are less locally concentrated with increasing depth. Therefore, a design with a pPIus lid is particularly advantageous in all variants, as the current path constriction from this direction can be made especially effective.

[0044] Fig. 4b shows a second preferred embodiment of the half-cell 200.

[0045] The difference from Fig. 4a lies in the highly p-doped, buried pPIus region 32, which is located laterally at least adjacent to parts of region 31. This region is connected to the source metal 2 via the pBody region 8 and the pPIus region 10. Laterally, it is spaced away from the trench 5 to prevent an undesirable increase in the threshold stress Vth. The source contact regions 9a and the optional source extension region 9b can optionally extend vertically into the pPIus region 32 or even to a greater depth.

[0046] The inventive sub-region 1 of the source region 9 is formed from parts of the pPIus cover 30, where it is arranged adjacently above region 31 and corresponds to segments 9f_2, 9e_2 of sub-region 1, and from region 31, which corresponds there to segments 9d_2, 9c_2, 9c_4, 9d_4 of sub-region 1, and from the corresponding parts of the buried pPIus region 32, where it is arranged adjacently below region 31 and corresponds to segments 9e_4, 9f_4 of sub-region 1. A current path constriction, particularly in the case of a short circuit, occurs here essentially from two sides, with the constriction originating from pPIus region 32 being more effective than that caused by the pBody region 8 in the embodiment described above.

[0047] Compared to the embodiment shown in Fig. 1b, the half-cell 200 has the advantage that a high doping density is possible in the depth of parts of the p-body region 8 without significantly increasing the threshold voltage Vth. Furthermore, region 32 makes punch-through of the channel region—i.e., the merging of the space charge region onto the source region and the weakening or reduction of the potential barrier between the source and channel regions, which could occur especially at high drain voltages—virtually impossible. This makes the transistor significantly less sensitive to short-channel effects, particularly at high drain voltages. Thus, the channel can be made shorter, which improves the transistor's performance and, in particular, reduces RdsonA.

[0048] Fig. 5a shows another preferred embodiment of the half-cell 300 of an n-channel SiC trench MISFET utilizing the sub-region 1. The difference from Fig. 4a lies in the strip-shaped design of the lateral dimensions of the source contact regions 9a. Therefore, the pPIus cover 30 is directly contacted by the source metal 2. The other structural properties and the basic operating principle correspond to the half-cell 100 in Fig. 4a. Analogous to the embodiment according to Fig. 4b, a highly doped pPIus region 32 can optionally be provided, which is arranged under parts of the pPIus cover 30.

[0049] Fig. 5b shows another preferred embodiment 500 of the half-cell of an n-channel SiC trench MISFET utilizing the sub-region 1. The difference from Fig. 4a is that the island-shaped source contact regions 9a extend laterally on the side of the half-cell opposite the trench 5 to its edge. This allows the lateral extent of the n-doped region 31 to be longer without increasing the pitch, and thus the negative feedback in the event of a short circuit can be made more effective. The other structural properties and the basic operating principle correspond to the half-cell 100 in Fig. 4a. Analogous to the embodiment according to Fig. 4b, a highly doped pPIus region 32 can optionally be provided, which is arranged under parts of the pPIus cover 30.

[0050] Fig. 5c shows another preferred embodiment 700 of the half-cell of an n-channel SiC trench MISFET utilizing sub-region 1. The difference from Fig. 5a is that the strip-shaped source contact regions 9a are omitted. Instead, the source metal 2 directly contacts the pPIus region 10, the pPIus cover 30, and the n-doped region 31. Here, the net n-doping in the n-doped region 31 is advantageously chosen to be sufficiently high to ensure a resistive contact. The other structural properties and the basic operating principle correspond to the half-cell 300 in Fig. 5a. Analogous to the aforementioned embodiments, a highly doped pPIus region 32 can also be optionally provided here, which is arranged under parts of the pPIus cover 30.

[0051] Fig. 6a shows another preferred embodiment 900 of the half-cell of an n-channel SiC trench MISFET utilizing sub-region 1. The difference from Fig. 4a is that the n-doped region 31 has at least one opening into which the pPIus cover 30 engages and contacts the pBody region 8, as shown in the partial sketch on the right, where the pPIus cover 30, the optional buffer 14, the substrate 13, and the drain metal 3 are omitted for clarity. The other structural properties and the basic operating principle correspond to the half-cell 100 in Fig. 4a. Current path constriction, particularly in the case of a short circuit, occurs essentially from three sides: from above by the pPIus cover 30 and laterally in some areas, and through the pBody region 8.

[0052] Fig. 6b shows another preferred embodiment 1000 of the half-cell of an n-channel SiC trench MISFET utilizing sub-region 1. The difference from Fig. 6a lies in the highly p-doped, buried pPIus region 32, which is arranged laterally at least adjacent to parts of region 31. This region is connected to the source metal 2 via the pBody region 8, the pPIus region 10, and the pPIus cover 30, which in this case need not contact the pBody region 8. Laterally, it is spaced away from the trench 5 to prevent an undesirable increase in the threshold voltage Vth. The source contact region 9a and the optional source extension region 9b can optionally extend vertically into the pPIus region 32 or even to a greater depth.

[0053] The inventive sub-area 1 of the source area 9 is formed in the present case from parts of the pPIus lid 30, where it is arranged adjacent above the area 31 and corresponds to the segments 9f_2, 9e_2 and in some areas 9f_3, 9e_3 or 9f_1, 9e_1 of the sub-area 1 and to the area 31, which there corresponds to the segments 9d_2, 9c_2, 9c_4, 9d_4 of the sub-area 1 and to the corresponding parts of the buried pPIus area 32, where it is arranged adjacent below area 31 and corresponds to the segment 9e_4, 9f_4 of the sub-area 1. A current path constriction, particularly in the case of a short circuit, occurs here essentially from three sides: from above through the pPIus cover 30 and laterally in some areas, and from the buried pPIus area 32. The constriction originating from the pPIus area 32 is more effective than that caused by the pBody area 8 in the embodiment described above.

[0054] Fig. 7a shows another preferred embodiment 1100 of the half-cell of an n-channel SiC trench MISFET utilizing the sub-region 1. The difference from Fig. 5a is that the pPIus cover 30 is segmented, and these segments are optionally connected to each other by p-doped webs 30s; in this embodiment as well, the pPIus cover 30 is directly contacted by the source metal 2. It can be implemented in the vertical direction as shown, but can also penetrate the n-doped region 31. The other structural properties and the basic operating principle correspond to the half-cell 300 in Fig. 5a. A current path constriction, particularly in the case of a short circuit, occurs here essentially from three sides, namely through the pPIus cover 30 laterally and the pBody region 8. Analogous to Fig. 6b, a highly doped pPIus region 32 can also be optionally provided here, which is arranged under parts of the pPIus cover 30.The buried pPIus region 32 can be segmented in a similar manner to the pPIus cover 30, and these segments can optionally be connected to each other by p-doped bridges. In this case, it is preferably located adjacent to and below 31 wherever no pPIus cover segment is present above 31. Current path constriction, particularly in the event of a short circuit, occurs essentially from three sides: laterally through the pPIus cover 30 and through the buried pPIus region 32.

[0055] Fig. 7b shows another preferred embodiment 1300 of the cell of an n-channel SiC trench MISFET utilizing the subregion 1 derived from Fig. 4a. The difference from Fig. 4a is that this cell can only open one channel because one side and part of the bottom of the trench 5 border the pPIus region 10. This allows for a lower pitch. Furthermore, this structure enables a significantly stronger JFET effect in the spreading region 11 below the trench 5, which further reduces the short-circuit current density. Analogous to Fig. 4b, a highly doped pPIus region 32 can also be optionally provided here, which is arranged under part of the pPIus cover 30.

[0056] Fig. 7c shows another preferred embodiment of the cell of an n-channel SiC trench MISFET. Unlike the embodiments shown previously, this one comprises a V-shaped trench 5 with an implantation area located in a bottom and side region of the trench. The other structural properties and the basic operating principle correspond to the half-cell 100 in Fig. 4a.

[0057] Fig. 8a shows another preferred embodiment 1500 of the half-cell of an n-channel SiC trench FinFET utilizing sub-region 1, which in particular enables a small pitch by utilizing the FinFET effect. Here, sub-region 1 is arranged vertically in the half-cell.

[0058] The semiconductor device comprises a highly n-doped substrate 13 ohmically contacted with a drain metallization 3, with an optional n-doped buffer 14 arranged above it, a drift region 15 arranged above it, an n-doped spreading region 11 arranged above it, which has been created epitaxially and / or by means of additional implantation and has a higher doping concentration than the drift region 15, a highly doped pPIus region 10 which extends vertically at least into or penetrates the spreading region 11, and a moderately p-doped pBody region 8 which is arranged on the spreading region 11 and laterally adjoins a trench 5 which extends from the semiconductor surface at least into the spreading region 11 and is lined with a gate dielectric 6 which is the highly n-doped substrate, typically made of polysilicon or a Gate electrode 4, which consists of other highly conductive material, is at least partially enclosed.The gate electrode 4 is separated by the gate dielectric 6 from at least an n-doped part of the source region 9.

[0059] The pBody region 8 is connected to the source metal 2 at least in the third dimension, either directly or via a deep pPIus contact region 40 (see illustration in Fig. 8c). The pPIus region 10 is connected to the source metal 2, for example, in the third dimension, either directly or via a deep pPIus contact region 40 (see Fig. 8c), and serves, among other things, to shield the bottom of the trench 5 from high fields. Region 10 implements a significantly stronger JFET effect in the spreading region 11 below the trench 5, which further reduces the short-circuit current density. It also reduces the feedback capacitance Cgd, which is beneficial for the switching behavior of the device.

[0060] The source region includes, in addition to subregion 1, a source contact region 9a connected to the source metal 2 (see contact region 20) and an optional source extension region 9b, which is partially covered vertically by the gate electrode 4, the latter being insulated from the semiconductor by the gate dielectric 4. The source extension region 9b serves to make the short-circuit current insensitive to tolerances of the gate recess and to homogenize the current conduction in the source region along the third dimension, so that, among other things, the largest possible channel width in the pBody region 8 can be used in the case of conduction. The pPIus cover 30 consists of several segments, borders the intermediate dielectric (not shown), and is connected to the source metal 2.The inventive subregion 1 of the source region is formed in the present case from parts of the pPIus cover 30, where it is arranged laterally adjacent to the region 31 and corresponds to segments 9f_2, 9e_2, 9f_4, 9e_4 of subregion 1 and to region 31, which there corresponds to segments 9d_2, 9c_2, 9c_4, 9d_4 of subregion 1. A current path constriction, particularly in the case of a short circuit, occurs here essentially from two sides.

[0061] In a possible further embodiment, the present sub-area additionally comprises the n-doped segments 9d_1, 9c_1, 9c_3, 9d_3 and the p-doped segments 9f_1, 9e_1, 9f_3, 9e_3, wherein the segments 9f_1, 9f_3 are connected either directly or via 30 to the source metal 2. A current path constriction, particularly in the case of a short circuit, then occurs essentially from four sides.

[0062] Fig. 8b shows another preferred embodiment of the variants of the n-channel FinFET described in connection with Fig. 8a, in which the formation of a fin is carried out after implantation.

[0063] Fig. 8d shows another preferred embodiment of the variants of the n-channel FinFET described in connection with Fig. 8a, b. In this embodiment, the subregion 1 is configured such that n-doped segments are arranged below the pPIus cover 30.

[0064] The application of the present invention is not limited to strip-shaped cells; rather, the basic concept can be transferred to various geometric embodiments, e.g., square, hexagonal, or round. Furthermore, the cells need not each have two channels; a larger or smaller number of channels is possible. The application of the invention is also not limited to devices with a homogeneously doped drift region 15, but can also be used in devices with an inhomogeneously doped drift region, in particular with increased doping in the upper region and / or in the lower region near the optional buffer or substrate 13. Moreover, the application of the invention is not limited to n-channel MISFETs or FinFETs, but can also be applied to p-channel MISFETs or FinFETs, wherein the corresponding n and p doping concentrations are interchanged and the potentials are adjusted accordingly.Furthermore, the application of this concept is not limited to SiC (silicon carbide) but can also be used with any other semiconductor material (e.g., GaN, Si, Ge, etc.). Moreover, the application of the invention is not limited to MISFETS and FinFETs but can also be applied to other devices, such as IGBTs and FinIGBTs.

[0065] In principle, part 1 of source region 9 can be created by implantation into an already existing, e.g., p-doped region and superimpose the doping originally present there.

[0066] In principle, at least one segment of part 1 of the source region 9) can be generated by over-doping at least one part of at least one other segment; partial compensation of the dopings is also possible.

[0067] In principle, the p-doped regions of section 1 can contain dopants with an energy position lower in the forbidden band than AI, such as boron, which only become electrically active at increasing temperatures.

Claims

1. Claims 1. Semiconductor device, preferably a power semiconductor device, preferably based on a wide-bandgap material, in particular silicon carbide (SiC), with an active region consisting of at least one active half-cell, comprising in at least one, preferably in all half-cells, a source region (9) which is arranged in a p-doped region (8) and has a resistive region (9c, 9d) for generating a voltage drop in the event of a short circuit, characterized in that the resistive region is realized as a sub-section (1) comprising several segments, comprising inner, n-doped segments (segments 9c_1, 9c_2, 9c_3, 9c_4, 9d_1, 9d_2, 9d_3, 9d_4) and outer, p-doped segments (9e_1, 9e_2, 9e_3, 9e_4 and 9f_1) at least partially surrounding these in cross-sectional view (AA'). 9f_2,9f_3, 9f_4), which are arranged in such a way,that in the event of a short circuit, a geometric constriction of the electron flow through the section (1) occurs from at least two sides.

2. Semiconductor device according to claim 1, characterized in that the inner segments (segments 9c_1 , 9c_2, 9c_3, 9c_4, 9d_1 , 9d_2, 9d_3, 9d_4) can be traversed by an electron current substantially perpendicular to the cross-section (AA') and the outermost segments (9f_1 , 9f_2, 9f_3, 9f_4) are connected to source potential or a potential of the same order of magnitude.

3. Semiconductor device according to claim 1 or 2, characterized in that the inner segments have first inner segments (9c_1 , 9c_2,9c_3,9c_4) and second inner segments (9d_1 , 9d_2, 9d_3, 9d_4) adjacent to these, and that the outer segments have first outer segments (9e_1 , 9e_2,9e_3,9e_4) adjacent to the second inner segments and second outer segments (9f_1 , 9f_2,9f_3, 9f_4) adjacent to these.

4. Semiconductor device according to one of the preceding claims, characterized in that the segments (9c_1 , 9c_2,9c_3,9c_4, 9d_1 , 9d_2, 9d_3, 9d_4, 9e_1 , 9e_2, 9e_3, 9e_4, 9f_1 , 9f_2, 9f_3, 9f_4) are arranged in cross-sectional view (AA') starting from a center (Z) of the sub-section (01) in a substantially layered manner relative to each other.

5. Semiconductor device according to one of the preceding claims, characterized in that the inner and outer segments (9c_1, 9c_2, 9c_3, 9c_4, 9d_1 , 9d_2, 9d_3, 9d_4, and 9e_1 , 9e_2, 9e_3, 9e_4, 9f_1, 9f_2, 9f_3, 9f_4) of the section (1) are arranged such that in the event of a short circuit and / or with increasing temperature, a geometric constriction of the electron current through the section (1) occurs from at least three sides, more preferably from four sides.

6. Semiconductor device according to one of the preceding claims, characterized in that the net doping of the inner, n-doped segments (9c_1 , 9c_2,9c_3,9c_4,9d_1 , 9d_2, 9d_3, 9d_4) is less than that of the outer, preferably highly p-doped segments (9e_1, 9e_2,9e_3,9e_4) adjacent to them.

7. Semiconductor device according to one of the preceding claims, characterized in that the net doping of first, inner n-doped segments (9c_1, 9c_2, 9c_3, 9c_4) is less than that of the second, inner segments (9d_1, 9d_2, 9d_3, 9d_4) arranged between them and the p-doped segments, wherein the p-doped segments (9e_1, 9e_2, 9e_3, 9e_4) adjacent to these are highly p-doped.

8. Semiconductor device according to one of claims 1 to 5, characterized in that the net doping of the inner, n-doped segments (9c_1, 9c_2, 9c_3, 9c_4, 9d_1, 9d_2, 9d_3, 9d_4) is substantially equal to or higher than that of the adjacent first outer, p-doped segments (9e_1, 9e_2, 9e_3, 9e_4), wherein the second outer segments (9f_1, 9f_2, 9f_3, 9f_4) adjacent to these are highly p-doped.

9. Semiconductor device according to one of the preceding claims, characterized in that the semiconductor device is configured as an n-channel trench- MISFET is formed, comprising a substrate (13), a drift region (15) arranged above it, an n-doped spreading region (11) arranged above it, a highly doped pPIus region (10), a p-doped pBody region (8) laterally adjacent to a trench (5), a highly doped pPIus cap (30), a source contact region (9a), an adjacent n-doped region (31) which is at least partially covered by the pPIus cap (30), wherein the part (1) of the source region is formed from parts of the pPIus cap (30) that are arranged adjacent above the n-doped region (31), the n-doped region (31), and parts of the pBody region (8) that are arranged adjacent below the n-doped region (31).

10. Semiconductor device according to any one of claims 1 to 8, characterized in that the semiconductor device is configured as an n-channel trench FinFET, comprising a substrate (13), a drift region (15) arranged above it, an n-doped spreading region (11) arranged above it, a highly doped pPIus region (10), a p-doped pBody region (8) laterally adjacent to a trench (5), a deep pPIus contact region (40) connecting the pBody region (8) to a source metal (2), a pPIus lid (30) consisting of several segments with an intervening n-doped region (31), wherein the portion (1) of the source region (9) is arranged vertically and comprises parts of the pPIus lid (30) that are arranged laterally adjacent to the n-doped region (31) and the intervening n-doped region (31) is formed.

11. Semiconductor device according to claim 9 or 10, characterized in that the semiconductor device additionally has a highly doped pPIus region (32) which is arranged under parts of the pPIus lid (30), and which may optionally be segmented, in particular in a similar manner to the pPIus lid 30, and the individual segments may optionally be connected to each other by p-doped bridges.

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