Controller, avalanche photodiode sensor, control method

Abstract

A controller for an avalanche photodiode sensor, including circuitry configured to: control a latch circuit to store one or more least significant bits of a counter value of a counter circuit at the end of a first frame, wherein the counter circuit is configured to count exposure time intervals of a frame in which an avalanche photodiode pixel has generated a light detection event; enable readout of the one or more least significant bits from the latch circuit in a second frame following the first frame; and enable readout of one or more most significant bits of the counter value from the counter circuit in the second frame.

Description

[0001] CONTROLLER, AVALANCHE PHOTODIODE SENSOR, CONTROL

[0002] METHOD

[0003] TECHNICAL FIELD

[0004] The present disclosure generally pertains to a controller for an avalanche photodiode sensor, an avalanche photodiode sensor and a control method for an avalanche photodiode sensor.

[0005] TECHNICAL BACKGROUND

[0006] Generally, single-photon avalanche photodiode (“SPAD”) sensors are known, which may be used, for example, as image sensors or for depth sensing.

[0007] A SPAD-based photon counting image sensor typically includes a pixel frontend with a counter circuit for counting light detection events (e.g., a voltage pulse generated due to an incident photon).

[0008] In a case of a global shutter operation at high frame rate, for example, a common practice is to latch the counter values of the counters and then restart the counting in order to start the next exposure period.

[0009] However, in this case, a full frame memory may be required with associated cost in area and power.

[0010] Although there exist techniques for controlling a SPAD sensor, it is generally desirable to improve the existing techniques.

[0011] SUMMARY

[0012] According to a first aspect, the disclosure provides a controller for an avalanche photodiode sensor, comprising circuitry configured to: control a latch circuit to store one or more least significant bits of a counter value of a counter circuit at the end of a first frame, wherein the counter circuit is configured to count exposure time intervals of a frame in which an avalanche photodiode pixel has generated a light detection event; enable readout of the one or more least significant bits from the latch circuit in a second frame following the first frame; and enable readout of one or more most significant bits of the counter value from the counter circuit in the second frame. According to a second aspect, the disclosure provides an avalanche photodiode sensor, comprising: an avalanche photodiode pixel configured to generate light detection events in response to incident light; a counter circuit configured to count exposure time intervals of a frame in which the avalanche photodiode pixel has generated a light detection event; a latch circuit configured to store one or more least significant bits of a counter value of the counter circuit; and a controller, including circuitry configured to: control a latch circuit to store one or more least significant bits of a counter value of the counter circuit at the end of a first frame, enable readout of the one or more least significant bits from the latch circuit in a second frame following the first frame, and enable readout of one or more most significant bits of the counter value from the counter circuit in the second frame.

[0013] According to a third aspect, the disclosure provides a control method for an avalanche photodiode sensor, comprising: controlling a latch circuit to store one or more least significant bits of a counter value of a counter circuit at the end of a first frame, wherein the counter circuit is configured to count exposure time intervals of a frame in which an avalanche photodiode pixel has generated a light detection event; enabling readout of the one or more least significant bits from the latch circuit in a second frame following the first frame; and enabling readout of one or more most significant bits of the counter value from the counter circuit in the second frame.

[0014] Further aspects are set forth in the dependent claims, the drawings and the following description.

[0015] BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Embodiments are explained by way of example with respect to the accompanying drawings, in which:

[0017] Fig. 1 schematically illustrates in a block diagram an embodiment of a single-photon avalanche sensor;

[0018] Fig. 2 schematically illustrates in a block diagram the embodiment of Fig. 1 in more detail; Fig. 3 schematically illustrates in a block diagram an embodiment of a single-photon avalanche diode pixel;

[0019] Fig. 4 schematically illustrates in a block diagram an embodiment of a single-photon avalanche diode;

[0020] Fig. 5 schematically illustrates in a block diagram an embodiment of a pixel frontend circuit connected to a single-photon avalanche diode pixel;

[0021] Fig. 6 schematically illustrates a principle of exposure time intervals;

[0022] Fig. 7 schematically illustrates in a block diagram an embodiment of a counter circuit and a latch circuit;

[0023] Fig. 8 schematically illustrates an embodiment of a control method; and

[0024] Fig. 9 schematically illustrates in a flow diagram an embodiment of a control method.

[0025] DETAILED DESCRIPTION OF EMBODIMENTS

[0026] Before a detailed description of the embodiments under reference of Fig. 5 is given, general explanations are made.

[0027] As mentioned in the outset, generally, single-photon avalanche photodiode (“SPAD”) sensors are known, which may be used, for example, as image sensors or for depth sensing.

[0028] For enhancing the general understanding of the present disclosure, an embodiment of an avalanche photodiode sensor 1 is discussed under reference of Figs. 1 to 4 in the following, wherein the embodiment of the avalanche photodiode sensor 1 also applies to other embodiments of the present disclosure.

[0029] The avalanche photodiode sensor l is a SPAD sensor and has a stacked structure which includes a first tier 2 and a second tier 3.

[0030] The first tier 2 includes a SPAD pixel array 4 which includes a plurality of SPAD pixels arranged, for example, in rows and columns.

[0031] The second tier 3 includes a readout circuit 5 which includes a pixel frontend 6 that is connected with the SPAD pixel array 4 via Cu-Cu (“Copper-Copper”) hybrid bonding, as schematically illustrated by the dotted lines.

[0032] Referring now to Fig. 2, as mentioned above, the SPAD pixel array 4 includes a plurality of SPAD pixels 11 that are arranged in rows and columns. For the sake of illustration only a 3x3 SPAD pixel array 4 is shown, however, the present disclosure is not limited to such an array size, for example, the array size may be 748x448 or the like or any size. In some embodiments, the SPAD sensor 1 only includes a single SPAD pixel 11.

[0033] The SPAD pixels 11 are connected via Cu-Cu connections 12 with the pixel frontend 6. For the sake of illustration only a single Cu-Cu connection 12 is shown for each row, however, each SPAD pixel 11 of the SPAD pixel array 4 is connected via a different Cu-Cu connection 12 with the pixel frontend 6.

[0034] In particular, the pixel frontend 6 includes a plurality of pixel frontend circuits such that each SPAD pixel 11 is connected via a Cu-Cu connection 12 with a different pixel frontend circuit. A pixel frontend circuit includes a counter for counting exposure time intervals in which the connected SPAD pixel 11 has generated a light detection event.

[0035] The readout circuit 5 further includes a pulse driver 13 and a vertical scanner 14 which together form a controller for the SPAD sensor 1 and generate various control signals such as, for instance, clocked recharge signals, latch enable signals, selection signals, reset signals and the like.

[0036] The readout circuit 5 further includes a digital unit 15 which includes storage elements for storing the readout counter values of a frame.

[0037] The readout circuit 5 further includes an output interface 16 via which the frames are output to an external device or the like.

[0038] In some embodiments, the controller includes the digital unit 15 and the output interface 16 such that the controller may generate further control signals to control a readout of the pixel frontend circuits.

[0039] Referring now to Fig. 3, an embodiment of a SPAD pixel 11 is discussed in the following, which schematically illustrates the embodiment in a block diagram.

[0040] The SPAD pixel 11 includes a SPAD 20, a resistor 21 and a NOT gate 22.

[0041] The SPAD 20 is coupled with its anode to GND potential and with its cathode to the resistor 21 and the NOT gate 22.

[0042] The resistor 21 is coupled to a bias voltage Vbias such that the SPAD 20 is reverse-biased via the resistor 21 with the bias voltage Vbias, wherein the bias voltage Vbias is above the breakdown voltage of the SPAD 20 to allow an avalanche current to be generated in the SPAD 20 when light is incident on the SPAD 20. Once the avalanche current is generated in response to an incident photon, the cathodic voltage Vc of the SPAD 20 drops until it is below the breakdown voltage. The cathodic voltage Vc is quickly restored to the bias voltage Vbias such that the cathodic voltage Vc includes a short voltage pulse which is received by the NOT gate 22. The NOT gate 22 then outputs a light detection event LDE as a digital pulse representing 1 -bit of binary data.

[0043] Generally, the present disclosure is not limited to such embodiments SPAD pixels 11 and other embodiments may be apparent to the skilled person. For example, the NOT gate 22 may not be present and the cathodic voltage Vc pulse may be output as an analog voltage. The SPAD pixel 11 may also include a switch such that a connection of the bias voltage Vbias may be controlled via the switch for activating the SPAD 20 or deactivating the SPAD 20.

[0044] Referring now to Fig. 4, an embodiment of a SPAD 20 is discussed in the following, which schematically illustrates the embodiment in a block diagram.

[0045] When light is incident on the SPAD 20, a photo-generated electron 30 may be present and may diffuse into a depletion region 31 of the SPAD 20.

[0046] Once the photo-generated electron 30 reaches the depletion region 31, an avalanche process may occur in which further electrons are generated, as generally known, such that these electrons are typically driven towards the cathode causing a voltage drop at the cathode and an avalanche signal to be output by the SPAD 20 until the cathodic voltage Vc drops below the breakdown voltage and the bias voltage Vbias is restored again at the cathode.

[0047] Returning to the general explanations, SPAD-based photon counting image sensors typically includes a pixel frontend with a counter circuit for counting light detection events (e.g., a voltage pulse generated due to an incident photon).

[0048] In cases of a global shutter operation at high frame rate, for example, a common practice is to latch the counter values of the counter circuits and then restart the counting in order to start the next exposure period.

[0049] However, in these cases, a full frame memory may be required with associated cost in area and power. In such cases, the memory elements needed to latch the information are located inside the pixel frontend which is, however, typically very tight in area. A latch circuit for each pixel is usually area and power consuming and may also cause some leakage. This may result in limitations on a maximum counter size. An alternative is to remove the latch circuits and stop exposing until the readout is finished, however, this may result in limitations on a maximum frame rate.

[0050] Another option is to readout only one or more most significant bits and store it in a memory external to the pixel frontend, however, this also requires an intermediate readout period which may not be suitable for high frame rates.

[0051] It has thus been recognized that a control of an avalanche photodiode (image) sensor or SPAD- based (image) sensor may be improved such that an area and / or power consumption at the pixel frontend may be reduced, while at the same time a high frame rate is enabled.

[0052] It has been recognized that skipping the latching and the resetting of the one or more most significant bits of the counter circuit at the end of a frame and reading them out in the next frame may allow to save latch circuit elements at the pixel frontend for the one or more most significant bits.

[0053] It is envisaged, in some embodiments, to organize the exposure periods and the readout in a way that the readout ends before a certain bit of the counter circuit may toggle, for example, in a case of maximum light (i.e. an increment of the counter value of the counter circuit each exposure period (exposure time interval)). This may be controlled by allowing only one light detection event to be counted in each exposure time interval such that a counter value has changed after a predetermined number of exposure time intervals at maximum by this predetermined number.

[0054] Such a certain bit may be the first of one or more most significant bits of the counter value, while all lower bits of the counter value - which might toggle before the readout ends - correspond to one or more least significant bits. The number of the most significant bits and least significant bits may depend on design, technology and readout speed.

[0055] It has thus been recognized that the resetting of the most significant bits and the least significant bits may be controlled separately such that latches may only be required for the least significant bits and an intermediate readout period of the most significant bits may not be required, thereby reducing an area and power consumption at the pixel frontend and enabling at the same time a high frame rate.

[0056] Hence, some embodiments pertain to a controller for an avalanche photodiode sensor, including circuitry configured to: control a latch circuit to store one or more least significant bits of a counter value of a counter circuit at the end of a first frame, wherein the counter circuit is configured to count exposure time intervals of a frame in which an avalanche photodiode pixel has generated a light detection event; enable readout of the one or more least significant bits from the latch circuit in a second frame following the first frame; and enable readout of one or more most significant bits of the counter value from the counter circuit in the second frame.

[0057] The controller generates various control signals to achieve the functions as described herein, for example, a clocked recharge signal for controlling a time duration of an exposure time interval, a latch enable signal for controlling the latch circuit to provide input voltage levels at the output, selection signals for controlling a connection to a signal line to enable readout, reset signals for resetting the counter value and the like.

[0058] Generally, the counter circuit counts exposure time intervals of the second frame in which the avalanche photodiode pixel has generated a light detection event in parallel to the readout of the one or more least significant bits from the latch circuit in the second frame and in parallel to the readout of the one or more most significant bits of the counter value from the counter circuit in the second frame.

[0059] The avalanche photodiode sensor may be a SPAD sensor, and the avalanche photodiode pixel may be a SPAD pixel.

[0060] The SPAD sensor may include a plurality of SPAD pixels arranged in rows and columns in an array. Each SPAD pixel may be connected to a different pixel frontend circuit, wherein each pixel frontend circuit includes a latch circuit and a counter circuit. The circuitry may be configured to control each pixel frontend circuit accordingly.

[0061] The circuitry may be implemented by typical electronic components configured to achieve the functionality as described herein. The circuitry may be implemented in parts by typical electronic components and in parts by software configured to achieve the functionality as described herein. The circuitry may be implemented by software configured to achieve the functionality as described herein.

[0062] The circuitry may include, for example, an application specific integrated circuit (“ASIC”), a digital signal processor (“DSP”), a field-programmable gate array (“FPGA”), a central processing unit (“CPU”) or the like. The circuitry may include one or more of: a memory, an input / output interface, a clock circuit, a (pulse) driver etc. The latch circuit may include one or more 1 -bit latches configured to store the one or more least significant bits of the counter value of the counter circuit at the end of the first frame. The number of 1 -bit latches may correspond to the number of the one or more least significant bits of the counter value to be stored. Each latch may receive a latch enable signal from the controller such that the voltage level at its input is provided at its output, thereby storing the one or more least significant bits of the counter value.

[0063] The counter circuit is configured to count exposure time intervals of a frame in which the avalanche photodiode pixel has generated a light detection event. The counter circuit may be an up counter that is configured to count voltage pulses and may be implemented, for example, by an asynchronous ripple counter or the like.

[0064] A frame includes a plurality of exposure time intervals. An exposure time interval may also be referred to as exposure period.

[0065] The counter value represents the number of exposure time intervals of a frame in which the avalanche photodiode pixel has generated at least one light detection event.

[0066] The controller may apply a clocked recharge scheme, in some embodiments, such that at maximum only one light detection event is counted every exposure time interval.

[0067] Thus, in some embodiments, the circuitry is further configured to supply a clocked recharge signal to the counter circuit such that a recharging operation occurs only once during an exposure time interval, wherein a time duration of an exposure time interval corresponds to a time duration between two subsequent recharge signals.

[0068] The controller may control a deadtime of the avalanche photodiode pixel, in some embodiments, such that at maximum only one light detection event is counted every exposure time interval.

[0069] Thus, in some embodiments, the circuitry is further configured to control a deadtime of the avalanche photodiode pixel such that the avalanche photodiode pixel generates only one light detection event in the exposure time interval.

[0070] In some embodiments, the counter circuit is configured to count light detection events generated by the avalanche photodiode pixel during an exposure time interval of a frame, and wherein the circuitry is further configured to control a deadtime of the avalanche photodiode pixel such that a number of light detection events generated during one exposure time interval is limited to a ratio between a time duration of the respective exposure time interval and the deadtime. In such embodiments, the time durations of the exposure time intervals are predetermined such that a maximum number of light detection events that are generated during a respective exposure time interval is predetermined. Accordingly, in such embodiments, the maximum number of light detection events for each exposure time interval can be calculated a priori.

[0071] The deadtime may be controlled by using active-quenching techniques in which the deadtime is controlled via a monostable circuit that may be part of the pixel frontend or part of the avalanche photodiode pixel. In such cases, the deadtime may be designed and controlled precisely and may have a selectable time duration.

[0072] It has thus been recognized that latches may only be required for storing the least significant bits for readout and that the most significant bits may be readout in the next frame, since the most significant bits may not toggle before the readout is finished.

[0073] Hence, as mentioned above, the circuitry is configured to enable readout of the one or more least significant bits from the latch circuit in a second frame following the first frame.

[0074] The circuitry may enable the readout via a selection signal to connect the latch circuit to the signal line.

[0075] Hence, as mentioned above, the circuitry is configured to enable readout of one or more most significant bits of the counter value from the counter circuit in the second frame.

[0076] The circuitry may enable the readout via a selection signal to connect the latch circuit to the signal line.

[0077] In some embodiments, the circuitry is further configured to reset the one or more least significant bits of the counter value of the counter circuit at the end of the first frame after controlling the latch circuit to store the one or more least significant bits.

[0078] In some embodiments, the circuitry is further configured to reset the one or more most significant bits of the counter value of the counter circuit after readout of the one or more most significant bits is finished.

[0079] Typically, in some embodiments, the plurality of exposure time intervals includes exposure time intervals with at least two different time durations and, thus, the plurality of exposure time intervals includes at least a first exposure time interval having a first time duration and a second exposure time interval having a second time duration shorter than the first time duration.

[0080] In some embodiments, the circuitry is further configured to arrange exposure time intervals having a longest time duration at the beginning of a frame. In this way, as the readout happens in parallel to the exposure, the counter value may be incremented less than if the exposure time intervals with the shortest time duration are arranged at the beginning of a frame, since less exposure time intervals occur during the fixed readout period and, thus, more significant bits may be used, thereby saving latches and reducing the area and power consumption of the pixel frontend.

[0081] In some embodiments, the circuitry is further configured to enable readout of at least one of the one or more most significant bits before enabling readout of the one or more least significant bits.

[0082] In such embodiments, at least one most significant bit is readout at first such that a toggling of the remaining most significant bits is less likely to occur and, thus, more significant bits may be used, thereby saving latches and reducing the area and power consumption of the pixel frontend.

[0083] In some embodiments, the circuitry is further configured to enable readout of all of the one or more most significant bits.

[0084] Hence, a different amount of most significant bits may be used depending on when the readout happens.

[0085] In some embodiments, a detection mechanism is added for a corrupted most significant bit, which may be implemented with an additional in-pixel latch or globally.

[0086] Some embodiments pertain to an avalanche photodiode sensor, wherein the avalanche photodiode sensor includes: an avalanche photodiode pixel configured to generate light detection events in response to incident light; a counter circuit configured to count exposure time intervals of a frame in which the avalanche photodiode pixel has generated a light detection event; a latch circuit configured to store one or more least significant bits of a counter value of the counter circuit; and a controller, including circuitry configured to: control a latch circuit to store one or more least significant bits of a counter value of the counter circuit at the end of a first frame, enable readout of the one or more least significant bits from the latch circuit in a second frame following the first frame, and enable readout of one or more most significant bits of the counter value from the counter circuit in the second frame. Some embodiments pertain to an electronic apparatus including an avalanche photodiode sensor as described herein.

[0087] The electronic apparatus may be a camera, a display device, a mobile computing device (e.g., smartphone, tablet, laptop etc.) or the like.

[0088] Some embodiments pertain to a control method for an avalanche photodiode sensor, wherein the control method includes: controlling a latch circuit to store one or more least significant bits of a counter value of a counter circuit at the end of a first frame, wherein the counter circuit is configured to count exposure time intervals of a frame in which an avalanche photodiode pixel has generated a light detection event; enabling readout of the one or more least significant bits from the latch circuit in a second frame following the first frame; and enabling readout of one or more most significant bits of the counter value from the counter circuit in the second frame.

[0089] The control method may be performed by the controller for an avalanche photodiode sensor as described herein and / or by the avalanche photodiode sensor as described herein, in particular, the avalanche photodiode sensor may be a SPAD sensor.

[0090] In some embodiments, the control method is applied in a rolling shutter readout operation or a global shutter readout operation.

[0091] The methods as described herein are also implemented in some embodiments as a computer program causing a computer and / or a processor to perform the method, when being carried out on the computer and / or processor. In some embodiments, also a non-transitory computer- readable recording medium is provided that stores therein a computer program product, which, when executed by a processor, such as the processor described above, causes the methods described herein to be performed.

[0092] Returning to Fig. 5, there is schematically illustrated in a block diagram an embodiment of a pixel frontend circuit 40 connected to a SPAD pixel 11, which is discussed in the following under reference of Figs. 2, 5 and 6.

[0093] The pixel frontend circuit 40 includes a clipping transistor 41, a recharge transistor 42, a counter circuit 43, a latch circuit 44, a multiplexer 45 and an inverter that has its input coupled to a line between the clipping transistor 41 and the recharge transistor 42 and that has its output coupled to the input of the counter circuit 43. The clipping transistor 41 receives a constant clipping voltage CLIP at its gate from the controller, which is formed e.g. by the pulse driver 13 and the vertical scanner of Fig. 2, in order to limit the voltage at the inverter input.

[0094] The recharge transistor 42 receives a clocked recharge signal XRCG at its gate from the controller to restore a voltage Vdd at the beginning of an exposure time interval.

[0095] When the SPAD pixel 11 generates a light detection event based on the SPAD 20 operation, the voltage pulse is transmitted via the Cu-Cu bonding 12 to the pixel frontend circuit 40.

[0096] The voltage at the inverter input drops such that a light detection event voltage Vide changes to a high level and the counter circuit 43 increments its counter value by one.

[0097] When another voltage pulse is transmitted from the SPAD pixel 11 via the Cu-Cu bonding 12 to the pixel frontend circuit 40 during the same exposure time interval, the counter circuit 43 does not count this light detection event, since the voltage at the inverter input does not change.

[0098] This principle of exposure time intervals is schematically illustrated in Fig. 6, which is discussed in the following.

[0099] At the beginning of each exposure time interval, the voltage at the inverter input is restored to Vdd by the clocked recharge signal XRCG.

[0100] As depicted in Fig. 6, in the first exposure time interval no photon is detected by the SPAD pixel 11 and thus no incrementation of the counter value occurs.

[0101] In the second exposure time interval, one photon is detected by the SPAD pixel 11 and, thus, the counter value is incremented by one.

[0102] In the third exposure time interval, three photons are detected by the SPAD pixel 11, however, as the recharging operation only occurs once at the beginning of each exposure time interval, the counter value is incremented only by one, even though multiple photons were detected.

[0103] Returning to Fig. 5, the counter circuit 43 provides one or more least significant bits (“LSB”) to the latch circuit 44 and one or more most significant bits (“MSB”) directly to the multiplexer 45.

[0104] The controller provides a latch enable signal L_EN to the latch circuit 44 such that the latch circuit 44 stores the LSB at the end of a first frame.

[0105] Moreover, the controller provides a first selection signal SEL1 to the multiplexer 45 to enable readout of either the LSB from the latch circuit 44 or the MSB directly from the counter circuit 43. The controller further provides a second selection signal SEL2 to close a switch in order to provide the output of the multiplexer 45 to a signal line SIG that is connected to the digital unit 15 of Fig. 2 to enable readout of either the LSB from the latch circuit 44 or the MSB directly from the counter circuit 43.

[0106] The controller enables readout of the LSB from the latch circuit 44 in a second frame following the first frame.

[0107] The controller enables readout of MSB of the counter value from the counter circuit in the second frame.

[0108] Thus, latches for the MSB are not required and an intermediate readout period for readout of the MSB is not required, thereby reducing an area and power consumption at the pixel frontend and enabling at the same time a high frame rate.

[0109] The controller provides a first reset signal CNT RST LSB for resetting the LSB at the end of the first frame after controlling the latch circuit 44 to store the LSB.

[0110] Moreover, the controller further provides a second reset signal CNT RST MSB for resetting the MSB after readout of the MSB is finished.

[0111] Fig. 7 schematically illustrates in a block diagram an embodiment of the counter circuit 43 and the latch circuit 44, which is discussed in the following.

[0112] For the sake of illustration only the counter circuit 43 is a 4-bit counter, however, the present disclosure is not limited to such a 4-bit counter which may also be an 8-bit, a 12-bit counter or the like.

[0113] The counter circuit 43 has four 1 -bit storage elements cnt[0], cnt

[0001] , cnt[2] and cnt[3], wherein cnt[0], cnt

[0001] and cnt[2] represent the LSB of the counter value of the counter circuit 43, and wherein cnt[3] represents the MSB of the counter value of the counter circuit 43.

[0114] The latch circuit 44 has three 1 -bit latches lat[0], lat

[0001] and [2], wherein lat[0] is connected to cnt[0], lat

[0001] is connected to cnt

[0001] , and lat[2] is connected to cnt[2].

[0115] Fig. 8 schematically illustrates an embodiment of a control method 50, which is discussed in the following under reference of Figs. 2, 5, 7 and 8.

[0116] The operation of the pixel frontend circuit 40 according to the control method 50 is basically as follows: At the end of a frame, the counter circuit 43 is storing the counter value of the frame that must be read out during the next frame.

[0117] At this point, the LSB are copied into the local readout latches (in this embodiment: lat[0], lat

[0001] and [2]) and after that they are readout from the latches. The MSB of the counter value are not copied and are not reset.

[0118] Then, a new frame starts and at the same time the readout starts. While the LSB of the counter value of the counter circuit 43 are already incremented again, the LSB stored in the latch circuit 44 are read out in parallel from the latch circuit 44.

[0119] Moreover, the MSB of the counter value of the counter circuit 43 still hold the previous value and are read out directly from the counter circuit 43.

[0120] Once the readout is finished, the controller applies asynchronous reset to the MSB of the counter value of the counter circuit 43, which are then ready to be incremented according to the ongoing counting operation.

[0121] As depicted in Fig. 8, at the end of frame #N-1, the controller provides the latch enable signal L_EN (as indicated by the vertical bar in the row L_EN) such that the LSB of cnt[3:0] is stored in lat[2:0] . As the counter value is “9”, the LSB represent the value “1” corresponding to the bit pattern “001”, since the bit pattern of the counter value is “1001”.

[0122] Moreover, at the end of frame #N-1, the controller provides the first reset signal CNT_RST_LSB (as indicated by the vertical bar in the row CNT RST LSB).

[0123] Then, at the beginning of frame #N, the counter value is “8” corresponding to the bit pattern “1000”.

[0124] The frame #N includes a plurality of exposure time intervals 51a-d in which the exposure time intervals 51a have the longest time duration T4, the exposure time intervals 51b have the second longest time duration T3, the exposure time intervals 51c have the second shortest time duration T2 and the exposure time intervals 5 Id have the shortest time duration Tl.

[0125] In the following it is assumed that in each exposure time interval 51a-d at least one light detection event is generated by the SPAD pixel 11 such that the counter value is incremented by one in each exposure time interval 51a-d.

[0126] Accordingly, the counter value represented by cnt[3:0] starts to increase with the beginning of the new frame #N following the frame #N-1. The counter value in Fig. 8 is notated in hexadecimal form for the sake of illustration. Moreover, the readout of the LSB from the latches lat[2 :0] and of the MSB from cnt[3] starts in parallel with the beginning of the new frame #N and which may take until the exposure time intervals 51b are finished. The controller enables the readout by providing the first and second selection signals SEL1 and SEL2 such that the digital unit 15 can store the values in a memory.

[0127] The controller may also generate, in some embodiments, the control signals for the digital unit 15 and, thus, may control the readout of the LSB and MSB.

[0128] Then, the controller provides the second reset signal CNT RST MSB (as indicated by the vertical bar in the row CNT RST MSB).

[0129] Then, after resetting the MSB of the counter circuit 43 in frame #N, the counter value is “6” corresponding to the bit pattern “0110”.

[0130] Then, at the end of frame #N, the same procedure as at the end of frame #N-1 occurs and the readout and resetting scheme as in frame #N is repeated in frame #N+1.

[0131] As depicted in Fig. 8, the exposure time intervals 51a with the longest time duration T4 are arranged at the beginning of a frame such that the counter value may be less incremented during the readout period compared to a situation in which the shortest exposure time intervals are arranged at the beginning of a frame.

[0132] This may allow to use more MSB such that more latches may be saved, thereby reducing the area and power consumption of the pixel frontend.

[0133] A control method for an avalanche photodiode sensor is schematically illustrated in a flow diagram in Fig. 9, which is discussed in the following.

[0134] The control method may be performed by the controller for an avalanche photodiode sensor as described herein and / or by the avalanche photodiode sensor as described herein, in particular, the avalanche photodiode sensor may be a SPAD sensor.

[0135] At 101, a latch circuit is controlled to store one or more least significant bits of a counter value of a counter circuit at the end of a first frame, wherein the counter circuit is configured to count exposure time intervals of a frame in which an avalanche photodiode pixel has generated a light detection event, as discussed herein.

[0136] At 102, readout of the one or more least significant bits from the latch circuit is enabled in a second frame following the first frame, as discussed herein.

[0137] At 103, readout of one or more most significant bits of the counter value from the counter circuit is enabled in the second frame, as discussed herein. At 104, the one or more least significant bits of the counter value of the counter circuit are reset at the end of the first frame after controlling the latch circuit to store the one or more least significant bits, as discussed herein.

[0138] At 105, the one or more most significant bits of the counter value of the counter circuit are reset after readout of the one or more most significant bits is finished, as discussed herein.

[0139] It should be recognized that the embodiments describe methods with an exemplary ordering of method steps. The specific ordering of method steps is however given for illustrative purposes only and should not be construed as binding.

[0140] It will be appreciated that the above description for clarity has described embodiments with reference to different functional units, circuitry and / or processors. However, it will be apparent that any suitable distribution of functionality between different functional units, circuitry and / or processors may be used without detracting from the embodiments.

[0141] Described embodiments may be implemented in any suitable form including hardware, software, firmware or any combination of these. Described embodiments may optionally be implemented at least partly as computer software running on one or more data processors and / or digital signal processors. The elements and components of any embodiment may be physically, functionally and logically implemented in any suitable way. Indeed, the functionality may be implemented in a single unit, in a plurality of units or as part of other functional units. As such, the disclosed embodiments may be implemented in a single unit or may be physically and functionally distributed between different units, circuitry and / or processors.

[0142] Although the present disclosure has been described in connection with some embodiments, it is not intended to be limited to the specific form set forth herein. Additionally, although a feature may appear to be described in connection with particular embodiments, one skilled in the art would recognize that various features of the described embodiments may be combined in any manner suitable to implement the technique.

[0143] All units and entities described in this specification and claimed in the appended claims can, if not stated otherwise, be implemented as integrated circuit logic, for example on a chip, and functionality provided by such units and entities can, if not stated otherwise, be implemented by software.

[0144] In so far as the embodiments of the disclosure described above are implemented, at least in part, using software-controlled data processing apparatus, it will be appreciated that a computer program providing such software control and a transmission, storage or other medium by which such a computer program is provided are envisaged as aspects of the present disclosure.

[0145] Note that the present technology can also be configured as described below.

[0146] (1) A controller for an avalanche photodiode sensor, including circuitry configured to: control a latch circuit to store one or more least significant bits of a counter value of a counter circuit at the end of a first frame, wherein the counter circuit is configured to count exposure time intervals of a frame in which an avalanche photodiode pixel has generated a light detection event; enable readout of the one or more least significant bits from the latch circuit in a second frame following the first frame; and enable readout of one or more most significant bits of the counter value from the counter circuit in the second frame.

[0147] (2) The controller of (1), wherein the circuitry is further configured to reset the one or more least significant bits of the counter value of the counter circuit at the end of the first frame after controlling the latch circuit to store the one or more least significant bits.

[0148] (3) The controller of (1) or (2), wherein the circuitry is further configured to reset the one or more most significant bits of the counter value of the counter circuit after readout of the one or more most significant bits is finished.

[0149] (4) The controller of any one of (1) to (3), wherein the circuitry is further configured to arrange exposure time intervals having a longest time duration at the beginning of a frame.

[0150] (5) The controller of any one of (1) to (4), wherein the circuitry is further configured to enable readout of at least one of the one or more most significant bits before enabling readout of the one or more least significant bits.

[0151] (6) The controller of (5), wherein the circuitry is further configured to enable readout of all of the one or more most significant bits.

[0152] (7) The controller of any one of (1) to (6), wherein the circuitry is further configured to supply a clocked recharge signal to the counter circuit such that a recharging operation occurs only once during an exposure time interval, wherein a time duration of an exposure time interval corresponds to a time duration between two subsequent recharge signals.

[0153] (8) The controller of any one of (1) to (7), wherein the counter circuit is configured to count light detection events generated by the avalanche photodiode pixel during an exposure time interval, and wherein the circuitry is further configured to control a deadtime of the avalanche photodiode pixel such that a number of light detection events generated during one exposure time interval is limited to a ratio between a time duration of the respective exposure time interval and the deadtime.

[0154] (9) An avalanche photodiode sensor, including: an avalanche photodiode pixel configured to generate light detection events in response to incident light; a counter circuit configured to count exposure time intervals of a frame in which the avalanche photodiode pixel has generated a light detection event; a latch circuit configured to store one or more least significant bits of a counter value of the counter circuit; and a controller, including circuitry configured to: control a latch circuit to store one or more least significant bits of a counter value of the counter circuit at the end of a first frame, enable readout of the one or more least significant bits from the latch circuit in a second frame following the first frame, and enable readout of one or more most significant bits of the counter value from the counter circuit in the second frame.

[0155] (10) The avalanche photodiode sensor of (9), wherein the avalanche photodiode sensor is a single-photon avalanche photodiode sensor, and wherein the avalanche photodiode pixel is a single-photon avalanche photodiode pixel.

[0156] (11) A control method for an avalanche photodiode sensor, including: controlling a latch circuit to store one or more least significant bits of a counter value of a counter circuit at the end of a first frame, wherein the counter circuit is configured to count exposure time intervals of a frame in which an avalanche photodiode pixel has generated a light detection event; enabling readout of the one or more least significant bits from the latch circuit in a second frame following the first frame; and enabling readout of one or more most significant bits of the counter value from the counter circuit in the second frame.

[0157] (12) The control method of (11), further including: resetting the one or more least significant bits of the counter value of the counter circuit at the end of the first frame after controlling the latch circuit to store the one or more least significant bits.

[0158] (13) The control method of (11) or (12), further including: resetting the one or more most significant bits of the counter value of the counter circuit after readout of the one or more most significant bits is finished.

[0159] (14) The control method of any one of (11) to (13), further including: arranging exposure time intervals having a longest time duration at the beginning of a frame.

[0160] (15) The control method of any one of (11) to (14), further including: enabling readout of at least one of the one or more most significant bits before enabling readout of the one or more least significant bits.

[0161] (16) The control method of (15), further including: enabling readout of all of the one or more most significant bits.

[0162] (17) The control method of any one of (11) to (16), further including: supplying a clocked recharge signal to the counter circuit such that a recharging operation occurs only once during an exposure time interval, wherein a time duration of an exposure time interval corresponds to a time duration between two subsequent recharge signals.

[0163] (18) The control method of any one of (11) to (17), wherein the counter circuit is configured to count light detection events generated by the avalanche photodiode pixel during an exposure time interval, and wherein the control method further includes: controlling a deadtime of the avalanche photodiode pixel such that a number of light detection events generated during one exposure time interval is limited to a ratio between a time duration of the respective exposure time interval and the deadtime.

[0164] (19) The control method of any one of (11) to (18), wherein the control method is applied in a rolling shutter readout operation or a global shutter readout operation.

[0165] (20) The control method of any one of (11) to (19), wherein the avalanche photodiode sensor is a single-photon avalanche photodiode sensor, and wherein the avalanche photodiode pixel is a single-photon avalanche photodiode pixel.

[0166] (21) A computer program comprising program code causing a computer to perform the control method according to any one of (11) to (20), when being carried out on a computer. (22) A non-transitory computer-readable recording medium that stores therein a computer program product, which, when executed by a processor, causes the control method according to any one of (11) to (20) to be performed.

[0167] (23) An electronic apparatus including an avalanche photodiode sensor of (9) or (10).

Claims

CLAIMS1. A controller for an avalanche photodiode sensor, comprising circuitry configured to: control a latch circuit to store one or more least significant bits of a counter value of a counter circuit at the end of a first frame, wherein the counter circuit is configured to count exposure time intervals of a frame in which an avalanche photodiode pixel has generated a light detection event; enable readout of the one or more least significant bits from the latch circuit in a second frame following the first frame; and enable readout of one or more most significant bits of the counter value from the counter circuit in the second frame.

2. The controller of claim 1, wherein the circuitry is further configured to reset the one or more least significant bits of the counter value of the counter circuit at the end of the first frame after controlling the latch circuit to store the one or more least significant bits.

3. The controller of claim 1, wherein the circuitry is further configured to reset the one or more most significant bits of the counter value of the counter circuit after readout of the one or more most significant bits is finished.

4. The controller of claim 1, wherein the circuitry is further configured to arrange exposure time intervals having a longest time duration at the beginning of a frame.

5. The controller of claim 1, wherein the circuitry is further configured to enable readout of at least one of the one or more most significant bits before enabling readout of the one or more least significant bits.

6. The controller of claim 5, wherein the circuitry is further configured to enable readout of all of the one or more most significant bits.

7. The controller of claim 1, wherein the circuitry is further configured to supply a clocked recharge signal to the counter circuit such that a recharging operation occurs only once during an exposure time interval, wherein a time duration of an exposure time interval corresponds to a time duration between two subsequent recharge signals.

8. The controller of claim 1, wherein the counter circuit is configured to count light detection events generated by the avalanche photodiode pixel during an exposure time interval, and wherein the circuitry is further configured to control a deadtime of the avalanche photodiode pixel such that a number of light detection events generated during one exposure time interval islimited to a ratio between a time duration of the respective exposure time interval and the deadtime.

9. An avalanche photodiode sensor, comprising: an avalanche photodiode pixel configured to generate light detection events in response to incident light; a counter circuit configured to count exposure time intervals of a frame in which the avalanche photodiode pixel has generated a light detection event; a latch circuit configured to store one or more least significant bits of a counter value of the counter circuit; and a controller, including circuitry configured to: control a latch circuit to store one or more least significant bits of a counter value of the counter circuit at the end of a first frame, enable readout of the one or more least significant bits from the latch circuit in a second frame following the first frame, and enable readout of one or more most significant bits of the counter value from the counter circuit in the second frame.

10. The avalanche photodiode sensor of claim 9, wherein the avalanche photodiode sensor is a single-photon avalanche photodiode sensor, and wherein the avalanche photodiode pixel is a single-photon avalanche photodiode pixel.

11. A control method for an avalanche photodiode sensor, comprising: controlling a latch circuit to store one or more least significant bits of a counter value of a counter circuit at the end of a first frame, wherein the counter circuit is configured to count exposure time intervals of a frame in which an avalanche photodiode pixel has generated a light detection event; enabling readout of the one or more least significant bits from the latch circuit in a second frame following the first frame; and enabling readout of one or more most significant bits of the counter value from the counter circuit in the second frame.

12. The control method of claim 11, further comprising: resetting the one or more least significant bits of the counter value of the counter circuit at the end of the first frame after controlling the latch circuit to store the one or more least significant bits.

13. The control method of claim 11, further comprising: resetting the one or more most significant bits of the counter value of the counter circuit after readout of the one or more most significant bits is finished.

14. The control method of claim 11, further comprising: arranging exposure time intervals having a longest time duration at the beginning of a frame.

15. The control method of claim 11, further comprising: enabling readout of at least one of the one or more most significant bits before enabling readout of the one or more least significant bits.

16. The control method of claim 15, further comprising: enabling readout of all of the one or more most significant bits.

17. The control method of claim 11, further comprising: supplying a clocked recharge signal to the counter circuit such that a recharging operation occurs only once during an exposure time interval, wherein a time duration of an exposure time interval corresponds to a time duration between two subsequent recharge signals.

18. The control method of claim 11, wherein the counter circuit is configured to count light detection events generated by the avalanche photodiode pixel during an exposure time interval, and wherein the control method further comprises: controlling a deadtime of the avalanche photodiode pixel such that a number of light detection events generated during one exposure time interval is limited to a ratio between a time duration of the respective exposure time interval and the deadtime.

19. The control method of claim 11, wherein the control method is applied in a rolling shutter readout operation or a global shutter readout operation.

20. The control method of claim 11, wherein the avalanche photodiode sensor is a singlephoton avalanche photodiode sensor, and wherein the avalanche photodiode pixel is a singlephoton avalanche photodiode pixel.

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