Nitride semiconductor element
The nitride semiconductor device with AlGaN layers of group V polarity addresses the challenge of high resistance and 2DHG induction in UWBG semiconductors by inducing 2DEG and enabling easy ohmic contact, resulting in low resistance and high breakdown voltage FETs.
Patent Information
- Application Number
- PCT/JP2024/021861
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-06-17
- Publication Date
- 2025-12-26
AI Technical Summary
The challenge in using ultra-wide-bandgap (UWBG) semiconductors for power devices is the difficulty in reducing channel resistance due to low free carrier concentration and the self-compensation effect at high doping concentrations, along with the induction of two-dimensional hole gas (2DHG) at the interface, which affects device characteristics and ohmic contact formation.
A nitride semiconductor device with a barrier layer and channel layer of AlGaN having group V polarity, where the channel layer has a smaller Al composition than the barrier layer, allowing for the formation of two-dimensional electron gas (2DEG) without 2DHG induction, and compositionally graded contact layers for easy ohmic contact with source/drain electrodes.
Enables low channel resistance and high breakdown voltage in UWBG semiconductor FETs by facilitating easy ohmic contact without affecting device characteristics, thereby improving current control and reducing resistance.
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Abstract
Description
nitride semiconductor devices
[0001] The present invention relates to a nitride semiconductor device.
[0002] Wide-gap semiconductors such as GaN and SiC are expected to be used as materials for power devices. These wide-gap semiconductors have a higher breakdown field than Si. Therefore, using wide-gap semiconductors makes it possible to fabricate semiconductor elements with low on-resistance and high breakdown voltage. Using ultra-wide-bandgap (UWBG) semiconductors with a bandgap of 5-6 eV, such as AlN and diamond, may further improve the performance of power devices. The breakdown field of UWBG semiconductors is 10-12 MV / cm, which is higher than that of GaN and SiC. Therefore, AlN and diamond have a figure of merit 10 times higher than that of GaN and SiC.
[0003] However, there are major challenges to using UWBG semiconductors for power device applications. The biggest challenge is the difficulty of reducing the channel resistance. In UWBG semiconductors, the ionization energies of donors and acceptors are large, and the free carrier concentration at room temperature is very low. For example, in AlN, the ionization energy of Si donors is 250-280 meV, and the ionization energy of Si is 10 18 cm -3 Even if doping is performed to a degree, the free electron concentration at room temperature is 10 15 cm -3 Therefore, the resistivity of a channel made of AlN is high, at about several tens of Ωcm. Furthermore, AlN has a limitation in that at high doping concentrations, the carrier concentration decreases due to a self-compensation effect.
[0004] Here, in nitride semiconductor devices, it is possible to induce electrons by the polarization effect without using doping. In commonly used nitride semiconductor devices with metal polarity (group III polarity), Al x Ga 1-x On the channel layer made of N, Al with a larger Al composition is formed. y Ga 1-yBy forming a barrier layer (0<x<y≦1) made of N, a two-dimensional electron gas (2DEG) is induced at the interface. It is possible to fabricate a heterostructure field effect transistor (HFET) using this 2DEG as a channel. x Ga 1-x By using N for the channel layer, the breakdown voltage can be improved.
[0005] In addition, a polarization-doped FET (PolFET) has been proposed that utilizes polarization doping in an AlGaN layer with a composition gradient along the thickness direction (Non-Patent Document 2). This technology has also been demonstrated in wide-gap semiconductors (Non-Patent Document 3). By using this polarization doping, a high concentration of free carriers can be generated in the channel without donor doping, making it possible to reduce the channel resistance in UWBG semiconductors.
[0006] In Non-Patent Document 2, an AlN buffer layer is formed on a substrate, and an Al 0.6 Ga 0.4 The structure includes a 0.25 μm N underlayer, and a 75 nm thick compositionally graded channel layer with an Al composition varying from 0.6 to 1 on the underlayer.
[0007] In the field effect transistor (device) used in the above-mentioned conventional UWBG AlGaN HFET or PolFET, each nitride semiconductor layer is formed as a metal polarity. y Ga 1-y N barrier layer is Al x Ga 1-x It is formed on the N-channel layer, and 2DEG is induced near the interface between them.
[0008] 3, a typical field effect transistor has a buffer layer 202, a channel layer 203, a barrier layer 204, a gate electrode 210, a source electrode 211, and a drain electrode 212 on a substrate 201. In this structure, Al constituting the channel layer 203 x Ga 1-x Al having a higher Al composition than N z Ga1-z When the buffer layer 202 is formed from N (0<x<z≦1), in addition to the 2DEG 221 near the interface with the barrier layer 204, a two-dimensional hole gas (2DHG) 222 is formed near the interface with the buffer layer 202 in the channel layer 203. When the 2DHG 222 is formed in this manner, the effective carrier concentration in the 2DEG 221 may be reduced, which may affect the current control characteristics of the gate electrode 211.
[0009] In addition, in the PolFET structure using a nitride semiconductor with metallic polarity, as shown in FIG. 4, the channel layer 203′ is made of a compositionally graded Al layer in which the Al composition increases toward the top. a Ga 1-a N (a: p→q, 0<p<q≦1). In this configuration, a three-dimensional electron slab (3DES) 223 is induced in the channel layer 203′. However, the buffer layer 202 has an Al composition higher than the lowest Al composition (p) of the channel layer 203′. b Ga 1-b When the channel layer 203′ is made of N (0<p<b≦1), a 2DHG 222 is formed in the vicinity of the interface between the channel layer 203′ and the buffer layer 202. Therefore, as described above, the current control characteristics of the gate electrode 211 are affected.
[0010] Furthermore, in the above-described configuration, the Al composition of the outermost layer (barrier layer 204 or channel layer 203′) is high. As the Al composition of AlGaN increases, the electron affinity decreases and the barrier to metals increases, making it difficult to obtain ohmic contact with the source electrode 211 and the drain electrode 212.
[0011] T. Nanjo et al., "Remarkable breakdown voltage enhancement in AlGaN channel high electron mobility transistors", Applied Physics Letters, vol. 92, no. 26, 263502, 2008. S. Rajan et al., "AlGaN / GaN polarization-doped field-effect transistor for microwave power applications", Applied Physics Letters, vol. 84, no. 9, pp. 1591-1593, 2004.AM Armstrong et al., "AlGaN polarization-doped field effect transistor with compositionally graded channel from Al0.6Ga0.4N to AlN", Applied Physics Letters, vol. 114, no. 5, 052103, 2019.
[0012] AlGaN, a UWBG semiconductor, is a promising material for next-generation power devices. Furthermore, by increasing the Al composition of the barrier layer, channel layer, and buffer layer, higher breakdown voltages can be expected. However, as mentioned above, while it is possible to induce 2DEG and 3DES by utilizing the polarization effect, there is a problem in that 2DHG inevitably occurs near the interface with the underlying layer due to the polarization effect, which affects device characteristics. Another problem is that the high-Al composition AlGaN layer on the source / drain side makes it difficult to obtain ohmic contact.
[0013] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to make it possible to easily obtain ohmic contact with source / drain electrodes in a nitride semiconductor device using AlGaN without affecting the device characteristics.
[0014] The nitride semiconductor device according to the present invention comprises: a barrier layer made of AlGaN having group V polarity and formed on a substrate; a channel layer made of AlGaN having group V polarity and a smaller Al composition than the barrier layer and formed in contact with the barrier layer; a gate electrode formed on the channel layer; first and second contact layers formed on either side of the gate electrode and made of AlGaN having group V polarity; a source electrode formed on the first contact layer; and a drain electrode formed on the second contact layer.
[0015] As described above, according to the present invention, a channel layer made of AlGaN having a group V polarity and a smaller Al composition than the barrier layer is formed on a barrier layer made of AlGaN having a group V polarity. Therefore, in a nitride semiconductor device using AlGaN, ohmic contact with the source / drain electrodes can be easily obtained without affecting the device characteristics.
[0016] Fig. 1 is a cross-sectional view showing the configuration of a nitride semiconductor device according to a first embodiment of the present invention. Fig. 2 is a cross-sectional view showing the configuration of a nitride semiconductor device according to a second embodiment of the present invention. Fig. 3 is a cross-sectional view showing the configuration of a conventional nitride semiconductor device. Fig. 4 is a cross-sectional view showing the configuration of a conventional nitride semiconductor device.
[0017] Hereinafter, a nitride semiconductor device according to an embodiment of the present invention will be described.
[0018] First Embodiment First, a nitride semiconductor device according to a first embodiment of the present invention will be described with reference to Fig. 1. This nitride semiconductor device is a field effect transistor.
[0019] This nitride semiconductor device includes a barrier layer 102 formed on a substrate 101, a channel layer 103 formed on and in contact with the barrier layer 102, and a gate electrode 110 formed on the channel layer 103. The barrier layer 102 can function as a buffer layer. The nitride semiconductor device also includes a first contact layer 104 and a second contact layer 105 formed on the channel layer 103 with the gate electrode 110 sandwiched therebetween, a source electrode 111 formed on the first contact layer 104, and a drain electrode 112 formed on the second contact layer 105.
[0020] The substrate 101 may be made of V-group polar AlN with a (000-1) plane orientation on its main surface. Alternatively, the substrate 101 may be a sapphire substrate with a nitrided surface. Alternatively, the substrate 101 may be made of C-polar hexagonal close-packed SiC.
[0021] The barrier layer 102 is made of Al, which has a group V polarity due to crystal growth in the −c-axis direction on the substrate 101. y Ga 1-y The channel layer 103 is made of V group polarity by crystal growth in the −c-axis direction on the substrate 101, and is made of Al x Ga 1-x N, where 0<x<y≦1. The channel layer 103 is made of AlGaN having a smaller Al composition than the barrier layer 102. A two-dimensional electron gas (2DEG) 121 is induced in the channel layer 103 near the interface with the barrier layer 102.
[0022] The gate electrode 110 is, for example, in Schottky junction with the channel layer 103. Alternatively, the gate electrode 110 may be provided on the channel layer 103 via a gate insulating layer (not shown). The source electrode 111 is formed on the first contact layer 104, and the drain electrode 112 is formed on the second contact layer 105.
[0023] The first contact layer 104 and the second contact layer 105 are formed on the channel layer 103 with the gate electrode 110 sandwiched therebetween. The first contact layer 104 and the second contact layer 105 are composed of AlGaN with group V polarity. The first contact layer 104 and the second contact layer 105 can be composed of compositionally graded AlGaN in which the Al composition increases with increasing distance from the channel layer 103. The first contact layer 104 and the second contact layer 105 composed of compositionally graded AlGaN can be doped with donor impurities or can be undoped. The first contact layer 104 and the second contact layer 105 can be composed of AlGaN that is heavily doped with donor impurities and has a lower Al composition than the channel layer 103.
[0024] Here, the substrate 101 can be made of a crystalline material (off-angle substrate) whose main surface is tilted at a maximum of 5° from the (000-1) plane. As is well known, when a nitride semiconductor crystal is grown with group V polarity, the surface flatness of the grown crystal tends to be low. In contrast, by using a substrate with an off-angle of a maximum of 5°, it is possible to achieve good surface flatness. Furthermore, when such an inclined substrate is used, the source electrode 111 and the drain electrode 112 are positioned so that current flows in a direction perpendicular to the tilt direction.
[0025] According to the first embodiment, since the channel layer 103 is made of AlGaN with group V polarity, there is no need to form a barrier layer made of AlGaN with a higher Al composition on the channel layer 103. Therefore, the induction of 2DHG does not occur, as occurs in the case of a channel layer made of AlGaN with group III polarity. As a result, there is no impact on the current control characteristics of the gate electrode 110. With group V polarity, it is possible to form a contact layer made of compositionally graded AlGaN on the channel layer. As a result, ohmic contact between the source electrode 111 and the drain electrode 112 can be easily obtained.
[0026] Next, a method for manufacturing the nitride semiconductor device according to the first embodiment will be briefly described.
[0027] First, nitride semiconductor layers, including a barrier layer 102, a channel layer 103, and first and second contact layers 104 and 105, are formed on a substrate 101 by metalorganic chemical vapor deposition (MOCVD) (Step 1). Next, a portion of the nitride semiconductor layer in the gate electrode region and the upper portion of the channel layer 103 is removed by dry etching using inductively coupled plasma (ICP) (Step 2). This process results in the formation of the first and second contact layers 104 and 105. Furthermore, electrode material is deposited on the nitride semiconductor layer (first and second contact layers 104 and 105) by electron beam evaporation to form source and drain electrodes 111 and 112, and ohmic contacts are formed by annealing or other processes (Step 3). Next, ICP dry etching is used to form element regions and separate the elements (Step 4). Next, gate electrode material is deposited by electron beam evaporation to form the gate electrode 110 (Step 5).
[0028] The order of steps 2 to 4 can be reversed. When a gate insulating layer is formed, a step of forming a gate insulating layer in the gate electrode region is included before step 5. A step of forming a passivation film can be added after step 5. Although the above description uses MOCVD for crystal growth, ICP dry etching for etching, and electron beam evaporation for depositing the electrode material, other methods can also be used.
[0029] The nitride semiconductor device according to the first embodiment can be manufactured as follows.
[0030] First, a barrier layer 102 and a channel layer 103 are formed on a substrate 101 by MOCVD (Step 1). Next, a first contact layer 104 and a second contact layer 105 are formed by regrowth on the channel layer 103 in the regions where the source electrode 111 and the drain electrode 112 are to be formed (Step 2). Next, an electrode material is deposited by electron beam evaporation on the first contact layer 104 and the second contact layer 105 formed by regrowth to form the source electrode 111 and the drain electrode 112, and ohmic contacts are formed by annealing or other processes (Step 3). Next, an element region is formed by ICP dry etching to separate the elements (Step 4). Next, a gate electrode 110 is formed by depositing a gate electrode material by electron beam evaporation or other processes (Step 5).
[0031] Regarding steps 2 to 4, step 2 must be performed before step 3, but the order of the other steps can be changed. When a gate insulating layer is formed, a step of forming a gate insulating layer in the gate electrode region is included before step 5. A step of forming a passivation film can be added after step 5. Although the above description uses MOCVD for crystal growth, ICP dry etching for etching, and electron beam evaporation for depositing the electrode material, other methods can also be used.
[0032] In addition to step 2, there is also a method in which a contact layer is formed on the channel layer 103 by the MOCVD method in step 1, and then the contact layer around the gate electrode and the upper part of the channel layer 103 are removed by ICP dry etching or wet etching, thereby forming the first contact layer 104 and the second contact layer 105.
[0033] Second Embodiment Next, a nitride semiconductor device according to a second embodiment of the present invention will be described with reference to Fig. 2. This nitride semiconductor device is a field effect transistor.
[0034] This nitride semiconductor device includes a barrier layer 102 formed on a substrate 101, a channel layer 103′ formed on and in contact with the barrier layer 102, and a gate electrode 110 formed on the channel layer 103′. The nitride semiconductor device also includes a first contact layer 104 and a second contact layer 105 formed on the channel layer 103′ with the gate electrode 110 sandwiched therebetween, a source electrode 111 formed on the first contact layer 104, and a drain electrode 112 formed on the second contact layer 105.
[0035] The substrate 101 may be made of V-group polar AlN with a (000-1) plane orientation on its main surface. Alternatively, the substrate 101 may be a sapphire substrate with a nitrided surface. Alternatively, the substrate 101 may be made of C-polar hexagonal close-packed SiC.
[0036] The barrier layer 102 is made of Al, which has a group V polarity due to crystal growth in the −c-axis direction on the substrate 101. b Ga 1-b The channel layer 103' is made of a compositionally graded AlN (0<b≦1) that is polarized to group V by growing crystals in the −c-axis direction on the substrate 101. a Ga 1-a N (0<a≦1). The Al composition of the channel layer 103' is smaller than that of the barrier layer 102, and the Al composition increases as it approaches the barrier layer 102 (a:q→p, 0<p<q≦1). In other words, the Al composition of the channel layer 103' decreases as it moves away from the barrier layer 102 and toward the top of the device. The Al composition b of the barrier layer 102 is at least the same as the composition-graded Al that constitutes the channel layer 103'. a Ga 1-a The N content is equal to or greater than the maximum Al composition q (q≦b).
[0037] In the second embodiment, the Al composition is gradually decreased toward the surface of the element. a Ga 1-a In the channel layer 103' made of N, a three-dimensional electron slab (3DES) 123 is induced.
[0038] The gate electrode 110 is, for example, in Schottky junction with the channel layer 103′. Alternatively, the gate electrode 110 may be provided on the channel layer 103′ via a gate insulating layer (not shown). The source electrode 111 is formed on the first contact layer 104, and the drain electrode 112 is formed on the second contact layer 105.
[0039] The first contact layer 104 and the second contact layer 105 are formed on the channel layer 103′ with the gate electrode 110 sandwiched therebetween. The first contact layer 104 and the second contact layer 105 are composed of AlGaN with group V polarity. The first contact layer 104 and the second contact layer 105 can be composed of compositionally graded AlGaN, in which the Al composition increases with increasing distance from the channel layer 103′. The first contact layer 104 and the second contact layer 105 composed of compositionally graded AlGaN can be doped with donor impurities or can be undoped. The first contact layer 104 and the second contact layer 105 can be composed of AlGaN heavily doped with donor impurities and having a lower Al composition than the channel layer 103′.
[0040] Here, the substrate 101 can be made of a crystalline material (off-angle substrate) whose main surface is tilted at a maximum of 5° from the (000-1) plane. As is well known, when a nitride semiconductor crystal is grown with group V polarity, the surface flatness of the grown crystal tends to be low. In contrast, by using a substrate with an off-angle of a maximum of 5°, it is possible to achieve good surface flatness. Furthermore, when such an inclined substrate is used, the source electrode 111 and the drain electrode 112 are positioned so that current flows in a direction perpendicular to the tilt direction.
[0041] According to the second embodiment, since the channel layer 103' is made of AlGaN with group V polarity, there is no need to form a barrier layer made of AlGaN with a higher Al composition on the channel layer 103'. Therefore, the induction of 2DHG does not occur, as occurs in the case of a channel layer made of AlGaN with group III polarity. As a result, there is no impact on the current control characteristics of the gate electrode 110. With group V polarity, it is possible to form a contact layer made of compositionally graded AlGaN on the channel layer. As a result, ohmic contact between the source electrode 111 and the drain electrode 112 can be easily obtained.
[0042] Next, a method for manufacturing a nitride semiconductor device according to the second embodiment will be briefly described.
[0043] First, nitride semiconductor layers, including a barrier layer 102, a channel layer 103', and first and second contact layers 104 and 105, are formed on a substrate 101 by metalorganic chemical vapor deposition (MOCVD) (Step 1). Next, inductively coupled plasma (ICP) dry etching is performed to remove a portion of the nitride semiconductor layer in the gate electrode region and the upper portion of the channel layer 103' (Step 2). This process results in the formation of the first and second contact layers 104 and 105. Furthermore, electrode material is deposited on the nitride semiconductor layers (first and second contact layers 104 and 105) by electron beam evaporation to form source and drain electrodes 111 and 112, and ohmic contacts are formed by annealing or other processes (Step 3). Next, ICP dry etching is performed to form element regions and separate the elements (Step 4). Next, gate electrode material is deposited by electron beam evaporation to form the gate electrode 110 (Step 5).
[0044] The order of steps 2 to 4 can be reversed. When a gate insulating layer is formed, a step of forming a gate insulating layer in the gate electrode region is included before step 5. A step of forming a passivation film can be added after step 5. Although the above description uses MOCVD for crystal growth, ICP dry etching for etching, and electron beam evaporation for depositing the electrode material, other methods can also be used.
[0045] The nitride semiconductor device according to the second embodiment can be manufactured as follows.
[0046] First, a barrier layer 102 and a channel layer 103' are formed on a substrate 101 by MOCVD (Step 1). Next, a first contact layer 104 and a second contact layer 105 are formed by regrowth on the channel layer 103' in the regions where the source electrode 111 and the drain electrode 112 are to be formed (Step 2). Next, electrode material is deposited by electron beam evaporation on the first contact layer 104 and the second contact layer 105 formed by regrowth to form the source electrode 111 and the drain electrode 112, and ohmic contacts are formed by annealing or other processes (Step 3). Next, an element region is formed by ICP dry etching to separate the elements (Step 4). Next, a gate electrode 110 is formed by depositing a gate electrode material by electron beam evaporation or other processes (Step 5).
[0047] Regarding steps 2 to 4, step 2 must be performed before step 3, but the order of the other steps can be changed. When a gate insulating layer is formed, a step of forming a gate insulating layer in the gate electrode region is included before step 5. A step of forming a passivation film can be added after step 5. Although the above description uses MOCVD for crystal growth, ICP dry etching for etching, and electron beam evaporation for depositing the electrode material, other methods can also be used.
[0048] As described above, according to the embodiment of the present invention, a channel layer made of AlGaN having a group V polarity and a smaller Al composition than the barrier layer is formed on a barrier layer made of AlGaN having a group V polarity. Therefore, in a nitride semiconductor device using AlGaN, ohmic contact with the source / drain electrodes can be easily obtained without affecting the device characteristics.
[0049] According to the embodiment of the present invention, it is possible to solve the problems that have been encountered in AlGaN FETs using metal polarity (group III polarity) UWBG, such as the generation of 2DHG at the buffer layer interface and the difficulty of forming ohmic contacts on the outermost surface. As a result, it becomes possible to fabricate UWBG semiconductor FETs with low channel resistance and high breakdown voltage.
[0050] Some or all of the above-described embodiments may also be described as, but are not limited to, the following supplementary notes.
[0051] [Supplementary Note 1] A nitride semiconductor device comprising: a barrier layer made of AlGaN having group V polarity and formed on a substrate; a channel layer made of AlGaN having group V polarity and a smaller Al composition than the barrier layer and formed in contact with the barrier layer; a gate electrode formed on the channel layer; first and second contact layers formed on the channel layer with the gate electrode in between, the first and second contact layers made of AlGaN having group V polarity; a source electrode formed on the first contact layer; and a drain electrode formed on the second contact layer.
[0052] [Supplementary Note 2] In the nitride semiconductor device according to Supplementary Note 1, the barrier layer is Al x Ga 1-x N (0<x≦1), and the channel layer has a smaller Al composition than the barrier layer. y Ga 1-y A nitride semiconductor device composed of N (0<y<1).
[0053] [Supplementary Note 3] In the nitride semiconductor device according to Supplementary Note 1, the barrier layer is Al b Ga 1-bThe channel layer is made of AlN (0<b≦1), and the Al composition of the channel layer is smaller than that of the barrier layer, and the Al composition of the channel layer increases as it approaches the barrier layer. a Ga 1-a A nitride semiconductor device comprising N (0<a≦1).
[0054] [Supplementary Note 4] In the nitride semiconductor device according to any one of Supplementary Notes 1 to 3, the first contact layer and the second contact layer are made of AlGaN in which the Al composition increases with increasing distance from the channel layer.
[0055] [Supplementary Note 5] In the nitride semiconductor device according to any one of Supplementary Notes 1 to 3, the first contact layer and the second contact layer are made of AlGaN doped with impurities.
[0056] [Supplementary Note 6] In the nitride semiconductor device according to any one of Supplementary Notes 1 to 5, the substrate is made of a crystalline material whose main surface is inclined at an angle of up to 5° from the (000-1) plane.
[0057] [Supplementary Note 7] The nitride semiconductor device according to Supplementary Note 6, wherein the source electrode and the drain electrode are arranged in a direction perpendicular to the tilt direction of the substrate.
[0058] It should be noted that the present invention is not limited to the above-described embodiments, and it is clear that many modifications and combinations can be made by a person having ordinary knowledge in the art within the technical concept of the present invention.
[0059] 101...substrate, 102...barrier layer, 103...channel layer, 104...first contact layer, 105...second contact layer, 110...gate electrode, 111...source electrode, 112...drain electrode, 121...two-dimensional electron gas (2DEG).
Claims
1. A nitride semiconductor device comprising: a barrier layer made of AlGaN with group V polarity and formed on a substrate; a channel layer made of AlGaN with group V polarity and a smaller Al composition than the barrier layer and formed in contact with the barrier layer; a gate electrode formed on the channel layer; first and second contact layers formed on either side of the gate electrode and made of AlGaN with group V polarity; a source electrode formed on the first contact layer, and a drain electrode formed on the second contact layer.
2. The nitride semiconductor device according to claim 1, wherein the barrier layer is Al x Ga 1-x N (0<x≦1), and the channel layer has a smaller Al composition than the barrier layer. y Ga 1-y A nitride semiconductor device composed of N (0<y<1).
3. The nitride semiconductor device according to claim 1, wherein the barrier layer is Al b Ga 1-b N (0<b≦1), and the channel layer has a smaller Al composition than the barrier layer, and the Al composition increases as it approaches the barrier layer. a Ga 1-a A nitride semiconductor device comprising N (0<a≦1).
4. A nitride semiconductor device according to claim 1, wherein the first contact layer and the second contact layer are made of AlGaN in which the Al composition increases with increasing distance from the channel layer.
5. A nitride semiconductor device according to claim 1, wherein the first contact layer and the second contact layer are made of AlGaN doped with impurities.
6. A nitride semiconductor device according to any one of claims 1 to 5, wherein the substrate is made of a crystalline material whose main surface is inclined at an angle of up to 5° from the (000-1) plane.
7. A nitride semiconductor device according to claim 6, wherein the source electrode and the drain electrode are arranged in a direction perpendicular to the tilt direction of the substrate.
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