Program execution device and program execution method

Abstract

A program execution device (1000) comprises: a task switching unit (1324) that, if a second computation task (1312) is being executed, transfers an execution right from the second computation task (1312) to a first computation task (1311); and a task modification unit (1323) that, if a request to transfer the execution right to the first computation task (1311) is made during execution of the second computation task (1312), interrupts execution of the second computation task (1312), modifies the next checkpoint of the second computation task (1312) on a secondary storage device (1300) so as to cause a call to the task switching unit (1324), and resumes execution of the second computation task (1312) from the point of interruption in the second computation task (1312).

Description

Program execution device and program execution method

[0001] The present disclosure relates to a program execution device and a program execution method.

[0002] In a computer system, the exclusive control function provided by the operating system (OS) can be used to exclusively control multiple threads or tasks, including critical sections, on a single core. For example, when using the exclusive control function provided by the OS from a user program, a system call is issued to invoke the exclusive control function of the kernel. Therefore, in addition to the cost of the exclusive processing itself, there is the cost of switching from userland to the kernel, and this overhead accumulates each time a critical section is executed, resulting in performance degradation.

[0003] Therefore, in Patent Document 1, a userland process sets a flag indicating preemption suppression in its own preemption prohibition variable to 1, and the process calls a setting process to set information about the address where the preemption prohibition variable is located in the OS.The OS, triggered by a periodically occurring timer interrupt, references the preemption prohibition variable using a pre-set preemption prohibition variable address, and if the value of the preemption prohibition flag is 1 and the elapsed time since the preemption suppression start time is less than the duration threshold, continues to execute the process without performing preemption.

[0004] International Publication No. 2016 / 063511

[0005] In Patent Document 1, a userland process can suppress preemption simply by setting a value in its own preemption-prohibited variable immediately before the critical section is executed. From an assembly-level perspective, this can be achieved by adding instructions to load a value into a register and store the register value in memory, and the degradation in process performance is considered small, but not zero. However, in Patent Document 1, if preemption execution is blocked during the execution of a critical section, there is no function to re-execute the blocked preemption after the critical section is executed, and the process must wait for the next preemption opportunity. This can result in long response times.

[0006] Furthermore, when multiple threads or tasks that contain a large number of critical sections densely are mutually exclusive controlled on a single core, overhead due to the processing time of the mutual exclusive control itself accumulates, resulting in a significant performance degradation that cannot be ignored. In addition, there is a problem that the side effect of the mutual exclusive control causes an extension of the response time of the threads or tasks. It is difficult for Patent Document 1 to solve both of these problems.

[0007] The present disclosure has been made in consideration of the above, and aims to provide a program execution device that can perform exclusive control while suppressing performance degradation and extension of response time, even when multiple threads or tasks that include a large number of critical sections at a high density are exclusively controlled on a single processor core.

[0008] To solve the above-mentioned problems and achieve the object, a program execution device according to the present disclosure includes a storage device that stores an operation program and a system program, and a microprocessor that has one or more processor cores and executes the operation program and the system program. The operation program includes a first operation task and a second operation task that has a scheduling priority lower than that of the first operation task, and is executed on a single processor core of the microprocessor. The second operation task includes multiple critical sections and checkpoints located at the beginning of each critical section. The program execution device includes a task switching unit that transfers execution right from the second operation task to the first operation task if the second operation task is being executed, and a task modification unit that, when a request to transfer execution right to the first operation task is received during execution of the second operation task, suspends execution of the second operation task, modifies the second operation task stored in the storage device to call the task switching unit at the next checkpoint in the second operation task, and resumes execution of the second operation task from the point of suspension in the second operation task.

[0009] According to the program execution device of the present disclosure, even when multiple threads or tasks that contain a large number of critical sections at a high density are exclusively controlled on a single processor core, it is possible to perform exclusive control while minimizing performance degradation and extension of response time.

[0010] FIG. 1 is a block diagram showing an example of the configuration of a program execution device according to a first embodiment; FIG. 2 is a time chart showing an example of the operation during execution of an operation program according to the first embodiment; FIG. 3 is a diagram showing an example of a C language description of a second operation task including a critical section according to the first embodiment; FIG. 4 is a diagram showing an example of an assembly description of a second operation task including a critical section according to the first embodiment; FIG. 5 is a diagram showing an example of the configuration of an address calculation unit of a system program of the program execution device according to the first embodiment; FIG. 1 is a block diagram showing an example of the configuration of a calculation program of a program execution device according to a second embodiment; FIG. 2 is a diagram showing an example of a C language description of a second calculation task including a critical section in a second embodiment; FIG. 3 is a flowchart showing an example of the operation of a task correction unit of a system program of a program execution device according to a second embodiment; FIG. 4 is a time chart showing an example of the operation during execution of a calculation program in a third embodiment; FIG. 5 is a diagram showing an example of a C language description of an h-th calculation task including a critical section in a third embodiment;FIG. 10 is a diagram showing an example of a C language description of an h-th operation task including a critical section. FIG. 11 is a diagram showing an example of a C language description of an i-th operation task including a critical section in the fourth embodiment.

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A program execution device and a program execution method according to an embodiment will be described in detail below with reference to the accompanying drawings.

[0012] By reducing the frequency of use of the exclusive control function provided by the OS depending on the execution status of the user program or by executing the exclusive control process in userland instead, it is possible to reduce performance degradation due to the overhead of the exclusive control process. However, when multiple threads or tasks that contain many critical sections at a high density are executed on a single processor core under exclusive control, problems with execution performance and response performance may still occur even if the above-mentioned technology is used.

[0013] As an example of multiple threads or tasks that contain a large number of critical sections at high density, consider the case where a target machine equipped with a dedicated hardware engine and shared memory, such as a PLC (Programmable Logic Controller), is emulated on a single processor core of a host machine, such as an industrial PC (Personal Computer).Incidentally, in embedded devices such as PLCs and industrial PCs, it is common to group similar or interdependent functions and assign them to the same processor core.

[0014] The emulator consists of multiple dedicated hardware engine models and a shared memory model. The dedicated hardware engine models simulate the instruction operations of the dedicated hardware engines using instructions from the host machine's processor. If the instruction to be simulated is a load or store instruction, it will access the shared memory model, so basically, the processing of one instruction in the dedicated hardware engine must be exclusively controlled as an indivisible process (critical section).

[0015] Generally, the performance of an emulator is required to be equal to or better than the specifications of the target machine. For example, if the processor frequency of the target machine is 100 MHz, the time required to execute one instruction must be 10 ns or less. It is easy to imagine that if even a few instructions from the host machine are added to simulate one instruction from the target machine due to mutual exclusion, the performance of the emulator as a whole will be significantly degraded.

[0016] Furthermore, when using exclusive control for critical sections, it is also necessary to consider how to prevent unintended long wait times due to the side effects of exclusive control. In the case of the PLC emulator mentioned above, each task corresponding to a dedicated hardware engine must be able to periodically calculate and send control commands to devices such as servos or motors in real time. For example, if an interrupt triggers task switching between the execution of each dedicated hardware engine model, it is important to have a short interrupt response time and good response performance.

[0017] Furthermore, when multiple threads or tasks that contain a large number of densely packed critical sections are mutually exclusive controlled on a single core, the overhead due to the processing time of the mutual exclusive control itself accumulates, resulting in a significant performance degradation that cannot be ignored. In addition, there is a problem that the side effect of the mutual exclusive control is that it causes an extension of the response time of the threads or tasks. The program execution device according to the embodiment described below solves both of these problems.

[0018] Embodiment 1. A program execution device and a program execution method according to embodiment 1 will be described below. In embodiment 1, an example will be described in which two computation tasks having an execution period and a scheduling priority are prioritized by the OS, but embodiment 1 can also be applied to computation tasks that do not have an execution period or are not prioritized.

[0019] 1 is a block diagram showing an example of the configuration of a program execution device 1000 according to the first embodiment. The program execution device 1000 according to the first embodiment can be constructed using, for example, an embedded controller, but is not limited to this.

[0020] The program execution device 1000 includes a microprocessor 1100, a main memory device 1200, and a secondary memory device 1300 as a memory device.

[0021] The microprocessor 1100 includes one or more processor cores 1100-1 to 1100-4 and executes various programs. While FIG. 1 illustrates a configuration with four processor cores 1100-1 to 1100-4, the number of processor cores is not limited to this. The main memory 1200 stores programs and data required for program execution. The main memory 1200 is, for example, a cache memory or a RAM (Random Access Memory). The secondary memory 1300 stores and retains programs and data required for program execution. The secondary memory 1300 is, for example, a flash memory or an eMMC (embedded multi-media card). The secondary memory 1300 includes an operation program 1310 and a system program 1320. The operation program 1310 includes a first operation task 1311 and a second operation task 1312. The system program 1320 includes an address calculation unit 1321 , a checkpoint information holding register 1322 , a task correction unit 1323 , and a task switching unit 1324 .

[0022] The task correction unit 1323 uses the address calculation unit 1321 to identify the checkpoint to be executed next for the second operation task 1312 being executed and performs correction. At this time, a pair of the address of the checkpoint where correction was performed and the instruction at the position pointed to by the address is stored in the checkpoint information holding register 1322. As will be described later, the checkpoint is simply a mark for identifying a critical section, and no processing is performed by the processor cores 1100-1 to 1100-4. The task switching unit 1324 performs restoration of the checkpoint in the second operation task 1312 corrected by the task correction unit 1323, and switches task execution between the first operation task 1311 and the second operation task 1312.

[0023] 2 is a time chart showing an example of the operation of the computing program 1310 during execution in the first embodiment. The first computing task 1311 and the second computing task 1312 are threads or tasks, which are the smallest units of processing executed by the OS. The first computing task 1311 and the second computing task 1312 share an address space with each other and do not have their own independent address spaces. In addition, the first computing task 1311 and the second computing task 1312 are not interrupt processing or exception processing. The following description will be given taking as an example a case where the first computing task 1311 and the second computing task 1312 are tasks.

[0024] The first calculation task 1311 has a first execution period 2110 and a first scheduling priority 2120. The second calculation task 1312 has a second execution period 2210 and a second scheduling priority 2220 that is lower than the first scheduling priority 2120. The first calculation task 1311 and the second calculation task 1312 are allocated to a single processor core 1100-n provided in the microprocessor 1100 and executed by the OS scheduler based on their respective scheduling priorities.

[0025] While the second operation task 1312 is being executed, a timer interrupt or the like occurs at the start of the first execution cycle 2110 of the first operation task 1311. Then, the execution of the second operation task 1312 is suspended, and because the first scheduling priority 2120 is higher than the second scheduling priority 2220, the OS starts execution of the first operation task 1311. When the execution of the first operation task 1311 ends, execution of the second operation task 1312 resumes from the point where it was interrupted.

[0026] FIG. 3 is a diagram showing an example of a C-language description of a second operation task 1312 including a critical section 3400-n in the first embodiment. n is 1, 2, 3, .... In FIG. 3, a running variable 3100 is defined, indicating whether the second operation task 1312 is running. A value of "true" for the running variable 3100 indicates that the second operation task 1312 is running, while a value of "false" indicates that the second operation task 1312 is not running. A task2() function 3200 is also defined as a routine executed by the second operation task 1312, and it is assumed that the entry point of this routine is linked to the second operation task 1312 when the second operation task 1312 is created. FIG. 3 shows an example of an implementation of the task2() function 3200, in which a code block containing a large number of densely packed critical sections is repeatedly processed using a while statement. The waitUntilDispatched() function is used at the beginning of the while statement block to wait until the OS grants execution permission and the task enters the running state. The waitUntilDispatched() function is written to clearly show the example in Figure 3, and in practice a function that acquires a semaphore or the like provided by the OS may be used. When the wait is released, the running variable 3100 is set to "true", and at the end of the while statement block, the running variable 3100 is set to "false".

[0027] A label is written as a checkpoint 3300-n at the beginning of each critical section 3400-n. In the first embodiment, the checkpoint 3300-n is simply a mark or label for identifying the critical section 3400-n, and no processing is performed by the processor cores 1100-1 to 1100-4. However, since each critical section 3400-n includes a checkpoint 3300-n at its beginning that is modified by the task modification unit 1323, care must be taken to ensure that the two consecutive critical sections 3400-n and 3400-(n+1) are optimized together during compilation so that the boundary between them is not removed. Therefore, for example, as shown in FIG. 3, it is appropriate to write the label equivalent to the checkpoint 3300-n using inline assembler with a volatile modifier.

[0028] Furthermore, the position at which the checkpoints 3300-n are inserted into the second operation task 1312 does not necessarily have to be before or after each critical section 3400-n. For example, a checkpoint may be inserted every third or every fourth critical section. There is a trade-off: the wider the interval at which the checkpoints 3300-n are inserted, the smaller the degree of degradation in execution performance but the longer the response time (poor responsiveness), and the narrower the interval, the greater the degree of degradation in execution performance but the shorter the response time (good responsiveness). Therefore, the insertion interval of the checkpoints 3300-n may be used as a parameter, and the insertion interval of the checkpoints 3300-n may be adjusted based on the degree of degradation in execution performance and the estimated or measured values ​​of the response time.

[0029] Fig. 4 is a diagram showing an example of an assembly description of the second operation task 1312 including a critical section in embodiment 1. Fig. 4 shows a simplified assembly description generated as a result of compiling the C language description of the second operation task 1312 shown in Fig. 3. Checkpoints 4100-n in Fig. 4 correspond to checkpoints 3300-n in Fig. 3, respectively.

[0030] 5 is a diagram showing an example of the configuration of the address calculation unit 1321 of the system program 1320 of the program execution device 1000 according to the first embodiment. The address calculation unit 1321 receives a program counter value as an input, and calculates, from the program counter value, the address of the checkpoint 3300-n to be executed next in the second operation task 1312. The address calculation unit 1321 includes an address table 5100.

[0031] 6 is a diagram showing an example of the configuration of the address table 5100 of the address calculation unit 1321 of the system program 1320 of the program execution apparatus 1000 according to the first embodiment. The address table 5100 is an array of addresses on the main memory device 1200 at which checkpoints 3300-n inserted in the second operation task 1312 are allocated. Entry 6100-n represents the state in which the addresses of checkpoints 3300-n in FIG. 3 and checkpoints 4100-n in FIG. 4 are stored (the addresses of the checkpoints in FIG. 3 and FIG. 4 are the same). The address of checkpoint 3300-n of the second operation task 1312 can be obtained, for example, by declaring a variable corresponding to the label equivalent to checkpoint 3300-n as extern in the second operation task 1312, and then referencing each variable during execution to obtain the address of each checkpoint 3300-n. The series of operations up to loading the acquired addresses into each entry 6100-n only needs to be performed once after the second operation task 1312 is loaded into the main memory 1200, and may be performed during the initialization process of the second operation task 1312.

[0032] 7 is a diagram showing an example of the configuration of the checkpoint information holding register 1322 of the system program 1320 of the program execution device 1000 according to the first embodiment. The checkpoint information holding register 1322 includes an address field 7100 for holding the address of a checkpoint, and an instruction field 7200 for holding the instruction at the location indicated by the checkpoint address.

[0033] 8 is a flowchart showing an example of the operation of the task modification unit 1323 of the system program 1320 of the program execution device 1000 according to the first embodiment. The task modification unit 1323 is called when an execution right transfer request occurs, and modifies the checkpoint 3300-n in the second operation task 1312 as necessary. Here, the execution right transfer request can be made using, for example, an interrupt or a semaphore, and a notification can be sent to the second operation task 1312 from a task assigned to a processor core 1100-m other than the processor core 1100-n to which the operation program 1310 is assigned. When an interrupt is used, the task modification unit 1323 may be implemented as an interrupt handler. When a semaphore is used, the task modification unit 1323 may be implemented as a task.

[0034] In step S8101, it is determined whether the second operation task is running by checking whether the value of the running variable 3100 in the second operation task 1312 is "true" or "false." If the second operation task is running, step S8102 is processed next, and if the second operation task is not running, step S8201 is processed next.

[0035] In step S8102, the program counter (PC) value (return address) at the time when the execution of the second computation task 1312 was interrupted due to the task correction unit 1323 being activated in response to the execution right transfer request is acquired. When the task correction unit 1323 is implemented as an interrupt handler, for example, if the architecture of the microprocessor 1100 is Armv8, the PC value is saved to a link register when an interrupt occurs, and the PC value is acquired by accessing the link register from the interrupt handler. When the task correction unit 1323 is implemented as a task, the OS usually saves register states and the like (context) to a save area on the main memory device 1200 when switching task execution, and the PC value is acquired by accessing the save area.

[0036] In step S8103, the PC value acquired in step S8102 is passed to the address calculation unit 1321, and the address of the checkpoint 3300-n to be executed next in the second operation task 1312 is acquired.

[0037] In step S8104, next checkpoint information, which is a pair of the address of the next checkpoint 3300-n obtained in step S8103 and the instruction placed at the position indicated by the address of the checkpoint 3300-n, is stored in the checkpoint information holding register 1322. These are stored in the address field 7100 and instruction field 7200, respectively.

[0038] In step S8105, the location pointed to by the address of the next checkpoint 3300-n obtained in step S8103 is rewritten to an instruction that calls the entry point of the task switching unit 1324. This is nothing more than rewriting the instruction in the executable text area loaded on the main memory device 1200. For example, if the executable format is ELF (Executable and Linkage Format), this means rewriting the load segment (called the text area) that includes the text section in which the instruction is stored. For this reason, the computation program 1310 needs to assign a writable attribute to the text area when it is compiled. In step S8106, the execution of the task modification unit 1323 ends, and execution of the second computation task 1312 is resumed.

[0039] In step S8201, since it is determined in step S8101 that the second calculation task 1312 is not being executed, the task corrector 1323 directly calls the task switcher 1324, and the first calculation task 1311 is started.

[0040] 9 is a flowchart showing an example of the operation of the task switching unit 1324 of the system program 1320 of the program execution device 1000 according to the first embodiment. The task switching unit 1324 restores the checkpoint in the second calculation task 1312 corrected by the task correction unit 1323, and transfers the execution right from a task with a low scheduling priority to a task with a high scheduling priority by using a function of the OS. The task switching unit 1324 may be implemented as, for example, a function.

[0041] In step S9101, it is determined whether the second operation task 1312 is running. For example, this determination may be made by referring to whether the value of the running variable 3100 in the second operation task 1312 is "true" or "false." If the second operation task 1312 is running, step S9102 is processed next, and if the second operation task 1312 is not running, step S9104 is processed next.

[0042] In step S9102, a pair of the address of the checkpoint 3300-n corrected by the task corrector 1323 and the instruction located at the position indicated by the address of the checkpoint 3300-n is obtained from the checkpoint information holding register 1322.

[0043] In step S9103, the location indicated by the address obtained in step S9102 is rewritten with the command obtained in step S9102.

[0044] In step S9104, the second operation task 1312, which has a lower second scheduling priority 2220, transfers the execution right to the first operation task 1311, which has a higher first scheduling priority 2120. The transfer of execution right can be achieved, for example, by using a binary semaphore. In the first operation task 1311 and the second operation task 1312, which are assigned to a single processor core 1100-n, the second operation task 1312 starts execution by acquiring a binary semaphore (P operation). During the execution of the second operation task 1312, when the task switcher 1324 is called from a checkpoint in the second operation task 1312 via steps S8101 to S8106 of the task corrector 1323 described above, or when the task switcher 1324 is called from the task corrector 1323 via steps S8101 to S8201, the task switcher 1324 releases the binary semaphore (V operation). As a result, the OS determines that the first calculation task 1311 has the highest scheduling priority among the calculation tasks currently being executed or executable on the processor core 1100-n, and switches execution from the second calculation task 1312 to the first calculation task 1311.

[0045] In step S9105, the process waits until the execution of the first operation task 1311 is completed.

[0046] In step S9106, the process returns to the address obtained in step S9102, and execution of the second operation task 1312 is resumed. Assuming that the task switching unit 1324 is implemented as a function, typically, when a function is called, the address of the instruction following the jump instruction to the entry point of the function is held in a dedicated register as a return address, and is used when returning from the function to the caller. In the first embodiment, the position of the first instruction at the beginning of each critical section 3400-n in the second operation task 1312 is set as the checkpoint 3300-n. When a request for transfer of execution right is made, the task modification unit 1323 rewrites the checkpoint 3300-(n+1) next to the critical section 3400-n that was being executed to an instruction that calls the task switching unit 1324. If the task switching unit 1324 is called from the checkpoint 3300-(n+1) and returns to the second operation task 1312 from the task switching unit 1324, returning to the return address held in the dedicated register will result in returning to the position of the second instruction from the beginning of the critical section 3400-n, and the first instruction from the beginning will not be executed. To avoid this, when returning to the second operation task 1312 from the task switching unit 1324, it is necessary to return to the address obtained from the checkpoint information holding register 1322.

[0047] 10 is a sequence diagram showing an example of a series of operations of the components of the program execution device 1000 according to the first embodiment. Fig. 10 shows how the first operation task 1311, the second operation task 1312, the task correction unit 1323, and the task switching unit 1324 interact with each other when an execution right transfer request occurs during execution of the critical section 3400-2 in the second operation task 1312.

[0048] First, when an execution right transfer request occurs during execution of the critical section 3400-2 in the second operation task 1312, the task correction unit 1323 is activated and performs correction so that the task switch unit 1324 is called from the checkpoint 3300-3 located at the beginning of the next critical section 3400-3. Execution of the task correction unit 1323 ends, and the unexecuted part of the critical section 3400-2 that was being executed in the second operation task 1312 is executed. Execution reaches the checkpoint 3300-3 at the beginning of the next critical section 3400-3, and the task switch unit 1324 is called. The task switch unit 1324 performs correction so that the task switch unit 1324 is not called from the checkpoint 3300-3, and the execution right is transferred from the second operation task 1312 to the first operation task 1311, and the first operation task 1311 is executed.

[0049] When the execution of the first calculation task 1311 is completed, the execution right is returned to the task switching unit 1324 and returned to the second calculation task 1312, and the execution of the second calculation task 1312 is resumed from the beginning of the critical section 3400-3.

[0050] <Effects of the First Embodiment> In the first embodiment, when two threads or tasks containing a large number of densely packed critical sections are executed on a single processor core 1100-n, when a request for transfer of execution rights occurs, the task modification unit 1323 modifies the currently executing task to call the task switching unit 1324 from a checkpoint in the currently executing task, and exclusive control is achieved by switching execution to another task starting from the modified checkpoint. When a request for transfer of execution rights does not occur, the task modification unit 1323 does not modify the currently executing task, and the original task simply has a checkpoint (label) inserted that is not processed by the processor core 1100-n, so performance degradation during execution is, in principle, zero. Furthermore, because task execution switching is always performed starting from a checkpoint, there is an effect of preventing an unintended extension of response time.

[0051] Second Embodiment. A program execution device and a program execution method according to the second embodiment will be described below. In the following description, components similar to those described in the first embodiment will be denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate. In the second embodiment, an example will be described in which two computation tasks having an execution period and a scheduling priority are priority-scheduled by the OS, but the second embodiment can also be applied to computation tasks that do not have an execution period or are not priority-scheduled.

[0052] In the first embodiment, when a request for transfer of execution rights occurs, the task modification unit 1323 rewrites the checkpoint in the task being executed. In other words, an operation is performed to rewrite the executable text area loaded on the main memory device 1200. Generally, a text area is set with a readable attribute and an executable attribute by a compiler, and rewriting to the text area is not possible during execution of the text area. If a text area intended to be read and executed is rewritten during execution, a malicious code block could be inserted and executed, and therefore this is suppressed from a security perspective. Therefore, in the second embodiment, a program execution device and a program execution method will be described that do not require the operation of rewriting the text area during execution.

[0053] 11 is a block diagram showing an example of the configuration of a system program 11000 of the program execution device 1000 according to the second embodiment. The system program 11000 includes a task correction unit 11100 and a task switching unit 11200.

[0054] FIG. 12 is a diagram showing an example of a C language description of the second operation task 1312 including a critical section 12400-n in the second embodiment. In FIG. 12, a function pointer 12200 is defined as a checkpoint and initialized to "0." The function pointer 12200 will be described in detail in the explanation of the operation flow of the task correction unit 11100, and this is a difference from the first embodiment. The task correction unit 11100 assigns the address of the entry point of the task switcher 11200 to the function pointer 12200. FIG. 12 shows an example of an implementation of the task2() function 12300 in which a code block including a large number of critical sections 12400-n densely is repeatedly processed using a while statement. The waitUntilDispatched() function is used at the beginning of the while statement block to wait until the OS grants execution permission and the task enters the running state. When the wait is released, the running variable 12100 is set to "true", and at the end of the while block the running variable 12100 is set to "false".

[0055] At the beginning of each critical section 12400-n, code is written as checkpoints 12200-1 to 12200-3 to check that the value of the function pointer is not "0" and to call the task switcher 11200 by referencing the function pointer. Thus, in the second embodiment, checkpoints 12200-1 to 12200-3 are code for calling the task switcher 11200 by referencing the function pointer, and overhead is generated during execution for conditional branching depending on the value of the function pointer at the checkpoint. This code for checking the value of the function pointer and calling the function using the function pointer generates overhead for processing the conditional branching compared to the first embodiment, in which the second operation task 1312 does not contain any extra code. Note that the label corresponding to checkpoint 3300-n in FIG. 3 is not processed during execution. Therefore, in order to reduce overhead, hint information indicating whether the conditional branch is more likely to be taken or not taken may be provided to the compiler. For example, if GCC (GNU Compiler Collection) is used as the compiler and there is a high probability that the conditional branch of the if statement at checkpoint 12200-n will not be satisfied, checkpoint 12200-n can be written as "if(__builtin_expect(!!(checkpoint)、0))checkpoint();" using the built-in functions provided by GCC.

[0056] 13 is a flowchart showing an example of the operation of the task modification unit 11100 of the system program 11000 of the program execution device 1000 according to the second embodiment. The task modification unit 11100 is called when a request for transfer of execution rights occurs, and modifies the checkpoint 12200-n in the second operation task 1312 as necessary. Here, the execution right transfer request can be made using, for example, an interrupt or a semaphore, and a notification can be sent to the second operation task 1312 from a task assigned to a processor core 1100-m other than the processor core 1100-n to which the operation program 1310 is assigned. When an interrupt is used, the task modification unit 11100 may be implemented as an interrupt handler. When a semaphore is used, the task modification unit 11100 may be implemented as a task.

[0057] In step S13101, it is determined whether the second operation task is being executed by checking whether the value of the running variable 12100 in the second operation task 1312 is "true" or "false." If the second operation task is being executed, step S13102 is processed next, and if the second operation task is not being executed, step S13201 is processed next.

[0058] In step S13102, the address of the entry point of the task switching unit 11200 is cast to the function pointer corresponding to checkpoint 12200-n and assigned to the function pointer. Unlike in the first embodiment, the task correction unit 11100 does not need to specify the position to be corrected, and only needs to rewrite the value of the function pointer.

[0059] In step S13103, the execution of the task modifier 11100 ends, and the execution of the second calculation task 1312 resumes.

[0060] In step S13201, since it is determined that the second calculation task 1312 is not being executed, the task corrector 11100 directly calls the task switcher 11200 and starts the first calculation task 1311.

[0061] 14 is a flowchart showing an example of the operation of the task switching unit 11200 of the system program 11000 of the program execution device 1000 according to the second embodiment. The task switching unit 11200 restores the checkpoint 12200-n in the second calculation task 1312 corrected by the task correction unit 11100, and transfers the execution right from a task with a low scheduling priority to a task with a high scheduling priority by using an OS function. The task switching unit 11200 may be implemented as a function, for example.

[0062] In step S14101, it is determined whether the second operation task 1312 is running. For example, this determination may be made by referring to whether the value of the running variable 12100 in the second operation task 1312 is "true" or "false." If the second operation task 1312 is running, step S14102 is processed next, and if the second operation task 1312 is not running, step S14103 is processed next.

[0063] In step S14102, the task corrector 11100 assigns an invalid value "0" to the function pointer corresponding to the checkpoint 12200-n corrected by the task corrector 11100.

[0064] In step S14103, the second computation task 1312 having the lower second scheduling priority 2220 transfers the execution right to the first computation task 1311 having the higher first scheduling priority 2120.

[0065] In step S14104, the process waits until the execution of the first operation task 1311 is completed.

[0066] In step S14105, the process returns to the checkpoint 12200-n in the second operation task 1312, and resumes the execution of the second operation task 1312. When the task switching unit 11200 is implemented as a function, this step is a return operation from a normal function.

[0067] <Effects of the Second Embodiment> In the second embodiment, similar to the first embodiment, when two threads or tasks that densely include a large number of critical sections 12400-n are executed on a single processor core 1100-n, when a request for transfer of execution rights occurs, the task modification unit 11100 modifies the currently executing task so that the task switching unit 11200 is called from a checkpoint in the currently executing task, and exclusive control is achieved by switching execution to another task starting from the modified checkpoint. In the second embodiment, compared to the first embodiment, there is overhead during execution due to conditional branching depending on the value of a function pointer at a checkpoint, but performance degradation is minimized by measures such as providing a hint to the compiler regarding the direction of the conditional branch. According to the second embodiment, the same effect as the first embodiment is achieved in terms of extending response time. In addition, in the second embodiment, the task modification unit 11100 does not rewrite the text area loaded on the main memory device 1200, which has the effect of closing security holes that allow malicious code blocks to be inserted and executed during execution.

[0068] Embodiment 3. A program execution device and a program execution method according to embodiment 3 will be described below. In the following description, components similar to those described in embodiments 1 and 2 will be illustrated with the same reference numerals, and detailed description thereof will be omitted as appropriate. Furthermore, embodiment 3 will be described by showing an example in which three or more computation tasks each having an execution period and a scheduling priority are prioritized by the OS, but embodiment 3 can also be applied to computation tasks that do not have an execution period or are not prioritized.

[0069] In the first and second embodiments, a program execution device was described in which an arithmetic program includes two arithmetic tasks, all of which are assigned to a single processor core for execution. In the third embodiment, a program execution device and a program execution method will be described in which an arithmetic program includes three or more tasks, all of which are assigned to a single processor core for execution. In particular, the third embodiment is based on the first embodiment and is a program execution device in which the number of arithmetic tasks is expanded to three or more. In the third embodiment, as in the first embodiment, checkpoints are simply marks or labels for identifying critical sections, and no processing is performed by the processor cores 1100-1 to 1100-4.

[0070] First, the basic idea of ​​the third embodiment will be described. In the first embodiment, since the number of computation tasks was two, one (the second computation task 1312) was an interrupted computation task, and the other (the first computation task 1311) was an interrupting computation task. Therefore, the number of simultaneous occurrences of execution right transfer requests during the execution of the second computation task 1312 was at most one. In contrast, in the third embodiment, since the number of computation tasks is three or more, there will be two or more interrupting computation tasks. In other words, it is assumed that there will be cases in which the number of simultaneous occurrences of execution right transfer requests during the execution of a certain computation task will be two or more.

[0071] Digging deeper into the cases where multiple execution right transfer requests may occur as described above, in FIG. 10 of the first embodiment, if another execution right transfer request occurs during the period from the time an execution right transfer request is generated until the time the first operation task 1311 starts executing, a problem occurs. During this period, the checkpoint in the second operation task 1312 that was originally being executed is rewritten to an instruction to jump to the entry point of the task switching unit 1324. If another execution right transfer request occurs during this period, it may happen that the same checkpoint in the second operation task 1312 is rewritten twice, or that the address of the checkpoint to be rewritten cannot be obtained. To avoid these cases, a mechanism is provided in which another execution right transfer request is not accepted during this period.

[0072] 15 is a block diagram showing an example of the configuration of a calculation program 15000 of the program execution device 1000 according to the third embodiment. The calculation program 15000 includes N tasks, including a first calculation task 15100, an h-th calculation task 15200, and an i-th calculation task 15300 (1<h<i≦N). The h-th calculation task 15200 corresponds to the second calculation task in the claims, and the i-th calculation task 15300 corresponds to the third calculation task in the claims.

[0073] 16 is a time chart showing an example of the operation during execution of the computing program 15000 in the third embodiment. The first computing task 15100 has a first execution period 16110 and a first scheduling priority 16120. The h-th computing task 15200 has an h-th execution period 16210 and an h-th scheduling priority 16220 that is lower than the first scheduling priority 16120. The i-th computing task 15300 has an i-th execution period 16310 and an i-th scheduling priority 16320 that is lower than the h-th scheduling priority 16220. The first computing task 15100, the h-th computing task 15200, and the i-th computing task 15300 are allocated to a single processor core 1100-n provided in the microprocessor 1100 and executed by the OS scheduler based on their respective scheduling priorities.

[0074] When the i-th operation task 15300 is being executed, a timer interrupt or the like occurs at the start of the h-th execution cycle 16210 of the h-th operation task 15200. Then, the execution of the i-th operation task 15300 is suspended, and since the h-th scheduling priority 16220 is higher than the i-th scheduling priority 16320, the h-th operation task 15200 is executed by the OS. When the execution of the h-th operation task 15200 is completed, execution of the i-th operation task 15300 is resumed from the point where it was interrupted.

[0075] When the h-th operation task 15200 is being executed, a timer interrupt or the like occurs at the start of the first execution cycle 16110 of the first operation task 15100. Then, the execution of the h-th operation task 15200 is suspended, and since the first scheduling priority 16120 is higher than the h-th scheduling priority 16220, the OS executes the first operation task 15100. When the execution of the first operation task 15100 ends, execution of the h-th operation task 15200 resumes from the point where it was interrupted.

[0076] FIG. 17 is a diagram showing an example of a C language description of an h-th operation task 15200 including a critical section 17400-n in the third embodiment (1≦h<i≦N). In FIG. 17, a running_h variable 17100 is defined, which indicates whether the h-th operation task 15200 is running. If the value of the running_h variable 17100 is "true", it indicates that it is running, and if it is "false", it indicates that it is not running. In addition, a task_h() function 17200 is defined as a routine executed by the h-th operation task 15200, and it is assumed that the entry point of this routine is linked to the h-th operation task 15200 when the h-th operation task 15200 is generated. In FIG. 17, an example is shown in which a while statement is used to repeatedly process a code block including a large number of critical sections 17400-n densely, as an implementation of the task_h() function 17200. The waitUntilDispatched() function is used at the beginning of the while statement block to wait until the execution right is granted by the task switching unit 1324 and the task enters a running state. When the wait is released, the running_h variable 17100 is set to "true", allowing acceptance of the execution right transfer request, and the running_h variable 17100 is set to "false" at the end of the while statement block.

[0077] At the beginning of each critical section 17400-n, a label is written as a checkpoint 17300-n.

[0078] FIG. 18 is a diagram showing an example of a C language description of the i-th operation task 15300 including a critical section 18400-n in the third embodiment (1≦h<i≦N). In FIG. 18, a running_i variable 18100 is defined, indicating whether the i-th operation task 15300 is running. A value of "true" for the running_i variable 18100 indicates that the task is running, and a value of "false" indicates that the task is not running. A task_i() function 18200 is also defined as a routine executed by the i-th operation task 15300, and it is assumed that the entry point of this routine is linked to the i-th operation task 15300 when the i-th operation task 15300 is generated. FIG. 18 shows an example of the implementation of the task_i() function 18200, in which a code block including a large number of densely packed critical sections 18400-n is repeatedly processed using a while statement. The waitUntilDispatched() function is used at the beginning of the while statement block to wait until the OS grants execution permission and the task enters the running state. When the wait is released, the running_i variable 18100 is set to "true", the acceptance of the execution right transfer request is permitted, and the running_i variable 18100 is set to "false" at the end of the while statement block.

[0079] At the beginning of each critical section 18400-n, a label is written as a checkpoint 18300-n.

[0080] 19 is a flowchart showing an example of the operation of the task modification unit 1323 of the system program 1320 of the program execution device 1000 according to the third embodiment. The task modification unit 1323 is called when an execution right transfer request occurs, and modifies the checkpoint in the computation task that was being executed as necessary. Here, the execution right transfer request can be made using, for example, an interrupt or a semaphore, and a notification can be sent to the i-th computation task 15300 from a task assigned to a processor core 1100-m other than the processor core 1100-n to which the computation program 15000 is assigned. When an interrupt is used, the task modification unit 1323 may be implemented as an interrupt handler. When a semaphore is used, the task modification unit 1323 may be implemented as a task.

[0081] In step S19101, the processor core 1100-n to which the computing program 15000 is assigned is prohibited from accepting a request for transfer of execution rights. When an interrupt is used for the request for transfer of execution rights, an interrupt with a specific ID (Identification) can be masked, or all interrupts can be prohibited. When a semaphore is used for the request for transfer of execution rights, similar measures can be taken. When a specific task is started by releasing a semaphore, the OS usually issues an interrupt to the processor core to switch the execution of the task.

[0082] In step S19102, the task modification unit 1323 identifies the task ID of the computation task to be executed next after the computation task that was being executed immediately before being called. Here, it is assumed that the execution right transfer request corresponds one-to-one with the computation task to be executed next. When an interrupt is used, one interrupt ID is associated with one task. When a semaphore is used, one semaphore is associated with one task. In this way, the task modification unit 1323 can identify the task ID of the computation task to be executed next by referring to the interrupt ID or the semaphore.

[0083] In step S19103, the value of the running variable of all the calculation tasks is checked to see if it is "true" or "false" to determine whether any calculation task is running. If it is running, step S19104 is processed next, and if it is not running, step S19201 is processed next.

[0084] In step S19104, the PC value at the time when the execution of the i-th calculation task 15300 was interrupted due to the task corrector 1323 being activated in response to the execution right transfer request is acquired.

[0085] In step S19105, the PC value acquired in step S19104 is passed to the address calculation unit 1321, and the address of the checkpoint 18300-n to be executed next in the calculation task that was being executed is acquired. Note that the address table 5100 provided in the address calculation unit 1321 may acquire the address of the checkpoint in the initialization process of each calculation task using the method described in the description of Fig. 6, for example, and load the acquired address into each entry 6100-n.

[0086] In step S19106, the next checkpoint information, which is a pair of the address of the next checkpoint 18300-n acquired in step S19105 and the instruction placed at the position indicated by the address of the checkpoint 18300-n, is stored in the checkpoint information holding register 1322.

[0087] In step S19107, the location indicated by the address of the next checkpoint 18300-n acquired in step S19106 is rewritten to a command to call the entry point of the task switching unit 1324.

[0088] In step S19108, the execution of the task corrector 1323 is completed, and the execution of the i-th operation task 15300 that was being executed is resumed.

[0089] In step S19201, since it is determined in step S19103 that no arbitrary calculation task is being executed, the task corrector 1323 directly calls the task switcher 1324, and starts the calculation task designated by the task ID.

[0090] 20 is a flowchart showing an example of the operation of the task switching unit 1324 of the system program 1320 of the program execution device 1000 according to the third embodiment. The task switching unit 1324 performs restoration for a checkpoint in an ongoing computation task that has been corrected by the task correction unit 1323. The task switching unit 1324 also uses an OS function to transfer the execution right from a task with a low scheduling priority to a task with a high scheduling priority. It is assumed that the task switching unit 1324 receives the task ID of the computation task from the task correction unit 1323.

[0091] In step S20101, it is determined whether any calculation task is running. For example, this determination may be made by referring to whether the value of the running variable of all calculation tasks is "true" or "false." If any calculation task is running, step S20102 is processed next, and if not running, step S20104 is processed next.

[0092] In step S20102, a pair of the checkpoint address corrected by the task corrector 1323 and the instruction located at the position indicated by the checkpoint address is obtained from the checkpoint information holding register 1322.

[0093] In step S20103, the location indicated by the address obtained in step S20102 is rewritten with the command obtained in step S20102.

[0094] In step S20104, the execution right is transferred from the currently running computation task to the computation task specified by the task ID. For example, the execution right is transferred from the i-th computation task 15300 having a lower i-th scheduling priority 16320 to the h-th computation task 15200 having a higher h-th scheduling priority 16220.

[0095] In step S20105, the process waits until the execution of the calculation task specified by the task ID is completed.

[0096] In step S20106, the process returns to the address obtained in step S20102, and the execution of the previously executing calculation task is resumed.

[0097] Fig. 21 is a sequence diagram showing an example of a series of operations of each component of the program execution device 1000 according to the third embodiment. Fig. 21 shows how the first operation task 15100, the h-th operation task 15200, the i-th operation task 15300, the task correction unit 1323, and the task switch unit 1324 interact with each other when a request for transfer of execution right to the h-th operation task 15200 occurs during the execution of the critical section 18400-2 in the i-th operation task 15300, and then a request for transfer of execution right to the first operation task 15100 occurs during the execution of the critical section 17400-1 in the h-th operation task 15200.

[0098] First, when a request for transfer of execution rights to the h-th operation task 15200 occurs during the execution of the critical section 18400-2 in the i-th operation task 15300, the task correction unit 1323 is activated, and after prohibiting acceptance of the execution rights transfer request at the beginning of the critical section, the task correction unit 1323 corrects the task so that the task switch unit 1324 is called from the checkpoint 18300-3 located at the beginning of the next critical section 18400-3. When the execution of the task correction unit 1323 ends, the unexecuted part of the critical section 18400-2 that was being executed in the i-th operation task 15300 is executed. When the execution reaches the checkpoint 18300-3 at the beginning of the next critical section 18400-3, the task switch unit 1324 is called. The task switching unit 1324 is modified so as not to call the task switching unit 1324 from the checkpoint 18300-3, and the execution right is transferred from the i-th operation task 15300 to the h-th operation task 15200, and the h-th operation task 15200 is executed, and the acceptance of the execution right transfer request is permitted at the head of the task.

[0099] Next, when a request for transfer of execution rights to the first operation task 15100 occurs during the execution of the critical section 17400-1 in the h-th operation task 15200, the task correction unit 1323 is activated, and after prohibiting acceptance of the execution rights transfer request at the beginning of the critical section, the task correction unit 1323 corrects the task so that the task switch unit 1324 is called from the checkpoint 17300-2 located at the beginning of the next critical section 17400-2. When the execution of the task correction unit 1323 ends, the unexecuted part of the critical section 17400-1 that was being executed in the h-th operation task 15200 is executed. When the execution reaches the checkpoint 17300-2 at the beginning of the next critical section 17400-2, the task switch unit 1324 is called. The task switching unit 1324 is modified so that it is not called from checkpoint 17300-2, and the execution right is transferred from the h-th operation task 15200 to the first operation task 15100. The h-th operation task 15200 is executed, and after allowing the acceptance of the execution right transfer request at the beginning of the task, the subsequent processing is executed.

[0100] When the execution of the first operation task 15100 is completed, the execution right is returned to the task switching unit 1324, and the execution is returned to the h-th operation task 15200, and the execution of the h-th operation task 15200 is resumed from the beginning of the critical section 17400-2. When the execution of the h-th operation task 15200 is completed, the execution is returned to the i-th operation task 15300, and the execution of the i-th operation task 15300 is resumed from the beginning of the critical section 18400-3.

[0101] <Effects of the Third Embodiment> In the third embodiment, when three or more threads or tasks containing a large number of closely spaced critical sections are executed on a single processor core 1100-n, when a request for transfer of execution rights occurs, the task modification unit 1323 modifies the currently executing task to call the task switching unit 1324 from a checkpoint in the currently executing task, and exclusive control is achieved by switching execution to another task starting from the modified checkpoint. When a request for transfer of execution rights does not occur, the task modification unit 1323 does not modify the currently executing task, and the original task simply has a checkpoint (label) inserted that is not processed by the processor core 1100-n, so performance degradation during execution is, in principle, zero. Furthermore, because task execution switching is always performed starting from a checkpoint, there is an effect of preventing an unintended extension of response time.

[0102] Fourth Embodiment. A program execution device and a program execution method according to a fourth embodiment will be described below. In the following description, components similar to those described in the first to third embodiments will be illustrated with the same reference numerals, and detailed description thereof will be omitted as appropriate. Furthermore, in the fourth embodiment, an example will be described in which three or more computation tasks each having an execution period and a scheduling priority are prioritized by the OS, but the fourth embodiment can also be applied to computation tasks that do not have an execution period or are not prioritized.

[0103] In the fourth embodiment, similar to the third embodiment, a program execution device and a program execution method will be described for a case where an operation program includes three or more operation tasks, all of which are assigned to a single processor core for execution. In particular, the fourth embodiment is a program execution device based on the second embodiment, in which the number of operation tasks is expanded to three or more.

[0104] FIG. 22 is a diagram showing an example of a C language description of the h-th operation task 15200 including a critical section 22400-n in the fourth embodiment. In FIG. 22, a function pointer 22200 is defined as a checkpoint and initialized to "0." The task modification unit 11100 assigns the address of the entry point of the task switcher 11200 to the function pointer 22200. FIG. 22 shows an example of an implementation of the task_h() function 22300 in which a code block including a large number of critical sections 22400-n densely is repeatedly processed using a while statement. The waitUntilDispatched() function is used at the beginning of the while statement block to wait until the task switcher 11200 grants execution rights and the task enters the running state. When the wait is released, the running_h variable 22100 is set to "true," allowing the acceptance of a request to transfer execution rights, and the running_h variable 22100 is set to "false" at the end of the while statement block.

[0105] At the beginning of each critical section 22400-n, code is written as checkpoints 22200-1 to 3 to check that the value of function pointer 22200 is not "0" and to call task switcher 11200 by referencing function pointer 22200. In this way, in the fourth embodiment, checkpoints 22200-1 to 3 are code to call task switcher 11200 by referencing the function pointer, as in the second embodiment, and during execution, overhead is generated for conditional branching depending on the value of the function pointer at the checkpoint.

[0106] FIG. 23 is a diagram showing an example of a C language description of the i-th operation task 15300 including a critical section 23400-n in the fourth embodiment. In FIG. 23, a function pointer 23200 is defined as a checkpoint and initialized to "0." The task modification unit 11100 assigns the address of the entry point of the task switching unit 11200 to the function pointer 23200. FIG. 23 shows an example of an implementation of the task_i() function 23300 in which a code block including a large number of critical sections densely is repeatedly processed using a while statement. The waitUntilDispatched() function is used at the beginning of the while statement block to wait until the OS grants execution rights and the task enters the running state. When the wait is released, the running_i variable 23100 is set to "true," allowing the execution rights transfer request to be accepted, and the running_i variable 23100 is set to "false" at the end of the while statement block.

[0107] At the beginning of each critical section 23400-n, there is written a code as checkpoints 23200-1 to 23200-3 for checking that the value of the function pointer 23200 is not "0" and for calling the task switcher 11200 by referencing the function pointer 23200.

[0108] 24 is a flowchart showing an example of the operation of the task modification unit 11100 of the system program 11000 of the program execution device 1000 according to the fourth embodiment. The task modification unit 11100 is invoked when a request for transfer of execution rights occurs, and performs modification, as necessary, to a checkpoint in the computation task that was being executed.

[0109] In step S24101, the processor core 1100-n to which the arithmetic program 16000 is allocated is prohibited from accepting an execution right transfer request.

[0110] In step S24102, the task modification unit 11100 identifies the task ID of the computation task to be executed next after the computation task that was being executed immediately before being called. Here, it is assumed that the execution right transfer request corresponds one-to-one with the computation task to be executed next. When an interrupt is used, one interrupt ID is associated with one task. When a semaphore is used, one semaphore is associated with one task. In this way, the task modification unit 11100 can identify the task ID of the computation task to be executed next by referring to the interrupt ID or semaphore.

[0111] In step S24103, the value of the running variable of all the calculation tasks is checked to see if it is "true" or "false" to determine whether any calculation task is running. If it is running, step S24104 is processed next, and if it is not running, step S24201 is processed next.

[0112] In step S24104, the address of the entry point of the task switching unit 11200 is cast to the function pointer corresponding to the checkpoint in the computation task that was being executed, and assigned to the function pointer. Unlike the first and third embodiments, the task correction unit 11100 does not need to specify the position to be corrected, and only needs to rewrite the value of the function pointer.

[0113] In step S24105, the execution of the task corrector 11100 is completed, and the execution of the calculation task that was being executed is resumed.

[0114] In step S24201, since it is determined in step S24103 that no arbitrary computation task is being executed, the task corrector 11100 directly calls the task switcher 11200 and starts the computation task designated by the task ID.

[0115] 25 is a flowchart showing an example of the operation of the task switching unit 11200 of the system program 11000 of the program execution device 1000 according to the fourth embodiment. The task switching unit 11200 performs restoration of the checkpoint in the currently running computation task corrected by the task correction unit 11100, and transfers the execution right from a task with a low scheduling priority to a task with a high scheduling priority by using an OS function. The task switching unit 11200 may be implemented as, for example, a function.

[0116] In step S25101, it is determined whether any calculation task is running. For example, this determination may be made by referring to whether the value of the running variable of all calculation tasks is "true" or "false". If any calculation task is running, step S25102 is processed next, and if not running, step S25103 is processed next.

[0117] In step S25102, the task corrector 11100 assigns "0" to the function pointer corresponding to the checkpoint corrected by the task corrector 11100.

[0118] In step S25103, the execution right is transferred from the currently running computation task to the computation task specified by the task ID. For example, the execution right is transferred from the i-th computation task 15300 having a lower i-th scheduling priority 16320 to the h-th computation task 15200 having a higher h-th scheduling priority 16220.

[0119] In step S25104, the process waits until the execution of the calculation task designated by the task ID is completed.

[0120] In step S25105, the process returns to the checkpoint in the previously executed computation task, and the execution of that computation task is resumed. If the task switching unit 11200 is implemented as a function, this step is a return operation from a normal function.

[0121] <Effects of the Fourth Embodiment> In the fourth embodiment, when three or more threads or tasks containing a large number of closely spaced critical sections are executed on a single processor core 1100-n, when a request for transfer of execution rights occurs, the task modification unit 11100 modifies the currently executing task so that the task switching unit 11200 is called from a checkpoint in the currently executing task, and exclusive control is achieved by switching execution to another task starting from the modified checkpoint. In the fourth embodiment, compared to the third embodiment, there is overhead during execution due to conditional branching based on the value of a function pointer at a checkpoint, but performance degradation is minimized by measures such as providing a hint to the compiler regarding the direction of the conditional branch. The fourth embodiment has the same effect as the third embodiment in terms of extending response time. In addition, in the fourth embodiment, the task modification unit 11100 does not rewrite the text area loaded on the main memory device 1200, which has the effect of closing security holes that allow malicious code blocks to be inserted and executed during execution.

[0122] It should be noted that within the scope of the present disclosure, the embodiments may be freely combined, modified, or omitted as appropriate. Although the present disclosure has been described in detail, the above description is illustrative in all respects and is not limiting. It is understood that countless variations not illustrated can be envisioned.

[0123] The configurations shown in the above embodiments are examples of the contents of the present disclosure, and may be combined with other known technologies, or embodiments may be combined with each other, and some of the configurations may be omitted or modified within the scope of the gist of the present disclosure.

[0124] 1000 program execution device, 1100 microprocessor, 1100-1 to 1100-4, 1100-n, 1100-m processor core, 1200 main memory, 1300 secondary memory, 1310, 15000 operation program, 1311, 15100 first operation task, 1312 second operation task, 1320, 11000 system program, 1321 address calculation unit, 1322 checkpoint information holding register, 1323, 11100 task correction unit, 1324, 11200 task switching unit, 3100, 12100 running variable, 3200, 12300 task2() function, 3300-n, 4100-n, 12200-n, 17300-n, 18300-n, 22200-n, 23200-n Checkpoint, 3400-n, 12400-n, 17400-n, 18400-n, 22400-n, 23400-n critical section, 5100 address table, 6100-n entry, 7100 address field, 7200 instruction field, 12200, 22200, 23200 function pointer, 15200 hth operation task, 15300 ith operation task, 17100, 22100 running_h variable, 17200, 22300 task_h() function, 18100, 23100 running_i variable, 18200, 22300, 23300 task_i() function.

Claims

1. A program execution device comprising: a storage device for storing an operation program and a system program; and a microprocessor having one or more processor cores and executing the operation program and the system program, wherein the operation program includes a first operation task and a second operation task having a scheduling priority lower than that of the first operation task, and is executed on a single processor core of the microprocessor, and the second operation task includes a plurality of critical sections and a checkpoint located at the beginning of each critical section; a task switching unit for transferring execution rights from the second operation task to the first operation task while the second operation task is being executed; and a task modification unit for suspending execution of the second operation task when a request to transfer execution rights to the first operation task is made during execution of the second operation task, modifying the second operation task on the storage device to call the task switching unit for the next checkpoint in the second operation task, and resuming execution of the second operation task from the point of suspension in the second operation task.

2. The program execution device according to claim 1, wherein the system program comprises an address calculation unit that calculates the address of the next checkpoint from a program counter value, and a checkpoint information holding register, and wherein the task correction unit, when the execution right transfer request is made during execution of the second calculation task, suspends execution of the second calculation task, obtains the program counter value at the suspension point, obtains the address of the next checkpoint from the address calculation unit, stores a pair of the checkpoint address and the instruction at the position pointed to by the address in the checkpoint information holding register, and rewrites the checkpoint on the storage device to an instruction that calls the task switching unit.

3. The program execution device according to claim 2, wherein the address calculation unit has an address table that stores the addresses of the checkpoints included in the second operation task, and calculates the address of the next checkpoint in the second operation task by searching the address table with the program counter value.

4. The program execution device according to claim 2, wherein the task switching unit, before transferring execution rights from the second operation task to the first operation task, obtains a pair of the address and instruction of the checkpoint from the checkpoint information holding register, and rewrites the location pointed to by the address in the second operation task on the storage device with the instruction.

5. The program execution device according to claim 1, wherein the checkpoint in the second operation task is a pointer capable of referencing the task switching unit inserted at the beginning of the critical section, and the task correction unit, when the execution right transfer request is made during execution of the second operation task, suspends execution of the second operation task and sets the address of the entry point of the task switching unit to the checkpoint next to the suspension point in the second operation task.

6. The program execution device according to claim 5, wherein the task switching unit sets an invalid value to the checkpoint in the second calculation task, and then transfers the execution right from the second calculation task to the first calculation task.

7. The program execution device according to any one of claims 1 to 6, wherein the operation program includes a third operation task having a lower scheduling priority than the second operation task, and having a plurality of critical sections and a checkpoint located at the beginning of each critical section; the task switching unit, if the third operation task is being executed, transfers execution rights to the first operation task or the second operation task; the task modification unit, when a request to transfer execution rights to the first operation task or the second operation task is made during execution of the third operation task, prohibits acceptance of the execution rights transfer request in the single processor core, suspends execution of the third operation task, modifies the third operation task on the storage device to call the task switching unit at the next checkpoint in the third operation task, and resumes execution of the third operation task from the interruption point in the third operation task; and when the first operation task or the second operation task is in an execution state, the task switching unit permits acceptance of the execution rights transfer request in the single processor core at the beginning of processing.

8. A program execution method using a storage device that stores an operation program and a system program, and a microprocessor that has one or more processor cores and executes the operation program and the system program, wherein the operation program includes a first operation task and a second operation task that has a scheduling priority lower than that of the first operation task, and is executed on a single processor core of the microprocessor, and the second operation task includes a plurality of critical sections and a checkpoint located at the beginning of each critical section, the program execution method comprising: a task switching step of transferring execution rights from the second operation task to the first operation task if the second operation task is being executed; and a task modification step of suspending execution of the second operation task when a request to transfer execution rights to the first operation task is made during execution of the second operation task, modifying the next checkpoint in the second operation task on the storage device so that the task switching step is called, and resuming execution of the second operation task from the point of suspension in the second operation task.

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