Receiver

Abstract

This receiver comprises: a first signal source (6) that outputs a first clock signal having a first frequency and a first phase; second through Mth signal sources (16, 26, 36), where M is an integer greater than or equal to 2, that output (M–1) second through Mth clock signals, each of said clock signals having the first frequency and an Mth phase that is different from the first phase; M first through Mth sample-and-hold circuits (2, 12, 22, 32) that use the M first through Mth clock signals to perform undersampling of a reception signal; M first through Mth phase shifters (5, 15, 25, 35) that shift the phases of output signals from the M first through Mth sample-and-hold circuits; and a synthesizer (9, 39) that synthesizes output signals from the M first through Mth phase shifters, wherein in the output from the M first through Mth phase shifters, components of an Nth Nyquist zone are of the same phase as each other, and components of Nyquist zones other than the Nth Nyquist zone are not of the same phase as each other.

Description

Receiver

[0001] The present disclosure relates to a receiver.

[0002] A receiver is a circuit that receives radio waves propagating through space. For example, a receiver is configured using an antenna, a filter, a frequency converter such as a mixer, an analog-to-digital converter (ADC), and an arithmetic circuit (also called a logic circuit or a digital circuit) such as a field programmable gate array (FPGA).

[0003] As a conventional receiver, for example, Patent Document 1 discloses a configuration in which multiple systems each including an antenna, a BPF (Band Pass Filter) for the RF (Radio Frequency) band, an amplifier, and an undersampling ADC are connected in parallel. In this receiver, of the desired signal, spurious (also called unwanted waves), or noise received by the antenna, the BPF is used to suppress the spurious or noise, allowing only the desired signal to pass, and the desired signal is then amplified and converted to a digital signal.

[0004] JP 2018-179724 A

[0005] However, the receiver disclosed in Patent Document 1 requires RF band BPFs for suppressing spurious or noise for the number of systems. Since RF band BPFs are large in size or cost, there is a problem in that the size or cost of the receiver increases.

[0006] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a receiver that can suppress spurious or noise without increasing the size or cost of the receiver.

[0007] One aspect of a receiver according to an embodiment of the present disclosure includes: a first signal source that outputs a first clock signal having a first frequency and a first phase; second to Mth signal sources that output second to Mth (M−1) clock signals, where M is an integer greater than or equal to 2, each clock signal having the first frequency and an Mth phase that is different from the first phase; first to Mth sample-and-hold circuits that undersample a received signal using the first to Mth clock signals, respectively; first to Mth phase shifters that shift the phases of the output signals of the first to Mth sample-and-hold circuits, respectively; and a combiner that combines output signals of the first to Mth phase shifters, wherein, in the outputs of the first to Mth phase shifters, components in the Nth (N is an integer greater than or equal to 1) Nyquist zone are in phase, and components in one or more Nyquist zones other than the Nth zone are not in phase.

[0008] According to the receiver of the present disclosure, a BPF in the RF band is not required, so spurious or noise can be suppressed without increasing the size or cost of the receiver.

[0009] FIG. 1 is a diagram illustrating an example configuration of a receiver according to a first embodiment of the present disclosure. FIG. 2 is a diagram illustrating the frequency spectrum of the output signal of antenna 1. FIG. 3 is a diagram illustrating the frequency spectrum of the output signal of filter 3. FIG. 4 is a table illustrating the initial phases of the received signal and noise N001 to 004 at the outputs of filter 3, phase shifter 5, filter 13, and phase shifter 15. FIG. 5 is a diagram illustrating an example configuration of a receiver according to a second embodiment of the present disclosure. FIG. 6 is a table illustrating the initial phases of the received signal and noise N001 to 004 at the outputs of phase shifter 5, phase shifter 15, phase shifter 25, and phase shifter 35. FIG. 7 is a table in which values ​​are substituted for the initial phases of the received signal and noise N001 to 004 shown in FIG. 6.

[0010] Various embodiments of the present disclosure will be described in detail below with reference to the drawings. In the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant explanations of such parts will be omitted. In addition, in this disclosure, the term "or" is used to mean an inclusive logical OR unless otherwise specified.

[0011] 1 is a diagram showing an example of the configuration of a receiver according to the first embodiment of this disclosure. This receiver is composed of an antenna 1, an S / H circuit 2, a filter 3, a quantizer 4, a phase shifter 5, a signal source 6, a phase control circuit 7, a phase control circuit 8, a combiner 9, an antenna 11, an S / H circuit 12, a filter 13, a quantizer 14, a phase shifter 15, a signal source 16, a phase control circuit 17, and a phase control circuit 18. ＣＬＫ are the frequencies of the first and second clock signals, θ ＣＬＫ１ is the initial phase of the first clock signal, θ ＣＬＫ２ is the initial phase of the second clock signal, f ｏｕｔ is the frequency of the output signals of the filter 3 and the filter 13, and θ ｏｕｔ１ is the initial phase of the output signal of the filter 3, θ ｏｕｔ２ is the initial phase of the output signal of the filter 13, θ ｏｕｔ３ is the initial phase of the output signal of the phase shifter 5, θ ｏｕｔ４ is the initial phase of the output signal of the phase shifter 15, θ ＰＳ１ is the phase shift amount of the phase shifter 5, θ ＰＳ２ is the amount of phase shift of the phase shifter 15. Here, the initial phase is defined as the phase of a signal at a certain time.

[0012] The antenna 1 is an antenna that receives a signal propagating through space and outputs the received signal to the S / H circuit 2. The output terminal of the antenna 1 is connected to the RF terminal of the S / H circuit 2. For example, an antenna such as a dipole antenna or a patch antenna can be used as the antenna 1. Of course, an array antenna that combines multiple element antennas can also be used. Any configuration can be used as the antenna 1 as long as it can receive a signal propagating through space and output the received signal.

[0013] The S / H circuit 2 is a sample-and-hold (also called track-and-hold) circuit that synchronizes with a first clock signal output by the signal source 6, undersamples (also called subsampling) the signal output by the antenna 1, and outputs the undersampled signal to the filter 3. The RF terminal of the S / H circuit 2 is connected to the output terminal of the antenna 1, the clock terminal of the S / H circuit 2 is connected to the output terminal of the signal source 6, and the output terminal of the S / H circuit 2 is connected to the input terminal of the filter 3. For example, the S / H circuit 2 may be a circuit including a switch that switches between open and short circuits for the input RF signal (the output signal of the antenna 1) and a capacitor that stores charge when the line for the input RF signal is open. The S / H circuit 2 may have any configuration as long as it can undersample the input RF signal and output the undersampled signal. Here, the undersampled signal refers to a signal generated by undersampling.

[0014] The filter 3 has a predetermined passband and passes signals within the passband among the signals output by the S / H circuit 2 and suppresses signals in frequency bands outside the passband. The filter 3 suppresses signals or unwanted waves outside the passband among the signals output by the S / H circuit 2, and outputs the result to the quantizer 4. The input terminal of the filter 3 is connected to the output terminal of the S / H circuit 2, and the output terminal of the filter 3 is connected to the input terminal of the quantizer 4. For example, the filter 3 may be a low pass filter (LPF), a high pass filter (HPF), or a band pass filter (BPF). The filter 3 is implemented using elements such as chip inductors or chip capacitors. The filter 3 may also be configured using other resonators such as microstrip or coaxial resonators depending on the frequency band to be passed or the required amount of suppression. Here, the pass band of the filter 3 is a low frequency band, and even if a BPF is used as the filter 3, the size and cost are not large as compared with a BPF for the RF band.

[0015] The quantizer 4 is a circuit that quantizes an input signal and outputs data of the quantized signal, and quantizes the signal output by the filter 3 and outputs the data of the quantized signal to the phase shifter 5. The input terminal of the quantizer 4 is connected to the output terminal of the filter 3, and the output terminal of the quantizer 4 is connected to the input terminal of the phase shifter 5. For example, an ADC can be used for the quantizer 4. When an ADC is used for the quantizer 4, quantization may be performed in synchronization with a clock signal input from the outside. The quantizer 4 may have any configuration as long as it can quantize an input signal and output data of the quantized signal.

[0016] The phase shifter 5 is a circuit that shifts the phase of an input signal and outputs the phase-shifted signal. ＰＳ１ The quantizer 4 phase-shifts the signal output based on a signal indicating the phase difference, and outputs the phase-shifted signal to the combiner 9. The input terminal of the phase shifter 5 is connected to the output terminal of the quantizer 4, the control terminal of the phase shifter 5 is connected to the output terminal of the phase control circuit 8, and the output terminal of the phase shifter 5 is connected to a first input terminal of the combiner 9. For example, an FPGA can be used for the phase shifter 5. In this case, the FPGA phase-shifts the input signal by changing the initial phase of an NCO (Numerically Controlled Oscillator) in an operation such as a DDC (Digital Down Converter). Alternatively, the FPGA may convert the input signal into a signal in the complex domain and shift the phase using a complex number operation. The phase shifter 5 may have any configuration as long as it can phase-shift the input signal and output the phase-shifted signal.

[0017] The signal source 6 is a circuit that can generate a signal of any waveform or any frequency, and receives the θ ＣＬＫ１ The frequency f ＣＬＫ , initial phase θ ＣＬＫ１The signal source 6 is a signal source that generates a first clock signal. The control terminal of the signal source 6 is connected to the output terminal of the phase control circuit 7, and the output terminal of the signal source 6 is connected to the clock terminal of the S / H circuit 2. For example, the signal source 6 may be a digital-to-analog converter (DAC), a direct digital synthesizer (DDS), or a phase locked loop (PLL) circuit. Although not shown in FIG. 1 , the signal source 6 may generate the first clock signal using an externally input control signal or reference signal. The signal source 6 may have any configuration as long as it can generate a signal of any waveform.

[0018] The phase control circuit 7 controls θ ＣＬＫ１ The phase control circuit 7 is a circuit that outputs a signal indicating θ to the signal source 6. The output terminal of the phase control circuit 7 is connected to the control terminal of the signal source 6. For example, the phase control circuit 7 may be an FPGA or a memory. ＣＬＫ１ The phase control circuit 7 may be configured to calculate θ ＣＬＫ１ Any configuration may be used as long as it can output a signal indicating

[0019] The phase control circuit 8 controls θ ＰＳ１ The phase control circuit 8 is a circuit that outputs a signal indicating θ to the phase shifter 5. The output terminal of the phase control circuit 8 is connected to the control terminal of the phase shifter 5. For example, the phase control circuit 8 may be an FPGA or a memory. ＰＳ１ The phase control circuit 8 may calculate θ ＰＳ１ Any configuration may be used as long as it can output a signal indicating

[0020] The combiner 9 is a circuit that combines (adds) multiple input signals and outputs the combined signal, combining the signal output by the phase shifter 5 and the signal output by the phase shifter 15 and outputting the combined signal to the outside. A first input terminal of the combiner 9 is connected to the output terminal of the phase shifter 5, and a second input terminal of the combiner 9 is connected to the output terminal of the phase shifter 15. For example, an FPGA can be used as the combiner 9. The combiner 9 may have any configuration as long as it can combine (add) multiple input signals and output a combined signal.

[0021] The antenna 11 is an antenna that receives a signal propagating through space and outputs the received signal to the S / H circuit 12. The output terminal of the antenna 11 is connected to the RF terminal of the S / H circuit 12. For example, the antenna 11 may be an antenna such as a dipole antenna or a patch antenna. Of course, an array antenna that combines multiple element antennas may also be used. The antenna 11 may have any configuration as long as it can receive a signal propagating through space and output the received signal.

[0022] The S / H circuit 12 is a sample-and-hold circuit that, in synchronization with the second clock signal output by the signal source 16, undersamples the signal output by the antenna 11 and outputs the undersampled signal to the filter 13. The RF terminal of the S / H circuit 12 is connected to the output terminal of the antenna 11, the clock terminal of the S / H circuit 12 is connected to the output terminal of the signal source 16, and the output terminal of the S / H circuit 12 is connected to the input terminal of the filter 13. For example, the S / H circuit 12 may be a circuit that includes a switch that switches between an open and a short circuit for the input RF signal (the output signal of the antenna 11) and a capacitor that stores charge when the line for the input RF signal is open. Any configuration may be used for the S / H circuit 12 as long as it can undersample the input RF signal and output the undersampled signal.

[0023] The filter 13 has a predetermined passband and passes signals within the passband among the signals output by the S / H circuit 12 and suppresses signals in frequency bands outside the passband. The filter 13 suppresses signals or unwanted waves outside the passband among the signals output by the S / H circuit 12, and outputs the result to the quantizer 14. The input terminal of the filter 13 is connected to the output terminal of the S / H circuit 12, and the output terminal of the filter 13 is connected to the input terminal of the quantizer 14. For example, the filter 13 may be an LPF, HPF, or BPF. The filter 13 is implemented using elements such as chip inductors or chip capacitors. Depending on the frequency band to be passed or the required amount of suppression, other resonators such as microstrip or coaxial resonators may also be used. Here, the passband of the filter 13 is a low-frequency band, and even if a BPF is used as the filter 13, it does not require large size or cost, unlike an RF-band BPF.

[0024] The quantizer 14 is a circuit that quantizes an input signal and outputs data of the quantized signal, and quantizes the signal output by the filter 13 and outputs the data of the quantized signal to the phase shifter 15. The input terminal of the quantizer 14 is connected to the output terminal of the filter 13, and the output terminal of the quantizer 14 is connected to the input terminal of the phase shifter 15. For example, an ADC can be used for the quantizer 14. Note that when an ADC is used for the quantizer 14, quantization may be performed in synchronization with a clock signal input from an external device. Any configuration may be used for the quantizer 14 as long as it can quantize an input signal and output data of the quantized signal.

[0025] The phase shifter 15 is a circuit that shifts the phase of an input signal and outputs the phase-shifted signal. ＰＳ２The phase shifter 15 phase-shifts the signal output by the quantizer 14 based on a signal indicating the phase difference, and outputs the phase-shifted signal to the combiner 9. The input terminal of the phase shifter 15 is connected to the output terminal of the quantizer 14, the control terminal of the phase shifter 15 is connected to the output terminal of the phase control circuit 18, and the output terminal of the phase shifter 15 is connected to the second input terminal of the combiner 9. For example, an FPGA can be used for the phase shifter 15. In this case, the FPGA phase-shifts the input signal by changing the initial phase of the NCO in a calculation such as a DDC. Alternatively, the FPGA may convert the input signal into a signal in the complex domain and shift the phase using a complex calculation. The phase shifter 15 may have any configuration as long as it can phase-shift the input signal and output the phase-shifted signal.

[0026] The signal source 16 is a circuit that can generate a signal of any waveform or any frequency, and receives the θ ＣＬＫ２ The frequency f ＣＬＫ , initial phase θ ＣＬＫ２ The signal source 16 is a signal source that generates a second clock signal of the above-mentioned type. A control terminal of the signal source 16 is connected to an output terminal of the phase control circuit 17, and an output terminal of the signal source 16 is connected to a clock terminal of the S / H circuit 12. For example, a DAC, a DDS, or a PLL circuit is used as the signal source 16. Although not shown in FIG. 1 , the signal source 16 may generate the second clock signal using a control signal or a reference signal input from an external source. Any configuration may be used as the signal source 16 as long as it can generate a signal of an arbitrary waveform.

[0027] The phase control circuit 17 controls θ ＣＬＫ２ The phase control circuit 17 is a circuit that outputs a signal indicating θ to the signal source 16. The output terminal of the phase control circuit 17 is connected to the control terminal of the signal source 16. For example, the phase control circuit 17 may be an FPGA or a memory. ＣＬＫ２ The phase control circuit 17 may be configured to calculate θ ＣＬＫ２ Any configuration may be used as long as it can output a signal indicating

[0028] The phase control circuit 18 controls θＰＳ２ The phase control circuit 18 is a circuit that outputs a signal indicating θ to the phase shifter 15. The output terminal of the phase control circuit 18 is connected to the control terminal of the phase shifter 15. For example, the phase control circuit 18 may be an FPGA or a memory. ＰＳ２ The phase control circuit 18 may calculate the phase θ by using a calculation or may read out data stored in advance in a memory or the like. ＰＳ２ Any configuration may be used as long as it can output a signal indicating

[0029] Next, the operation of the first embodiment of the present disclosure will be described. For simplicity of explanation, the received signal input to the receiver is assumed to be 1.1 GHz, and f ＣＬＫ = 1 GHz, θ ＣＬＫ１ = 0°, θ ＣＬＫ２ = 30°, θ ＰＳ１ = 0°, and θ ＰＳ２ = 30°. Filters 3 and 13 are LPFs with a passband of 0.5 GHz, quantizers 4 and 14 are ADCs, phase shifters 5, 15, and combiner 9 are FPGAs, phase control circuits 7, 8, 17, and 18 are FPGAs and memories, and signal sources 6 and 16 are PLL circuits. The memories may be internal or external to the FPGA. Phase shifters 5 and 15 convert input signals into complex domain signals and shift the phase using complex operations. Both ADCs used as quantizers 4 and 14 perform quantization in synchronization with an externally input clock signal and are oversampled. It is assumed that there are no spurious signals propagating through space, and that the received signal and noise arrive from the front of the receiver (the antenna plane formed by antennas 1 and 11). Furthermore, the initial phase of the received signal and noise is all set to 0°.

[0030] First, in this receiver, antennas 1 and 11 receive a 1.1 GHz signal and noise propagating through space, and output the received signal and noise to S / H circuits 2 and 12. A signal source 6 outputs a 1 GHz frequency and an initial phase θＣＬＫ１ The signal source 16 generates a first clock signal having a frequency of 1 GHz and an initial phase θ ＣＬＫ２ and outputs the generated second clock signal to the S / H circuit 12. The S / H circuit 2, in synchronization with the first clock signal, undersamples the received signal and noise output by the antenna 1. The S / H circuit 12, in synchronization with the second clock signal, undersamples the received signal and noise output by the antenna 11.

[0031] FIG. 2 is a diagram showing the frequency spectrum of the output signal from antenna 1. The horizontal axis represents frequency, and the vertical axis represents power. The solid arrow represents the received signal output from antenna 1, and N001, N002, N003, and N004 represent noise. S / H circuit 2 undersamples the signal output from antenna 1 using the first clock signal output from signal source 6. Due to undersampling, aliasing components occur in the output spectrum of S / H circuit 2 at half the frequency of the first clock signal (hereinafter referred to as the Nyquist frequency), i.e., every 0.5 GHz. In this case, if p is a positive integer, the frequency region from (p-1) × Nyquist frequency to p × Nyquist frequency is called the pth Nyquist zone. The output signal from S / H circuit 2 has multiple frequency components. This frequency is called f Ｓ／Ｈ２ Then, f Ｓ／Ｈ２ is expressed by the following formula (1).

[0032] where α is a sign function and takes either +1 or −1 so that the entire right side of equation (1) is positive. ｉｎ are the frequencies of the signal and noise input to the S / H circuit 2, and k is an integer equal to or greater than 0. The frequency spectrum of the output signal from the antenna 11 is also the same as that shown in FIG. 2, and therefore will not be described here.

[0033] The phase control circuit 7 controls θ ＣＬＫ１ The phase control circuit 17 outputs data indicating θ ＣＬＫ２ θ ＣＬＫ１ and θＣＬＫ２ The calculation of may be performed by the phase control circuit 7 and the phase control circuit 17, or the result of calculation performed outside the receiver may be input to the phase control circuit 7 and the phase control circuit 17 and stored.

[0034] The S / H circuits 2 and 12 receive clock signals with the same frequency but different phases (θ ＣＬＫ１ ≠θ ＣＬＫ２ ), the output signals of the S / H circuits 2 and 12 have different phases. That is, the output signals of the filters 3 and 13 have the same frequency but different phases. Let the initial phases of the output signals of the S / H circuits 2 and 12 be θ Ｓ／Ｈ２ and θ Ｓ／Ｈ１２ Then, θ Ｓ／Ｈ２ and θ Ｓ／Ｈ１２ are expressed by the following equations (2) and (3), respectively.

[0035] However, θ ｉｎ is the initial phase of the signal and noise input to S / H circuit 2. Filters 3 and 13 pass components within the first Nyquist zone among the many frequency components contained in the output signals of S / H circuit 2 and S / H circuit 12. Figure 3 shows the frequency spectrum of the output signal of filter 3. The horizontal axis represents frequency and the vertical axis represents power. Due to aliasing caused by undersampling in S / H circuit 2, all of the received signal and noise are frequency converted to the first Nyquist zone. At this time, the spectrum of the received signal or noise that existed in the even-order Nyquist zone is inverted. Filter 3 suppresses the received signal and noise that exist in the second Nyquist zone or higher Nyquist zones. The frequency spectrum of the output signal of filter 13 is the same as that shown in Figure 3, so a description thereof will be omitted here.

[0036] Since the noise N001 is in the first Nyquist zone, the frequency does not change between the output of antenna 1 and the outputs of filters 3 and 13. That is, from equation (1), α=1 and k=0. The initial phase of the noise N001 in the output of filter 3 is set as θ оｕｔ１＿Ｎ００１ , the initial phase of the noise N001 in the filter 13 output is θоｕｔ２＿Ｎ００１ , and the initial phase of the noise N001 at the antenna 1 output is θ ｉｎ＿Ｎ００１ Then, from equations (2) and (3), α=1 and k=0, so θ оｕｔ１＿Ｎ００１ and θ оｕｔ２＿Ｎ００１ are expressed by the following equations (4) and (5), respectively.

[0037] The noise N002 is frequency converted to the first Nyquist zone by undersampling. At this time, the frequency of the noise N002 in the outputs of the filters 3 and 13 is expressed as f оｕｔ＿Ｎ００２ , the frequency of noise N002 at the antenna 1 output is f ｉｎ＿Ｎ００２ Then, from equation (1), f оｕｔ＿Ｎ００２ is expressed by the following equation (6).

[0038] From equation (6), α = -1, k = -1. The initial phase of the noise N002 in the filter 3 output is θ оｕｔ１＿Ｎ００２ , the initial phase of the noise N002 in the filter 13 output is θ оｕｔ２＿Ｎ００２ , and the initial phase of the noise N002 at the antenna 1 output is θ ｉｎ＿Ｎ００２ Then, from equations (2) and (3), θ оｕｔ１＿Ｎ００２ and θ оｕｔ２＿Ｎ００２ are expressed by the following equations (7) and (8), respectively.

[0039] The received signal is frequency converted to the first Nyquist zone by undersampling. At this time, the frequency of the received signal at the outputs of the filters 3 and 13 is expressed as f оｕｔ＿Ｓ , the frequency of the received signal at the antenna 1 output is f ｉｎ＿Ｓ Then, from equation (1), f оｕｔ＿Ｓ is expressed by the following equation (9).

[0040] From equation (9), α = +1, k = -1. The initial phase of the received signal at the filter 3 output is θ оｕｔ１＿Ｓ , the initial phase of the received signal at the output of the filter 13 is θ оｕｔ２＿Ｓ , and the initial phase of the received signal at the antenna 1 output is θｉｎ＿Ｓ Then, from equations (2) and (3), θ оｕｔ１＿Ｓ and θ оｕｔ２＿Ｓ are expressed by the following equations (10) and (11), respectively.

[0041] The noise N003 is frequency converted to the first Nyquist zone by undersampling. At this time, the frequency of the noise N003 in the outputs of the filters 3 and 13 is expressed as f оｕｔ＿Ｎ００３ , the frequency of noise N003 at the antenna 1 output is f ｉｎ＿Ｎ００３ Then, from equation (1), f оｕｔ＿N００３ is expressed by the following equation (12).

[0042] From equation (12), α = -1, k = -2. The initial phase of the noise N003 in the filter 3 output is θ оｕｔ１＿N００３ , the initial phase of the noise N003 in the filter 13 output is θ оｕｔ２＿N００３ , and the initial phase of the noise N003 at the antenna 1 output is θ ｉｎ＿N００３ Then, from equations (2) and (3), θ оｕｔ１＿N００３ and θ оｕｔ２＿N００３ are expressed by the following equations (13) and (14), respectively.

[0043] The noise N004 is frequency converted to the first Nyquist zone by undersampling. At this time, the frequency of the noise N004 in the outputs of the filters 3 and 13 is expressed as f оｕｔ＿Ｎ００４ , the frequency of noise N004 at the antenna 1 output is f ｉｎ＿Ｎ００４ Then, from equation (1), f оｕｔ＿N００４ is expressed by the following equation (15).

[0044] From equation (15), α = +1, k = -2. The initial phase of the noise N004 in the filter 3 output is θ оｕｔ１＿N００４ , the initial phase of the noise N004 in the filter 13 output is θ оｕｔ２＿N００４ , and the initial phase of the noise N004 at the antenna 1 output is θ ｉｎ＿N００４ Then, from equations (2) and (3), θ оｕｔ１＿N００４and θ оｕｔ２＿N００４ are expressed by the following equations (16) and (17), respectively.

[0045] Filters 3 and 13 are provided to prevent malfunctions caused by the input of a large number of frequency components to quantizers 4 and 14, or failures caused by the input of high-power frequency components. Because frequency components of the second or higher Nyquist zones are present in the output signals of S / H circuits 2 and 12, the passbands or implementation methods of the filters are determined so as to sufficiently suppress the components of the second or higher Nyquist zones. Furthermore, if the frequency components of the second or higher Nyquist zones contained in the output signals of S / H circuits 2 and 12 are outside the operable frequencies of quantizers 4 and 14, or if the power of these frequency components is low, and no malfunction or failure occurs in quantizers 4 and 14, filters 3 and 13 may be omitted and may be replaced with through circuits.

[0046] The quantizers 4 and 14 quantize the analog signals output by the filters 3 and 13, respectively, and output the quantized signal data as a digital signal to the phase shifters 5 and 15, respectively. The phase shifter 5 converts the signal data output by the quantizer 4 into a signal in the complex domain, and shifts the initial phase of the signal by θ ＰＳ１ The phase shifter 15 converts the signal data output by the quantizer 14 into a signal in the complex domain, and shifts the initial phase of the signal by θ ＰＳ２ The phase shifts only.

[0047] The phase control circuit 8 controls θ ＰＳ１ The phase control circuit 18 outputs data indicating θ ＰＳ２ θ ＰＳ１ and θ ＰＳ２ The calculation of may be performed by the phase control circuit 8 and the phase control circuit 18, or the result of calculation performed outside the receiver may be input to the phase control circuit 8 and the phase control circuit 18 and stored.

[0048] At this time, θоｕｔ３ and θ оｕｔ４ are expressed by the following equations (18) and (19), respectively.

[0049] Here, the initial phase of the noise N001 at the output of the phase shifter 5 is θ оｕｔ３＿N００１ , the initial phase of the noise N001 at the output of the phase shifter 15 is θ оｕｔ４＿N００１ Then, from equations (4), (5), (18), and (19), θ оｕｔ３＿N００１ and θ оｕｔ４＿N００１ are expressed by the following equations (20) and (21), respectively.

[0050] The initial phase of the noise N002 at the output of the phase shifter 5 is θ оｕｔ３＿N００２ The initial phase of the noise N002 in the output of the phase shifter 15 is set as θ оｕｔ４＿N００２ Then, from equations (7), (8), (18), and (19), θ оｕｔ３＿N００２ and θ оｕｔ４＿N００２ are expressed by the following equations (22) and (23), respectively.

[0051] The initial phase of the received signal at the output of the phase shifter 5 is θ оｕｔ３＿Ｓ , the initial phase of the received signal at the output of the phase shifter 15 is θ оｕｔ４＿Ｓ Then, from equations (10), (11), (18), and (19), θ оｕｔ３＿Ｓ and θ оｕｔ４＿Ｓ are expressed by the following equations (24) and (25), respectively.

[0052] The initial phase of the noise N003 at the output of the phase shifter 5 is θ оｕｔ３＿N００３ , the initial phase of the noise N003 at the output of the phase shifter 15 is θ оｕｔ４＿N００３ Then, from equations (13), (14), (18), and (19), θ оｕｔ３＿N００３ and θ оｕｔ４＿N００３ are expressed by the following equations (26) and (27), respectively.

[0053] The initial phase of the noise N004 at the output of the phase shifter 5 is θ оｕｔ３＿N００４ , the initial phase of the noise N004 at the output of the phase shifter 15 is θ оｕｔ４＿N００４ Then, from equations (16), (17), (18), and (19), θ оｕｔ３＿N００４ and θ оｕｔ４＿N００４ are expressed by the following equations (28) and (29), respectively.

[0054] The combiner 9 combines (adds) the signal and noise output by the phase shifter 5 with the signal and noise output by the phase shifter 15, and outputs the combined signal to the outside of the receiver. Figure 4 is a table showing the initial phases of the received signal and noise N001 to 004 at the outputs of the filter 3, the phase shifter 5, the filter 13, and the phase shifter 15. Note that, here, for the equations obtained so far, θ ＣＬＫ１ = 0°, θ ＣＬＫ２ = 30°, θ ＰＳ１ = 0°, θ ＰＳ２ = 30°, and the initial phase of the received signal and noise is set to 0° (i.e., θ ｉｎ＿Ｓ = θ ｉｎ＿N００１ = θ ｉｎ＿N００２ = θ ｉｎ＿N００３ = θ ｉｎ＿N００４= 0°). As can be seen from FIG. 4, the received signal output by phase shifter 5 and the received signal output by phase shifter 15 both have the same initial phase. When the received signals are combined, they have the same amplitude and phase, so the amplitude of the combined signal is doubled compared to before combination, i.e., the power is improved by 6 dB. On the other hand, the noise N001 to N004 output by phase shifter 5 and the noise N001 to N004 output by phase shifter 15 have different initial phases. When the noise N001 to N004 are combined, they are not combined in phase, so the amplitude of the combined signal is less than doubled compared to before combination, i.e., the power is improved by less than 6 dB. Although not shown in FIG. 4, if the initial phases of the noise were opposite, they would cancel out when combined. In this case, the received signal in the third Nyquist zone has its power increased by 6 dB at the output of the combiner 9, but the noise in the other Nyquist zones has its power increased by less than 6 dB at the output of the combiner 9, resulting in relative noise suppression relative to the received signal. Although not shown in Figure 2, if there is noise in the same Nyquist zone as the received signal, that noise will have its power increased by 6 dB at the output of the combiner 9, and therefore no relative suppression will be obtained.

[0055] As described above, according to the first embodiment, a received signal containing noise or spurious signals is undersampled using two S / H circuits to which clock signals of the same frequency but different phases are input, and the output signals of the two S / H circuits are phase-shifted using phase shifters so that the received signals after undersampling are in phase but the noise or spurious signals after undersampling are not in phase. When the output signals of the two phase shifters are combined, the power of the received signal is greatly improved due to in-phase combination, but the noise or spurious signals are not combined in phase and the power does not improve as much as the signal. This makes it possible to provide a receiver that can suppress noise or spurious signals in the Nyquist zone where there is no received signal in the high frequency band, without requiring an RF band BPF and without increasing size or cost.

[0056] In the first embodiment, the phase is shifted after quantization, but quantization may be performed after the phase is shifted. Also, although the case where there are two systems each consisting of an antenna, an S / H circuit, a filter, a quantizer, a phase shifter, a signal source, and two phase control circuits has been described, there may be three or more systems as long as the received signals after undersampling in each system are in phase and the noise or spurious after undersampling are not in phase.

[0057] Here, the signal with the lowest frequency component among the signals output by S / H circuits 2 and 12 is passed using filters 3 and 13, but signals with other frequency components may also be passed. As long as the Nyquist zone in which the received signal exists is different from the frequency components passed by filters 3 and 13, signals with frequency components existing outside the first Nyquist zone may also be passed.

[0058] Although the case where digital signals are combined by combiner 9 has been described here, analog signals may also be combined. In this case, a quantizer is not used, and the output signals (analog signals) of the filters are combined after being phase-shifted by a phase shifter, and the combined analog signal is output from the receiver. Also, in this embodiment, a case where noise is present in addition to the received signal has been described, but it is also possible that there is spurious in addition to noise, or there is only spurious without noise.

[0059] In the first embodiment, the case where the phases of noise in the four Nyquist zones of the first, second, fourth, and fifth orders are not in phase has been described. However, the number of Nyquist zones in which the phases are not in phase may be three or less, or five or more.

[0060] Second Embodiment <Configuration> In the first embodiment, the amount of suppression of noise or spurious signals outside the Nyquist zone where the received signals are located was small. In the second embodiment, the received signals are in phase and the noise or spurious signals are in opposite phase, thereby canceling out the noise or spurious signals and achieving a large amount of suppression of the noise or spurious signals.

[0061] 5 is a diagram illustrating an example of the configuration of a receiver according to the second embodiment of the present disclosure. In FIG. 5, the same reference numerals as in FIG. 1 denote the same or equivalent parts, and their explanations will be omitted. θ ＣＬＫ３ is the initial phase of the third clock signal, θ ＣＬＫ４ is the initial phase of the fourth clock signal, θ ｏｕｔ５ is the initial phase of the output signal of the filter 23, θ ｏｕｔ６ is the initial phase of the output signal of the filter 33, θ ｏｕｔ７ is the initial phase of the output signal of the phase shifter 25, θ ｏｕｔ８ is the initial phase of the output signal of the phase shifter 35, θ ＰＳ３ is the phase shift amount of the phase shifter 25, and θ ＰＳ４ is the phase shift amount of the phase shifter 35.

[0062] The antenna 21 is an antenna that receives a signal propagating through space and outputs the received signal to the S / H circuit 22. The output terminal of the antenna 21 is connected to the RF terminal of the S / H circuit 22. For example, an antenna such as a dipole antenna or a patch antenna can be used as the antenna 21. Of course, an array antenna that combines multiple element antennas can also be used. Any configuration can be used for the antenna 21 as long as it can receive a signal propagating through space and output the received signal.

[0063] The S / H circuit 22 is a sample-and-hold circuit that undersamples the signal output by the antenna 21 in synchronization with a third clock signal output by the signal source 26 and outputs the undersampled signal to the filter 23. The RF terminal of the S / H circuit 22 is connected to the output terminal of the antenna 21, the clock terminal of the S / H circuit 22 is connected to the output terminal of the signal source 26, and the output terminal of the S / H circuit 22 is connected to the input terminal of the filter 23. For example, the S / H circuit 22 may be configured with a switch that switches between open and short circuits for the input RF signal (output signal from the antenna 21) and a capacitor that stores charge when the line for the input RF signal is open. Any configuration may be used for the S / H circuit 22 as long as it can undersample the input RF signal and output the undersampled signal. Here, the undersampled signal refers to a signal generated by undersampling.

[0064] The filter 23 has a predetermined passband and passes signals within the passband among the signals output by the S / H circuit 22 and suppresses signals in frequency bands outside the passband. The filter 23 suppresses signals or unwanted waves outside the passband among the signals output by the S / H circuit 22, and outputs the resulting signal to the quantizer 24. The input terminal of the filter 23 is connected to the output terminal of the S / H circuit 22, and the output terminal of the filter 23 is connected to the input terminal of the quantizer 24. For example, the filter 23 may be an LPF, HPF, or BPF. The filter 23 is implemented using elements such as chip inductors or chip capacitors. Depending on the frequency band to be passed or the required amount of suppression, other resonators such as microstrip or coaxial resonators may also be used. Here, the passband of the filter 23 is a low-frequency band, and even if a BPF is used as the filter 23, it does not require large size or cost, unlike an RF-band BPF.

[0065] The quantizer 24 is a circuit that quantizes an input signal and outputs data of the quantized signal, and quantizes the signal output by the filter 3 and outputs the data of the quantized signal to the phase shifter 25. The input terminal of the quantizer 24 is connected to the output terminal of the filter 23, and the output terminal of the quantizer 24 is connected to the input terminal of the phase shifter 25. For example, an ADC can be used for the quantizer 24. Note that when an ADC is used for the quantizer 24, quantization may be performed in synchronization with a clock signal input from the outside. Any configuration may be used for the quantizer 24 as long as it can quantize an input signal and output data of the quantized signal.

[0066] The phase shifter 25 is a circuit that shifts the phase of an input signal and outputs the phase-shifted signal. ＰＳ３ The phase shifter 25 phase-shifts the signal output by the quantizer 24 based on a signal indicating the phase difference, and outputs the phase-shifted signal to the combiner 39. The input terminal of the phase shifter 25 is connected to the output terminal of the quantizer 24, the control terminal of the phase shifter 25 is connected to the output terminal of the phase control circuit 28, and the output terminal of the phase shifter 25 is connected to the first input terminal of the combiner 39. For example, an FPGA can be used for the phase shifter 25. In this case, the FPGA phase-shifts the input signal by changing the initial phase of the NCO in a calculation such as a DDC. Alternatively, the FPGA may convert the input signal into a signal in the complex domain and shift the phase using a complex calculation. The phase shifter 25 may have any configuration as long as it can phase-shift the input signal and output the phase-shifted signal.

[0067] The signal source 26 is a circuit that can generate a signal of any waveform or any frequency, and receives the θ ＣＬＫ３ The frequency f ＣＬＫ , initial phase θ ＣＬＫ３The signal source 26 is a signal source that generates a third clock signal. A control terminal of the signal source 26 is connected to an output terminal of the phase control circuit 27, and an output terminal of the signal source 26 is connected to a clock terminal of the S / H circuit 22. For example, a DAC, a DDS, or a PLL circuit is used as the signal source 26. Although not shown in FIG. 5 , the signal source 26 may generate the third clock signal using a control signal or a reference signal that is input from an external source. Any configuration may be used as the signal source 26 as long as it can generate a signal of an arbitrary waveform.

[0068] The phase control circuit 27 controls θ ＣＬＫ３ The phase control circuit 27 is a circuit that outputs a signal indicating θ to the signal source 26. The output terminal of the phase control circuit 27 is connected to the control terminal of the signal source 26. For example, the phase control circuit 27 may be an FPGA or a memory. ＣＬＫ３ The phase control circuit 27 may calculate θ ＣＬＫ３ Any configuration may be used as long as it can output a signal indicating

[0069] The phase control circuit 28 controls θ ＰＳ３ The phase control circuit 28 is a circuit that outputs a signal indicating θ to the phase shifter 25. The output terminal of the phase control circuit 28 is connected to the control terminal of the phase shifter 25. For example, the phase control circuit 28 may be an FPGA or a memory. ＰＳ３ The phase control circuit 28 may calculate the phase θ by reading out data stored in advance in a memory or the like. ＰＳ３ Any configuration may be used as long as it can output a signal indicating

[0070] The antenna 31 is an antenna that receives a signal propagating through space and outputs the received signal to the S / H circuit 32. The output terminal of the antenna 31 is connected to the RF terminal of the S / H circuit 32. For example, an antenna such as a dipole antenna or a patch antenna can be used as the antenna 31. Of course, an array antenna that combines multiple element antennas can also be used. The antenna 31 may have any configuration as long as it can receive a signal propagating through space and output the received signal.

[0071] The S / H circuit 32 is a sample-and-hold circuit that undersamples the signal output by the antenna 31 in synchronization with the fourth clock signal output by the signal source 36 and outputs the undersampled signal to the filter 33. The RF terminal of the S / H circuit 32 is connected to the output terminal of the antenna 31, the clock terminal of the S / H circuit 32 is connected to the output terminal of the signal source 36, and the output terminal of the S / H circuit 32 is connected to the input terminal of the filter 33. For example, the S / H circuit 32 may be configured with a switch that switches between open and short circuits for the input RF signal (output signal from the antenna 31) and a capacitor that stores charge when the line for the input RF signal is open. Any configuration may be used for the S / H circuit 32 as long as it can undersample the input RF signal and output the undersampled signal.

[0072] The filter 33 has a predetermined passband and passes signals within the passband among the signals output by the S / H circuit 32 and suppresses signals in frequency bands outside the passband. The filter 33 suppresses signals or unwanted waves outside the passband among the signals output by the S / H circuit 32, and outputs the result to the quantizer 34. The input terminal of the filter 33 is connected to the output terminal of the S / H circuit 32, and the output terminal of the filter 33 is connected to the input terminal of the quantizer 34. For example, the filter 33 may be an LPF, HPF, or BPF. The filter 33 is implemented using elements such as chip inductors or chip capacitors. Depending on the frequency band to be passed or the required amount of suppression, other resonators such as microstrip or coaxial resonators may also be used. Here, the passband of the filter 33 is a low-frequency band, and even if a BPF is used as the filter 33, it does not require large size or cost, unlike an RF-band BPF.

[0073] The quantizer 34 is a circuit that quantizes an input signal and outputs data of the quantized signal, and quantizes the signal output by the filter 33 and outputs the data of the quantized signal to the phase shifter 35. The input terminal of the quantizer 34 is connected to the output terminal of the filter 33, and the output terminal of the quantizer 34 is connected to the input terminal of the phase shifter 35. For example, an ADC can be used for the quantizer 34. Note that when an ADC is used for the quantizer 34, quantization may be performed in synchronization with a clock signal input from an external device. Any configuration may be used for the quantizer 34 as long as it can quantize an input signal and output data of the quantized signal.

[0074] The phase shifter 35 is a circuit that shifts the phase of an input signal and outputs the phase-shifted signal. ＰＳ４ The phase shifter 35 phase-shifts the signal output by the quantizer 34 based on a signal indicating the phase difference, and outputs the phase-shifted signal to the combiner 39. The input terminal of the phase shifter 35 is connected to the output terminal of the quantizer 34, the control terminal of the phase shifter 35 is connected to the output terminal of the phase control circuit 38, and the output terminal of the phase shifter 35 is connected to the fourth input terminal of the combiner 39. For example, an FPGA can be used for the phase shifter 35. In this case, the FPGA phase-shifts the input signal by changing the initial phase of the NCO in a calculation such as a DDC. Alternatively, the FPGA may convert the input signal into a signal in the complex domain and shift the phase using a complex calculation. The phase shifter 35 may have any configuration as long as it can phase-shift the input signal and output the phase-shifted signal.

[0075] The signal source 36 is a circuit that can generate a signal of any waveform or any frequency, and receives the θ ＣＬＫ４ The frequency f ＣＬＫ , initial phase θ ＣＬＫ４The signal source 36 is a signal source that generates a fourth clock signal. A control terminal of the signal source 36 is connected to an output terminal of the phase control circuit 37, and an output terminal of the signal source 36 is connected to a clock terminal of the S / H circuit 32. For example, a DAC, a DDS, or a PLL circuit is used as the signal source 36. Although not shown in FIG. 5 , the signal source 36 may generate the fourth clock signal using a control signal or a reference signal input from an external source. Any configuration may be used as the signal source 36 as long as it can generate a signal of an arbitrary waveform.

[0076] The phase control circuit 37 controls θ ＣＬＫ４ The phase control circuit 37 is a circuit that outputs a signal indicating θ to the signal source 36. The output terminal of the phase control circuit 37 is connected to the control terminal of the signal source 36. For example, the phase control circuit 37 may be an FPGA or a memory. ＣＬＫ４ The phase control circuit 37 may be configured to calculate θ ＣＬＫ４ Any configuration may be used as long as it can output a signal indicating

[0077] The phase control circuit 38 controls θ ＰＳ４ The phase control circuit 38 is a circuit that outputs a signal indicating θ to the phase shifter 35. The output terminal of the phase control circuit 38 is connected to the control terminal of the phase shifter 35. For example, the phase control circuit 38 may be an FPGA or a memory. ＰＳ４ The phase control circuit 38 may calculate the phase θ by using a calculation or may read out data stored in advance in a memory or the like. ＰＳ４ Any configuration may be used as long as it can output a signal indicating

[0078] The combiner 39 is a circuit that combines (adds) multiple input signals and outputs the combined signal. The combiner 39 combines the signals output by the phase shifters 5, 15, 25, and 35 and outputs the combined signal to the outside. A first input terminal of the combiner 39 is connected to the output terminal of the phase shifter 5, a second input terminal of the combiner 39 is connected to the output terminal of the phase shifter 15, a third input terminal of the combiner 39 is connected to the output terminal of the phase shifter 25, and a fourth input terminal of the combiner 39 is connected to the output terminal of the phase shifter 35. For example, an FPGA can be used as the combiner 39. The combiner 39 may have any configuration as long as it can combine (add) multiple input signals and output a combined signal.

[0079] Next, the operation of the receiver according to the second embodiment of the present disclosure will be described. For simplicity of explanation, the received signal input to the receiver is assumed to be 1.1 GHz, and f ＣＬＫ = 1 GHz, θ ＣＬＫ１ = 0°, θ ＣＬＫ２ = 90°, θ ＣＬＫ３ = 180°, θ ＣＬＫ４ = -90°, θ ＰＳ１ = 0°, θ ＰＳ２ = 90°, θ ＰＳ３ = 180°, and θ ＰＳ４= -90°. Each phase is expressed in the range of -180 to 180°. LPFs with a passband of 0.5 GHz are used as filters 3, 13, 23, and 33; ADCs are used as quantizers 4, 14, 24, and 34; FPGAs are used as phase shifters 5, 15, 25, 35, and combiner 39; FPGAs and memories are used as phase control circuits 7, 8, 17, 18, 27, 28, 37, and 38; and PLL circuits are used as signal sources 6, 16, 26, and 36. The memories may be either internal or external to the FPGA. Phase shifters 5, 15, 25, and 35 convert input signals into complex domain signals and shift the phase using complex number arithmetic. The ADCs used as quantizers 4, 14, 24, and 34 perform quantization in synchronization with an externally input clock signal and are oversampled. It is assumed that there are no spurious signals propagating through space, and that the received signal and noise arrive from the front of the receiver (the antenna plane formed by antennas 1, 11, 21, and 31). Furthermore, it is assumed that the initial phase of all received signals and noise is 0°. The frequency spectrum of the output signals from antennas 1, 11, 21, and 31 is the same as that shown in FIG. 2. Note that a description of components that operate in the same manner as the receiver according to the first embodiment will be omitted here.

[0080] First, in this receiver, antennas 21 and 31 receive a 1.1 GHz signal and noise propagating through space, and output the received signal and noise to S / H circuits 22 and 32. A signal source 26 outputs a 1 GHz frequency and an initial phase θ ＣＬＫ３ and outputs the generated third clock signal to the S / H circuit 22. The signal source 36 generates a third clock signal having a frequency of 1 GHz and an initial phase θ ＣＬＫ４and outputs the generated fourth clock signal to the S / H circuit 32. The S / H circuit 22 synchronizes with the third clock signal to undersample the received signal and noise output by the antenna 21. The S / H circuit 32 synchronizes with the fourth clock signal to undersample the received signal and noise output by the antenna 31.

[0081] S / H circuit 22 undersamples the signal output by antenna 21 using the third clock signal output by signal source 26. S / H circuit 32 undersamples the signal output by antenna 31 using the fourth clock signal output by signal source 36. Due to undersampling, aliasing components occur in the output spectra of S / H circuit 22 and S / H circuit 32 at each Nyquist frequency (0.5 GHz). The output signal of S / H circuit 22 has multiple frequency components. Since the frequency of the clock signal input to S / H circuit 2, S / H circuit 12, S / H circuit 22, and S / H circuit 32 is the same, the frequency of the output signal of S / H circuit 22 or S / H circuit 32 is the same as that expressed by equation (1). The frequencies of the received signal and noises N001 to N004 have been explained in the first embodiment and are therefore omitted here.

[0082] The phase control circuit 27 controls θ ＣＬＫ３ The phase control circuit 37 outputs data indicating θ ＣＬＫ４ 5, data indicating θ ＣＬＫ３ and θ ＣＬＫ４ The calculation of may be performed by the phase control circuit 27 and the phase control circuit 37, or the result of calculation performed outside the receiver may be input to the phase control circuit 27 and the phase control circuit 37 and stored.

[0083] The S / H circuits 22 and 32 receive clock signals having the same frequency but different phases (θ ＣＬＫ３ ≠θ ＣＬＫ４), the output signals of the S / H circuits 22 and 32 have different phases. That is, the output signals of the filters 23 and 33 have the same frequency but different phases. When the initial phases of the output signals of the S / H circuits 22 and 32 are respectively set to θ Ｓ／Ｈ２２ , θ Ｓ／Ｈ３２ Then, θ Ｓ／Ｈ２２ and θ Ｓ／Ｈ３２ are expressed by the following equations (31) and (32), respectively.

[0084] However, filters 23 and 33 pass components within the first Nyquist zone among the many frequency components contained in the output signals of S / H circuits 22 and 32. The frequency spectra of the output signals of filters 23 and 33 are the same as those in Fig. 3, and therefore will not be described here.

[0085] Since the noise N001 is in the first Nyquist zone, the frequency does not change between the output of the antenna 21 and the outputs of the filters 23 and 33. That is, from equation (1), α=1 and k=0. The initial phase of the noise N001 in the output of the filter 23 is set as θ оｕｔ５＿Ｎ００１ The initial phase of the noise N001 in the output of the filter 33 is set as θ оｕｔ６＿Ｎ００１ Then, from equations (31) and (32), α=1 and k=0, so θ оｕｔ５＿Ｎ００１ and θ оｕｔ６＿Ｎ００１ are expressed by the following equations (33) and (34), respectively.

[0086] For the noise N002, α=−1 and k=−1 according to equation (6). The initial phase of the noise N002 in the output of the filter 23 is set as θ оｕｔ５＿Ｎ００２ , the initial phase of the noise N002 in the filter 33 output is θ оｕｔ６＿Ｎ００２ Then, θ оｕｔ５＿Ｎ００２ and θ оｕｔ６＿Ｎ００２ are expressed by the following equations (35) and (36), respectively.

[0087] For the received signal, α=+1 and k=−1 according to equation (9). The initial phase of the received signal at the output of the filter 23 is θ оｕｔ５＿Ｓ The initial phase of the received signal at the output of the filter 33 is set as θ оｕｔ６＿Ｓ Then, θ оｕｔ５＿Ｓ and θ оｕｔ６＿Ｓ are expressed by the following equations (37) and (38), respectively.

[0088] For the noise N003, α=−1 and k=−2 according to equation (12). The initial phase of the noise N003 in the filter 23 output is θ оｕｔ５＿N００３ The initial phase of the noise N003 in the output of the filter 33 is set as θ оｕｔ６＿N００３ Then, θ оｕｔ５＿N００３ and θ оｕｔ６＿N００３ are expressed by the following equations (39) and (40), respectively.

[0089] For the noise N004, α=+1 and k=−2 according to equation (12). The initial phase of the noise N004 in the output of the filter 23 is θ оｕｔ５＿N００４ The initial phase of the noise N004 in the output of the filter 33 is set as θ оｕｔ６＿N００４ Then, θ оｕｔ５＿N００４ and θ оｕｔ６＿N００４ are expressed by equations (41) and (42), respectively.

[0090] The filters 23 and 33 are provided to prevent malfunctions caused by inputting a large number of frequency components to the quantizers 24 and 34, or failures caused by inputting high-power frequency components. Because the output signals of the S / H circuits 22 and 32 contain frequency components in the second or higher Nyquist zone, the passbands or implementation methods of the filters are determined so as to sufficiently suppress the components in the second or higher Nyquist zone. Furthermore, if the frequency components in the second or higher Nyquist zones contained in the output signals of the S / H circuits 22 and 32 are outside the operable frequencies of the quantizers 24 and 34, or if the power of these frequency components is low, and no malfunction or failure occurs in the quantizers 24 and 34, the filters 23 and 33 may be omitted and may be implemented as through circuits.

[0091] The quantizers 24 and 34 quantize the analog signals output by the filters 23 and 33, respectively, and output the quantized signal data as digital signals to the phase shifters 25 and 35, respectively. The phase shifter 25 converts the signal data output by the quantizer 24 into a signal in the complex domain, and shifts the initial phase of the signal by θ ＰＳ３ The phase shifter 35 converts the data of the signal output by the quantizer 34 into a signal in the complex domain, and performs complex number calculations to shift the initial phase of the signal by θ ＰＳ４ The phase shifts only.

[0092] The phase control circuit 28 controls θ ＰＳ３ The phase control circuit 38 outputs data indicating θ ＰＳ４ 5, the data indicating θ ＰＳ３ and θ ＰＳ４ The calculation of may be performed by the phase control circuit 28 and the phase control circuit 38, or the result of calculation performed outside the receiver may be input to the phase control circuit 28 and the phase control circuit 38 and stored.

[0093] At this time, θ оｕｔ７ and θ оｕｔ８ are expressed by the following equations (43) and (44), respectively.

[0094] Here, the initial phase of the noise N001 at the output of the phase shifter 25 is θ оｕｔ７＿N００１ The initial phase of the noise N001 at the output of the phase shifter 35 is set as θ оｕｔ８＿N００１ Then, θ оｕｔ７＿N００１ and θ оｕｔ８＿N００１ are expressed by the following equations (45) and (46), respectively.

[0095] The initial phase of the noise N002 at the output of the phase shifter 25 is θ оｕｔ７＿N００２ The initial phase of the noise N002 at the output of the phase shifter 35 is set as θ оｕｔ８＿N００２ Then, θ оｕｔ７＿N００２ and θ оｕｔ８＿N００２ are expressed by the following equations (47) and (48), respectively.

[0096] The initial phase of the received signal at the output of the phase shifter 25 is θ оｕｔ７＿Ｓ The initial phase of the received signal at the output of the phase shifter 35 is set as θ оｕｔ８＿Ｓ Then, θ оｕｔ７＿Ｓ and θ оｕｔ８＿Ｓ are expressed by the following equations (49) and (50), respectively.

[0097] The initial phase of the noise N003 at the output of the phase shifter 25 is θ оｕｔ７＿N００３ The initial phase of the noise N003 in the output of the phase shifter 35 is set as θ оｕｔ８＿N００３ Then, θ оｕｔ７＿N００３ and θ оｕｔ８＿N００３ are expressed by the following equations (51) and (52), respectively.

[0098] The initial phase of the noise N004 at the output of the phase shifter 25 is θ оｕｔ７＿N００４ The initial phase of the noise N004 in the output of the phase shifter 35 is set as θ оｕｔ８＿N００４ Then, θ оｕｔ７＿N００４ and θ оｕｔ８＿N００４ are expressed by the following equations (53) and (54), respectively.

[0099] 6 is a table showing the initial phases of the received signal and noise N001 to 004 at the outputs of the phase shifters 5, 15, 25, and 35. Here, the passing phase of the received signal and noise in the mth (m is an integer of 1 or more) Nyquist zone is expressed as θ ｍ＿ｉ Then, θ ｍ＿ｉ can be expressed by the following equation (55).

[0100] where i = 1, 2, 3, or 4. The passing phase indicates the amount by which the received signal and noise are phase-shifted from the output terminal of antenna 1, antenna 11, antenna 21, or antenna 31 to the output terminal of phase shifter 5, phase shifter 15, phase shifter 25, or phase shifter 35. Combiner 39 combines (adds) the signals and noise output by phase shifters 5, 15, 25, and 35, and outputs the combined signal to the outside of the receiver. Here, when the received signals in the third Nyquist zone output by phase shifters 5, 15, 25, and 35 are combined in phase, the following equation (56) holds true from equation (55) and m = 3.

[0101] where n = 1, 2, or 3. When the noises output from phase shifter 5, phase shifter 15, phase shifter 25, and phase shifter 35 that are in the first, second, fourth, or fifth Nyquist zone are combined in antiphase, the following equation (57) holds true from equation (55).

[0102] where l=1, 2, 4, 5, and t is a positive integer. Figure 7 is a table in which values ​​are substituted for the initial phases of the received signal and noises N001 to 004 shown in Figure 6. Here, θ ＣＬＫ１ = 0°, θ ＣＬＫ２ = 90°, θ ＣＬＫ３ = 180°, θ ＣＬＫ４ = -90°, θ ＰＳ１ = 0°, θ ＰＳ２ = 90° θ ＰＳ３ = 180°, θ ＰＳ４= -90°, and 0° is substituted as the initial phase for all received signals and noise. As shown in FIG. 7, the received signals output by phase shifter 5, phase shifter 15, phase shifter 25, and phase shifter 35 all have the same initial phase. When the received signals are combined, they have the same amplitude and phase, resulting in a signal with four times the amplitude of the combined signal, i.e., a 12 dB increase in power. Meanwhile, the noises N001 to N004 output by phase shifter 5, phase shifter 15, phase shifter 25, and phase shifter 35 are in opposite phases (for example, the noise N001 output by phase shifter 5 and the noise N001 output by phase shifter 25 are in opposite phases, and the noise N001 output by phase shifter 15 and the noise N001 output by phase shifter 35 are in opposite phases). Therefore, when the noises N001 to N004 are combined, they are canceled out due to their opposite phases. The received signal in the third Nyquist zone has its power increased by 12 dB at the output of combiner 39, but the noise in the other Nyquist zones is canceled out and eliminated, so theoretically an infinite amount of suppression can be obtained. Although not shown in Figure 2, if there is noise in the same Nyquist zone as the received signal, the power of that noise will increase by 12 dB at the output of combiner 39, so no relative suppression can be obtained.

[0103] As described above, according to the second embodiment, it is possible to obtain the same effect as the receiver of the first embodiment. In addition, by setting the received signals to be in phase and the noise or spurious signals to be in opposite phases, they can be canceled out, thereby obtaining a greater amount of suppression than in the first embodiment.

[0104] In the second embodiment, the phase is shifted after quantization, but quantization may be performed after the phase is shifted. Also, although the case where there are four systems, each consisting of an antenna, an S / H circuit, a filter, a quantizer, a phase shifter, a signal source, and two phase control circuits, has been described, the number of systems may be less than four or five or more, as long as the received signals after undersampling in each system are in phase and the noise or spurious after undersampling are in opposite phase.

[0105] Here, the case has been described where the received signals are in phase and the noise or spurious signals are in opposite phases, but the received signals do not have to be in opposite phases and the noise or spurious signals may be in opposite phases.

[0106] Here, the signal with the lowest frequency component among the signals output by S / H circuit 2, S / H circuit 12, S / H circuit 22, and S / H circuit 32 is passed using filter 3, filter 13, filter 23, and filter 33, but signals with other frequency components may also be passed. As long as the Nyquist zone in which the received signal exists is different from the frequency components passed by filter 3, filter 13, filter 23, and filter 33, signals with frequency components existing outside the first Nyquist zone may also be passed.

[0107] Although the case where digital signals are combined by combiner 39 has been described here, analog signals may also be combined. In this case, a quantizer is not used, and the output signals (analog signals) of the filters are combined after being phase-shifted by a phase shifter, and the combined analog signal is output from the receiver. Also, in this embodiment, a case where noise is present in addition to the received signal has been described, but it is also possible that there is spurious in addition to noise, or there is no noise and only spurious.

[0108] In the second embodiment, the case where noises in the four Nyquist zones of the first, second, fourth, and fifth orders are in antiphase has been described. However, the number of Nyquist zones in which noises are in antiphase may be three or less, or five or more.

[0109] It is possible to combine the embodiments, and to modify or omit each embodiment as appropriate.

[0110] The receiver of the present disclosure can be used as a device for receiving radio waves.

[0111] 1 Antenna, 2 S / H circuit, 3 Filter, 4 Quantizer, 5 Phase shifter, 6 Signal source, 7 Phase control circuit, 8 Phase control circuit, 9 Combiner, 11 Antenna, 12 S / H circuit, 13 Filter, 14 Quantizer, 15 Phase shifter, 16 Signal source, 17 Phase control circuit, 18 Phase control circuit, 21 Antenna, 22 S / H circuit, 23 Filter, 24 Quantizer, 25 Phase shifter, 26 Signal source, 27 Phase control circuit, 28 Phase control circuit, 31 Antenna, 32 S / H circuit, 33 Filter, 34 Quantizer, 35 Phase shifter, 36 Signal source, 37 Phase control circuit, 38 Phase control circuit, 39 Combiner.

Claims

1. A receiver comprising: a first signal source that outputs a first clock signal having a first frequency and a first phase; second to Mth signal sources that output second to Mth (M-1) clock signals, where M is an integer greater than or equal to 2, each clock signal having the first frequency and an Mth phase that is different from the first phase; first to Mth sample-and-hold circuits that undersample received signals using the first to Mth clock signals; first to Mth phase shifters that shift the phases of the output signals of the first to Mth sample-and-hold circuits, respectively; and a combiner that combines output signals from the first to Mth phase shifters, wherein in the outputs of the first to Mth phase shifters, components in the Nth (N is an integer greater than or equal to 1) Nyquist zone are in phase, and components in one or more Nyquist zones other than the Nth zone are not in phase.

2. The receiver according to claim 1, characterized in that, in the outputs of the first to M phase shifters, the components of the Nth Nyquist zone are not out of phase with each other, and the components of one or more Nyquist zones other than the Nth Nyquist zone are out of phase with each other.

3. A receiver according to claim 1 or 2, characterized in that, in the outputs of the first to M phase shifters, the components of the Nth Nyquist zone are in phase with each other.

4. The first phase of the first clock signal is θ ＣＬＫ１ , the Mth phase of the Mth clock signal is θ ＣＬＫM , the phase shift amount of the first phase shifter is θ ＰＳ１ , and the phase shift amount of the M phase shifters is θ ＰＳＭ The passing phase θ of the component of the mth (m is an integer equal to or greater than 1) Nyquist zone is ｍ＿Ｍ can be expressed by the following formula: And, l is an integer from 1 to M other than N, t is an integer, i=1,...,M, and the following two formulas θ N_1 =・・・=θ N_M 4. The receiver according to claim 1, wherein the following holds true:

Images