Photodetection element

Abstract

A photodetection element according to an embodiment includes a sensor substrate and a readout circuit substrate. The sensor substrate is provided with a photoelectric conversion element that photoelectrically converts incident light into a signal charge. The readout circuit substrate is bonded to a surface on the reverse side from a light receiving surface of the sensor substrate, and is provided with a readout circuit that reads out the signal charge from the photoelectric conversion element. The readout circuit substrate has a semiconductor layer, gate wiring, a conductive part, and a connection part. A transistor is formed in the semiconductor layer. The gate wiring is provided in an interlayer insulating film between the semiconductor layer and the sensor substrate, and is connected to a gate of the transistor. The conductive part is provided at a position closer to the semiconductor layer than the gate wiring. The connection part penetrates the semiconductor layer in the thickness direction and electrically connects the conductive part and a wiring layer provided on the opposite side from the interlayer insulating film, with the semiconductor layer interposed therebetween.

Description

Photodetector element

[0001] The present disclosure relates to a light-detecting element.

[0002] There is an imaging element with a three-layer structure in which a substrate on which sensor pixels that photoelectrically convert incident light into signal charges are provided, a substrate on which a readout circuit that reads out the signal charges is provided, and a substrate on which a logic circuit that processes the readout signal charges are provided are stacked (see, for example, Patent Document 1).

[0003] In such an image sensor, a floating diffusion that temporarily holds signal charges on a substrate on which sensor pixels are provided is electrically connected to a substrate on which a logic circuit is provided via multilayer wiring.

[0004] Japanese Patent Application Laid-Open No. 2020-88380

[0005] In an imaging element having a three-layer structure as described above, for example, if the parasitic capacitance occurring between the multilayer wiring of the substrate on which the readout circuit is provided increases, the signal conversion efficiency decreases in the process of photoelectrically converting incident light into signal charges, amplifying the signal charges, and outputting them.

[0006] Therefore, the present disclosure provides a photodetector element that can suppress a decrease in signal conversion efficiency.

[0007] A photodetector according to an embodiment of the present disclosure includes a sensor substrate and a readout circuit substrate. The sensor substrate is provided with a photoelectric conversion element that photoelectrically converts incident light into a signal charge. The readout circuit substrate is attached to the surface of the sensor substrate opposite the light-receiving surface and is provided with a readout circuit that reads out the signal charge from the photoelectric conversion element. The readout circuit substrate includes a semiconductor layer, a gate wiring, a conductive portion, and a connection portion. A transistor is formed in the semiconductor layer. The gate wiring is provided in an interlayer insulating film between the semiconductor layer and the sensor substrate and is connected to the gate of the transistor. The conductive portion is provided closer to the semiconductor layer than the gate wiring. The connection portion penetrates the semiconductor layer in the thickness direction and electrically connects the conductive portion to a wiring layer provided on the opposite side of the interlayer insulating film via the semiconductor layer.

[0008] FIG. 1 is an explanatory diagram showing a portion of a cross section of a photodetector element according to a comparative example of the present disclosure. FIG. 1 is an explanatory diagram showing a portion of a cross section of a photodetector element according to a first embodiment. FIG. 2 is an explanatory diagram showing a manufacturing process of a photodetector element according to the first embodiment. FIG. 3 is an explanatory diagram showing a manufacturing process of a photodetector element according to the first embodiment. FIG. 4 is an explanatory diagram showing a manufacturing process of a photodetector element according to the first embodiment. FIG. 5 is an explanatory diagram showing a manufacturing process of a photodetector element according to the first embodiment. FIG. 6 is an explanatory diagram showing a manufacturing process of a photodetector element according to the first embodiment. FIG. 7 is an explanatory diagram showing a manufacturing process of a photodetector element according to the first embodiment. FIG. 8 is an explanatory diagram showing a manufacturing process of a photodetector element according to the first embodiment. FIG. 9 is an explanatory diagram showing a manufacturing process of a photodetector element according to the first embodiment.

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that in the following embodiments, the same components are designated by the same reference numerals, and redundant description will be omitted. Below, a case will be described in which the photodetection element according to the embodiment is an image sensor, but the photodetection element according to the embodiment may also be a light receiving element included in a distance measuring device. In this case, the photodetection element receives reflected light from the distance measuring target of laser light emitted toward the distance measuring target, and outputs the light to an information processing device. The information processing device measures the distance to the distance measuring target, for example, based on the phase of the emitted laser light and the phase of the received reflected light.

[0010] 1. Photodetector element according to a comparative example First, the configuration of a conventional photodetector element according to a comparative example will be described with reference to Fig. 1. Fig. 1 is an explanatory diagram showing a portion of a cross section of a photodetector element 100 according to a comparative example of the present disclosure. The photodetector element 100 has a three-layer structure in which a logic circuit board 10, a readout circuit board 20, and a sensor board 30 are stacked.

[0011] The sensor substrate 30 is provided with photodiodes PD, which are an example of photoelectric conversion elements that photoelectrically convert incident light into signal charges. Specifically, the sensor substrate 30 is provided with on-chip lenses OCL on the top layer, and color filters CF are provided below and inside each on-chip lens OCL.

[0012] Furthermore, photodiodes PD, which are photoelectric conversion elements, are provided in the Si (silicon) layer directly below each color filter CF. The photodiodes PD are provided corresponding to each pixel of the captured image. That is, the on-chip lenses OCL, color filters CF, and photodiodes PD are arranged in a matrix in the pixel area so as to correspond to the captured pixels.

[0013] Each pixel is provided with a transfer gate TG that transfers signal charges photoelectrically converted by the photodiode PD to a floating diffusion FD. The floating diffusion FD is a charge holding region that temporarily holds the signal charges photoelectrically converted by the photodiode PD.

[0014] Furthermore, the pixels are electrically isolated from one another by deep trench isolation DTI, which may be a partial deep trench isolation or shallow trench isolation structure, for example.

[0015] An interlayer insulating film 31 is provided below the photodiode PD and outside the pixel area on the sensor substrate 30. An aluminum connection pad AL is embedded in the interlayer insulating film 31 outside the pixel area.

[0016] Furthermore, multi-layer wiring is embedded in the interlayer insulating film 31 below the photodiode PD. Fig. 1 shows two-layer wiring consisting of first-layer wiring M1 and second-layer wiring M2 as an example of multi-layer wiring. Furthermore, copper wiring CC is embedded in the lower end of the interlayer insulating film 31 for electrical connection to the readout circuit board 20. In the example shown in Fig. 1, the floating diffusion FD, first-layer wiring M1, second-layer wiring M2, and copper wiring CC are electrically connected by vias.

[0017] The readout circuit board 20 is attached to the surface of the sensor substrate 30 opposite to the light-receiving surface. In other words, the sensor substrate 30 and the readout circuit board 20 are connected face-to-face, that is, facing each other. The readout circuit board 20 is provided with a readout circuit that reads out signal charges from the sensor substrate 30.

[0018] For example, the read circuit includes an amplification transistor, a selection transistor, a reset transistor (not shown), etc. The amplification transistor is a transistor that amplifies the signal charge held in the floating diffusion FD.

[0019] The selection transistor is a transistor that selects a photodiode PD that reads out signal charges from the plurality of photodiodes PD. The reset transistor is a transistor that resets (discharges) the signal charges held in the floating diffusion FD.

[0020] Specifically, the readout circuit board 20 includes a semiconductor layer 22 made of Si or the like in which the sources and drains of the amplification transistor, selection transistor, and reset transistor are formed. Gates are provided on the upper surface of the semiconductor layer 22 between the sources and drains of the amplification transistor, selection transistor, and reset transistor.

[0021] 1 illustrates the gate AMP of the amplifier transistor and the gate SEL of the select transistor provided on the upper surface of the semiconductor layer 22, but does not illustrate the gate of the reset transistor. Portions of the amplifier transistor, select transistor, and reset transistor inside the semiconductor layer 22 are electrically isolated by shallow trench isolation (STI).

[0022] Furthermore, the readout circuit board 20 has an interlayer insulating film 21 provided between the semiconductor layer 22 and the sensor substrate 30, outside the pixel region, and between the semiconductor layer 22 and the logic circuit board 10. Multilayer wiring is embedded in the interlayer insulating film 21 above the semiconductor layer 22 and outside the pixel region. Figure 2 shows three-layer wiring, including first-layer wiring M1, second-layer wiring M2, and third-layer wiring M3, as an example of multilayer wiring.

[0023] Furthermore, copper wiring CC is embedded in the upper end of the interlayer insulating film 21 for electrical connection to the sensor substrate 30. Copper wiring CC is embedded in the lower end of the interlayer insulating film 21 for electrical connection to the logic circuit board 10.

[0024] 1, the gate AMP of the amplification transistor and the copper wiring CC of the readout circuit board 20 are electrically connected by the first-layer and second-layer wiring M1, M2 and vias. Therefore, when the sensor substrate 30 and the readout circuit board 20 are bonded together and the copper wiring CC is connected to each other, the floating diffusion FD and the gate AMP of the amplification transistor are electrically connected.

[0025] Furthermore, the drain D of the amplification transistor is connected to a power supply (not shown) via first-layer and second-layer wiring M1, M2 and a via. As a result, a power supply voltage is applied to the drain D of the amplification transistor. Furthermore, the source S of the selection transistor is electrically connected to the logic circuit board 10 via the first-layer and second-layer wiring M1, M2 and a via directly above the source S, and the first-layer to third-layer wiring M1, M2, M3 and a via VA provided outside the pixel region.

[0026] The logic circuit board 10 is provided with a P-channel MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) and an N-channel MOSFET for processing the signal charges read out by the readout circuit.

[0027] Specifically, the logic circuit board 10 includes an N-type semiconductor layer 13 in which the source and drain of a P-channel MOSFET are formed, and a P-type semiconductor layer 12 in which the source and drain of an N-channel MOSFET are formed.

[0028] A gate PMOS of the P-channel MOSFET is provided between the source and drain of the P-channel MOSFET on the upper surface of the N-type semiconductor layer 13. A gate NMOS of the N-channel MOSFET is provided between the source and drain of the N-channel MOSFET on the upper surface of the P-type semiconductor layer 12.

[0029] Furthermore, the logic circuit board 10 has an interlayer insulating film 11 provided between the P-type semiconductor layer 12, the N-type semiconductor layer 13, and the readout circuit board 20, and outside the pixel region. A wiring layer is embedded in the interlayer insulating film 11 above the P-type semiconductor layer 12 and the N-type semiconductor layer 13 and outside the pixel region. FIG. 1 shows a single-layer wiring of a first-layer wiring M1 as an example of the wiring layer. Furthermore, copper wiring CC is embedded in the upper end of the interlayer insulating film 11 for electrical connection to the readout circuit board 20.

[0030] In the photodetector element 100, when light is incident on the photodiode PD, the photodiode PD photoelectrically converts the incident light into a signal charge, and the signal charge is accumulated in the photodiode PD. After that, when a predetermined voltage is applied to the transfer gate TG, the signal charge is transferred from the photodiode PD to the floating diffusion FD, and the signal charge is held in the floating diffusion FD.

[0031] As a result, a voltage corresponding to the amount of signal charge is applied from the floating diffusion FD to the gate AMP of the amplification transistor, and a voltage resulting from the amplified signal charge is applied from the drain D of the amplification transistor to the source (not shown). The source of the amplification transistor and the drain of the selection transistor are connected.

[0032] Therefore, when a predetermined voltage is applied to the gate SEL of the selection transistor, a voltage resulting from the amplified signal charge is applied from the drain of the selection transistor to the source S. The source S of the selection transistor is electrically connected to the logic circuit board 10 via first-layer and second-layer wiring M1, M2 and a via immediately above the source S, and first-layer to third-layer wiring M1, M2, M3 and a via VA provided outside the pixel region.

[0033] As a result, the voltage of the signal charge read out and amplified by the readout circuit is output to the logic circuit board 10, and is subjected to signal processing by the logic circuit of the logic circuit board 10, and is output as a pixel signal from the logic circuit board 10 to an external device. The external device is, for example, a memory for storing images or a display device for displaying images.

[0034] In such a photodetector element 100, if the parasitic capacitance occurring between the multilayer wiring of the readout circuit board 20 increases, the signal conversion efficiency decreases in the process of photoelectrically converting incident light into signal charges and amplifying and outputting the signal charges.

[0035] For example, if the first-layer wiring M1, second-layer wiring M2, and vias in the area surrounded by the dashed ellipse in FIG. 1 and the adjacent first-layer wiring M1, second-layer wiring M2, and vias form parasitic capacitance and accumulate charge, the voltage of the signal charge held in the floating diffusion FD will attenuate. As a result, the signal conversion efficiency of the signal charge will decrease. Therefore, the photodetector according to the first embodiment described below has a configuration that suppresses the decrease in the signal conversion efficiency of the signal charge.

[0036] 2. Photodetector element according to first embodiment Fig. 2 is an explanatory diagram showing a part of a cross section of the photodetector element 1 according to the first embodiment. The photodetector element 1 does not have the components enclosed by the dashed ellipse shown in Fig. 1, but instead has the components enclosed by the dashed ellipse shown in Fig. 2.

[0037] In the photodetector element 1, among the wirings embedded in the interlayer insulating film 31 in the comparative example, the wirings other than the wirings that must be provided closer to the sensor substrate 30 than the semiconductor layer 22 are provided closer to the logic circuit substrate 10 than the semiconductor layer 22.

[0038] Specifically, the gate AMP of the amplification transistor is connected to the floating diffusion FD arranged above it. Therefore, the gate wiring connecting the gate AMP of the amplification transistor and the floating diffusion FD must be provided closer to the sensor substrate 30 than the semiconductor layer 22.

[0039] On the other hand, wiring other than the gate wiring of the amplification transistor, such as the drain wiring DL connected to the drain D of the amplification transistor and the source wiring SL connected to the source S of the reset transistor, does not necessarily need to be arranged closer to the sensor substrate 30 than the semiconductor layer 22.

[0040] Therefore, as shown in FIG. 2, in the photodetector element 1, for example, the drain wiring DL of the amplification transistor and the source wiring SL of the reset transistor are buried in an interlayer insulating film 11 of a logic circuit board 10.

[0041] The readout circuit board 20 of the photodetector element 1 also includes a conductive portion POLY that is provided at a position closer to the semiconductor layer 22 than the gate wiring (first-layer wiring M1) connected to the gate AMP of the amplification transistor. The conductive portion POLY is made of, for example, doped polysilicon to which N-type impurities are added.

[0042] For example, the conductive portion POLY is provided on the same plane as the gate AMP of the amplification transistor. Note that the conductive portion POLY may be made of a highly heat-resistant conductive material such as tungsten (W), titanium (Ti), or titanium nitride (TiN).

[0043] One of the conductive parts POLY is provided so as to be in contact with, for example, the drain D of the amplification transistor. Also, one of the conductive parts POLY is provided so as to be in contact with, for example, the source S of the selection transistor.

[0044] The readout circuit substrate 20 of the light detection element 1 also includes a connection portion TSV that penetrates the semiconductor layer 22 in the thickness direction and electrically connects the drain wiring DL and source wiring SL, which are provided on the opposite side of the interlayer insulating film 21 via the semiconductor layer 22, to the conductive portion POLY.

[0045] The connection portion TSV is, for example, a through silicon via. The connection portion TSV is electrically connected to the drain wiring DL of the amplification transistor and the source wiring SL of the reset transistor via copper wiring CC and vias.

[0046] In this way, in the readout circuit board 20 of the photodetector element 1, the first-layer wiring M1 connected to the drain D of the amplification transistor and the first-layer wiring M1 connected to the source of the reset transistor are not present in the interlayer insulating film 21. This reduces the number of adjacent first-layer wirings M1 in the readout circuit board 20 of the photodetector element 1, thereby reducing the parasitic capacitance generated inside the interlayer insulating film 21. Therefore, the photodetector element 1 can suppress a decrease in the signal change rate of the signal charge.

[0047] Furthermore, in the readout circuit board 20 of the photodetector element 1, the first-layer wiring M1 connected to the drain D of the amplification transistor and the first-layer wiring M1 connected to the source of the reset transistor are not present in the interlayer insulating film 21, which improves the degree of freedom in designing the first-layer wiring M1.

[0048] As a result, the first layer wiring M1 of the photodetector element 1 has improved design freedom, allowing the wiring length from the floating diffusion FD to the gate AMP of the amplifying transistor to be shortened, which also improves the signal conversion efficiency (conversion gain) of the oscillating charge.

[0049] Furthermore, since the drain wiring DL of the amplifier transistor is connected to a power supply and a relatively high voltage is applied thereto, it is desirable to provide the wiring DL away from other wiring. However, when the drain wiring DL of the amplifier transistor is provided in the interlayer insulating film 21 of the readout circuit substrate 20, it is difficult to provide the wiring DL away from other wiring because pixel transistors are densely packed as the pixel density increases. The pixel transistors include, for example, an amplifier transistor, a selection transistor, and a reset transistor.

[0050] Furthermore, it is desirable to increase the thickness of the drain wiring DL of the amplifier transistor to reduce its resistance in order to efficiently amplify the signal charge. However, when the drain wiring DL of the amplifier transistor is provided in the interlayer insulating film 21 of the readout circuit substrate 20, it is not easy to increase the thickness because the pixel transistors are densely packed as described above.

[0051] In contrast, the drain wiring DL of the amplification transistor provided in the photodetector element 1 is buried in the interlayer insulating film 11 of the logic circuit board 10, not in the interlayer insulating film 31 of the readout circuit board 20 where pixel transistors are densely arranged.

[0052] Therefore, the drain wiring DL of the amplification transistor can be provided away from other wirings and the wiring thickness can be increased, thereby improving the signal conversion efficiency of the photodetector 1.

[0053] 3 to 12, a manufacturing process of the photodetector element 1 according to the first embodiment will be described. When manufacturing the photodetector element 1, as shown in Fig. 3, first, shallow trench isolation STI is formed so as to partition the formation region of the pixel transistor in the semiconductor layer 22. The shallow trench isolation STI is formed, for example, by forming a trench in the semiconductor layer 22 and filling the trench with an insulator such as silicon oxide.

[0054] Thereafter, the gate AMP of the amplification transistor, the gate SEL of the selection transistor, and the gate of the reset transistor (not shown) are formed at predetermined positions on the upper surface of the semiconductor layer 22. Then, N-type impurities are ion-implanted into the interior of the semiconductor layer 22 on both sides of each gate to form the sources and drains of the amplification transistor, selection transistor, and reset transistor.

[0055] 4, deep trench isolation DTI is formed at a formation position of the connection part TSV (see FIG. 2) in the semiconductor layer 22. The deep trench isolation DTI is formed, for example, by forming a trench (groove) deeper than the shallow trench isolation STI in the semiconductor layer 22 and filling the trench with an insulator such as silicon oxide.

[0056] 5, a conductive portion POLY is formed on the upper surface of the deep trench isolation DTI (on the same plane as the gate AMP of the amplification transistor). The conductive portion POLY is formed of doped polysilicon to which N-type impurities are added.

[0057] 6, the steps of forming an interlayer insulating film 21 on the semiconductor layer 22, forming vias in the interlayer insulating film 21, and forming wiring are repeated to bury first-layer to third-layer wirings M1, M2, and M3 inside the interlayer insulating film 21. Then, copper wiring CC is buried in the surface layer of the interlayer insulating film 21.

[0058] 7, the sensor substrate 30 is bonded to the readout circuit substrate 20 formed in the steps shown in Fig. 3 to Fig. 6. At this time, the copper wiring CC of the sensor substrate 30 and the copper wiring CC of the readout circuit substrate 20 are joined together to bond the two substrates together. This electrically connects the floating diffusion FD and the gate AMP of the amplification transistor.

[0059] 8, the readout circuit board 20 is ground and polished from the underside to thin the readout circuit board 20, and an interlayer insulating film 21 is formed below the semiconductor layer 22. Thereafter, a via VA is formed that reaches the underside of the readout circuit board 20 from the first to third layer wirings M1, M2, and M3 formed outside the pixel region.

[0060] 9, a connection portion TSV is formed that penetrates the deep trench isolation DTI in the readout circuit substrate 20 in the thickness direction of the semiconductor layer 22. As described above, the connection portion TSV is, for example, a through silicon via.

[0061] 10, copper wiring CC connected to the connection parts TSV and vias VA is buried in the lower layer of the interlayer insulating film 21 of the readout circuit board 20. Then, as shown in Fig. 11, the logic circuit board 10 is attached to the surface of the readout circuit board 20 opposite to the surface to which the sensor substrate 30 is attached.

[0062] At this time, the copper wiring CC of the readout circuit board 20 and the copper wiring CC of the logic circuit board 10 are joined together to bond the two boards together, thereby electrically connecting the readout circuit board 20 and the logic circuit board 10.

[0063] 12, a color filter CF and an on-chip lens OCL are sequentially formed on the upper surface of each photodiode PD of the sensor substrate 30. Finally, an opening extending from the upper surface toward the inside of the interlayer insulating film 31 is formed outside the pixel region of the sensor substrate 30, and an aluminum connection pad AL, for example, is formed inside the opening, thereby completing the photodetector element 1 shown in FIG.

[0064] 2 to 12 omits the step of forming the connection portion TSV connected to the source S of the reset transistor. The connection portion TSV connected to the source S of the reset transistor can be formed by the same step as the step of forming the connection portion TSV connected to the drain D of the amplification transistor.

[0065] 4. Photodetection element according to second embodiment Next, a photodetection element 1A according to a second embodiment will be described with reference to Fig. 13. Fig. 13 is an explanatory diagram showing a part of a cross section of the photodetection element 1A according to the second embodiment.

[0066] 13 , the photodetector element 1A is different from the first embodiment in that the conductive portion POLY is embedded inside the semiconductor layer 22, but other configurations are the same as those of the first embodiment. The conductive portion POLY according to the second embodiment corresponds to a side contact structure that may be used in the sensor substrate 30.

[0067] That is, the conductive part POLY according to the second embodiment is connected to the drain D of the amplification transistor inside the semiconductor layer 22 and is connected to the source of the selection transistor inside the semiconductor layer 22 .

[0068] The conductive portion POLY according to the second embodiment is made of, for example, doped polysilicon to which N-type impurities are added. The conductive portion POLY may be made of a conductive material with high heat resistance, such as tungsten (W), titanium (Ti), or titanium nitride (TiN).

[0069] According to the photodetector element 1A of the second embodiment, the distance from the conductive portion POLY to the first-layer wiring M1 can be further increased compared to when the conductive portion POLY is provided inside the interlayer insulating film 21.

[0070] This further reduces the parasitic capacitance formed by the conductive portion POLY and the first-layer wiring M1 in the photodetector element 1A, thereby further improving the signal conversion efficiency of the signal charge. Also, since the conductive portion POLY is not provided in the interlayer insulating film 21 in the photodetector element 1A, the degree of freedom in designing the first-layer wiring M1 can be further improved.

[0071] 5. Light-detecting element according to third embodiment Next, a light-detecting element 1B according to a third embodiment will be described with reference to Fig. 14. Fig. 14 is an explanatory diagram showing a part of a cross section of the light-detecting element 1B according to the third embodiment.

[0072] As shown in Figure 14, the photodetector element 1B of the third embodiment does not have a conductive portion POLY, and one of the connection portions TSV is directly connected to the drain D of the amplification transistor, and one of the connection portions TSV is directly connected to the source S of the selection transistor.

[0073] In other words, the conductive portion (a member corresponding to the conductive portion POLY in the second embodiment) provided at a position closer to the semiconductor layer 22 than the gate wiring in the third embodiment is a region doped with N-type impurities inside the semiconductor layer 22 on the side where the gate is provided. The conductive portion in the third embodiment functions as at least one of the source and drain of the transistor.

[0074] As a result, like the first and second embodiments, the photodetector element 1B improves the signal conversion efficiency while enabling the size in the planar direction to be reduced because the conductive portion POLY, the drain D of the amplification transistor, and the source S of the selection transistor are not arranged side by side.

[0075] 6. Light-detecting element according to the fourth embodiment Next, a light-detecting element 1C according to the fourth embodiment will be described with reference to Fig. 15. Fig. 15 is an explanatory diagram showing a part of a cross section of the light-detecting element 1C according to the fourth embodiment.

[0076] 15 , the photodetector element 1C according to the fourth embodiment includes an impurity region IP1 doped with an N-type impurity at a position facing the drain D of the amplification transistor and at a position facing the source S of the selection transistor in the semiconductor layer 22. The impurity region IP1 is formed by ion-implanting the N-type impurity into the semiconductor layer 22.

[0077] Furthermore, the photodetector element 1C includes, instead of the connection portion TSV, a connection portion IP2 in which the semiconductor layer 22 is doped with N-type impurities so as to penetrate the semiconductor layer 22 in the thickness direction. The connection portion IP2 is formed by ion-implanting the N-type impurities into the semiconductor layer 22.

[0078] The connection part IP2 electrically connects the drain D of the amplification transistor to the impurity region IP1, and electrically connects the source S of the selection transistor to the impurity region IP1. The impurity region IP1 is electrically connected to the copper wiring CC on the underside of the readout circuit substrate 20 through a via.

[0079] According to the photodetector element 1C, for example, there is no need to form the conductive portion POLY using polysilicon or the like, and the connection portion IP2 can be formed by utilizing the ion implantation process used when forming the drain D of the amplification transistor and the source S of the selection transistor. Therefore, the photodetector element 1C can improve the signal conversion efficiency, similar to the first to third embodiments, while simplifying the manufacturing process.

[0080] 7. Light-detecting element according to fifth embodiment Next, a light-detecting element 1D according to a fifth embodiment will be described with reference to Fig. 16. Fig. 16 is an explanatory diagram showing a part of a cross section of the light-detecting element 1D according to the fifth embodiment.

[0081] In the first embodiment, the case has been described in which all source wirings and drain wirings other than the gate wirings are provided closer to the logic circuit substrate 10 than the semiconductor layer 22 of the readout circuit substrate 20, and are connected to the source and drain of each transistor via the connection parts TSV.

[0082] In contrast, the photodetector element 1D according to the fifth embodiment has a configuration in which, as shown in FIG. 16, only the drain wiring DL of the amplification transistor is provided closer to the logic circuit substrate 10 than the semiconductor layer 22, and is connected to the drain D of the amplification transistor via a connection part TSV.

[0083] It is generally desirable for the drain wiring DL of the amplification transistor to have a wider line width than other wiring in order to prevent voltage drop (IR-Drop), and by placing just the drain wiring DL of the amplification transistor on the back surface, as in the photodetector element 1D, the effect of improving the layout freedom is significant.

[0084] 8. Modifications In the above embodiment, the drain wiring DL of the amplification transistor and the source wiring SL of the selection transistor are provided on the logic circuit substrate 10. However, this is just one example. Wiring other than the gate wiring of the readout circuit substrate 20 may be embedded in the interlayer insulating film 21 that is present between the logic circuit substrate 10 and the semiconductor layer 22 of the readout circuit substrate 20.

[0085] In the first embodiment described above, the conductive portion POLY is provided on the same plane as the gate AMP of the amplifier transistor, but this is just one example. The conductive portion POLY according to the first embodiment does not necessarily have to be provided on the same plane as the gate AMP of the amplifier transistor, as long as it is located closer to the semiconductor layer 22 than the first-layer wiring M1.

[0086] Furthermore, the connection portion TSV according to the first to third embodiments and the fifth embodiment may be replaced with the connection portion IP2 according to the fourth embodiment. That is, the connection portion TSV according to the first to third embodiments and the fifth embodiment may be formed by ion-implanting N-type impurities into the semiconductor layer 22.

[0087] Furthermore, the connection portion IP2 according to the fourth embodiment may be replaced with the connection portion TSV according to the first to third embodiments and the fifth embodiment. Any of the above-described modifications can improve the signal conversion efficiency of the photodetector element and the degree of freedom in designing the first-layer wiring M1.

[0088] The present technology can also be configured as follows. (1) A photodetector including a sensor substrate provided with a photoelectric conversion element that photoelectrically converts incident light into a signal charge, and a readout circuit board attached to a surface of the sensor substrate opposite to a light-receiving surface thereof and provided with a readout circuit that reads out the signal charge from the sensor substrate, wherein the readout circuit board has: a semiconductor layer in which a transistor is formed; gate wiring provided in an interlayer insulating film between the semiconductor layer and the sensor substrate and connected to a gate of the transistor; a conductive portion provided at a position closer to the semiconductor layer than the gate wiring; and a connection portion that penetrates the semiconductor layer in a thickness direction and electrically connects the conductive portion to a wiring layer provided on the opposite side of the interlayer insulating film via the semiconductor layer. (2) The photodetector according to (1), wherein the conductive portion is provided on the same plane as the gate. (3) The photodetector according to (1), wherein the conductive portion is embedded inside the semiconductor layer on the side where the gate is provided. (4) The photodetector element according to (2) or (3), wherein the conductive portion is formed of polysilicon. (5) The photodetector element according to (3), wherein the conductive portion is a region doped with impurities inside the semiconductor layer on a side where the gate is provided, and functions as at least one of the source and drain of the transistor. (6) The photodetector element according to any one of (1) to (5), wherein the connection portion is a TSV (Through Silicon Via). (7) The photodetector element according to any one of (1) to (6), wherein the connection portion is a region doped with impurities in the semiconductor layer. (8) The photodetector element according to any one of (1) to (7), wherein the transistor is an amplifier transistor that amplifies the signal charge, wherein the conductive portion is provided so as to be in contact with the drain of the amplifier transistor, and wherein the wiring layer is a drain wiring connected to a power supply and applying a power supply voltage to the drain of the amplifier transistor. (9) The light-detecting element according to (8), wherein the drain wiring has a thickness greater than that of other wirings provided in the interlayer insulating film.(10) The photodetector element according to any one of (1) to (7), wherein the transistor is a selection transistor that selects a photoelectric conversion element that reads out the signal charge from the plurality of photoelectric conversion elements, and the conductive portion is provided so as to be in contact with a source of the selection transistor. (11) The photodetector element according to any one of (1) to (10), further including a logic circuit board that is attached to a surface of the readout circuit board opposite to a surface to which the sensor substrate is attached, and that has a logic circuit that processes the readout signal charge, and wherein the wiring layer is embedded in an interlayer insulating film of the logic circuit board. (12) The photodetector element according to any one of (1) to (10), wherein the readout circuit board further includes an interlayer insulating film that is provided on the opposite side of the interlayer insulating film with the semiconductor layer interposed therebetween, and the wiring layer is embedded in an interlayer insulating film that is provided on the opposite side of the interlayer insulating film with the semiconductor layer interposed therebetween.

[0089] 100, 1, 1A, 1B, 1C, 1D Photodetector element 10 Logic circuit board 11 Interlayer insulating film 12, 13, 22 Semiconductor layer 20 Readout circuit board 21 Interlayer insulating film 30 Sensor substrate 31 Interlayer insulating film AMP, SEL Gate CC Copper wiring D Drain S Source DL Drain wiring SL Source wiring DTI Deep trench isolation STI Shallow trench isolation FD Floating diffusion IP1 Impurity region M1 First layer wiring M2 Second layer wiring M3 Third layer wiring OCL On-chip lens PD Photodiode POLY Conductive portion TG Transfer gate TSV, IP2 Connection portion

Claims

1. A photodetector comprising: a sensor substrate provided with a photoelectric conversion element that photoelectrically converts incident light into a signal charge; and a readout circuit board attached to the surface of the sensor substrate opposite to the light-receiving surface and provided with a readout circuit that reads out the signal charge from the sensor substrate, wherein the readout circuit board has: a semiconductor layer in which a transistor is formed; gate wiring provided in an interlayer insulating film between the semiconductor layer and the sensor substrate and connected to the gate of the transistor; a conductive portion provided at a position closer to the semiconductor layer than the gate wiring; and a connection portion that penetrates the semiconductor layer in the thickness direction and electrically connects the conductive portion to a wiring layer provided on the opposite side of the interlayer insulating film via the semiconductor layer.

2. The photodetector element according to claim 1, wherein the conductive portion is provided on the same plane as the gate.

3. The photodetector element according to claim 1, wherein the conductive portion is embedded inside the semiconductor layer on the side where the gate is provided.

4. The photodetector element according to claim 2 or 3, wherein the conductive portion is formed from polysilicon.

5. The photodetector element according to claim 3, wherein the conductive portion is a region doped with impurities inside the semiconductor layer on the side where the gate is provided, and functions as at least one of the source and drain of the transistor.

6. The photodetector element according to claim 1, wherein the connection portion is a TSV (Through Silicon Via).

7. The photodetector element according to claim 1, wherein the connection portion is a region in the semiconductor layer where impurities are doped.

8. The photodetector element according to claim 1, wherein the transistor is an amplifying transistor that amplifies the signal charge, the conductive portion is provided so as to be in contact with the drain of the amplifying transistor, and the wiring layer is a drain wiring that is connected to a power supply and applies a power supply voltage to the drain of the amplifying transistor.

9. The photodetector element according to claim 8, wherein the drain wiring is thicker than other wirings provided in the interlayer insulating film.

10. The photodetector element according to claim 1, wherein the transistor is a selection transistor that selects a photoelectric conversion element from which the signal charge is to be read out from the plurality of photoelectric conversion elements, and the conductive portion is provided so as to be in contact with the source of the selection transistor.

11. The photodetector element according to claim 1, further comprising a logic circuit board attached to the surface of the readout circuit board opposite to the surface to which the sensor substrate is attached, and having a logic circuit for processing the read-out signal charges, wherein the wiring layer is embedded in an interlayer insulating film of the logic circuit board.

12. The photodetector element according to claim 1, wherein the readout circuit board further comprises an interlayer insulating film provided on the opposite side of the interlayer insulating film with the semiconductor layer interposed therebetween, and the wiring layer is embedded in the interlayer insulating film provided on the opposite side of the interlayer insulating film with the semiconductor layer interposed therebetween.

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