PAM-2n system with optimized clock-data recovery characteristics

Abstract

Proposed is a PAM-2N system capable of supporting a training pattern and optimizing clock-data recovery characteristics through data encoding. The PAM-2N system with optimized clock-data recovery characteristics includes a receiver, a de-serializer, a data encoder, a PAM-2N transmitter, a PAM-2N receiver, a CDR, and a serializer & transmitter.

Description

PAM 2's N-square system with optimized clock-data recovery characteristics

[0001] The present invention relates to a PAM system, and more particularly, to a PAM 2-to-N (hereinafter referred to as PAM-2) system capable of supporting a training pattern and optimizing clock data recovery characteristics through data encoding. N ) is about the system.

[0002] When transmitting and receiving data (or signals) between two points, it would be desirable and efficient to be able to transmit larger amounts of data at faster speeds than before. For example, to double the data transmission speed between two points, a channel or lane could be added to transmit the data. In this case, in addition to adding a channel to the existing one that serves as the data transmission path, an additional transmitter and receiver would be required for the added channel. The increased power consumption caused by the additional transmitter and receiver is a drawback of simply adding channels.

[0003] To overcome the drawbacks of the technique of adding channels, it was proposed to serialize two bit streams, but this proposal also has the problem of doubling the bandwidth of the signal.

[0004] To overcome the drawbacks of serializing two bit streams, the PAM-4 (Pulse Amplitude Modulation 4) method was proposed. PAM-4 divides the LSB (Least Significant Bit) signal in half and adds it to the MSB (Most Significant Bit) signal, resulting in four (4) levels of the transmitted and received signal instead of two (2 levels). While one bit can implement two levels, including 0 and 1, two bits can implement four levels, such as 00, 01, 10, and 11. Assuming that one bit and two bits are transmitted at the same rate, the amount of data transmitted in the same amount of time will be twice that of two levels for four levels.

[0005] Recent high-speed interfaces use clock and data recovery (CDR) technology to reduce the number of pins in a package. This is because CDR reduces the number of clock lanes.

[0006] The CDR receives a training pattern (or toggling pattern) signal and random data, and generates one-unit interval (One Unit Interval) information of the data from the toggling of the received data, thereby generating a clock having a frequency matching the data transmission rate (Data Rate). However, if the received data maintains the same DC value, i.e., the '0' or '1' state for a certain period of time, the CDR may not be able to update the data information, which may cause a problem in that the frequency of the clock (CLK) may be different from the data transmission rate (frequency).

[0007] To solve this problem, applications that use CDR adopt the 8Bit / 10B encoding technique to generate DC balanced data of '0' and '1'.

[0008] Figure 1 shows a block diagram of a conventional PAM-4 system.

[0009] Referring to FIG. 1, a conventional PAM-4 system (100) includes a receiver (110), a PLL (120), a de-serializer (130), a PAM-4 transmitter (140), a PAM-4 receiver (150), a half-rate CDR (160), and a serializer & transmitter (170).

[0010] The receiver (110, Receiver) receives two serial input data (IN) encoded 8B / 10B. P , IN M ) is a serial data (D) arranged with the MSB and LSB alternately arranged IN ) is converted to 10-bit serial data (D IN ) has the form of, for example, MSB0, LSB0, MSB1, LSB1, … MSB4, LSB4.

[0011] The de-serializer (130) uses the clock (CLK) generated by the PLL (120) to generate serial data (D IN ) are separated and arranged into MSB and LSB respectively to produce 2-bit de-serialized data (D MSB, D LSB ) is converted to the first 2-bit de-serialized data (D MSB) has the form of MSB0, MSB1, MSB2, MSB3, MSB4, and is the second 2-bit de-serialized data (D LSB) It has the form of LSB0, LSB1, LSB2, LSB3, LSB4.

[0012] The PAM-4 transmitter (140) transmits 2-bit de-serialized data (D MSB, D LSB ) using two transmission data (TX) with 4 levels OP , TX OM ) is created.

[0013] The PAM-4 receiver (150) receives two transmission data (TX OP , TX OM ) to create three 3-level data (D) with three levels (H, M, L) H , D M , D L ) is created.

[0014] Half-rate CDR (160) is a three-level data (D H , D M , D L ) using six 6-level data (DH_ MSB , DH_ LSB , DM_ MSB , DM_ LSB , DL_ MSB , DL_ LSB ) is created.

[0015] Serializer & Transmitter (170) is a 6-level data (DH_ MSB , DH_ LSB , DM_ MSB , DM_ LSB , DL_ MSB , DL_ LSB ) to two output data (TX OP2 , TX OM2 ) is serialized.

[0016] Figure 2 shows a timing diagram of a conventional PAM-4 system.

[0017] Referring to FIG. 2, in a conventional PAM-4 system (100), two serial input data (IN) received by a receiver (110) P , IN M) is a representative DC balanced data, a toggle pattern. The black and gray data are each two serial input data (IN P , IN M ) is indicated. The receiver (110) receives two serial input data (IN P , IN M ) is a serial data (D) that lists the MSB and LSB alternately. IN ) is created.

[0018] The de-serializer (130) synchronizes with the clock (CLK) received from the PLL (120) to generate serial data (D). IN ) as the first 2-bit de-serialized data (D MSB, D LSB ) is converted to. For convenience of explanation, as shown in Fig. 2, the first 2-bit de-serialized data (D MSB ) outputs only the value “1” and the second 2-bit de-serialized data (D LSB ) assumes that only the DC value of “0” is output.

[0019] The PAM-4 transmitter (140) transmits 2-bit de-serialized data (D MSB, D LSB ) with two transmission data (TX) with 4 levels OP , TX OM ) is converted to .

[0020] The PAM-4 receiver (150) has two transmission data (TX OP , TX OM ) and receives three 3-level data (D) having three levels (H, M, L). H , D M , D L ) is converted to .

[0021] Half-rate CDR (160) is a three-level data (D H , D M , D L) has six 6-level data (DH_ MSB , DH_ LSB , DM_ MSB , DM_ LSB , DL_ MSB , DL_ LSB ) is converted to .

[0022] Referring to Figure 2, two transmission data (TX OP , TX OM ) and three 3-level data (D H , D M , D L ) all have the same DC value of '1' or '0' for a certain period of time, so the half-rate CDR (160) cannot operate normally, so 6 6-level data (DH_ MSB , DH_ LSB , DM_ MSB , DM_ LSB , DL_ MSB , DL_ LSB ) will no longer be able to maintain DC balance.

[0023] Ultimately, there are two output data signals (TX OP2 , TX OM2 ) are two serial input data signals (IN P , IN M ) will be a data signal that cannot be modulated into a data value that targets the target.

[0024] The technical problem to be solved by the present invention is to provide a PAM-2 that can support training patterns and optimize clock data recovery characteristics through data encoding. N It's about providing a system.

[0025] The technical problems to be achieved in the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the present invention belongs from the description below.

[0026] PAM-2 with optimized clock data recovery characteristics according to the present invention to achieve the above technical task N The system consists of a receiver, a de-serializer, a data encoder, and a PAM-2 N Transmitter, PAM-2 N Includes receiver and CDR.

[0027] The receiver converts the received serial input data into serial data by listing the MSB and LSB alternately. The deserializer converts the serial data into N (where N is a natural number greater than or equal to 2)-bit deserialized data using a clock. The data encoder encodes the N-bit deserialized data to generate N-bit encoded deserialized data. The PAM-2 N The transmitter generates a differential signal using the N-bit encoded de-serialized data. The PAM-2 N The receiver receives the above differential signal (2 N -1) Generates bit data. The above CDR is (2 N -1) Use bit data.

[0028] The technical problems to be achieved in the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned can be clearly understood by a person having ordinary skill in the technical field to which the present invention belongs from the description below.

[0029] PAM-2 with optimized clock data recovery characteristics according to the present invention as described above N The system has the advantage of being able to support training patterns and improving clock data recovery characteristics by supplying improved DC balanced data to the CDR even from random data.

[0030] The effects that can be obtained from the present invention are not limited to the effects mentioned above, and other effects not mentioned can be clearly understood by a person having ordinary skill in the art to which the present invention belongs from the description below.

[0031] Figure 1 shows a block diagram of a conventional PAM-4 system.

[0032] Figure 2 shows a timing diagram of a conventional PAM-4 system.

[0033] Figure 3 is a PAM-2 optimized for clock data recovery characteristics according to the present invention. N Shows a block diagram of the system.

[0034] Figure 4 shows a block diagram of a data encoder.

[0035] Figure 5 is PAM-2 according to the present invention. N Shows the timing diagram of the system.

[0036] Figures 6a to 6c show timing diagrams of a data encoder.

[0037] Figure 7 shows the results of a computer simulation of the number of data repetitions before and after the data encoder is applied.

[0038] In order to fully understand the present invention, its operational advantages, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings illustrating embodiments of the present invention and the contents described in the accompanying drawings.

[0039] Hereinafter, the present invention will be described in detail by describing preferred embodiments thereof with reference to the attached drawings. The same reference numerals in each drawing represent the same components.

[0040] Figure 3 is a PAM-2 optimized for clock data recovery characteristics according to the present invention. N Shows a block diagram of the system.

[0041] Referring to FIG. 3, PAM-2 optimized for clock data recovery characteristics according to the present invention N System (300, hereinafter PAM-2) N The system (N is a natural number greater than or equal to 2) comprises a receiver (310), a PLL (320), a de-serializer (330), a data encoder (335), and a PAM-2 N Includes a transmitter (340), a PAM-4 receiver (350), a half-rate CDR (360), and a serializer & transmitter (370).

[0042] Below, PAM-4 with N equal to 2 is used as an example, but it is not difficult for a person skilled in the art to apply this explanation to an embodiment with N equal to 3 or more.

[0043] The receiver (310, Receiver) receives two serial input data (IN) encoded in 8B / 10B. P , IN M ) and receives two serial input data (IN P , IN M ) is a serial data (D) that lists the MSB and LSB alternately. IN ) is converted to .

[0044] The de-serializer (330) uses the clock (CLK) generated by the PLL (320) to generate serial data (D IN ) as 2-bit de-serialized data (D MSB, D LSB ) is converted to .

[0045] The data encoder (335) outputs 2-bit de-serialized data (D MSB, D LSB ) encoded 2-bit encoded de-serialized data (D MSB2, D LSB2 ) is created.

[0046] Figure 4 shows a block diagram of a data encoder.

[0047] Referring to FIG. 4, the data encoder (335) includes a pipeline memory (410), a counter (420), a data sorter (430), and a multiplexer & sampler (440).

[0048] The pipeline memory (410) receives 2-bit de-serialized data (D) from the de-serializer (430). MSB, D LSB ) and store the 2-bit de-serialized data (D) according to the clock (CLK) output from the PLL (420). MSB, D LSB ) and sorted by separating the MSB and LSB to obtain the 10-bit MSB (DP MSB [9:0]) and 10-bit LSB (DP LSB [9:0]) is output. Therefore, the 10-bit MSB (DP MSB [9:0]) and 10-bit LSB (DP LSB [9:0]) is 2-bit deserialized data (D MSB, D LSB ) has a phase difference of one clock cycle (CLK).

[0049] The counter (420, Counter) divides the clock (CLK) by 10 to generate a clock count signal (CO[9:0]), which is a pulse signal with a duty of 10%.

[0050] The data alignment device (430, Data Aligner) aligns the timing of data with the clock (CLK) by 10-bit MSB (DP) MSB [9:0]) and 10-bit LSB (DP LSB [9:0]) aligned to the clock count signal (CO[9:0]) with the 10-bit MSB (DA) MSB [9:0]) and alignment 10-bit LSB (DA LSB Creates [9:0].

[0051] The multiplexer & sampler (440) includes a 20-to-2 multiplexer (MUX, not shown; hereinafter referred to as multiplexer) and a sampler (Sampler, not shown), and the multiplexer uses a clock (CLK) and a clock count signal (CO[9:0]) to align 10-bit MSB (DA). MSB [9:0]) and alignment 10-bit LSB (DA LSB [9:0]) is multiplexed and then sampled by a sampler (not shown) to produce 2-bit encoded de-serialized data (D MSB2, D LSB2 ) is created.

[0052] 2-bit deserialized data maintained as DC (D MSB, D LSB ) is encoded in the order of {MSB0, LSB0, …, MSB4, LSB4} through the data encoder (335) as the first encoded 2-bit de-serialized data (D MSB2 ) is output, followed by the second encoded 2-bit deserialized data (D) encoded in the order of {MSB5, LSB5, …, MSB9, LSB9}. LSB2 ) is printed.

[0053] The following 2-bit deserialized data (D MSB, D LSB ) also 2-bit encoded de-serialized data (D MSB2, D LSB2 ) is output. The reason why it is encoded by dividing it into 10-bit units is because the 8B / 10B encoding technique has a DC balance based on 10 bits. If encoded in this way, the input of the half-rate CDR will also be a toggle pattern like the input of the de-serializer (330).

[0054] PAM-2 N The transmitter (340) outputs 2-bit encoded de-serialized data (D MSB2, D LSB2) to transmit two transmission data (TX) which are differential signals with 4 levels. OP , TX OM ) is created.

[0055] PAM-2 N The receiver (350) transmits two differential signals (TX) OP , TX OM ) and each has three levels (H, M, L) (2 N -1) bit data (D H , D M , D L ) is created.

[0056] CDR(360) is (2 N -1) bit data (D H , D M , D L ) to create six 6-level data (DH_ MSB , DH_ LSB , DM_ MSB , DM_ LSB , DL_ MSB , DL_ LSB ) is created.

[0057] Serializer & Transmitter (370) is a 6-level data (DH_ MSB , DH_ LSB , DM_ MSB , DM_ LSB , DL_ MSB , DL_ LSB ) to two output data (TX OP2 , TX OM2 ) is serialized.

[0058] PAM-2 according to the present invention as shown in Fig. 3 N The configuration of the system (300) and the configuration of the conventional PAM-4 system (100) illustrated in FIG. 1 are the same except for the data encoder (335), so the PAM-2 illustrated in FIG. 3 NWhen describing the timing diagram of the system (300), descriptions of signals that overlap with the timing diagram of the conventional PAM-4 system (100) illustrated in FIG. 2 are omitted, and only additional signals and signals that differ in level are described.

[0059] Figure 5 is PAM-2 according to the present invention. N Shows the timing diagram of the system.

[0060] In the timing diagram illustrated in FIG. 5, the characteristics of the timing diagram of the receiver (410), PLL (420) and de-serializer (330) are replaced with the description of the timing diagram illustrated in FIG. 2.

[0061] Referring to FIG. 5, the 2-bit encoded de-serialized data (D) generated by the data encoder (335) MSB2, D LSB2 ) of the first 2-bit encoded de-serialized data (D MSB2 ) is a 10-bit (MSB0, LSB0 … MSB4, LSB4) in which the upper 5 bits of the 10-bit MSB and LSB are arranged alternately, and the second 2-bit encoded de-serialized data (D LSB2 ) is a 10-bit (MSB5, LSB5 … MSB9, LSB9) that alternates the MSB and LSB, which are the lower 5 bits of the 10-bit MSB and LSB, respectively.

[0062] Each 10-bit first 2-bit encoded de-serialized data (D MSB2 ) and the second 2-bit encoded de-serialized data (D LSB2 ) contains toggling data, and is output from the de-serializer (330) as 2-bit de-serialized data (D MSB, D LSB ) is a data encoder (335) and PAM-2 NTwo transmission data (TX) which are differential signals with 4 levels are transmitted through the transmitter (340). OP , TX OM ) becomes.

[0063] PAM-2 N The receiver (350) transmits two differential signals (TX) OP , TX OM ) and each has three levels (H, M, L) (2 N -1) bit data (D H , D M , D L ) is created.

[0064] CDR(360) is (2 N -1) bit data (D H , D M , D L ) to create six 6-level data (DH_ MSB , DH_ LSB , DM_ MSB , DM_ LSB , DL_ MSB , DL_ LSB ) is created.

[0065] Figure 6 shows a timing diagram of a data encoder.

[0066] Referring to FIGS. 4 and 6, the pipeline memory (410) uses a clock (CLK) to store 10-bit parallel data (10-bit MSB (DP)) in which DP[N+1] is delayed by one cycle compared to DP[N]. MSB [9:0] and 10-bit LSB (DP LSB [9:0]) is generated. Here, 10-bit MSB DP MSB [0] is the 2-bit de-serialized data D, which is the input data signal. MSB Use as is. LSB signal DP LSB It is also created in the same way.

[0067] In the data sorting device (430), the MSB DP is used using the clock count signal CO[0].MSB [5] Sampling MSB0 and sorting MSB DA MSB Generate [0] and use clock count signal CO[2] to generate MSB DP MSB [6] Sampling MSB1 of the aligned MSB signal DA MSB [1] is created. DA in the same way MSB [9:0] and DA LSB [9:0] is created.

[0068] In the multiplexer (440), the MSB (DA) is aligned according to the clock count signal CO[9:0]. MSB [9:0]) and alignment LSB (DA LSB [9:0]) is selected to convert a 10-bit parallel data signal into a 1-bit serial data signal. Aligned according to the clock count signal CO[1] MSB DA MSB Select [0] to select data D PRE-MSB2 Output as and sort MSB DA according to clock count signal CO[3] MSB Select [1] to select data D PRE-MSB2 is output. In the same way, the 10-bit aligned MSB (DA) MSB [9:0]) and alignment LSB (DA LSB [9:0]) is serial data (D PRE-MSB2 and D PRE-LSB2 ) are converted into serialized data (D PRE-MSB2 and D PRE-LSB2 ) is 2-bit encoded de-serialized data (D) through a sampler (440). MSB2 Wow D LSB2 ) is printed.

[0069] Figure 7 shows the results of a computer simulation of the number of data repetitions before and after the data encoder is applied.

[0070] Figure 7a shows the process before applying random data to the data encoder (335) (Conv. D M ) and after (Prop. D M ) shows the results of computer simulation experiments.

[0071] Referring to FIG. 7a, before applying random data to the data encoder (335), the maximum repetition number of data “1” is measured as “11” and the maximum repetition number of “0” is measured as “12”, whereas after applying random data to the data encoder (335), the maximum repetition number of both “1” and “0” is “5”, confirming that the maximum repetition number has decreased compared to before the data encoder (335) is applied.

[0072] Figure 7b shows the training pattern before applying it to the data encoder (335) (Conv. D M ) and after (Prop. D M ) shows the results of computer simulation experiments.

[0073] Referring to FIG. 7b, before applying the training pattern to the data encoder (335), the maximum number of repetitions continues to increase because the training pattern is transformed into DC data, whereas after applying the training pattern to the data encoder (335), the maximum number of repetitions is measured as “1” because the training pattern is transformed into a toggle pattern.

[0074] Therefore, the data encoder (335) proposed in the present invention has the advantage of being able to support a training pattern in a PAM4 system and of being able to improve clock data recovery characteristics by supplying improved DC balanced data to a half-rate CDR (360) even in random data.

[0075] The above description has been given only for PAM-4 as an example to facilitate understanding of the present invention, but it is obvious to those skilled in the art that the present invention can be extended and applied to PAM-8 with N=3 and PAM-16 with N=4.

[0076] In particular, PAM-2 has been recently applied to the automotive semiconductor field. NThe system has enormous potential to expand across industries.

[0077] The present invention described above can be implemented as computer-readable code on a program-recorded medium. Computer-readable media include all types of recording devices that store data readable by a computer system. Examples of computer-readable media include hard disk drives (HDDs), solid-state disk drives (SSDs), silicon disk drives (SDDs), read-only memory (ROM), random-access memory (RAM), CD-ROMs, magnetic tapes, floppy disks, and optical data storage devices.

[0078] While the technical concepts of the present invention have been described above, along with the accompanying drawings, they are merely illustrative of preferred embodiments of the invention and are not intended to limit the scope of the invention. Furthermore, it is readily apparent that anyone skilled in the art will be able to make various modifications and imitations without departing from the scope of the technical concepts of the present invention.

[0079] The present invention relates to pulse amplitude modulation (PAM) that can support training patterns and optimizes clock data recovery characteristics through data encoding. PAM-2 with optimized clock data recovery characteristics N The system consists of a receiver, a de-serializer, a data encoder, and a PAM-2 N Transmitter, PAM-2 N Includes receivers, CDRs, and serializers & transmitters.

Claims

1. A receiver that converts the MSB and LSB of the received serial input data into serial data listed alternately; A deserializer that converts the serial data into N-bit (N is a natural number greater than or equal to 2) deserialized data using a clock; A data encoder that encodes the N-bit de-serialized data to generate N-bit encoded de-serialized data; PAM-2 generating a differential signal using the above N-bit encoded de-serialized data. N transmitter; By receiving the above differential signal (2 N -1) PAM-2 generating bit data N receiver; and Above (2) N -1) CDR using bit data; PAM-2 including N System.

2. In the first paragraph, the data encoder, PAM-2 encoding the N-bit encoded de-serialized data to be a toggle pattern even when the N-bit de-serialized data maintains the same DC value. N System.

3. In the second paragraph, the data encoder, A pipeline memory that stores the N-bit de-serialized data, samples the N-bit de-serialized data by distinguishing the MSB and the LSB according to the clock, sorts the samples, and outputs a 10-bit MSB and a 10-bit LSB; A counter that generates a clock count signal using the above clock; A data alignment device that aligns the 10-bit MSB and the 10-bit LSB to the clock count signal to generate an aligned 10-bit MSB and an aligned 10-bit LSB; and A multiplexer & sampler that generates the N-bit encoded de-serialized data using the aligned 10-bit MSB and the aligned 10-bit LSB using the clock and the clock count signal; PAM-2 including N System.

4. In the third paragraph, the multiplexer & sampler, A multiplexer that multiplexes the aligned 10-bit MSB and the aligned 10-bit LSB using the clock and the clock count signal; and A sampler for sampling the output of the multiplexer to generate the N-bit encoded de-serialized data; PAM-2 including N System.

5. In paragraph 3, The above 10-bit MSB and the above 10-bit LSB are PAM-2 with a phase difference of one cycle of the N-bit de-serialized data and the clock. N System.

6. In the third paragraph, the clock count signal is PAM-2, a pulse signal with a duty of 10%, is generated by dividing the above clock by 10. N System.

7. In paragraph 1, PLL that generates the above clock; PAM-2 including more N System.

8. In paragraph 1, The above two transmission data are PAM-2 with 4 levels N System.

9. In paragraph 1, Above (2) N -1) PAM-2 bit data has 3 levels N System.

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