Display and electronic device comprising same

Abstract

This electronic device may comprise a gate driver circuit, a display driver integrated circuitry (IC), and a display panel including sub-pixels. Each of the sub-pixels can include: a light-emitting element; a storage capacitor for storing data voltage; and a transistor including a gate electrode connected to the storage capacitor. The display driver IC can transmit a clock signal for generating a scan signal to the gate driver circuit within an active section of a vertical synchronization signal, during which the scan signal is transmitted to the gate electrode of the transistor by using the gate driver circuit, and stop transmitting the clock signal for generating the scan signal to the gate driver circuit within a porch section of the vertical synchronization signal, during which the scan signal is not transmitted to the gate electrode of the transistor by using the gate driver circuit.

Description

Display and electronic device including it

[0001] The descriptions below relate to displays and electronic devices including them.

[0002] A display may be used to display an image. The display may include a display panel and a display driving circuit. The display driving circuit may be configured to display the image acquired from a processor of the electronic device on the display panel. For example, the display driving circuit may be configured to control a source driver (or data driver) of the electronic device and a gate driver (or scan driver) of the electronic device to display the image on the display panel.

[0003] The above information may be provided as background art to aid in understanding the present disclosure. No claim or determination is made as to whether any of the above is applicable as prior art related to the present disclosure.

[0004] A display is described. The display may include a gate driver circuit. The display may include a display driving integrated circuit (IC). The display may include a display panel including pixels. Each of the pixels may include sub-pixels. Each of the sub-pixels may include a light-emitting element; a storage capacitor configured to store a data voltage; and a transistor having a gate electrode connected to the storage capacitor, a source electrode, and a drain electrode connectable to an anode electrode of the light-emitting element, the transistor being configured to generate a current to be provided to the light-emitting element according to the data voltage stored in the storage capacitor. The display driving IC may be configured to transmit a clock signal for generating a scan signal to the gate driver circuit within an active period of a vertical synchronization signal that transmits a scan signal to the gate electrode of the transistor using the gate driver circuit. The display driving IC may be configured to stop transmitting the clock signal for generating the scan signal to the gate driver circuit within a porch period of the vertical synchronization signal that refrain from transmitting the scan signal to the gate electrode of the transistor using the gate driver circuit.

[0005] The display may include a gate driver circuit. The display may include a display driving integrated circuit (IC). The display may include a display panel including pixels. Each of the pixels may include sub-pixels. Each of the sub-pixels may include a light-emitting element; a storage capacitor configured to store a data voltage; and a transistor configured to generate a current to be provided to the light-emitting element according to the data voltage stored in the storage capacitor, the transistor including a gate electrode connected to the storage capacitor, a source electrode, and a drain electrode connectable to an anode electrode of the light-emitting element. The display driving IC may be configured to transmit first pulse signals to the gate driver circuit within an active period of a vertical synchronization signal that transmits a scan signal to the gate electrode of the transistor using the gate driver circuit. Each of the first pulse signals may have a first pulse width. The display driving IC may be configured to transmit a second pulse signal having a second pulse width greater than the first pulse width to the gate driver circuit within a porch period of the vertical synchronization signal that refrain from transmitting the scan signal to the gate electrode of the transistor using the gate driver circuit. A length of the first pulse width may be shorter than a length of the active period of the vertical synchronization signal. A length of the second pulse width may be longer than or equal to a length of the porch period of the vertical synchronization signal.

[0006] The display may be incorporated into an electronic device. For example, the electronic device may be described as a portable device, a multi-function device, or a mobile device. For example, the electronic device may include at least one processor (e.g., including a processing circuit) and a memory that stores instructions and includes one or more storage media. The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to generate an image to be displayed on the display panel and provide the generated image to the display driver IC.

[0007] Figures 1a and 1b illustrate examples of a method for controlling transmission of a clock signal within a porch period of a vertical synchronization signal.

[0008] Figure 2a illustrates an example of a simplified block diagram of an electronic device.

[0009] Figure 2b illustrates an example of a clock signal between a display driver IC (integrated circuitry) and a gate driver circuit, and a scan signal between the gate driver circuit and a display panel.

[0010] FIG. 2c illustrates an example of a method for identifying a porch section of a vertical synchronization signal using a signal obtained from a source driver circuit and controlling transmission of a clock signal within the porch section using a gate driver circuit.

[0011] Figure 3 illustrates an example of a subpixel within a display panel.

[0012] FIG. 4 illustrates an example of a method for controlling transmission of a clock signal within a porch interval of a vertical synchronization signal having an adjusted length.

[0013] FIG. 5 illustrates an example of a method for controlling transmission of a clock signal within a porch period of a vertical synchronization signal and an active period of another vertical synchronization signal.

[0014] Figure 6 illustrates an example of a method for adjusting the clock frequency of a clock signal transmitted within a porch period of a vertical synchronization signal.

[0015] Figure 7 illustrates examples of images to be displayed through a display panel of an electronic device in a low power mode.

[0016] FIGS. 8A to 8C illustrate examples of a method for transmitting a clock signal having a clock frequency according to an image to be displayed through a display panel.

[0017] FIG. 9 illustrates an example of a graph showing changes in current consumption as transmission of a clock signal is controlled within a porch period of a vertical synchronization signal.

[0018] FIG. 10 is a block diagram of an electronic device within a network environment according to various embodiments.

[0019] FIG. 11 is a block diagram of a display module according to various embodiments.

[0020] The terms used in this disclosure are used only to describe specific embodiments and may not be intended to limit the scope of other embodiments. The singular expression may include plural expressions unless the context clearly indicates otherwise. Terms used herein, including technical or scientific terms, may have the same meaning as commonly understood by those of ordinary skill in the art described in this disclosure. Terms defined in general dictionaries among the terms used in this disclosure may be interpreted as having the same or similar meaning in the context of the relevant technology, and shall not be interpreted in an idealized or overly formal sense unless explicitly defined in this disclosure. In some cases, even if a term is defined in this disclosure, it cannot be interpreted to exclude embodiments of the present disclosure.

[0021] The various embodiments of the present disclosure described below illustrate a hardware-based approach as an example. However, since the various embodiments of the present disclosure include techniques utilizing both hardware and software, the various embodiments of the present disclosure do not exclude a software-based approach.

[0022] In addition, in the present disclosure, expressions such as "more than" or "less than" may be used to determine whether a specific condition is satisfied or fulfilled. However, this is merely a description for expressing an example and does not exclude descriptions such as "more than" or "less than." Conditions described as "more than" may be replaced with "more than," conditions described as "less than," and conditions described as "more than and less than" may be replaced with "more than and less than." In addition, hereinafter, "A" to "B" mean at least one of the elements from A (including A) to B (including B).

[0023] An electronic device according to the present disclosure may include a display. For example, the display may include at least a portion of the display module (1060) of FIG. 10 or correspond to at least a portion of the display module (1060) of FIG. 10. For example, the display may be described as a display device. For example, the display may be included in the electronic device. For example, the electronic device including the display may include at least a portion of the electronic device (1001) of FIG. 10 or correspond to at least a portion of the electronic device (1001) of FIG. 10. Alternatively, for example, the electronic device including the display may include an electronic device (1002) connected to the electronic device (1001) of FIG. 10.

[0024] For example, an electronic device according to the present disclosure may be implemented in various form factors. For example, the electronic device may include a wearable device in the shape of a watch. However, the present disclosure is not limited thereto. For example, the electronic device may include not only an electronic device including the display of the bar type, but also an electronic device including the display that is a flexible display. For example, the flexible display may include a rollable display, a foldable display, or a multi-foldable display. Furthermore, for example, the electronic device may include a head mounted display (HMD). However, the present disclosure is not limited thereto.

[0025] For example, an electronic device according to the present disclosure may include at least one processor (e.g., including a processing circuit) (e.g., including a central processing unit (CPU), a graphic processing unit (GPU), and a display processing unit (DPU)). For example, the at least one processor may include at least a portion of, or correspond to at least a portion of, the processor (1020) of FIG. 10. For example, the electronic device may include a memory that includes one or more storage media and stores instructions. The memory may include at least a portion of, or correspond to at least a portion of, the memory (1030) of FIG. 10. The instructions, when individually or collectively executed by the at least one processor, may cause the electronic device to generate or acquire an image to be displayed through the display. The above instructions, when executed individually or collectively by at least one processor, may provide data for the image to the display (or the display driver IC (DDI) (1130), the display driving IC (1130) of FIG. 11) to display the image through the display. As a non-limiting example, at least some of the components included in the electronic device according to the present disclosure are described and illustrated with reference to FIG. 2A below.

[0026] The display may include a display driving IC and a display panel. The display driving IC may be referred to as a display driving circuit, a control circuit, or a DDI. For example, the display driving IC may include at least a portion of the DDI (1130) of FIG. 11 or correspond to at least a portion of the DDI (1130) of FIG. 11. For example, the display panel may include at least a portion of the display panel (1110) of FIG. 11 or correspond to at least a portion of the display panel (1110) of FIG. 11. For example, the display driving IC may be used to display an image (e.g., an image provided from the at least one processor) on the display panel. The display driving IC is described and exemplified with reference to FIGS. 2A to 2C below.

[0027] For example, the display panel may include pixels. Each of the pixels may include sub-pixels. The sub-pixels may include a first sub-pixel configured to emit light of a first color (e.g., red), a second sub-pixel configured to emit light of a second color (e.g., blue), and a third sub-pixel configured to emit light of a third color (e.g., green). As a non-limiting example, the sub-pixels may further include a fourth sub-pixel configured to emit light of a fourth color (e.g., white).

[0028] For example, each of the sub-pixels may include a light-emitting element (e.g., an organic light-emitting diode (OLED)) and a transistor (or a driving transistor (e.g., the first transistor (301) of FIG. 3) for providing current to the light-emitting element (or obtaining current provided to the light-emitting element). For example, each of the sub-pixels may include an operation control transistor (e.g., the fifth transistor (305) of FIG. 3) including a drain electrode electrically connected to a source electrode of the driving transistor and a source electrode electrically connected to a driving voltage line for transmitting a driving voltage (VDD). For example, each of the sub-pixels may include an emission control transistor (e.g., the sixth transistor (306) of FIG. 3) including a source electrode electrically connected to a drain electrode of the driving transistor and a drain electrode electrically connected to an anode electrode of the light-emitting element. For example, the display driving IC may provide an emission signal to each of the gate electrodes of the operation control transistor and the gate electrode of the emission control transistor. When the above-described light-emitting signal is provided to each of the gate electrode of the operation control transistor and the gate electrode of the light-emitting control transistor, the current obtained through the driving transistor can be provided to the light-emitting element. For example, the light-emitting element can emit light according to the current.

[0029] As a non-limiting example, each of the sub-pixels may further include, in addition to the driving transistor, the operation control transistor, and the light emission control transistor exemplified above, one or more other transistors and one or more capacitors. An example configuration of each of the sub-pixels is described and illustrated with reference to FIG. 3 below.

[0030] The display driving IC may perform (or execute) a first scan to display the image on the display panel. For example, the first scan may be described as an address scan. For example, the first scan may include initiating a gate electrode of the driving transistor, providing a data voltage to the initialized gate electrode of the driving transistor, and providing current to the light emitting element through the driving transistor having the provided data voltage at the gate electrode. For example, the first scan may further include initializing the gate electrode of the driving transistor by providing an initialization voltage to the gate electrode of the driving transistor, and providing a data voltage to the initialized gate electrode of the driving transistor, compared to the second scan exemplified below. For example, the first scan may represent a time interval (or frame) of a vertical synchronization signal in which data (or data voltage) is refreshed.

[0031] The display driving IC may perform (or execute) a second scan to maintain the image on the display panel. For example, the second scan may be described as a self-scan. For example, the second scan may include providing current to the light-emitting element through the driving transistor while the data voltage provided to the gate electrode of the driving transistor according to the first scan is maintained. For example, the second scan may include skipping initializing the gate electrode of the driving transistor to maintain the data voltage provided to the gate electrode of the driving transistor according to the first scan. For example, unlike the first scan, the second scan may not include initializing the gate electrode of the driving transistor and providing a data voltage to the initialized gate electrode of the driving transistor. For example, unlike the second scan, the second scan may represent a time interval (or frame) of a vertical synchronization signal during which data (or data voltage) is blanked.

[0032] Figures 1a and 1b illustrate examples of a method for controlling transmission of a clock signal within a porch period of a vertical synchronization signal.

[0033] Fig. 1a illustrates an example (100) of controlling transmission of a clock signal in response to a time interval of a vertical synchronization signal. Example (100) illustrates a state (110) of the display panel. With respect to the state (110) of the display panel, a time interval (101) of a first vertical synchronization signal, a time interval (102) of a second vertical synchronization signal following the first vertical synchronization signal, and a time interval (103) of a third vertical synchronization signal following the second vertical synchronization signal are illustrated.

[0034] For example, each of the time intervals (101, 102, 103) can be defined from a time (or timing, point in time) at which a vertical synchronization signal is provided (or triggered). For example, referring to a state (111) of a vertical synchronization signal, a vertical synchronization signal can be provided (or generated, transmitted). For example, referring to a state (111) of a vertical synchronization signal, a vertical synchronization signal (111-1) (or the first vertical synchronization signal) and a vertical synchronization signal (111-2) (or the second vertical synchronization signal) can be provided. For example, the time interval (101) can start from a time at which the vertical synchronization signal (111-1) is provided. For example, the time interval (102) can start from a time at which the vertical synchronization signal (111-2) is provided. For example, a TE (tearing effect) signal can be synchronized with respect to the vertical synchronization signal. For example, referring to the state (112) of the TE signal, the TE signal may be provided (or transmitted) from the display driving IC to the at least one processor at the time when the vertical synchronization signal (111-1) is provided and at the time when the vertical synchronization signal (111-2) is provided. In addition, for example, an FLM (frame line mark) signal may also be synchronized with the vertical synchronization signal. For example, referring to the state (130) of the FLM signal, the FLM signal (131) and the FLM signal (132) corresponding to the time when the vertical synchronization signal (111-1) is provided and the time when the vertical synchronization signal (111-2) is provided, respectively, may be transmitted from the display driving IC to the gate driver circuit (e.g., the gate driver (239) of FIG. 2A).

[0035] In the example (100) of Fig. 1a, three vertical synchronization signals are illustrated for convenience of explanation, but the present disclosure is not limited thereto. For example, within the time interval (101) of the first vertical synchronization signal, the display driving IC can perform (or execute) the first scan (or address scan). For example, within the time interval (102) of the second vertical synchronization signal, the display driving IC can perform (or execute) the second scan (or self-scan). For example, within the time interval (103) of the third vertical synchronization signal, the display driving IC can perform (or execute) the second scan (or self-scan).

[0036] For example, each of the time intervals (101, 102, 103) of the vertical synchronization signal may include an active interval and a porch interval. For example, the active interval may include a interval in which an image is displayed through the display panel. As a non-limiting example, the active interval may be described as a interval in which a data voltage (or data) for displaying the image is applied to the display panel (or subpixels of the display panel). For example, the porch interval may include a interval in which an image is not displayed through the display panel. As a non-limiting example, the porch interval may be described as a interval in which the data voltage (or data) for displaying the image is stopped from being applied to the display panel (or subpixels of the display panel). For example, the porch interval may include a vertical front porch (VFP) and / or a vertical back porch (VBP).

[0037] As a non-limiting example, the electronic device of Example (100) may be in a low power mode. For example, the electronic device in the low power mode may display an image through the display panel according to a refresh rate of the display panel. In this case, the refresh rate may indicate the number of times the image is displayed per unit time (e.g., 1 second). For example, if the refresh rate is N, in the low power mode, the display driver IC may perform the first scan once and the second scan M times, which is a natural number exceeding 1. In this case, N may be defined as M+1. In one example, the electronic device may execute (or enter) the low power mode in order to display a relatively unchanging image (or a still image). In this case, while displaying the still image, the electronic device may operate in the low power mode, thereby reducing power consumption of the display driver IC.

[0038] In the present disclosure, the low-power mode (or low-power state) may refer to a state in which a processor (e.g., the processor (220) of FIG. 2A) is in a sleep state at least for a portion of the time while an image is displayed on a display panel (e.g., the display panel (210) of FIG. 2A). However, the present disclosure is not limited thereto. For example, within the low-power mode, the processor may be in an active state. For example, the low-power mode may be referred to as low frequency driving (LFD). For example, within the low-power mode, a screen for the low-power (e.g., an always-on display (AOD) screen) may be displayed. However, the present disclosure is not limited thereto.

[0039] For example, a time interval (101) may include an active interval (101a) and a porch interval (101b). A time interval (102) may include an active interval (102a) and a porch interval (102b). A time interval (103) may include an active interval (103a) and a porch interval (103b). Within the active interval (101a) of the time interval (101) in which the first scan is performed, data may be provided via MIPI (mobile industry processor interface). For example, the data may be provided from the at least one processor to the display driving IC within the active interval (101a) via MIPI. Referring to the state (113) of MIPI, the data may be provided from the at least one processor to the display driving IC within the active interval (101a). As the above data is provided, the source driver (or source driver circuit) can generate a data voltage and provide (or apply, transmit) the data voltage to the display panel (or each of the sub-pixels of the display panel). Referring to the state (114) of the source driver, within the active period (102a) (or active period (103a)) of the time period (102) (or time period (103)) in which the second scan is performed, a reference voltage having a fixed voltage level can be provided (or applied, transmitted).

[0040] Referring to Example (100), the display driving IC may provide (or transmit) clock signals to a gate driver (or gate driver circuit) to generate a signal (or scan signal) used for scanning (e.g., the first scan or the second scan) in the display panel. In Example (100), for convenience of explanation, a GW clock signal, a GB clock signal, a GW_o clock signal, and an EM clock signal are exemplified, but the present disclosure is not limited thereto. For example, the clock signals may further include a GI (global initial) clock signal.

[0041] For example, the GW clock signal can be used to generate a GW scan signal (e.g., the fourth signal (314) of FIG. 3). For example, the GB clock signal can be used to generate a GB scan signal (e.g., the third signal (313) of FIG. 3). For example, the GW_o clock signal can be used to generate a GW_o scan signal (e.g., the second signal (312) of FIG. 3). For example, the EM clock signal can be used to generate an EM scan signal (e.g., the emission signal (315) of FIG. 3). For example, the GI clock signal can be used to generate a GI scan signal (e.g., the first signal (311) of FIG. 3).

[0042] Referring to example (100), each of the clock signals can be synchronized with respect to the vertical synchronization signal. For example, the clock signals can start to be provided (or transmitted) or can start to cease being provided (or transmitted) from the time the vertical synchronization signal (111-1) is provided and the time the vertical synchronization signal (111-2) is provided.

[0043] In the present disclosure, the transmission of a clock signal within a specific time interval may indicate that the clock signal is toggled (or that a clock operation of a vertical porch signal is performed) within the specific time interval. For example, the toggling of the clock signal may indicate that the state (or voltage level) of the clock signal transmitted (or provided) from the display driving IC to the gate driver (or gate driver circuit) is repeatedly changed. In other words, the toggling of the clock signal may indicate that the state (or voltage level) of the clock signal is repeatedly changed from the second state (or second level) to the first state (or first level), and then changed back to the second state. For example, a GW clock signal may be transmitted as it is changed from the first state to the second state, and then changed back to the first state from the second state. For example, the GW_o clock signal may be transmitted as the second state changes to the first state, and then changes from the first state back to the second state. However, the present disclosure is not limited thereto. For example, the GW_o clock signal may also be transmitted as the first state changes to the second state, and then changes from the second state back to the first state.

[0044] In the above example, while the clock signal is toggled, the state of the clock signal is described as changing from the second state to the first state and then back to the second state, but the present disclosure is not limited thereto. For example, while the clock signal is toggled, the state of the clock signal may change from the first state to the second state and then back to the first state. For example, the clock signal being toggled once may indicate that the state of the clock signal is changed from the second state to the first state, and then back to the second state. A clock signal that has been toggled once may be referred to as a pulse signal. For example, a clock signal that has been toggled multiple times may include multiple pulse signals. For example, the clock frequency of the clock signal within the specific time interval may indicate the number of times (or toggle count) that the clock signal toggles within the specific time interval.

[0045] In the present disclosure, within a specific time interval, the interruption of transmission of a clock signal may indicate that the clock signal stops toggling (or, toggling is turned off, a clock operation of the clock signal is not performed) within the specific time interval. For example, the toggling of the clock signal may indicate that the state of the clock signal transmitted (or provided) from the display driving IC to the gate driver (or gate driver circuit) is maintained in a specific state. For example, the specific state may be preset for the clock signal. In other words, the interruption of toggling of the clock signal within the specific time interval may indicate that the state of the clock signal is maintained in the second state or the first state.

[0046] Referring to the state (121) of the GW clock signal of example (100), within the time period (101) of the vertical synchronization signal (111-1), the vertical synchronization signal (111-1) may be transmitted from the display driving IC to the gate driver (or gate driver circuit). For example, within the time period (101) including an active period (101a) and a porch period (101b), a clock signal (141-1), which is a GW clock signal, may be transmitted. For example, within the time period (101) including an active period (101a) and a porch period (101b), as the clock signal (141-1) is transmitted to the gate driver, the gate driver circuit may transmit a GW scan signal to the display panel.

[0047] In addition, referring to the state (121) of the GW clock signal of example (100), within the time period (102) of the vertical synchronization signal (111-2), transmission from the display driving IC to the gate driver (or gate driver circuit) may be stopped (or, stopped, paused, skipped, bypassed, prevented). For example, within the active period (102a) and the porch period (102b) of the time period (102) (and the active period (103a) and the porch period (103b) of the time period (103), transmission of the GW clock signal may be stopped. While transmission of the GW clock signal is stopped, the state of the GW clock signal (voltage level of the GW clock signal) may have (or be maintained) the first state (141-2) (or the first level). For example, the first state (141-2) (or first level) may be referred to as a direct current (DC) high (or high state). For example, within the active period (102a) and the porch period (102b) of the time period (102) (and the active period (103a) and the porch period (103b) of the time period (103), as transmission of the GW clock signal to the gate driver is interrupted, the gate driver circuit may refrain from (or, cease, stop, pause, skip, bypass, prevent) transmitting the GW scan signal to the display panel.

[0048] Referring to the state (122) of the GB clock signal of example (100), the vertical synchronization signal (111-1) may be transmitted from the display driving IC to the gate driver (or gate driver circuit) within time intervals (101, 102, 103) from the time at which it is provided. For example, within time intervals (101, 102, 103), a clock signal (142), which is a GB clock signal, may be transmitted. For example, as the clock signal (142) is transmitted to the gate driver within time intervals (101, 102, 103), the gate driver circuit may transmit a GB scan signal to the display panel.

[0049] Referring to the state (123) of the GW_o clock signal of example (100), within the time period (101) of the vertical synchronization signal (111-1), the vertical synchronization signal (111-1) may be transmitted from the display driving IC to the gate driver (or gate driver circuit). For example, within the time period (101) including an active period (101a) and a porch period (101b), the clock signal (143-1), which is a GW_o clock signal, may be transmitted. For example, within the time period (101) including an active period (101a) and a porch period (101b), as the clock signal (143-1) is transmitted to the gate driver, the gate driver circuit may transmit a GW_o scan signal to the display panel.

[0050] Also, referring to the state (123) of the GW_o clock signal of example (100), within the time period (102) of the vertical synchronization signal (111-2), transmission from the display driving IC to the gate driver (or gate driver circuit) may be stopped (or, stopped, paused, skipped, bypassed, prevented). For example, within the active period (102a) and the porch period (102b) of the time period (102) (and the active period (103a) and the porch period (103b) of the time period (103), transmission of the GW_o clock signal may be stopped. While transmission of the GW_o clock signal is stopped, the state of the GW_o clock signal (voltage level of the GW_o clock signal) may have (or be maintained) a second state (143-2) (or a second level). For example, the second state (143-2) (or second level) may be referred to as a direct current (DC) low (or low state). For example, within the active period (102a) and the porch period (102b) of the time period (102) (and the active period (103a) and the porch period (103b) of the time period (103)), as transmission of the GW_o clock signal to the gate driver is stopped, the gate driver circuit may refrain from transmitting the GW_o scan signal to the display panel.

[0051] Referring to the state (124) of the EM clock signal of example (100), the vertical synchronization signal (111-1) may be transmitted from the display driving IC to the gate driver (or gate driver circuit) within time intervals (101, 102, 103) from the time at which it is provided. For example, within the time intervals (101, 102, 103), the clock signal (144), which is an EM clock signal, may be transmitted. For example, within the time interval (101) including the active interval (101a) and the porch interval (101b), as the clock signal (144) is transmitted to the gate driver, the gate driver circuit may transmit a light emission signal (or, EM scan signal) to the display panel.

[0052] As described above, in example (100), clock signals can be controlled in response to the time at which the vertical synchronization signal (111-1) is provided or the time at which the vertical synchronization signal (111-2) is provided. For example, clock signals can be transmitted or transmission can be stopped by being synchronized with the vertical synchronization signal. At this time, some of the clock signals (e.g., the GW clock signal and the GW_o clock signal) may not be transmitted from the time period (102) during which the second scan is performed because scan signals (e.g., the GW scan signal and the GW_o scan signal) according to some of the clock signals are not used for the second scan. In other words, the electronic device (or the display driver IC) can control the clock operation (or toggle) of some of the clock signals within the time period (e.g., the time period (102) and / or the time period (103)) during which the second scan is performed in order to reduce power consumption within the low-power mode.

[0053] As a non-limiting example, within the low power mode, the length of the porch interval (e.g., porch interval (101b), porch interval (102b), porch interval (103b)) may be adjusted to adjust the refresh rate (or base frequency) of the display panel. For example, to lower the refresh rate, the length of the porch interval may be lengthened. When the refresh rate is lowered, the length of the porch interval may be lengthened, and the number of time intervals for performing the second scan may be reduced. For example, when the refresh rate is 60 Hz, the first scan may be performed once, and the second scan may be performed 59 times. Alternatively, when the refresh rate is 40 Hz, the first scan may be performed once, and the second scan may be performed 39 times. For the same unit time, the length of the pouch section may be increased as the number of full scans (the first scan and the second scan) decreases (e.g., from 60 to 40). In the example (100) of Fig. 1a and the example (105) of Fig. 1b, it is assumed that the refresh rate (or base frequency) of the display panel is 40 Hz.

[0054] In the above example, in order to reduce power consumption, the refresh rate (or base frequency) of the display panel may be lowered within the low-power mode. When the refresh rate is lowered, the length of the porch period of the vertical synchronization signal may be increased. Within the porch period, since actual display of an image is not performed, performing a scan may be unnecessary. In other words, transmission of a clock signal may be unnecessary within the porch period in which actual display of an image is not performed. Transmission of a clock signal (or clock operation of a clock signal, toggle of a clock signal) may be unnecessary within the porch period. However, referring to the example (100) of FIG. 1A, the clock operation (or toggle) of the clock signals may be maintained within the porch period (e.g., porch period (101b), porch period (102b), porch period (103b)). For example, the clock operation (or toggle) of the clock signal may be referred to as transmission of a clock signal (e.g., clock signal (141-1)) including a plurality of pulse signals (or toggled signals). Since the transmission of the clock signals is controlled in synchronization with respect to the vertical synchronization signal, the transmission of the clock signal within the porch period may not be controlled (or, the transmission of the clock signal within the porch period may be maintained continuously from the active period).

[0055] As described above, when lowering the refresh rate to reduce power consumption within the low-power mode, the length of the porch interval increases, which may result in unnecessary clock signal toggling for a longer period of time. Consequently, the power consumption reduction effect may be reduced.

[0056] Unlike FIG. 1A, FIG. 1B illustrates a method in which an electronic device controls the transmission of a clock signal (or clock operation, toggle) not only for a time period of a vertical synchronization signal (or a start time of a vertical synchronization signal, a start time of an active period of a vertical synchronization signal) but also for a start time of a porch period of a vertical synchronization signal. The electronic device and method according to the present disclosure can increase the effect of reducing power consumption by controlling the transmission of the clock signal in synchronization with not only the start time of the vertical synchronization signal but also the start time of the porch period.

[0057] FIG. 1B illustrates an example (105) of controlling transmission of a clock signal in response to a time interval of a vertical synchronization signal and a start time of a porch interval of the vertical synchronization signal. For example, the time interval of the vertical synchronization signal may be referred to as a start time of the vertical synchronization signal or a start time of an active interval of the vertical synchronization signal.

[0058] In FIGS. 1A and 1B, the same reference numerals may be used for the same description. For example, the state (110) of the display panel in the example (105) of FIG. 1B may be substantially identically applied to the state (110) of the display panel in FIG. 1A. In addition, for example, the states (121, 122, 123, 124) of the clock signals in the example (105) of FIG. 1B may be substantially identically applied to the states (121, 122, 123, 124) of the clock signals in the example (100) of FIG. 1B. In FIG. 1B below, content that is substantially identical to the content described in FIG. 1A is omitted for convenience of description.

[0059] Referring to Example (105), the display driving IC may provide (or transmit) clock signals to a gate driver (or gate driver circuit) to generate a signal (or scan signal) used for scanning (e.g., the first scan or the second scan) in the display panel. In Example (105), for convenience of explanation, a GW clock signal, a GB clock signal, a GW_o clock signal, and an EM clock signal are exemplified, but the present disclosure is not limited thereto. For example, the clock signals may further include a GI clock signal.

[0060] Referring to example (105), each of the clock signals can be synchronized with respect to the vertical synchronization signal. For example, the display driving IC can start transmitting, or stop providing (or transmitting) the clock signals at the time when the vertical synchronization signal (111-1) is provided.

[0061] Referring to the state (121) of the GW clock signal of example (105), the GW clock signal can be transmitted from the display driving IC to the gate driver (or gate driver circuit) within the active period (101a). For example, within the active period (101a), a clock signal (161-1), which is a GW clock signal, can be transmitted. For example, as the clock signal (161-1) is transmitted to the gate driver within the active period (101a), the gate driver circuit can transmit a GW scan signal to the display panel.

[0062] Referring to the state (122) of the GB clock signal of example (105), the GB clock signal can be transmitted from the display driving IC to the gate driver (or gate driver circuit) within the active period (101a). For example, within the active period (101a), the clock signal (162-1), which is a GB clock signal, can be transmitted. For example, as the clock signal (162-1) is transmitted to the gate driver within the active period (101a), the gate driver circuit can transmit a GB scan signal to the display panel.

[0063] Referring to the state (123) of the GW_o clock signal of example (105), the GW_o clock signal can be transmitted from the display driving IC to the gate driver (or gate driver circuit) within the active period (101a). For example, within the active period (101a), the clock signal (163-1), which is a GW_o clock signal, can be transmitted. For example, as the clock signal (163-1) is transmitted to the gate driver within the active period (101a), the gate driver circuit can transmit a GW_o scan signal to the display panel.

[0064] Referring to the state (124) of the EM clock signal of example (105), the EM clock signal can be transmitted from the display driving IC to the gate driver (or gate driver circuit) within the active period (101a). For example, within the active period (101a), the clock signal (164-1), which is an EM clock signal, can be transmitted. For example, as the clock signal (164-1) is transmitted to the gate driver within the active period (101a), the gate driver circuit can transmit a light emission signal (or, EM scan signal) to the display panel.

[0065] Example (105) of FIG. 1B illustrates a state (170) of a vertical porch signal. For example, the state (170) of the vertical porch signal may be changed to indicate a porch period. For example, when the state (170) of the vertical porch signal changes from the second state to the first state, it may indicate that a porch period has started. The state (170) of the vertical porch signal changing from the second state to the first state and then changing from the first state back to the second state may indicate that the vertical porch signal is being transmitted (or, that the vertical porch signal is toggled, or that the clock operation of the vertical porch signal is being performed). In example (105), the state (170) of the vertical porch signal is merely exemplary, and the present disclosure is not limited thereto. For example, the state (170) of the vertical porch signal may be changed from the first state to the second state, and then changed from the second state back to the first state to indicate that a porch section has begun.

[0066] Referring to example (105), the display driving IC can identify the porch period (101b) based on acquiring (or receiving, identifying) the vertical porch signal (171). For example, the display driving IC can acquire the vertical porch signal (171) for indicating the porch period (101b) from a source driver (or source driver circuit). For example, the display driving IC can control transmission of a clock signal within the porch period (101b). For example, the display driving IC can provide (or transmit) some clock signals to a gate driver (or gate driver circuit) to generate a signal (or scan signal) used for scanning (e.g., the first scan or the second scan) in the display panel, and can stop transmission of other some clock signals.

[0067] Referring to Example (105), unlike Example (100) of FIG. 1A, each of the clock signals can be synchronized with respect to the vertical porch signal. For example, the display driver IC can start transmitting, or stop providing (or transmitting), the clock signals at the time when the vertical porch signal (171) is provided.

[0068] Referring to the state (121) of the GW clock signal of example (105), the GW clock signal may be stopped from being transmitted from the display driving IC to the gate driver (or gate driver circuit) within the porch period (101b). For example, the state (121) of the GW clock signal may be maintained at a first level (161-2) within the porch period (101b). For example, the state (121) of the GW clock signal being maintained at the first level (161-2) within the porch period (101b) may indicate that the transmission of the GW clock signal from the display driving IC to the gate driver is stopped. For example, as the transmission of the GW clock signal to the gate driver is stopped within the porch period (101b) of the time period (101), the gate driver circuit may refrain from transmitting a GW scan signal to the display panel.

[0069] Referring to the state (122) of the GB clock signal of example (105), the GB clock signal may be stopped from being transmitted from the display driving IC to the gate driver (or gate driver circuit) within the porch period (101b). For example, the state (122) of the GB clock signal may be maintained at a first level (162-2) within the porch period (101b). For example, the state (122) of the GB clock signal being maintained at the first level (162-2) within the porch period (101b) may indicate that the transmission of the GB clock signal from the display driving IC to the gate driver is stopped. For example, as the transmission of the GB clock signal to the gate driver is stopped within the porch period (101b) of the time period (101), the gate driver circuit may refrain from transmitting a GB scan signal to the display panel.

[0070] Referring to the state (123) of the GW_o clock signal of example (105), the GW_o clock signal may be stopped from being transmitted from the display driving IC to the gate driver (or gate driver circuit) within the porch period (101b). For example, the state (123) of the GW_o clock signal may be maintained at the second level (163-2) within the porch period (101b). For example, the state (123) of the GW_o clock signal being maintained at the second level (163-2) within the porch period (101b) may indicate that the transmission of the GW_o clock signal from the display driving IC to the gate driver is stopped. For example, within the porch section (101b) of the time section (101), as transmission of the GW_o clock signal to the gate driver is stopped, the gate driver circuit may refrain from transmitting the GW_o scan signal to the display panel.

[0071] Referring to the state (124) of the EM clock signal of example (105), the EM clock signal may be stopped from being transmitted from the display driving IC to the gate driver (or gate driver circuit) within the porch period (101b). For example, the state (124) of the EM clock signal may be maintained at a first level (164-2) within the porch period (101b). For example, the state (124) of the EM clock signal being maintained at the first level (164-2) within the porch period (101b) may indicate that the transmission of the EM clock signal from the display driving IC to the gate driver is stopped. For example, as the transmission of the EM clock signal to the gate driver is stopped within the porch period (101b) of the time period (101), the gate driver circuit may refrain from transmitting a light emission signal (or an EM scan signal) to the display panel.

[0072] Additionally, referring to example (105), each of the clock signals may be synchronized with respect to a vertical synchronization signal. For example, the display driving IC may start transmitting, or may stop providing (or transmitting) the clock signals at the time when the vertical synchronization signal (111-2) is provided.

[0073] Referring to the state (121) of the GW clock signal in example (105), the GW clock signal may be stopped from being transmitted from the display driving IC to the gate driver (or gate driver circuit) within the active period (102a). In example (105), even within the active period (102a) extending to the porch period (101b), the state (121) of the GW clock signal may be maintained at the first level (161-2). For example, as the transmission of the GW clock signal to the gate driver is stopped within the active period (102a) extending to the porch period (101b), the gate driver circuit may refrain from transmitting a GW scan signal to the display panel.

[0074] Referring to the state (122) of the GB clock signal of example (105), the GB clock signal can be transmitted from the display driving IC to the gate driver (or gate driver circuit) within the active period (102a). For example, unlike the porch period (101b), the clock signal (162-3), which is a GB clock signal, can be transmitted within the active period (102a). For example, as the clock signal (162-3) is transmitted to the gate driver within the active period (102a), the gate driver circuit can transmit a GB scan signal to the display panel.

[0075] Referring to the state (123) of the GW_o clock signal in example (105), the GW_o clock signal may be stopped from being transmitted from the display driving IC to the gate driver (or gate driver circuit) within the active period (102a). In example (105), even within the active period (102a) extending to the porch period (101b), the state (123) of the GW_o clock signal may be maintained at the second level (163-2). For example, as the transmission of the GW_o clock signal to the gate driver is stopped within the active period (102a) extending to the porch period (101b), the gate driver circuit may refrain from transmitting a GW_o scan signal to the display panel.

[0076] Referring to the state (124) of the EM clock signal of example (105), the EM clock signal can be transmitted from the display driving IC to the gate driver (or gate driver circuit) within the active period (102a). For example, unlike the porch period (101b), the clock signal (164-3), which is an EM clock signal, can be transmitted within the active period (102a). For example, as the clock signal (164-3) is transmitted to the gate driver within the active period (102a), the gate driver circuit can transmit a light emission signal (or, EM scan signal) to the display panel.

[0077] Also, referring to example (105), the display driving IC can identify the porch period (102b) based on acquiring (or receiving, identifying) the vertical porch signal (172). For example, the display driving IC can acquire the vertical porch signal (171) for indicating the porch period (102b) from a source driver (or source driver circuit). For example, the display driving IC can control transmission of a clock signal within the porch period (102b). For example, the display driving IC can provide (or transmit) some clock signals to a gate driver (or gate driver circuit) to generate a signal (or scan signal) used for scanning (e.g., the first scan or the second scan) in the display panel, and can stop transmission of other some clock signals.

[0078] For example, each of the clock signals may be synchronized with respect to the vertical porch signal. For example, the display driver IC may start transmitting, or stop providing (or transmitting) the clock signals at the time the vertical porch signal (172) is provided.

[0079] Referring to the state (121) of the GW clock signal of example (105), the GW clock signal may be stopped from being transmitted from the display driving IC to the gate driver (or gate driver circuit) within the porch period (102b). For example, within the porch period (102b) extending from the active period (102a), the state (121) of the GW clock signal may be maintained at a first level (161-2). For example, the state (121) of the GW clock signal being maintained at the first level (161-2) within the porch period (102b) may indicate that the transmission of the GW clock signal from the display driving IC to the gate driver is stopped. For example, as the transmission of the GW clock signal to the gate driver is stopped within the porch period (102b) of the time period (102), the gate driver circuit may refrain from transmitting a GW scan signal to the display panel.

[0080] Referring to the state (122) of the GB clock signal of example (105), the GB clock signal may be stopped from being transmitted from the display driving IC to the gate driver (or gate driver circuit) within the porch period (102b). For example, the state (122) of the GB clock signal may be maintained at a first level (162-4) within the porch period (102b). For example, the state (122) of the GB clock signal being maintained at the first level (162-4) within the porch period (102b) may indicate that the transmission of the GB clock signal from the display driving IC to the gate driver is stopped. For example, as the transmission of the GB clock signal to the gate driver is stopped within the porch period (102b) of the time period (102), the gate driver circuit may refrain from transmitting a GB scan signal to the display panel.

[0081] Referring to the state (123) of the GW_o clock signal of example (105), the GW_o clock signal may be stopped from being transmitted from the display driving IC to the gate driver (or gate driver circuit) within the porch period (102b). For example, within the porch period (102b) extending from the active period (102a), the state (123) of the GW_o clock signal may be maintained at the second level (163-2). For example, the state (123) of the GW_o clock signal being maintained at the second level (163-2) within the porch period (102b) may indicate that the transmission of the GW_o clock signal from the display driving IC to the gate driver is stopped. For example, within a porch period (102b) of a time period (102), as transmission of the GW_o clock signal to the gate driver is stopped, the gate driver circuit may refrain from transmitting the GW_o scan signal to the display panel.

[0082] Referring to the state (124) of the EM clock signal of example (105), the EM clock signal may be stopped from being transmitted from the display driving IC to the gate driver (or gate driver circuit) within the porch period (102b). For example, the state (124) of the EM clock signal may be maintained at a first level (164-4) within the porch period (102b). For example, the state (124) of the EM clock signal being maintained at the first level (164-4) within the porch period (102b) may indicate that the transmission of the EM clock signal from the display driving IC to the gate driver is stopped. For example, as the transmission of the EM clock signal to the gate driver is stopped within the porch period (102b) of the time period (102), the gate driver circuit may refrain from transmitting a light emission signal (or an EM scan signal) to the display panel.

[0083] In example (105), transmission of all clock signals (e.g., GW clock signal, GB clock signal, GW_o clock signal, EM clock signal) is exemplified as being stopped within the porch period, but the present disclosure is not limited thereto. For example, some of the clock signals may not be transmitted within the porch period. As a non-limiting example, in the case of the GW clock signal and / or the GW_o clock signal, even if transmission is stopped within the porch period, the display of the image and the driving of the display panel may be less affected. Therefore, in order to improve the effect of reducing power consumption, transmission of the GW clock signal and / or the GW_o clock signal may be stopped within the porch period. Unlike example (105) of FIG. 1B, the GB clock signal and / or the EM clock signal may also be transmitted within the porch period.

[0084] In the example (100) of Fig. 1a, a clock signal (e.g., a GW clock signal, a GB clock signal, a GW_o clock signal, an EM clock signal, a GI clock signal) may be transmitted from the display driving IC to the gate driver circuit within the active period. Within the active period, the gate driver circuit may generate a scan signal (e.g., a GW scan signal, a GB scan signal, a GW_o scan signal, an EM scan signal, a GI scan signal) using the clock signal, and transmit the scan signal to the display panel. In the example (100) of Fig. 1a, a clock signal may be transmitted from the display driving IC to the gate driver circuit within the porch period. Within the porch period, the gate driver circuit may not generate a scan signal using the clock signal. The number of blocks in the gate driver circuit (e.g., blocks (265, 266, 267, 268) of FIG. 2b) corresponds to the number of lines of the display panel, so that even if the clock signal is received, no additional scan signal may be generated.

[0085] In the example (105) of Fig. 1b, similar to the example (100) of Fig. 1a, a clock signal (e.g., a GW clock signal, a GB clock signal, a GW_o clock signal, an EM clock signal, a GI clock signal) may be transmitted from the display driver IC to the gate driver circuit within the active period. Within the active period, the gate driver circuit may generate a scan signal (e.g., a GW scan signal, a GB scan signal, a GW_o scan signal, an EM scan signal, a GI scan signal) using the clock signal and transmit the scan signal to the display panel. In the example (105) of Fig. 1b, unlike the example (100) of Fig. 1a, a clock signal may not be transmitted from the display driver IC to the gate driver circuit within the porch period. The display driver IC may stop transmitting the clock signal to the gate driver circuit. Accordingly, the gate driver circuit may not generate a scan signal within the porch period.

[0086] In the example (105) of FIG. 1b, the display driver IC is illustrated as stopping transmission of the clock signal to the gate driver circuit within a porch period, but the present disclosure is not limited thereto. The display driver IC may perform transmission of the clock signal to the gate driver circuit within some porch periods, and stop transmission of the clock signal to the gate driver circuit within other porch periods. For example, the display driver IC may perform transmission of the clock signal to the gate driver circuit within a porch period (101b), stop transmission of the clock signal to the gate driver circuit within a porch period (102b), and perform transmission of the clock signal to the gate driver circuit within a porch period (103b). Alternatively, for example, the display driving IC may transmit the clock signal to the gate driver circuit within the porch section (101b) and the porch section (102b), and stop transmitting the clock signal to the gate driver circuit within the porch section (103b).

[0087] For example, as the refresh rate (or base frequency) of the display panel or the driving frequency of the display driver IC changes from a higher frequency to a lower frequency, the number of porch periods (or length of porch periods) during which the display driver IC stops transmitting the clock signal to the gate driver circuit may increase. Additionally, as the battery level of the electronic device including the display driver IC decreases, the number of porch periods (or length of porch periods) during which the display driver IC stops transmitting the clock signal to the gate driver circuit may increase. Additionally, when the electronic device (or the display driving IC) changes the mode of the electronic device to a mode for low power consumption (e.g., power saving mode or ultra power saving mode), the display driving IC may stop transmitting the clock signal to the gate driver circuit within all porch periods, or increase the number of porch periods during which transmission of the clock signal to the gate driver circuit is stopped.

[0088] Referring to FIGS. 1A and 1B , the electronic device and method according to the present disclosure can control the transmission of a clock signal (or clock operation, toggle) not only for the time interval of a vertical synchronization signal (or the start time of the vertical synchronization signal, the start time of the active interval of the vertical synchronization signal) but also for the start time of the porch interval of the vertical synchronization signal. In other words, the electronic device and method according to the present disclosure can control the transmission of a clock signal not only in units of frames, but also by segmenting it into units of active intervals and units of porch intervals within a frame. Accordingly, the electronic device and method according to the present disclosure can increase the effect of reducing power consumption. The effect of reducing power consumption is described in detail through the graph of FIG. 9 below.

[0089] Figure 2a illustrates an example of a simplified block diagram of an electronic device.

[0090] Referring to FIG. 2A, the electronic device (200) may include a processor (220), a display driving IC (230), and a display panel (210). The display driving IC (230) may be referred to as a DDI, a display driving circuit, or a control circuit. For example, the electronic device (200) may be an example of the electronic device (1001) or the electronic device (1002) of FIG. 10.

[0091] For example, the display panel (210) may include sub-pixels. As a non-limiting example, the display panel (210) may include a hybrid oxide poly-Si (HOP) display. For example, the HOP display may be formed of low-temperature polycrystalline oxide (LTPO).

[0092] For example, the processor (220) may be used to acquire an image. For example, the processor (220) may provide the image to the display driving IC (230). For example, the processor (220) may provide at least one command related to displaying the image to the display driving IC (230). For example, the processor (220) may include at least a part of the processor (1020) of FIG. 10.

[0093] For example, the processor (220) may include a central processing unit (CPU), a graphics processing unit (GPU), or a display controller (or display processing unit (DPU)) configured to process an image obtained from a volatile memory into a format suitable for the display panel (210). For example, the processor (220) may be operatively or operably coupled with a display driver IC (230). For example, operatively coupling the processor (220) with the display driver IC (230) may indicate that the processor (220) is directly connected to the display driver IC (230). For example, operatively coupling the processor (220) with the display driver IC (230) may indicate that the processor (220) is connected to the display driver IC (230) through another component of the electronic device (200). For example, the processor (220) may be connected to the display driver IC (230) via an interface (225). For example, the interface (225) may be used to transmit an image from the processor (220) to the display driver IC (230). For example, the interface (225) may be a display serial interface (DSI) of the mobile industry process interface (MIPI) alliance. However, the embodiments of the present disclosure are not limited thereto. For example, the fact that the processor (220) is operatively coupled with the display driver IC (230) may indicate that the display driver IC (230) operates based on instructions executed by the processor (220). For example, the fact that the processor (220) is operatively coupled with the display driver IC (230) may indicate that the display driver IC (230) is controlled by the processor (220).For example, the processor (220) can display an image on the display panel (210) using the display driving IC (230) based on the video mode of the DSI.

[0094] Additionally, the processor (220) may include at least one processor. For example, the at least one processor may be an example of the processor (1020) of FIG. 10. For example, the processor (220) may include various processing circuits and / or multiple processors. For example, the term "processor" as used herein, including in the claims, may include various processing circuits including at least one processor, and one or more of the at least one processors may be configured to perform the various functions described below individually or collectively in a distributed manner. As used herein, when "processor," "at least one processor," and "one or more processors" are described as being configured to perform various functions, these terms encompass, for example, and without limitation, situations where one processor performs some of the recited functions and other processor(s) perform other parts of the recited functions, as well as situations where one processor can perform all of the recited functions. Additionally, the at least one processor may comprise a combination of processors that perform the various functions enumerated / disclosed, for example, in a distributed manner. At least one processor may execute program instructions to achieve or perform the various functions.

[0095] For example, the display driver IC (230) can process the image based on the characteristics of the image and / or the characteristics of the display panel (210). For example, the display driver IC (230) can provide signals for displaying the image to the display panel (210). For example, the display driver IC (230) can include at least a portion of a DDI (e.g., DDI (1130) of FIG. 11). For example, the display driver IC (230) can be operatively coupled with the display panel (210). For example, the display driver IC (230) being operatively coupled with the display panel (210) can indicate that the display driver IC (230) is connected to the display panel (210). For example, the display driver IC (230) being operatively coupled with the display panel (210) can indicate that the display panel (210) is controlled by the display driver IC (230). However, it is not limited to this.

[0096] For example, the display driving IC (230) may include a first set (231) of circuits for processing the image obtained from the processor (220). For example, the first set (231) may be connected to the processor (220) among the processor (220) and the display panel (210). For example, the display driving IC (230) may include a second set (236) of circuits for obtaining the processed image from the first set (231) and providing signals for displaying the obtained image to the display panel (210). For example, the second set (236) may be connected to the display panel (210) among the processor (220) and the display panel (210). For example, the second set (236) may be used to initialize a gate (or gate electrode), apply the data voltage to the initialized gate, and cause the light-emitting diode to emit light. For example, the gate (or gate electrode) may represent a gate of a transistor associated with each of a plurality of sub-pixels included in the display panel (210). The light-emitting diode may represent a diode that emits light associated with each of the plurality of sub-pixels.

[0097] For example, the first set (231) may include an interface controller (232) connected to the processor (220) via an interface (225). For example, the interface controller (232) may be used to provide the image acquired from the processor (220) to an image processing circuit (233) or a graphic random access memory (GRAM) (234) and to provide a command acquired from the processor (220) to a command controller (not shown). For example, the interface controller (232) may be included in the interface module (1131) of FIG. 11.

[0098] For example, the first set (231) may include an image processing circuit (233). For example, the image processing circuit (233) may process the image from the processor (220) to adjust the resolution, brightness, and / or size of the image. For example, the processed image may be provided to the second set (236). For example, the image processing circuit (233) may be included in the image processing module (1135) of FIG. 11.

[0099] For example, the first set (231) may further include a GRAM (234) and a GRAM controller (235). For example, the GRAM (234) may be used to store or record the image obtained from the processor (220). For example, the GRAM controller (235) may be used to control the GRAM (234). The GRAM (234) and the GRAM controller (235) may be included in the memory (1133) of FIG. 11.

[0100] For example, the second set (236) may include a timing controller (237). For example, the timing controller (237) may be used to provide a synchronization signal (or timing signal) to the GRAM controller (235), the source driver circuit (238), the gate driver circuit (239), and / or the light emitting driver (not shown). For example, the synchronization signal may include a vertical synchronization signal (Vsync) and a horizontal synchronization signal (Hsync). For example, the synchronization signal may be generated by the timing controller (237) or may be generated by a synchronization signal generation circuit located outside the display driver IC (230). For example, the timing controller (237) may be used to provide signals for controlling the source driver circuit (238), the gate driver circuit (239), and / or the light emitting driver. For example, the timing controller (237) may further include at least one signal generation circuit (as exemplified in the descriptions below). For example, the at least one signal generation circuit within the second set (236) may be located outside the timing controller (237). For example, at least a portion of the second set (236) may be included in the mapping module (1137) of FIG. 11.

[0101] For example, the second set (236) may include a source driver circuit (238). For example, the source driver circuit (238) may be used to provide the data voltage to be applied to the gate. For example, the source driver circuit (238) may be used to provide the data voltage corresponding to a specific gradation within the gradation that the sub-pixels of the display panel (210) can implement. For example, depending on the magnitude of the data voltage, the gradation implemented by each of the sub-pixels may change. For example, the source driver circuit (238) may generate a signal (e.g., a vertical porch signal (171 or 172) of FIG. 1B) indicating that the provision (or application) of the data voltage for displaying an image is terminated (or indicating a porch period). For example, the display driver IC (230) can identify a porch section among the time sections of the vertical synchronization signal by sensing (or identifying, acquiring, receiving) the signal. The source driver circuit (238) can be referred to as a source driver.

[0102] For example, the second set (236) may include a gate driver circuit (239). For example, the gate driver circuit (239) may be used to provide a gate voltage to the display panel (210). The gate voltage may include a voltage for driving (e.g., turning on / off) a transistor included in a sub-pixel. The gate driver circuit (239) may be referred to as a gate driver.

[0103] Although not illustrated in FIG. 2A, for example, the second set (236) may include a light-emitting driver circuit (or light-emitting driver). For example, the light-emitting driver circuit may be used to provide the light-emitting signal to the display panel (210). In one example, the light-emitting driver circuit may be included in the gate driver circuit (239).

[0104] In FIG. 2A, the gate driver circuit (239) is illustrated as being included in the display driving IC (230), but the present disclosure is not limited thereto. For example, the gate driver circuit (239) may be located outside the display driving IC (230).

[0105] For a specific example of a clock signal transmitted (or provided) from a display driving IC (230) to a gate driver circuit (239) and a scan signal transmitted (or provided) from a gate driver circuit (239) to a display panel (210), reference may be made to FIG. 2B.

[0106] Figure 2b illustrates an example of a clock signal between a display driver IC (integrated circuitry) and a gate driver circuit, and a scan signal between the gate driver circuit and a display panel.

[0107] Fig. 2b illustrates an example (240) of a clock signal generated by a display driver IC (230) and a scan signal generated by a gate driver circuit (250). The gate driver circuit (250) of Fig. 2b may be an example of the gate driver circuit (239) of Fig. 2a. In the example (240) of Fig. 2b, unlike the gate driver circuit (239) of Fig. 2a, the gate driver circuit (250) is illustrated as being located outside the display driver IC (230). However, the present disclosure is not limited thereto.

[0108] Referring to example (240), the display driving IC (230) may include a timing controller (237). For example, the display driving IC (230) may transmit a control signal to the register circuits (241, 242) using the timing controller (237). The register circuits (241, 242) may be referred to as registers or shift registers. For example, the control signal may include a register value for generating a clock signal to be generated using the register circuits (241, 242) and transmitted to the gate driver circuit (250). In one example, the timing controller (237) may include a block (or module, circuit, engine, structure) for timing control and a block for generating a control signal. As described in FIG. 2A, the timing controller (237) may generate a vertical synchronization signal and provide the generated vertical synchronization signal to the source driver circuit (238). In one example, the timing controller (237) may transmit the control signal to the register circuits (241, 242) in response to the vertical synchronization signal. Alternatively, in one example, the timing controller (237) may transmit the control signal to the register circuits (241, 242) in response to a vertical porch signal for indicating a porch section of the vertical synchronization signal. Transmitting the control signal may be referred to as providing a register value to the register circuits (241, 242). For specific details related thereto, reference may be made to FIG. 2C below.

[0109] For example, the gate driver circuit (250) may include a first gate driver circuit (251) for generating a GW scan signal, a second gate driver circuit (252) for generating a GB scan signal, a third gate driver circuit (253) for generating a GW_o (and / or GI (GI_o)) scan signal, and a fourth gate driver circuit (254) for generating an EM signal. In example (240), the third gate driver circuit (253) is illustrated as generating both the GW_o scan signal and the GI scan signal, but the present disclosure is not limited thereto. For example, the gate driver circuit (250) may further include a fifth gate driver circuit for generating a GI scan signal. Referring to example (240), the gate driver circuit (250) may include separate gate driver circuits for generating each scan signal. In other words, the display driving IC (230) can generate a scan signal using a specific gate driver circuit by transmitting a clock signal to the specific gate driver circuit, and transmit the generated scan signal to the display panel (210) (or each sub-pixel of the display panel (210). For example, the display driving IC (230) can independently control each gate driver circuit in the gate driver circuit (250) by using a control signal (or a register value in the control signal) to the register circuit (241 or 242).

[0110] In the example (240) of FIG. 2B, a display driving IC (230) is illustrated including a first register circuit (241) for generating a clock signal (or GW clock signal) of a first gate driver circuit (251) of a gate driver circuit (250) and a clock signal (or EM clock signal) of a fourth gate driver circuit (254), and a second register circuit (242) for generating a clock signal (or GB clock signal) of a second gate driver circuit (252) of a gate driver circuit (250) and a clock signal (or GW_o clock signal) of a third gate driver circuit (253), but the present disclosure is not limited thereto. For example, the display driving IC (230) may include one register circuit, or may include three or more register circuits. For example, the number of register circuits may correspond to the number of gate driver circuits (e.g., four).

[0111] Referring to example (240), the display driving IC (230) can transmit a clock signal (260) to the first gate driver circuit (251). For example, the clock signal (260) can include FLM (261), CLK1 (262), and CLK2 (263). For example, the first gate driver circuit (251) can generate a scan signal (270) using the clock signal (260).

[0112] Fig. 2B illustrates a specific example of a first gate driver circuit (251). Referring to the example of the first gate driver circuit (251) of Fig. 2B, the first gate driver circuit (251) may generate signals (or scan signals) to be used in sub-pixels. For example, the first gate driver circuit (251) may include a transmission line for providing an FLM (261) indicating the start of a clock for sub-pixel lines of the display panel (210), transmission lines for providing CLK1 (262) and CLK2 (263), and a block associated with each sub-pixel line. Each of the sub-pixel lines may include sub-pixels on a horizontal line of the display panel (210).

[0113] For example, the FLM (261) can indicate a start time (or start timing) of one frame (or a time section of a vertical synchronization signal). In addition, the FLM (261) can indicate a start timing of a time section of a first horizontal synchronization signal in the one frame. The first horizontal synchronization signal can be associated with a first sub-pixel line. For example, the first gate driver circuit (251) can provide the FLM (261), CLK1 (262), and CLK2 (263) to a block (265) associated with the first sub-pixel line. The first gate driver circuit (251) can generate an output associated with the first sub-pixel line through the block (265) at a timing determined using the FLM (261), CLK1 (262), and CLK2 (263). For example, the output of block (265) may include a scan signal (271) (e.g., a GW scan signal) to be used in each of the sub-pixels of the first sub-pixel line. In addition, the first gate driver circuit (251) may provide the outputs of CLK1 (262), CLK2 (263), and block (265) to block (266) associated with the second sub-pixel line. The first gate driver circuit (251) may generate an output associated with the second sub-pixel line through block (266) at a timing determined using the outputs of CLK1 (262), CLK2 (263), and block (265). For example, the output of block (266) may include a scan signal (272) to be used in each of the sub-pixels of the second sub-pixel line. Additionally, the first gate driver circuit (251) can provide the outputs of CLK1 (262), CLK2 (263), and block (266) to the block (267) associated with the third sub-pixel line.The first gate driver circuit (251) can generate an output related to the third sub-pixel line through the block (267) at a timing determined using the outputs of CLK1 (262), CLK2 (263), and the block (266). For example, the output of the block (267) can include a scan signal (273) to be used in each of the sub-pixels of the third sub-pixel line. In addition, the first gate driver circuit (251) can provide the outputs of CLK1 (262), CLK2 (263), and the n-1th block to the block (268) related to the nth sub-pixel line. The first gate driver circuit (251) can generate an output related to the nth sub-pixel line through the block (268) at a timing determined using the outputs of CLK1 (262), CLK2 (263), and the block (267). For example, the output of block (268) may include a scan signal (274) to be used in each of the sub-pixels of the nth sub-pixel line. In example (240), the display panel (210) may include n sub-pixel lines. For example, scan signals (271, 272, 273, 274) for each sub-pixel line may be included in the scan signal (270).

[0114] In example (240), for convenience of explanation, a clock signal (260) transmitted to the first gate driver circuit (251) and a scan signal (270) transmitted from the first gate driver circuit (251) to the display panel (210) are illustrated, but the present disclosure is not limited thereto. The description of example (240) may also be applied to a case where other clock signals are transmitted to other gate driver circuits (e.g., the second gate driver circuit (252)) and other scan signals generated thereby are transmitted to the display panel (210).

[0115] FIG. 2c illustrates an example of a method for identifying a porch section of a vertical synchronization signal using a signal obtained from a source driver circuit and controlling transmission of a clock signal within the porch section using a gate driver circuit.

[0116] For example, the display driver IC (230) can identify (or sense) the time (or timing, point in time) at which the provision (or application) of the data voltage is stopped within the time period of the vertical synchronization signal by using the source driver circuit (238). For example, the display driver IC (230) can identify (or sense) the time (or timing, point in time) at which the provision (or application) of the data voltage is stopped within the time period of the vertical synchronization signal according to the on / off of the source AMP (source amplifier) ​​(280) of the source driver circuit (238). In one example, the display driver IC (230) can identify (or sense) the time (or timing, point in time) at which the provision (or application) of the data voltage is stopped within the time period of the vertical synchronization signal by obtaining (or identifying, receiving) a vertical porch signal (290) generated as the source AMP (280) is turned on and off.

[0117] For example, the display driver IC (230) may generate a control signal to be provided (or transmitted) to the first register circuit (241). In FIG. 2C, a display driver IC (230) including the first register circuit (241) of FIG. 2B is illustrated, but the present disclosure is not limited thereto. For example, the display driver IC (230) may also generate a control signal to be provided to the second register circuit (242) or an integrated single register circuit.

[0118] In one example, the display driving IC (230) can generate a control signal (245-1) corresponding to (or synchronized with, triggered by) a start time of a vertical synchronization signal (or an active period of the vertical synchronization signal, a start time of an active period of the vertical synchronization signal). The display driving IC (230) can generate the control signal (245-1) based on identifying the start time of the vertical synchronization signal that is triggered. In one example, the display driving IC (230) can generate a control signal (245-2) corresponding to (or synchronized with, triggered by) a start time of a porch period of the vertical synchronization signal (or a porch period of the vertical synchronization signal) based on acquiring a vertical porch signal (290).

[0119] For example, the control signal (245-1 or 245-2) may include a register value. Examples of register values ​​may be referenced in the table below.

[0120]

[0121] Referring to the above table, the Description may indicate a clock signal to be controlled, the Sync_Mode[1:0] may indicate first information indicating a section of a vertical synchronization signal related to the clock signal, the CLK_CTRL may indicate second information indicating whether to transmit the clock signal, the CLK_Toggle Freq.[2:0] may indicate third information indicating a clock frequency of the clock signal, and the DISABLE_SET[1:0] may indicate fourth information indicating a voltage level of the clock signal while stopping transmission of the clock signal. The register value including the information shown in the above table is merely an example for the convenience of description, and the present disclosure is not limited thereto. For example, the order of the information included in the register value, the size of the information, and the name of the information are not limited to the above table. In addition, the register value may include at least some of the first information, the second information, the third information, and the fourth information, or may further include other information.

[0122] For example, the first information may indicate a section of a vertical synchronization signal related to a clock signal to be controlled. For example, the first information may indicate one of a value indicating that the section of the vertical synchronization signal is an active section (e.g., 10), a value indicating that the section of the vertical synchronization signal is a porch section (e.g., 01), and a value indicating that the section of the vertical synchronization signal is both the active section and the porch section (e.g., 11). For example, the first information having a value of 10 may indicate a V-sync mode in which the section of the vertical synchronization signal related to the clock signal to be controlled indicates a start time of the vertical synchronization signal (or an active section of the vertical synchronization signal, a start time of the active section of the vertical synchronization signal). For example, the first information having a value of 01 may indicate a V-porch mode in which the section of the vertical synchronization signal (or a start section of the porch section of the vertical synchronization signal) is indicated. For example, the first information having a value of 11 may indicate a Hybrid mode indicating a time interval of a vertical synchronization signal (or an active interval and a porch interval of the vertical synchronization signal). In one example, when the value of the first information is 11, the interval of the vertical synchronization signal for which a clock signal is to be generated (or provided, or applied) may include time intervals of two vertical synchronization signals (e.g., a porch interval of a first vertical synchronization signal and an active interval of a second vertical synchronization signal that is continuous to the first vertical synchronization signal).

[0123] For example, the second information may indicate one of a value indicating transmission of the clock signal (e.g., 1) and a value indicating cessation of transmission of the clock signal (e.g., 0). For example, transmission of the clock signal may be referred to as Enable. For example, cessation of transmission of the clock signal may be referred to as Disable.

[0124] For example, the third information may indicate one candidate frequency value among a plurality of candidate frequency values ​​to be used as the clock frequency of the clock signal. For example, when the third information is 001, the candidate frequency values ​​may include a candidate frequency value whose number of toggles is 1 (= 1 / 2^0) within a time interval in which the clock signal is generated (or transmitted) (e.g., a time interval indicated by the first information). In addition, for example, when the third information is 111, the candidate frequency values ​​may include a candidate frequency value whose number of toggles is 256 (= 1 / 2^(-8)) within a time interval in which the clock signal is generated. As described above, the candidate frequency values ​​of the third information and the size of the third information (e.g., 3 bits) are merely examples for convenience of description, and the present disclosure is not limited thereto. Alternatively, for example, the third information may indicate a variable number of toggles relative to a standard toggle count (e.g., 256). For example, if the third information is 111, the number of toggles may be 1 (= 256*1 / (2^8)). For example, if the third information is 001, the number of toggles may be 256 (= 256*1 / (2^0)).

[0125] For example, the fourth information may indicate one value used as the voltage level (or state) of the clock signal among a first DC (direct current) value (e.g., 10), a second DC value lower than the first DC value (e.g., 01), and a ground value (e.g., 00) while stopping transmitting the clock signal. For example, the fourth information may indicate the state (or voltage level) of the clock signal while stopping transmitting the clock signal. For example, the first DC value may be referenced as a first state (or a first level, a high state). For example, the second DC value may be referenced as a second state (or a second level, a low state). For example, the ground value may be referenced as a GND state (or a third level, a ground state).

[0126] In the example of FIG. 2C, the control signal (245-1) generated in response to the start time of the vertical synchronization signal may include the first information (e.g., 10) indicating the active period of the vertical synchronization signal. In addition, the control signal (245-1) generated in response to the porch period of the vertical synchronization signal (or generated based on acquiring the vertical porch signal (290)) may include the first information (e.g., 01) indicating the porch period of the vertical synchronization signal. For example, when the control signal (245-1) or the control signal (245-2) is used to generate and transmit a clock signal (260) through the first register circuit (241) within the corresponding period, the control signal (245-1) or the control signal (245-2) may include the second information (e.g., 1) indicating transmission of the clock signal. In contrast, when the control signal (245-1) or the control signal (245-2) is used to not generate (or to stop transmitting) the clock signal (260) through the first register circuit (241) within the corresponding section, the control signal (245-1) or the control signal (245-2) may include the second information (e.g., 0) indicating the stoppage of transmission of the clock signal.

[0127] For example, the display driving IC (230) can control transmission of the clock signal (260) within the porch period of the vertical synchronization signal by generating a control signal (245-2) in response to the vertical porch signal (290) and transmitting the control signal (245-2) to the register circuit (241) based on executing a mode for low power. For example, within the mode for low power, the electronic device (200) can display a screen for low power (AOD (always on display) screen).

[0128] The display driving IC (230) can identify an image to be displayed within the screen for low power consumption and adjust a register value according to the image. For example, the display driving IC (230) can determine whether a brightness parameter of the image satisfies a criterion. For example, if the brightness parameter of the image satisfies a first criterion, the display driving IC (230) can set the second information of the register value to a value (e.g., 0) indicating discontinuation of transmission of a clock signal. For example, if the brightness parameter of the image satisfies a second criterion, the display driving IC (230) can set the second information of the register value to a value (e.g., 1) indicating transmission of a clock signal and set the third information of the register value to a first candidate frequency value. For example, the display driving IC (230) may set the second information of the register value to a value (e.g., 1) indicating transmission of a clock signal when the brightness parameter of the image satisfies a third criterion, and may set the third information of the register value to a second candidate frequency value. As a non-limiting example, the second candidate frequency value may indicate a frequency greater than the first candidate frequency value. In other words, the number of toggles of a clock signal having the second candidate frequency value of the third criterion may be greater than the number of toggles of a clock signal having the first candidate frequency value of the second criterion.

[0129] For example, the brightness parameter may include at least one of an on-pixel ratio (OPR) indicating the number of sub-pixels for displaying the image among the sub-pixels of the display panel (210), illuminance outside the electronic device (200) (or the display panel (210)), or luminance of the display panel (210). As a non-limiting example, when the brightness parameter is the OPR, the first criterion may indicate a case where the OPR is 10% or less, the second criterion may indicate a case where the OPR is more than 10% and less than 15%, and the third criterion may indicate a case where the OPR is more than 15% and less than 25%. The number of criteria of the present disclosure and the range (or criterion values) of each of the criteria are not limited to the above examples. As described above, the display driving IC (230) may adjust whether to transmit a clock signal and a clock frequency by using the brightness parameter of the image to be displayed in the low-power mode. Specific details related to this are described in FIGS. 7 to 8c below.

[0130] Referring to FIGS. 2A to 2C, the display driving IC (230) can identify a porch section of a vertical synchronization signal using a signal (e.g., a vertical porch signal (290)) obtained from a source driver circuit (238), and control transmission of a clock signal to be used within the porch section of the vertical synchronization signal accordingly. Accordingly, the gate driver circuit (239) (or gate driver circuit (250)) can transmit the clock signal to the display panel (210) within the porch section of the vertical synchronization signal, or stop transmitting the clock signal to the display panel (210) within the porch section of the vertical synchronization signal.

[0131] Figure 3 illustrates an example of a subpixel within a display panel.

[0132] FIG. 3 illustrates an example of a circuit (or compensation circuit) of each of the sub-pixels within the display panel (210). The sub-pixels illustrated in FIG. 3 are merely for convenience of explanation, and the structure of the sub-pixels of the present disclosure is not limited to the example illustrated in FIG. 3. For example, the structure of the sub-pixel may include fewer transistors (e.g., seven transistors) than eight transistors (301, 302, 303, 304, 305, 306, 307, 308), or may include more transistors (e.g., nine or ten transistors).

[0133] Referring to FIG. 3, each of the plurality of sub-pixels may include a light-emitting element (300) (e.g., a light-emitting diode (300) or an OLED (300)), a first transistor (301) (e.g., the driving transistor, transistor), a second transistor (302) (e.g., a switching transistor), a third transistor (303) (e.g., a compensation transistor), a fourth transistor (304) (e.g., an initialization transistor), a fifth transistor (305) (e.g., the operation control transistor), a sixth transistor (306) (e.g., the light-emitting control transistor), a seventh transistor (307) (e.g., a bypass transistor), an eighth transistor (308) (e.g., a threshold voltage adjustment transistor), a capacitor (309) (e.g., a storage capacitor), and a capacitor (310) (e.g., a boost capacitor). The components, their relationships, and their functions within each of the plurality of sub-pixels illustrated in FIG. 3 are exemplary only and do not limit the implementations described or claimed within this document. For example, the capacitor (310) may be omitted.

[0134] For example, the gate electrode (G) of the first transistor (301) may be connected to the drain electrode (D) of the third transistor (303). For example, the gate electrode (G) of the first transistor (301) may be connected to the drain electrode (D) of the fourth transistor (304). For example, the gate electrode of the first transistor (301) may be connected to a capacitor (309) used to store a data voltage (Vdata). For example, the gate electrode of the first transistor (301) may be connected to a capacitor (310) used to compensate for a voltage drop caused by stopping providing the fourth signal (314). For example, the source electrode of the first transistor (301) may be connected to the drain electrode of the second transistor (302). For example, the source electrode of the first transistor (301) may be connected to the drain electrode of the fifth transistor (305). For example, the source electrode of the first transistor (301) may be connected to the drain electrode of the eighth transistor (308). For example, the drain electrode of the first transistor (301) may be connected to the source electrode of the third transistor (303). For example, the drain electrode of the first transistor (301) may be connected to the source electrode of the sixth transistor (306). For example, the first transistor (301) may be used to provide a current (320) according to a data voltage (Vdata) to the light emitting diode (300).

[0135] For example, the gate electrode of the second transistor (302) may be configured to receive the fourth signal (314). For example, the source electrode of the second transistor (302) may be configured to obtain the data voltage (Vdata). For example, the fourth signal (314) may be used to apply the data voltage (Vdata) to the first transistor (301). For example, the fourth signal (314) may be referred to as GW, GW signal, switching signal, switching scan signal, GW scan signal, or fourth scan signal.

[0136] For example, the gate electrode of the third transistor (303) may be configured to receive a second signal (312). For example, the second signal (312) may be referred to as a GW_o signal, GW_o, a GC signal, a GC, a compensation signal, a compensation scan signal, a GW_o scan signal, or a second scan signal.

[0137] For example, the gate electrode of the fourth transistor (304) may be configured to receive the first signal (311). For example, the source electrode of the fourth transistor (304) may be configured to obtain a first initialization voltage (Vint1) (e.g., about -3.5 (V)). For example, the first signal (311) may be used to initialize the gate electrode of the first transistor (301). For example, the first signal (311) may be referred to as GI, GI_o, GI signal, initialization signal, initialization scan signal, GI (GI_o) scan signal, or first scan signal.

[0138] For example, the gate electrode of the fifth transistor (305) may be configured to receive the light emission signal (315). For example, the source electrode of the fifth transistor (305) may be configured to obtain the first driving voltage (VDD).

[0139] For example, the gate electrode of the sixth transistor (306) may be configured to receive the emission signal (315). For example, the drain electrode of the sixth transistor (306) may be connected to the source electrode of the seventh transistor (307). For example, the drain electrode of the sixth transistor (306) may be connected to the anode of the light emitting element (300). For example, the emission signal (315) may be referred to as an EM signal, an EM, an emission scan signal, an EM scan signal, or a fifth scan signal.

[0140] For example, the gate electrode of the seventh transistor (307) may be configured to receive the third signal (313). For example, the drain electrode of the seventh transistor (307) may be configured to obtain the second initialization voltage (Vint2) (e.g., about -3 (V)).

[0141] For example, the gate electrode of the eighth transistor (308) may be configured to receive the third signal (313). For example, the source electrode of the eighth transistor (308) may be configured to obtain a bias voltage (Vbias) (e.g., about 6 (V)).

[0142] For example, the third signal (313) may be used to initialize a light-emitting element (300) including an anode connected to the source electrode of the seventh transistor (307). For example, the third signal (313) may be used to initialize a light-emitting element (300) (or a parasitic capacitor of the light-emitting element (300)). For example, the third signal (313) may be referenced as GB, a GB signal, a bypass signal, a bypass scan signal, a GB scan signal, or a third scan signal.

[0143] For example, the cathode of the light emitting element (300) can be configured to obtain a second driving voltage (VSS).

[0144] For example, the display driving IC (230) can display an image on the display panel (210) based on providing a first signal (311), a second signal (312), a third signal (313), a fourth signal (314), and a light emitting signal (315) to each of the plurality of sub-pixels.

[0145] FIG. 4 illustrates an example of a method for controlling transmission of a clock signal within a porch interval of a vertical synchronization signal having an adjusted length.

[0146] FIG. 4 illustrates an example (400) of a method for controlling transmission of a clock signal within a porch interval having an adjusted length when the length of the porch interval of a vertical synchronization signal is adjusted as the electronic device (200) within the low power mode adjusts the refresh rate of the display panel (210).

[0147] Example (400) of Fig. 4 may represent a case where the refresh rate of the display panel (210) is 60 Hz, assuming that the refresh rate of the display panel (210) in Example (105) of Fig. 1b is 40 Hz. In other words, the length of the porch section (401b) of the vertical synchronization signal in Example (400) of Fig. 4 may be shorter than the length of the porch section (101b) of the vertical synchronization signal in Example (105) of Fig. 1b.

[0148] Referring to FIG. 4, an example (400) illustrates a state (410) of a display panel (210). For the state (410) of the display panel (210), a time interval (401) of a first vertical synchronization signal, a time interval (402) of a second vertical synchronization signal following the first vertical synchronization signal, and a time interval (403) of a third vertical synchronization signal following the second vertical synchronization signal are exemplified.

[0149] For example, each of the time intervals (401, 402, 403) can be defined from a time (or timing, point in time) at which a vertical synchronization signal is provided (or triggered). For example, referring to a state (411) of a vertical synchronization signal, a vertical synchronization signal can be provided (or generated, transmitted). For example, referring to a state (411) of a vertical synchronization signal, a vertical synchronization signal (411-1) (or the first vertical synchronization signal) and a vertical synchronization signal (411-2) (or the second vertical synchronization signal) can be provided. For example, the time interval (401) can start from a time at which the vertical synchronization signal (411-1) is provided. For example, the time interval (402) can start from a time at which the vertical synchronization signal (411-2) is provided. For example, a TE (tearing effect) signal can be synchronized with the vertical synchronization signal. For example, referring to the state (412) of the TE signal, the TE signal may be provided (or transmitted) from the display driver IC (230) to the processor (220) at the time when the vertical synchronization signal (411-1) is provided and at the time when the vertical synchronization signal (411-2) is provided. In addition, for example, the FLM signal may also be synchronized with the vertical synchronization signal. For example, referring to the state (430) of the FLM signal, the FLM signal (431) and the FLM signal (432) may be transmitted from the display driver IC (230) to the gate driver circuit (239) corresponding to the time when the vertical synchronization signal (411-1) is provided and the time when the vertical synchronization signal (411-2) is provided, respectively.

[0150] In the example (400) of FIG. 4, three vertical synchronization signals are illustrated for convenience of explanation, but the present disclosure is not limited thereto. For example, within the time interval (401) of the first vertical synchronization signal, the display driving IC (230) can perform (or execute) the first scan (or address scan). For example, within the time interval (402) of the second vertical synchronization signal, the display driving IC (230) can perform (or execute) the second scan (or self-scan). For example, within the time interval (403) of the third vertical synchronization signal, the display driving IC (230) can perform (or execute) the second scan (or self-scan).

[0151] For example, each of the time intervals (401, 402, 403) of the vertical synchronization signal may include an active interval and a porch interval. For example, the time interval (401) may include an active interval (401a) and a porch interval (401b). For example, the length of the active interval (401a) may correspond to the length of the active interval (101a) of FIG. 1B. For example, the length of the porch interval (401b) may be shorter than the length of the porch interval (101b) of FIG. 1B. The time interval (402) may include an active interval (402a) and a porch interval (402b). For example, the length of the active interval (402a) may correspond to the length of the active interval (102a) of FIG. 1B. For example, the length of the porch section (402b) may be shorter than the length of the porch section (102b) of FIG. 1B. The time section (403) may include an active section (403a) and a porch section (403b). For example, the length of the active section (403a) may correspond to the length of the active section (103a) of FIG. 1B. For example, the length of the porch section (403b) may be shorter than the length of the porch section (103b) of FIG.

[0152] For example, within the active period (401a) of the time period (401) in which the first scan is performed, data may be provided via MIPI (mobile industry processor interface). For example, the data may be provided from the processor (220) to the display driver IC (230) via MIPI within the active period (401a). Referring to the state (413) of MIPI, the data may be provided from the processor (220) to the display driver IC (230) within the active period (401a). As the data is provided, the source driver circuit (238) may generate a data voltage and provide (or apply, transmit) the data voltage to the display panel (210) (or each of the sub-pixels of the display panel (210). Referring to the state (414) of the source driver, within the active period (402a) (or active period (403a)) of the time period (402) (or time period (403)) in which the second scan is performed, a reference voltage having a fixed voltage level can be provided (or applied, transmitted).

[0153] Referring to Example (400), the display driving IC (230) may provide (or transmit) clock signals to the gate driver circuit (239) to generate a signal (or scan signal) used for scanning (e.g., the first scan or the second scan) in the display panel (210). In Example (400), for convenience of explanation, a GW clock signal, a GB clock signal, a GW_o clock signal, and an EM clock signal are exemplified, but the present disclosure is not limited thereto. For example, the clock signals may further include a GI clock signal.

[0154] Referring to example (400), each of the clock signals can be synchronized with respect to the vertical synchronization signal. For example, the clock signals can start to be provided (or transmitted) or can start to cease being provided (or transmitted) from the time the vertical synchronization signal (411-1) is provided and the time the vertical synchronization signal (411-2) is provided.

[0155] Referring to the state (421) of the GW clock signal of example (400), the GW clock signal can be transmitted from the display driving IC (230) to the gate driver circuit (239) within the active period (401a). For example, within the active period (401a), a clock signal (441-1), which is a GW clock signal, can be transmitted. For example, as the clock signal (441-1) is transmitted to the gate driver circuit (239) within the active period (401a), the gate driver circuit (239) can transmit a GW scan signal to the display panel (210).

[0156] Referring to the state (422) of the GB clock signal of example (400), the GB clock signal can be transmitted from the display driving IC (230) to the gate driver circuit (239) within the active period (401a). For example, within the active period (401a), the clock signal (442-1), which is a GB clock signal, can be transmitted. For example, as the clock signal (442-1) is transmitted to the gate driver circuit (239) within the active period (401a), the gate driver circuit (239) can transmit a GB scan signal to the display panel (210).

[0157] Referring to the state (423) of the GW_o clock signal of example (400), the GW_o clock signal can be transmitted from the display driving IC (230) to the gate driver circuit (239) within the active period (401a). For example, within the active period (401a), the clock signal (443-1), which is the GW_o clock signal, can be transmitted. For example, as the clock signal (443-1) is transmitted to the gate driver circuit (239) within the active period (401a), the gate driver circuit (239) can transmit a GW_o scan signal to the display panel (210).

[0158] Referring to the state (424) of the EM clock signal of example (400), the EM clock signal can be transmitted from the display driving IC (230) to the gate driver circuit (239) (or gate driver circuit) within the active period (401a). For example, within the active period (401a), the clock signal (444-1), which is an EM clock signal, can be transmitted. For example, as the clock signal (444-1) is transmitted to the gate driver circuit (239) within the active period (401a), the gate driver circuit (239) can transmit a light emission signal (or, EM scan signal) to the display panel (210).

[0159] In example (400), the state (470) of the vertical porch signal may be changed to indicate a porch period. For example, when the state (470) of the vertical porch signal changes from the second state to the first state, it may indicate that a porch period has started. Referring to example (400), each of the clock signals may be synchronized with the vertical porch signal. For example, the display driver IC (230) may start transmitting, or may stop providing (or transmitting), the clock signals at the time when the vertical porch signal (471) is provided.

[0160] Referring to the state (421) of the GW clock signal of the example (400), the GW clock signal may be stopped from being transmitted from the display driving IC (230) to the gate driver circuit (239) within the porch period (401b). For example, the state (421) of the GW clock signal may be maintained at the first level (441-2) within the porch period (401b). For example, the state (421) of the GW clock signal being maintained at the first level (441-2) within the porch period (401b) may indicate that the transmission of the GW clock signal from the display driving IC (230) to the gate driver circuit (239) is stopped. For example, within the porch section (401b) of the time section (401), as transmission of the GW clock signal to the gate driver circuit (239) is interrupted, the gate driver circuit (239) may refrain from transmitting the GW scan signal to the display panel (210).

[0161] Referring to the state (422) of the GB clock signal of the example (400), the GB clock signal may be stopped from being transmitted from the display driving IC (230) to the gate driver circuit (239) within the porch period (401b). For example, the state (422) of the GB clock signal may be maintained at the first level (442-2) within the porch period (401b). For example, the state (422) of the GB clock signal being maintained at the first level (442-2) within the porch period (401b) may indicate that the transmission of the GB clock signal from the display driving IC (230) to the gate driver circuit (239) is stopped. For example, within the porch section (401b) of the time section (401), as transmission of the GB clock signal to the gate driver circuit (239) is interrupted, the gate driver circuit (239) may refrain from transmitting the GB scan signal to the display panel (210).

[0162] Referring to the state (423) of the GW_o clock signal of example (400), the GW_o clock signal may be stopped from being transmitted from the display driving IC (230) to the gate driver circuit (239) within the porch period (401b). For example, the state (423) of the GW_o clock signal may be maintained at the second level (443-2) within the porch period (401b). For example, the state (423) of the GW_o clock signal being maintained at the second level (443-2) within the porch period (401b) may indicate that the transmission of the GW_o clock signal from the display driving IC (230) to the gate driver circuit (239) is stopped. For example, within the porch section (401b) of the time section (401), as transmission of the GW_o clock signal to the gate driver circuit (239) is stopped, the gate driver circuit (239) may refrain from transmitting the GW_o scan signal to the display panel (210).

[0163] Referring to the state (424) of the EM clock signal of the example (400), the EM clock signal may be stopped from being transmitted from the display driving IC (230) to the gate driver circuit (239) within the porch period (401b). For example, the state (424) of the EM clock signal may be maintained at the first level (444-2) within the porch period (401b). For example, the state (424) of the EM clock signal being maintained at the first level (444-2) within the porch period (401b) may indicate that the transmission of the EM clock signal from the display driving IC (230) to the gate driver circuit (239) is stopped. For example, within the porch section (401b) of the time section (401), as transmission of the EM clock signal to the gate driver circuit (239) is interrupted, the gate driver circuit (239) may refrain from transmitting a light emission signal (or, EM scan signal) to the display panel (210).

[0164] In the example (400) of FIG. 4, the display driving IC (230) is illustrated as stopping transmission of a clock signal (e.g., a GW clock signal, a GB clock signal, a GW_o clock signal, an EM clock signal, a GI clock signal) to the gate driver circuit (239) within a porch section, but the present disclosure is not limited thereto. The display driving IC (230) may perform transmission of the clock signal to the gate driver circuit (239) within some porch sections, and stop transmission of the clock signal to the gate driver circuit (239) within other porch sections. For example, the display driving IC (230) can transmit the clock signal to the gate driver circuit (239) within the porch section (401b), stop transmitting the clock signal to the gate driver circuit (239) within the porch section (402b), and transmit the clock signal to the gate driver circuit (239) within the porch section (403b). Alternatively, for example, the display driving IC (230) can transmit the clock signal to the gate driver circuit (239) within the porch section (401b) and the porch section (402b), and stop transmitting the clock signal to the gate driver circuit (239) within the porch section (403b).

[0165] For example, based on the refresh rate (or base frequency) of the display panel (210), or the driving frequency of the display driving IC (230), or the battery level of the electronic device (200) including the display driving IC (230), or the mode of the electronic device (200) (or the display driving IC (230)) for low power consumption (e.g., power saving mode or ultra power saving mode), the display driving IC (230) may stop transmitting the clock signal to the gate driver circuit (239) within all porch periods, or change the number of porch periods during which it stops transmitting the clock signal to the gate driver circuit (239).

[0166] Referring to FIG. 1b and FIG. 4, the display driving IC (230) can check (or sense) the start time of the pouch period and perform dynamic control on the transmission of a clock signal within the pouch period, even if the length of the pouch period is changed to adjust the refresh rate of the display panel (210).

[0167] FIG. 5 illustrates an example of a method for controlling transmission of a clock signal within a porch period of a vertical synchronization signal and an active period of another vertical synchronization signal.

[0168] FIG. 5 illustrates an example (500) of a method for controlling transmission of a clock signal within a porch period of a vertical synchronization signal and an active period of another vertical synchronization signal that is continuous with the vertical synchronization signal.

[0169] Example (500) of FIG. 5 may represent a case where the refresh rate of the display panel (210) is 30 Hz, assuming that the refresh rate of the display panel (210) in Example (105) of FIG. 1b is 40 Hz. In other words, the length of the porch section (501b) of the vertical synchronization signal in Example (500) of FIG. 5 may be longer than the length of the porch section (101b) of the vertical synchronization signal in Example (105) of FIG. 1b. In Example (500) of FIG. 5, the length of the active section (501a) of the vertical synchronization signal may correspond to the length of the porch section (501b) of the vertical synchronization signal. In other words, in Example (500), the active section, the porch section, the active section, and the porch section may be sequentially repeated at the same cycle. Example (500) is merely an example for convenience of explanation, and the present disclosure is not limited thereto. For example, a method of controlling transmission of a clock signal within a porch period of a vertical synchronization signal and an active period of another vertical synchronization signal that is continuous with the vertical synchronization signal can also be applied to example (400) of FIG. 4 or example (105) of FIG. 1b.

[0170] Referring to FIG. 5, an example (500) illustrates a state (510) of a display panel (210). For the state (510) of the display panel (210), a time interval (501) of a first vertical synchronization signal, a time interval (502) of a second vertical synchronization signal following the first vertical synchronization signal, and a time interval (503) of a third vertical synchronization signal following the second vertical synchronization signal are exemplified.

[0171] For example, each of the time intervals (501, 502, 503) can be defined from a time (or timing, point in time) at which a vertical synchronization signal is provided (or triggered). For example, referring to a state (511) of a vertical synchronization signal, a vertical synchronization signal can be provided (or generated, transmitted). For example, referring to a state (511) of a vertical synchronization signal, a vertical synchronization signal (511-1) (or the first vertical synchronization signal) and a vertical synchronization signal (511-2) (or the second vertical synchronization signal) can be provided. For example, the time interval (501) can start from a time at which the vertical synchronization signal (511-1) is provided. For example, the time interval (502) can start from a time at which the vertical synchronization signal (511-2) is provided. For example, a TE (tearing effect) signal can be synchronized with the vertical synchronization signal. For example, referring to the state (512) of the TE signal, the TE signal may be provided (or transmitted) from the display driver IC (230) to the processor (220) at the time when the vertical synchronization signal (511-1) is provided and at the time when the vertical synchronization signal (511-2) is provided. In addition, for example, the FLM signal may also be synchronized with the vertical synchronization signal. For example, referring to the state (530) of the FLM signal, the FLM signal (531) and the FLM signal (532) may be transmitted from the display driver IC (230) to the gate driver circuit (239) corresponding to the time when the vertical synchronization signal (511-1) is provided and the time when the vertical synchronization signal (511-2) is provided, respectively.

[0172] In the example (500) of FIG. 5, three vertical synchronization signals are illustrated for convenience of explanation, but the present disclosure is not limited thereto. For example, within the time interval (501) of the first vertical synchronization signal, the display driving IC (230) can perform (or execute) the first scan (or address scan). For example, within the time interval (502) of the second vertical synchronization signal, the display driving IC (230) can perform (or execute) the second scan (or self-scan). For example, within the time interval (503) of the third vertical synchronization signal, the display driving IC (230) can perform (or execute) the second scan (or self-scan).

[0173] For example, each of the time intervals (501, 502, 503) of the vertical synchronization signal may include an active interval and a porch interval. For example, the time interval (501) may include an active interval (501a) and a porch interval (501b). For example, the length of the active interval (501a) may correspond to the length of the active interval (101a) of FIG. 1B. For example, the length of the porch interval (501b) may correspond to the length of the active interval (501a). The time interval (502) may include an active interval (502a) and a porch interval (502b). For example, the length of the active interval (502a) may correspond to the length of the active interval (101a) of FIG. 1B. For example, the length of the porch interval (502b) may correspond to the length of the active interval (502a). The time interval (503) may include an active interval (503a) and a porch interval (503b). For example, the length of the active interval (503a) may correspond to the length of the active interval (101a) of FIG. 1B. For example, the length of the porch interval (503b) may correspond to the length of the active interval (503a).

[0174] For example, within the active period (501a) of the time period (501) in which the first scan is performed, data may be provided via MIPI (mobile industry processor interface). For example, the data may be provided from the processor (220) to the display driver IC (230) via MIPI within the active period (501a). Referring to the state (513) of MIPI, the data may be provided from the processor (220) to the display driver IC (230) within the active period (501a). As the data is provided, the source driver circuit (238) may generate a data voltage and provide (or apply, transmit) the data voltage to the display panel (210) (or each of the sub-pixels of the display panel (210). Referring to the state (514) of the source driver, within the active period (502a) (or active period (503a)) of the time period (502) (or time period (503)) in which the second scan is performed, a reference voltage having a fixed voltage level can be provided (or applied, transmitted).

[0175] Referring to Example (500), the display driving IC (230) may provide (or transmit) clock signals to the gate driver circuit (239) to generate a signal (or scan signal) used for scanning (e.g., the first scan or the second scan) in the display panel (210). In Example (500), for convenience of explanation, a GW clock signal, a GB clock signal, a GW_o clock signal, and an EM clock signal are exemplified, but the present disclosure is not limited thereto. For example, the clock signals may further include a GI clock signal.

[0176] Referring to example (500), each of the clock signals may be synchronized with respect to a vertical synchronization signal. For example, the clock signals may begin to be provided (or transmitted) or may cease to be provided (or transmitted) from the time the vertical synchronization signal (511-1) is provided and from the time the vertical synchronization signal (511-2) is provided.

[0177] Referring to the state (521) of the GW clock signal of example (500), the GW clock signal can be transmitted from the display driving IC (230) to the gate driver circuit (239) within the active period (501a). For example, within the active period (501a), a clock signal (541-1), which is a GW clock signal, can be transmitted. For example, as the clock signal (541-1) is transmitted to the gate driver circuit (239) within the active period (501a), the gate driver circuit (239) can transmit a GW scan signal to the display panel (210).

[0178] Referring to the state (522) of the GB clock signal of example (500), the GB clock signal can be transmitted from the display driving IC (230) to the gate driver circuit (239) within the active period (501a). For example, a clock signal (542-1), which is a GB clock signal, can be transmitted within the active period (501a). For example, as the clock signal (542-1) is transmitted to the gate driver circuit (239) within the active period (501a), the gate driver circuit (239) can transmit a GB scan signal to the display panel (210).

[0179] Referring to the state (523) of the GW_o clock signal of example (500), the GW_o clock signal can be transmitted from the display driving IC (230) to the gate driver circuit (239) within the active period (501a). For example, within the active period (501a), the clock signal (543-1), which is the GW_o clock signal, can be transmitted. For example, as the clock signal (543-1) is transmitted to the gate driver circuit (239) within the active period (501a), the gate driver circuit (239) can transmit a GW_o scan signal to the display panel (210).

[0180] Referring to the state (524) of the EM clock signal of example (500), the EM clock signal can be transmitted from the display driving IC (230) to the gate driver circuit (239) (or gate driver circuit) within the active period (501a). For example, within the active period (501a), the clock signal (544-1), which is an EM clock signal, can be transmitted. For example, as the clock signal (544-1) is transmitted to the gate driver circuit (239) within the active period (501a), the gate driver circuit (239) can transmit a light emission signal (or, EM scan signal) to the display panel (210).

[0181] Referring to example (500), the display driving IC (230) can provide (or transmit) a clock signal to the gate driver circuit (239) within the porch period (501b) of the vertical synchronization signal and the active period (502a) of another vertical synchronization signal. The clock signal transmitted within the porch period (501b) of the vertical synchronization signal and the active period (502a) of another vertical synchronization signal can be generated to be transmitted by both the vertical porch signal (571) indicating the porch period (501b) and the vertical synchronization signal (511-2) indicating the active period (502a). For example, the display driving IC (230) can set the value of the first information of the control signal (or register value) provided to the register circuit (e.g., the first register circuit (241) of FIG. 2b) to 11 (or hybrid mode) and generate the clock signal accordingly.

[0182] Referring to the state (521) of the GW clock signal of the example (500), transmission of the GW clock signal from the display driving IC (230) to the gate driver circuit (239) may be interrupted within the porch period (501b) and the active period (502a). For example, the state (521) of the GW clock signal may be changed within the porch period (501b) and the active period (502a). The display driving IC (230) may interrupt transmission of the GW clock signal within the porch period (501b) in response to the vertical porch signal (571) and maintain the state (521) of the GW clock signal at the first level (541-2). When the display driving IC (230) changes from the porch period (501b) to the active period (502a) in response to the vertical synchronization signal (511-2), the state (521) of the GW clock signal can be changed from the first level (541-2) to the second level (541-3) and maintained at the second level (541-3) within the active period (502a). Accordingly, the state (521) of the GW clock signal can be maintained at the first level (541-2) within the porch period (501b) and at the second level (541-3) within the active period (502a). The GW clock signal can be substantially toggled across the porch period (501b) and the active period (502a). Even if the toggle is substantially performed across the porch section (501b) and the active section (502a), the GW clock signal may not be transmitted to the gate driver circuit (239). Since the toggle is substantially performed across the active section (502a) from the porch section (501b) to the active section (502a) rather than within the active section (502a) in which the gate driver circuit (239) is driven by the transmission of the FLM signal (532), the GW clock signal for generating the scan signal may not be transmitted. For example, the GW clock signal may toggle once across the porch section (501b) and the active section (502a).In the example (500) of FIG. 5, the GW clock signal is illustrated as being toggled once, but the present disclosure is not limited thereto.

[0183] For example, within the porch period (501b) of the time period (501), as the transmission of the GW clock signal to the gate driver circuit (239) is interrupted, the gate driver circuit (239) may refrain from transmitting the GW scan signal to the display panel (210). For example, at the start time of the active period (502a) within the time period (502), the state (521) of the GW clock signal may change from the first level (541-2) to the second level (541-3). For example, within the active period (502a) of the time period (502), as the transmission of the GW clock signal to the gate driver circuit (239) is interrupted, the gate driver circuit (239) may refrain from transmitting the GW scan signal to the display panel (210).

[0184] Referring to the state (523) of the GW_o clock signal of the example (500), transmission of the GW_o clock signal from the display driving IC (230) to the gate driver circuit (239) may be stopped within the porch period (501b) and the active period (502a). For example, the state (523) of the GW_o clock signal may be changed within the porch period (501b) and the active period (502a). The display driving IC (230) may stop transmission of the GW_o clock signal within the porch period (501b) in response to the vertical porch signal (571) and maintain the state (523) of the GW_o clock signal at the first level (543-2). When the display driving IC (230) changes from the porch period (501b) to the active period (502a) in response to the vertical synchronization signal (511-2), the state (523) of the GW_o clock signal can be changed from the first level (543-2) to the second level (543-3) and maintained at the second level (543-3) within the active period (502a). Accordingly, the state (523) of the GW_o clock signal can be maintained at the first level (543-2) within the porch period (501b) and at the second level (543-3) within the active period (502a). Even if the GW_o clock signal is substantially toggled across the porch period (501b) and the active period (502a), it may not be transmitted to the gate driver circuit (239). Since the gate driver circuit (239) is not toggled within the active period (502a) driven by the transmission of the FLM signal (532), but is substantially toggled from the porch period (501b) to the active period (502a), the GW_o clock signal for generating the scan signal may not be transmitted. For example, the GW_o clock signal may be toggled once across the porch period (501b) and the active period (502a). In the example (500) of FIG. 5, the GW_o clock signal is illustrated as toggling once, but the present disclosure is not limited thereto.

[0185] For example, within the porch period (501b) of the time period (501), as transmission of the GW_o clock signal to the gate driver circuit (239) is stopped, the gate driver circuit (239) may refrain from transmitting the GW_o scan signal to the display panel (210). For example, within the time period (502), at the start time of the active period (502a), the state (523) of the GW_o clock signal may change from the first level (543-2) to the second level (543-3). Within the active period (502a) of the time period (502), the state (523) of the GW_o clock signal may be maintained at the second level (543-3). For example, within the active period (502a) of the time period (502), as transmission of the GW_o clock signal to the gate driver circuit (239) is stopped, the gate driver circuit (239) may refrain from transmitting the GW_o scan signal to the display panel (210).

[0186] Additionally, referring to example (500), some of the clock signals may be synchronized with respect to the vertical synchronization signal. For example, the display driver IC may start transmitting the clock signals at the time when the vertical synchronization signal (511-2) is provided.

[0187] Referring to the state (522) of the GB clock signal of the example (500), the GB clock signal may be stopped from being transmitted from the display driving IC (230) to the gate driver circuit (239) within the porch period (501b). For example, the state (522) of the GB clock signal may be maintained at the first level (542-2) within the porch period (501b). For example, the state (522) of the GB clock signal being maintained at the first level (542-2) within the porch period (501b) may indicate that the transmission of the GB clock signal from the display driving IC (230) to the gate driver circuit (239) is stopped. For example, within the porch period (501b) of the time period (501), as the transmission of the GB clock signal to the gate driver circuit (239) is stopped, the gate driver circuit (239) may refrain from transmitting the GB scan signal to the display panel (210). The GB clock signal may be transmitted from the display driving IC (230) to the gate driver circuit (239) within the active period (502a). For example, unlike the porch period (501b), the clock signal (542-3), which is a GB clock signal, may be transmitted within the active period (502a). For example, as the clock signal (542-3) is transmitted to the gate driver circuit (239) within the active period (502a), the gate driver circuit (239) may transmit the GB scan signal to the display panel (210).

[0188] Referring to the state (524) of the EM clock signal of the example (500), the EM clock signal may be stopped from being transmitted from the display driving IC (230) to the gate driver circuit (239) within the porch period (501b). For example, the state (524) of the EM clock signal may be maintained at the second level (544-2) within the porch period (501b). For example, the state (524) of the EM clock signal being maintained at the second level (544-2) within the porch period (501b) may indicate that the transmission of the EM clock signal from the display driving IC (230) to the gate driver circuit (239) is stopped. For example, within the porch period (501b) of the time period (501), as transmission of the EM clock signal to the gate driver circuit (239) is stopped, the gate driver circuit (239) may refrain from transmitting an EM scan signal to the display panel (210). The EM clock signal may be transmitted from the display driving IC (230) to the gate driver circuit (239) within the active period (502a). For example, unlike the porch period (501b), the clock signal (544-3), which is an EM clock signal, may be transmitted within the active period (502a). For example, as the clock signal (544-3) is transmitted to the gate driver circuit (239) within the active period (502a), the gate driver circuit (239) may transmit a light emission signal (or an EM scan signal) to the display panel (210).

[0189] In the example (500) of FIG. 5, the display driving IC (230) is illustrated as stopping transmission of a clock signal (e.g., a GW clock signal, a GB clock signal, a GW_o clock signal, an EM clock signal, a GI clock signal) to the gate driver circuit (239) within a porch section, but the present disclosure is not limited thereto. The display driving IC (230) may perform transmission of the clock signal to the gate driver circuit (239) within some porch sections, and stop transmission of the clock signal to the gate driver circuit (239) within other porch sections. For example, the display driving IC (230) can transmit the clock signal to the gate driver circuit (239) within the porch section (501b), stop transmitting the clock signal to the gate driver circuit (239) within the porch section (502b), and transmit the clock signal to the gate driver circuit (239) within the porch section (503b). Alternatively, for example, the display driving IC (230) can transmit the clock signal to the gate driver circuit (239) within the porch section (501b) and the porch section (502b), and stop transmitting the clock signal to the gate driver circuit (239) within the porch section (503b).

[0190] For example, based on the refresh rate (or base frequency) of the display panel (210), or the driving frequency of the display driving IC (230), or the battery level of the electronic device (200) including the display driving IC (230), or the mode of the electronic device (200) (or the display driving IC (230)) for low power consumption (e.g., power saving mode or ultra power saving mode), the display driving IC (230) may stop transmitting the clock signal to the gate driver circuit (239) within all porch periods, or change the number of porch periods during which it stops transmitting the clock signal to the gate driver circuit (239).

[0191] Figure 6 illustrates an example of a method for adjusting the clock frequency of a clock signal transmitted within a porch period of a vertical synchronization signal.

[0192] FIG. 6 illustrates an example (600) of a method for adjusting the clock frequency of a clock signal transmitted within a porch interval of a vertical synchronization signal.

[0193] Example (600) of Fig. 6 may represent a case where the refresh rate of the display panel (210) is 30 Hz, as in Example (500) of Fig. 5. In other words, the length of the porch section (601b) of the vertical synchronization signal of Example (600) of Fig. 6 may be longer than the length of the porch section (101b) of the vertical synchronization signal of Example (105) of Fig. 1B. In Example (600), the active section, the porch section, the active section, and the porch section may be sequentially repeated at the same cycle. Example (600) is merely an example for the convenience of explanation, and the present disclosure is not limited thereto. For example, a method of adjusting the clock frequency of a clock signal transmitted within the porch section of a vertical synchronization signal may also be applied to Example (400) of Fig. 4 or Example (105) of Fig. 1B.

[0194] Referring to FIG. 6, an example (600) illustrates a state (610) of a display panel (210). For the state (610) of the display panel (210), a time interval (601) of a first vertical synchronization signal, a time interval (602) of a second vertical synchronization signal following the first vertical synchronization signal, and a time interval (603) of a third vertical synchronization signal following the second vertical synchronization signal are illustrated.

[0195] For example, each of the time intervals (601, 602, 603) can be defined from a time (or timing, point in time) at which a vertical synchronization signal is provided (or triggered). For example, referring to a state (611) of a vertical synchronization signal, a vertical synchronization signal can be provided (or generated, transmitted). For example, referring to a state (611) of a vertical synchronization signal, a vertical synchronization signal (611-1) (or the first vertical synchronization signal) and a vertical synchronization signal (611-2) (or the second vertical synchronization signal) can be provided. For example, the time interval (601) can start from a time at which the vertical synchronization signal (611-1) is provided. For example, the time interval (602) can start from a time at which the vertical synchronization signal (611-2) is provided. For example, a TE (tearing effect) signal can be synchronized with the vertical synchronization signal. For example, referring to the state (612) of the TE signal, the TE signal may be provided (or transmitted) from the display driver IC (230) to the processor (220) at the time when the vertical synchronization signal (611-1) is provided and at the time when the vertical synchronization signal (611-2) is provided. In addition, for example, the FLM signal may also be synchronized with the vertical synchronization signal. For example, referring to the state (630) of the FLM signal, the FLM signal (631) and the FLM signal (632) may be transmitted from the display driver IC (230) to the gate driver circuit (239) corresponding to the time when the vertical synchronization signal (611-1) is provided and the time when the vertical synchronization signal (611-2) is provided, respectively.

[0196] In the example (600) of FIG. 6, three vertical synchronization signals are illustrated for convenience of explanation, but the present disclosure is not limited thereto. For example, within the time interval (601) of the first vertical synchronization signal, the display driving IC (230) can perform (or execute) the first scan (or address scan). For example, within the time interval (602) of the second vertical synchronization signal, the display driving IC (230) can perform (or execute) the second scan (or self-scan). For example, within the time interval (603) of the third vertical synchronization signal, the display driving IC (230) can perform (or execute) the second scan (or self-scan).

[0197] For example, each of the time intervals (601, 602, 603) of the vertical synchronization signal may include an active interval and a porch interval. For example, the time interval (601) may include an active interval (601a) and a porch interval (601b). The time interval (602) may include an active interval (602a) and a porch interval (602b). The time interval (603) may include an active interval (603a) and a porch interval (603b).

[0198] For example, within the active period (601a) of the time period (601) in which the first scan is performed, data may be provided via MIPI (mobile industry processor interface). For example, the data may be provided from the processor (220) to the display driver IC (230) via MIPI within the active period (601a). Referring to the state (613) of MIPI, the data may be provided from the processor (220) to the display driver IC (230) within the active period (601a). As the data is provided, the source driver circuit (238) may generate a data voltage and provide (or apply, transmit) the data voltage to the display panel (210) (or each of the sub-pixels of the display panel (210). Referring to the state (614) of the source driver, within the active period (602a) (or active period (603a)) of the time period (602) (or time period (603)) in which the second scan is performed, a reference voltage having a fixed voltage level can be provided (or applied, transmitted).

[0199] Referring to Example (600), the display driving IC (230) may provide (or transmit) clock signals to the gate driver circuit (239) to generate a signal (or scan signal) used for scanning (e.g., the first scan or the second scan) in the display panel (210). In Example (600), for convenience of explanation, a GW clock signal, a GB clock signal, a GW_o clock signal, and an EM clock signal are exemplified, but the present disclosure is not limited thereto. For example, the clock signals may further include a GI clock signal.

[0200] Referring to example (600), each of the clock signals may be synchronized with respect to a vertical synchronization signal. For example, the clock signals may begin to be provided (or transmitted) from the time the vertical synchronization signal (611-1) is provided, or the provision (or transmission) may begin to cease.

[0201] Referring to the state (621) of the GW clock signal of example (600), the GW clock signal can be transmitted from the display driving IC (230) to the gate driver circuit (239) within the active period (601a). For example, within the active period (601a), a clock signal (641-1), which is a GW clock signal, can be transmitted. For example, as the clock signal (641-1) is transmitted to the gate driver circuit (239) within the active period (601a), the gate driver circuit (239) can transmit a GW scan signal to the display panel (210).

[0202] Referring to the state (622) of the GB clock signal of example (600), the GB clock signal can be transmitted from the display driving IC (230) to the gate driver circuit (239) within the active period (601a). For example, a clock signal (642-1), which is a GB clock signal, can be transmitted within the active period (601a). For example, as the clock signal (642-1) is transmitted to the gate driver circuit (239) within the active period (601a), the gate driver circuit (239) can transmit a GB scan signal to the display panel (210).

[0203] Referring to the state (623) of the GW_o clock signal of example (600), the GW_o clock signal can be transmitted from the display driving IC (230) to the gate driver circuit (239) within the active period (601a). For example, within the active period (601a), the clock signal (643-1), which is the GW_o clock signal, can be transmitted. For example, as the clock signal (643-1) is transmitted to the gate driver circuit (239) within the active period (601a), the gate driver circuit (239) can transmit a GW_o scan signal to the display panel (210).

[0204] Referring to the state (624) of the EM clock signal of example (600), the EM clock signal can be transmitted from the display driving IC (230) to the gate driver (or gate driver circuit) within the active period (601a). For example, within the active period (601a), the clock signal (644-1), which is an EM clock signal, can be transmitted. For example, as the clock signal (644-1) is transmitted to the gate driver circuit (239) within the active period (601a), the gate driver circuit (239) can transmit a light emission signal (or, EM scan signal) to the display panel (210).

[0205] For example, the display driving IC (230) can provide (or transmit) a clock signal to the gate driver circuit (239) within the porch period (601b) of the vertical synchronization signal and the active period (602a) of another vertical synchronization signal. The clock signal transmitted within the porch period (601b) of the vertical synchronization signal and the active period (602a) of another vertical synchronization signal can be generated to be transmitted by both the vertical porch signal (671) indicating the porch period (601b) and the vertical synchronization signal (611-2) indicating the active period (602a). For example, the display driving IC (230) can set the value of the first information of the control signal provided to the register circuit (e.g., the first register circuit (241) of FIG. 2b) to 11 (or hybrid mode) and generate the clock signal accordingly.

[0206] Referring to the state (621) of the GW clock signal of the example (600), transmission of the GW clock signal from the display driving IC (230) to the gate driver circuit (239) may be interrupted within the porch period (601b) and the active period (602a). For example, the state (621) of the GW clock signal may be changed within the porch period (601b) and the active period (602a). The display driving IC (230) may interrupt transmission of the GW clock signal within the porch period (601b) in response to the vertical porch signal (671) and maintain the state (621) of the GW clock signal at the first level (641-2). When the display driving IC (230) changes from the porch period (601b) to the active period (602a) in response to the vertical synchronization signal (611-2), the state (621) of the GW clock signal can be changed from the first level (641-2) to the second level (641-3) and maintained at the second level (641-3) within the active period (602a). Accordingly, the state (621) of the GW clock signal can be maintained at the first level (641-2) within the porch period (601b) and at the second level (641-3) within the active period (602a). The GW clock signal can be substantially toggled across the porch period (601b) and the active period (602a). Even if the toggle is substantially performed across the porch period (601b) and the active period (602a), the GW clock signal may not be transmitted to the gate driver circuit (239). Since the toggle is substantially performed across the active period (602a) from the porch period (601b) to the active period (602a) rather than within the active period (602a) in which the gate driver circuit (239) is driven by the transmission of the FLM signal (632), the GW clock signal for generating the scan signal may not be transmitted. For example, the GW clock signal may toggle once across the porch period (601b) and the active period (602a).In the example (600) of FIG. 6, the GW clock signal is illustrated as being toggled once, but the present disclosure is not limited thereto.

[0207] For example, within the porch period (601b) of the time period (601), as the transmission of the GW clock signal to the gate driver circuit (239) is interrupted, the gate driver circuit (239) may refrain from transmitting the GW scan signal to the display panel (210). For example, at the start time of the active period (602a) within the time period (602), the state (621) of the GW clock signal may change from the first level (641-2) to the second level (641-3). For example, within the active period (602a) of the time period (602), as the transmission of the GW clock signal to the gate driver circuit (239) is interrupted, the gate driver circuit (239) may refrain from transmitting the GW scan signal to the display panel (210).

[0208] Referring to the state (623) of the GW_o clock signal of the example (600), transmission of the GW_o clock signal from the display driving IC (230) to the gate driver circuit (239) may be stopped within the porch period (601b) and the active period (602a). For example, the state (623) of the GW_o clock signal may be changed within the porch period (601b) and the active period (602a). The display driving IC (230) may stop transmission of the GW_o clock signal within the porch period (601b) in response to the vertical porch signal (671) and maintain the state (623) of the GW_o clock signal at the first level (643-2). When the display driving IC (230) changes from the porch period (601b) to the active period (602a) in response to the vertical synchronization signal (611-2), the state (623) of the GW_o clock signal can be changed from the first level (643-2) to the second level (643-3) and maintained at the second level (643-3) within the active period (602a). Accordingly, the GW_o clock signal can be maintained at the first level (643-2) within the porch period (601b) and at the second level (643-3) within the active period (602a). The GW_o clock signal can be substantially toggled across the porch period (601b) and the active period (602a). Even if the toggle is substantially performed across the porch section (601b) and the active section (602a), it may not be transmitted to the gate driver circuit (239). Since the toggle is substantially performed across the active section (602a) from the porch section (601b) to the active section (602a) rather than within the active section (602a) in which the gate driver circuit (239) is driven by the transmission of the FLM signal (632), the GW_o clock signal for generating the scan signal may not be transmitted. For example, the GW_o clock signal may toggle once across the porch section (601b) and the active section (602a).In the example (600) of FIG. 6, the GW_o clock signal is illustrated as being toggled once, but the present disclosure is not limited thereto.

[0209] For example, within the porch period (601b) of the time period (601), as the transmission of the GW_o clock signal to the gate driver circuit (239) is interrupted, the gate driver circuit (239) may refrain from transmitting the GW_o scan signal to the display panel (210). For example, at the start time of the active period (602a) within the time period (602), the state (623) of the GW_o clock signal may change from the first level (643-2) to the second level (643-3). For example, within the active period (602b) of the time period (602), as the transmission of the GW_o clock signal to the gate driver circuit (239) is interrupted, the gate driver circuit (239) may refrain from transmitting the GW_o scan signal to the display panel (210).

[0210] For example, the display driving IC (230) can provide (or transmit) a clock signal to the gate driver circuit (239) within the porch section (601b) of the vertical synchronization signal. The display driving IC (230) can adjust the clock frequency of the clock signal transmitted within the porch section (601b). For example, the display driving IC (230) can set the value of the first information of the control signal (or register value) provided to the register circuit (e.g., the first register circuit (241) of FIG. 2b) to 01 (or V-porch mode), set the value of the second information of the control signal (or register value) to 1 (or Enable), and set the value of the third information of the control information (or register value) to one of the candidate frequency values. For example, the candidate frequency value can indicate that the clock signal toggles three times within the porch section (601b). The display driving IC (230) can generate the clock signal according to the value of the control signal.

[0211] Referring to the state (622) of the GB clock signal of the example (600), the GB clock signal can be transmitted from the display driving IC (230) to the gate driver circuit (239) within the porch period (601b). For example, a clock signal (642-2), which is a GB clock signal, can be transmitted within the porch period (601b). The number of toggles of the clock signal (642-2) within the porch period (601b) can be 3. The clock frequency (or toggle number) of the clock signal (642-2) transmitted within the porch period (601b) can be lower (or less) than the clock frequency (or toggle number) of the clock signal (642-1) transmitted within the active period (601a). For example, the pulse width (or length) of each of the pulse signals (e.g., three pulse signals) included in the clock signal (642-2) may be longer than the pulse width of each of the pulse signals included in the clock signal (642-1). In each of the time periods having the same time length (e.g., the time length of the active period (601a) and the time length of the porch period (601b)), the higher the clock frequency (or toggle count) of the clock signal, the shorter the pulse width of each of the pulse signals of the clock signal. For example, even if the clock signal (642-2) is transmitted to the gate driver circuit (239) within the porch period (601b), the gate driver circuit (239) may stop (or refrain from) transmitting the GB scan signal to the display panel (210) because the FLM signal for the clock signal (642-2) is not provided.

[0212] Referring to the state (624) of the EM clock signal of example (600), the EM clock signal can be transmitted from the display driving IC (230) to the gate driver circuit (239) within the porch period (601b). For example, a clock signal (644-2), which is an EM clock signal, can be transmitted within the porch period (601b). The number of toggles of the clock signal (644-2) within the porch period (601b) can be 3. The clock frequency (or toggle number) of the clock signal (644-2) transmitted within the porch period (601b) can be lower (or less) than the clock frequency (or toggle number) of the clock signal (644-1) transmitted within the active period (601a). In example (600), the clock frequency of the EM clock signal transmitted within the porch section (601b) and the clock frequency of the GB clock signal correspond, but the present disclosure is not limited thereto. For example, the clock frequency of the EM clock signal transmitted within the porch section (601b) may be different from the clock frequency of the GB clock signal transmitted within the porch section (601b). For example, even if the clock signal (644-2) is transmitted to the gate driver circuit (239) within the porch section (601b), the gate driver circuit (239) may stop (or refrain from) transmitting the light emission signal (or EM scan signal) to the display panel (210) because the FLM signal for the clock signal (644-2) is not provided.

[0213] Referring to example (600), the display driving IC (230) can transmit a clock signal to the gate driver circuit (239) at a time when the vertical synchronization signal (611-2) is provided (or during the active period (602a) of the vertical synchronization signal (611-2)). Referring to the state (622) of the GB clock signal of example (600), the GB clock signal can be transmitted from the display driving IC (230) to the gate driver circuit (239) within the active period (602a). For example, a clock signal (642-3), which is a GB clock signal, can be transmitted within the active period (602a). For example, as the clock signal (642-3) is transmitted to the gate driver circuit (239) within the active period (602a), the gate driver circuit (239) circuit can transmit a GB scan signal to the display panel (210). Referring to the state (624) of the EM clock signal of example (600), the EM clock signal can be transmitted from the display driving IC (230) to the gate driver (or gate driver circuit) within the active period (602a). For example, within the active period (602a), the clock signal (644-3), which is an EM clock signal, can be transmitted. For example, as the clock signal (644-3) is transmitted to the gate driver circuit (239) within the active period (602a), the gate driver circuit (239) can transmit a light emission signal (or, EM scan signal) to the display panel (210).

[0214] Referring to the example (600) of FIG. 6, unlike the example (105) of FIG. 1b, the example (400) of FIG. 4, or the example (500) of FIG. 5, the display driving IC (230) may adjust (or lower) the clock frequency used in transmission, rather than stopping transmission of some clock signals (e.g., GB clock signals and EM clock signals) within the porch period (e.g., porch period 601b). Accordingly, the power consumption within the porch period is reduced, and changes in the bias characteristics of the gate driver circuit (239), which may be caused by stopping transmission of some clock signals within the porch period (or by maintaining the clock signals at a specific state (or voltage level)), may be minimized (or suppressed, reduced).

[0215] In the example (600) of FIG. 6, the display driving IC (230) is illustrated as stopping transmission of some clock signals (e.g., GW clock signal, GW_o clock signal) to the gate driver circuit (239) within the porch period, but the present disclosure is not limited thereto. The display driving IC (230) may perform transmission of some clock signals to the gate driver circuit (239) within some porch periods, and stop transmission of some clock signals to the gate driver circuit (239) within other porch periods. For example, the display driving IC (230) may perform transmission of some clock signals to the gate driver circuit (239) within the porch period (601b), stop transmission of some clock signals to the gate driver circuit (239) within the porch period (602b), and perform transmission of some clock signals to the gate driver circuit (239) within the porch period (603b). Alternatively, for example, the display driving IC (230) may transmit some of the clock signals to the gate driver circuit (239) within the porch section (601b) and the porch section (602b), and may stop transmitting some of the clock signals to the gate driver circuit (239) within the porch section (603b).

[0216] For example, based on the refresh rate (or base frequency) of the display panel (210), or the driving frequency of the display driving IC (230), or the battery level of the electronic device (200) including the display driving IC (230), or the mode of the electronic device (200) (or the display driving IC (230)) for low power consumption (e.g., power saving mode or ultra power saving mode), the display driving IC (230) may stop transmitting some of the clock signals to the gate driver circuit (239) within all porch periods, or change the number of porch periods during which it stops transmitting some of the clock signals to the gate driver circuit (239).

[0217] Figure 7 illustrates examples of images to be displayed through a display panel of an electronic device in a low power mode.

[0218] FIG. 7 illustrates examples of images (710, 720, 730) to be displayed through the display panel (210) within the low-power mode of the display driving IC (230). In the example illustrated in FIG. 7, for convenience of explanation, images (710, 720, 730) representing a watch (or watch face) are illustrated, but the present disclosure is not limited thereto.

[0219] For example, the display driving IC (230) can display an image (710) representing an analog clock within the low-power mode. For example, the display driving IC (230) can display an image (710) included in the low-power screen (or AOD screen) through the display panel (210) within the low-power mode.

[0220] For example, the display driving IC (230) can display an image (720) representing a digital clock within the low-power mode. For example, the display driving IC (230) can display an image (720) included in the low-power screen (or AOD screen) through the display panel (210) within the low-power mode.

[0221] For example, the display driving IC (230) can display an image (730) representing a digital clock including a background image within the low-power mode. For example, the display driving IC (230) can display an image (730) included in the low-power screen (or AOD screen) through the display panel (210) within the low-power mode.

[0222] In the example of FIG. 7, the display driving IC (230) can identify an image to be displayed within the low-power mode. For example, the display driving IC (230) can obtain an image to be displayed within the low-power mode based on obtaining an input (or user input) for setting an image to be displayed within the low-power mode. Alternatively, for example, the display driving IC (230) can identify an image to be displayed within the low-power mode based on executing the low-power mode.

[0223] For example, the display driving IC (230) can identify a brightness parameter for an image to be displayed within the low-power mode. For example, the brightness parameter may include at least one of an on-pixel ratio (OPR) indicating the number of sub-pixels for displaying the image among the sub-pixels of the display panel (210), illuminance outside the electronic device (200) (or the display panel (210)), or luminance of the display panel (210). As a non-limiting example, when the brightness parameter is the OPR, the first criterion may indicate a case where the OPR is 10% or less, the second criterion may indicate a case where the OPR is more than 10% and less than or equal to 15%, and the third criterion may indicate a case where the OPR is more than 15% and less than or equal to 25%. The number of criteria of the present disclosure and the range (or criterion values) of each of the criteria are not limited to the examples above.

[0224] In the example of FIG. 7, it is assumed that the brightness parameter (or OPR) of the image (710) satisfies the first criterion, the brightness parameter (or OPR) of the image (720) satisfies the second criterion, and the brightness parameter (or OPR) of the image (730) satisfies the third criterion. For example, when the image (710) is displayed, the display driving IC (230) may determine the clock frequency for the time period of at least one vertical synchronization signal during which the image (710) is displayed as the first clock frequency, upon determining that the brightness parameter of the image (710) satisfies the first criterion. For example, the first clock frequency may indicate that the clock signal toggles once within the time period. Alternatively, when the image (720) is displayed, the display driving IC (230) may determine the clock frequency for the time period of at least one vertical synchronization signal during which the image (720) is displayed as the second clock frequency upon determining that the brightness parameter of the image (720) satisfies the second criterion. For example, the second clock frequency may indicate that the clock signal toggles four times within the time period. Alternatively, when the image (730) is displayed, the display driving IC (230) may determine the clock frequency for the time period of at least one vertical synchronization signal during which the image (730) is displayed as the third clock frequency upon determining that the brightness parameter of the image (730) satisfies the third criterion. For example, the third clock frequency may indicate that the clock signal toggles eight times within the time period.

[0225] In the above-described example, the display driving IC (230) can set the third information of the control signal (or register value) used to generate the clock signal to a value corresponding to the determined clock frequency. The display driving IC (230) can generate the clock signal using the control signal including the set third information, and transmit the generated clock signal to the gate driver circuit (239). For specific examples of adjusting the clock frequency of a clock signal to be transmitted within a specific time interval and transmitting a clock signal having the adjusted clock frequency, reference may be made to FIGS. 8A to 8C below.

[0226] FIGS. 8A to 8C illustrate examples of a method for transmitting a clock signal having a clock frequency according to an image to be displayed through a display panel.

[0227] FIGS. 8A to 8C illustrate examples (800-1, 800-2, 800-3) of a method for transmitting a clock signal having a clock frequency according to an image to be displayed through a display panel (210).

[0228] Examples (800-1, 800-2, 800-3) of FIGS. 8A to 8C may represent a case where the refresh rate of the display panel (210) is 30 Hz, similar to example (500) of FIG. 5. In other words, the length of the porch section (801b) of the vertical synchronization signal of examples (800-1, 800-2, 800-3) of FIGS. 8A to 8C may be longer than the length of the porch section (101b) of the vertical synchronization signal of example (105) of FIG. 1B. In example (800), an active section, a porch section, an active section, and a porch section may be sequentially repeated at the same cycle. Examples (800-1, 800-2, 800-3) are merely exemplary for convenience of explanation, and the present disclosure is not limited thereto. For example, the method of adjusting the clock frequency of a clock signal transmitted within the porch interval of a vertical synchronization signal can also be applied to the example (400) of FIG. 4 or the example (105) of FIG. 1b.

[0229] Referring to FIGS. 8A to 8C, examples (800-1, 800-2, 800-3) each illustrate a state (810) of the display panel (210). For the state (810) of the display panel (210), a time interval (801) of a first vertical synchronization signal, a time interval (802) of a second vertical synchronization signal following the first vertical synchronization signal, and a time interval (803) of a third vertical synchronization signal following the second vertical synchronization signal are illustrated.

[0230] In the examples (800-1, 800-2, 800-3) of FIGS. 8A to 8C, the case where the clock frequency of the GB clock signal is adjusted according to the image to be displayed through the display panel (210) is illustrated, but the present disclosure is not limited thereto. The method of adjusting the clock frequency of the clock signal transmitted within the porch section of the vertical synchronization signal can also be applied to other clock signals (e.g., GW clock signal, GW_o clock signal, EM clock signal, GI clock signal).

[0231] Referring to examples (800-1, 800-2, 800-3) of FIGS. 8A to 8C, each of the time intervals (801, 802, 803) may be defined from a time (or timing, point in time) at which a vertical synchronization signal is provided (or triggered). For example, referring to a state (811) of a vertical synchronization signal, a vertical synchronization signal may be provided (or generated, transmitted). For example, referring to a state (811) of a vertical synchronization signal, a vertical synchronization signal (811-1) (or the first vertical synchronization signal) and a vertical synchronization signal (811-2) (or the second vertical synchronization signal) may be provided. For example, a time interval (801) may start from a time at which a vertical synchronization signal (811-1) is provided. For example, a time interval (802) may start from a time at which a vertical synchronization signal (811-2) is provided. For example, with respect to the vertical synchronization signal, a TE (tearing effect) signal can be synchronized. For example, referring to the state (812) of the TE signal, the TE signal can be provided (or transmitted) from the display driver IC (230) to the processor (220) at the time when the vertical synchronization signal (811-1) is provided and at the time when the vertical synchronization signal (811-2) is provided. In addition, for example, an FLM signal can also be synchronized with the vertical synchronization signal. For example, referring to the state (830) of the FLM signal, an FLM signal (831) and an FLM signal (832) corresponding to the time when the vertical synchronization signal (811-1) is provided and the time when the vertical synchronization signal (811-2) is provided, respectively, can be transmitted from the display driver IC (230) to the gate driver circuit (239).

[0232] In examples (800-1, 800-2, 800-3) of FIGS. 8A to 8C, three vertical synchronization signals are illustrated for convenience of explanation, but the present disclosure is not limited thereto. For example, within the time interval (801) of the first vertical synchronization signal, the display driving IC (230) can perform (or execute) the first scan (or address scan). For example, within the time interval (802) of the second vertical synchronization signal, the display driving IC (230) can perform (or execute) the second scan (or self-scan). For example, within the time interval (803) of the third vertical synchronization signal, the display driving IC (230) can perform (or execute) the second scan (or self-scan).

[0233] For example, each of the time intervals (801, 802, 803) of the vertical synchronization signal may include an active interval and a porch interval. For example, the time interval (801) may include an active interval (801a) and a porch interval (801b). The time interval (802) may include an active interval (802a) and a porch interval (802b). The time interval (803) may include an active interval (803a) and a porch interval (803b).

[0234] For example, within the active period (801a) of the time period (801) in which the first scan is performed, data may be provided via MIPI (mobile industry processor interface). For example, the data may be provided from the processor (220) to the display driver IC (230) via MIPI within the active period (801a). Referring to the state (813) of MIPI, the data may be provided from the processor (220) to the display driver IC (230) within the active period (801a). As the data is provided, the source driver circuit (238) may generate a data voltage and provide (or apply, transmit) the data voltage to the display panel (210) (or each of the sub-pixels of the display panel (210). Referring to the state (814) of the source driver, within the active period (802a) (or active period (803a)) of the time period (802) (or time period (803)) in which the second scan is performed, a reference voltage having a fixed voltage level can be provided (or applied, transmitted).

[0235] Referring to examples (800-1, 800-2, 800-3), the display driving IC (230) may provide (or transmit) clock signals to the gate driver circuit (239) to generate a signal (or scan signal) used for scanning (e.g., the first scan or the second scan) in the display panel (210). Referring to examples (800-1, 800-2, 800-3), the GB clock signal may be synchronized with the vertical synchronization signal. For example, the GB clock signal may start to be provided (or transmitted) from the time the vertical synchronization signal (811-1) is provided, or the provision (or transmission) thereof may start to be stopped. Referring to the state (822) of the GB clock signal of examples (800-1, 800-2, 800-3), the GB clock signal can be transmitted from the display driving IC (230) to the gate driver circuit (239) within the active period (801a). For example, within the active period (801a), a clock signal (842-1), which is a GB clock signal, can be transmitted. For example, as the clock signal (842-1) is transmitted to the gate driver circuit (239) within the active period (801a), the gate driver circuit (239) can transmit a GB scan signal to the display panel (210).

[0236] For example, the display driving IC (230) can provide (or transmit) a GB clock signal synchronized with respect to the porch period of the vertical synchronization signal to the gate driver circuit (239). For example, the GB clock signal can start to be provided (or transmitted) from the time the vertical porch signal (871) is provided, or the provision (or transmission) can start to be stopped.

[0237] Referring to the state (822) of the GB clock signal in the example (800-1) of FIG. 8A, transmission of the GB clock signal from the display driving IC (230) to the gate driver circuit (239) may be interrupted within the porch period (801b) and the active period (802a). For example, the state (822) of the GB clock signal may be changed within the porch period (801b) and the active period (802a). The display driving IC (230) may interrupt transmission of the GB clock signal within the porch period (801b) in response to the vertical porch signal (871) and maintain the state (822) of the GB clock signal at the first level (842-2). When the display driving IC (230) changes from the porch period (801b) to the active period (802a) in response to the vertical synchronization signal (811-2), the state (822) of the GB clock signal can be changed from the first level (842-2) to the second level (842-3) and maintained at the second level (842-3) within the active period (802a). Accordingly, the state (842) of the GB clock signal can be maintained at the first level (842-2) within the porch period (801b) and at the second level (842-3) within the active period (802a). The GB clock signal can be substantially toggled across the porch period (801b) and the active period (802a). Even if the toggle is substantially performed across the porch section (801b) and the active section (802a), the GB clock signal may not be transmitted to the gate driver circuit (239). Since the toggle is substantially performed across the active section (802a) from the porch section (801b) to the active section (802a) rather than within the active section (802a) in which the gate driver circuit (239) is driven by the transmission of the FLM signal (832), the GB clock signal for generating the scan signal may not be transmitted.For example, the pulse width of a pulse signal (e.g., one pulse signal) included in the GB clock signal may be longer than the pulse width of each of the pulse signals included in the GB clock signal.

[0238] For example, within the porch period (801b) of the time period (801), as the transmission of the GB clock signal to the gate driver circuit (239) is interrupted, the gate driver circuit (239) may refrain from transmitting the GB scan signal to the display panel (210). For example, at the start time of the active period (802a) within the time period (802), the state (822) of the GB clock signal may change from the first level (842-2) to the second level (842-3). For example, within the active period (802a) of the time period (802), as the transmission of the GB clock signal to the gate driver circuit (239) is interrupted, the gate driver circuit (239) may refrain from transmitting the GB scan signal to the display panel (210).

[0239] For example, the display driving IC (230) may generate a GB clock signal of example (800-1) using the control signal (or register value) including the third information indicating the first clock frequency determined based on identifying that the image (710) of FIG. 7 is to be displayed, and may be toggled once within the porch period (801b) and the active period (802a). In example (800-1), the GB clock signal may have the first clock frequency for the porch period (801b) and the active period (802a). The clock frequency of the clock signal (842-1) transmitted within the active period (801a) of examples (800-1, 800-2, 800-3) may be higher than the first clock frequency.

[0240] Referring to the state (822) of the GB clock signal in the example (800-2) of FIG. 8b, the GB clock signal can be transmitted from the display driving IC (230) to the gate driver circuit (239) within the porch period (801b). For example, the clock signal (842-4), which is a GB clock signal, can be transmitted within the porch period (801b). The display driving IC (230) can transmit the clock signal (842-4) to the gate driver circuit (239) within the porch period (801b) in response to the vertical porch signal (871). For example, the clock signal (842-4) can be toggled four times within the porch period (801b). For example, the pulse width of each of the pulse signals (e.g., four pulse signals) included in the clock signal (842-4) may be longer than the pulse width of each of the pulse signals included in the clock signal (842-1). For example, the pulse width of each of the pulse signals (e.g., four pulse signals) included in the clock signal (842-4) may be shorter than the pulse width of a pulse signal (e.g., one pulse signal) included in the GB clock signal having the first clock frequency of example (800-1). For example, within the porch period (801b), even if the clock signal (842-4) is transmitted to the gate driver circuit (239), since the FLM signal for the clock signal (842-4) is not provided, the gate driver circuit (239) may stop (or refrain from) transmitting the GB scan signal to the display panel (210).

[0241] For example, the display driver IC (230) may transmit the clock signal (842-4) of example (800-2) generated using the control signal (or register value) including the third information indicating the second clock frequency determined based on identifying that the image (720) of FIG. 7 is to be displayed, to the gate driver circuit (239), within the porch period (801b). In example (800-2), the clock signal (842-4) may have the second clock frequency for the porch period (801b). Furthermore, in example (800-2) of FIG. 8b, the display driver IC (230) may transmit another clock signal to the gate driver circuit (239) within the active period (802a) in response to the vertical synchronization signal (811-2). For example, the other clock signal of example (800-2) may be transmitted continuously to the clock signal (842-4). For example, the clock frequency of the other clock signal of example (800-2) may correspond to the second clock frequency of the clock signal (842-4).

[0242] Referring to the state (822) of the GB clock signal in the example (800-3) of FIG. 8c, the GB clock signal can be transmitted from the display driving IC (230) to the gate driver circuit (239) within the porch period (801b). For example, the clock signal (842-5), which is a GB clock signal, can be transmitted within the porch period (801b). The display driving IC (230) can transmit the clock signal (842-5) to the gate driver circuit (239) within the porch period (801b) in response to the vertical porch signal (871). For example, the clock signal (842-5) can be toggled eight times within the porch period (801b). For example, the pulse width of each of the pulse signals (e.g., eight pulse signals) included in the clock signal (842-4) may be longer than the pulse width of each of the pulse signals included in the clock signal (842-1). For example, the pulse width of each of the pulse signals (e.g., eight pulse signals) included in the clock signal (842-5) may be shorter than the pulse width of each of the pulse signals (e.g., four pulse signals) included in the clock signal (842-4). For example, within the porch period (801b), even if the clock signal (842-5) is transmitted to the gate driver circuit (239), since the FLM signal for the clock signal (842-5) is not provided, the gate driver circuit (239) may stop (or refrain from) transmitting the GB scan signal to the display panel (210).

[0243] For example, the display driver IC (230) may transmit a clock signal (842-5) of example (800-3) generated using the control signal (or register value) including the third information indicating the third clock frequency determined based on identifying that the image (730) of FIG. 7 is to be displayed, to the gate driver circuit (239) within the porch period (801b). In example (800-3), the clock signal (842-5) may have the third clock frequency for the porch period (801b). Furthermore, in example (800-3) of FIG. 8c, the display driver IC (230) may transmit another clock signal to the gate driver circuit (239) within the active period (802a) in response to the vertical synchronization signal (811-2). For example, the other clock signal of example (800-3) may be transmitted consecutively to the clock signal (842-5). For example, the clock frequency of the other clock signal of example (800-3) may correspond to the third clock frequency of the clock signal (842-5).

[0244] Referring to FIGS. 7 to 8C, the display driving IC (230) may provide (or apply) periodic bias power to the source electrode of the driving transistor (e.g., the first transistor (301) of FIG. 3) in order to reduce flickering that may be visible through the display panel (210) within the low-power mode. As a non-limiting example, the flickering may be relatively more easily visible when displaying a specific image (e.g., the image (730) of FIG. 7) according to the brightness parameter than when displaying another image (e.g., the image (710) of FIG. 7). The display driving IC (230) may reduce the flickering by dynamically increasing the clock frequency (or clock count) of a clock signal (e.g., a GB clock signal) within a porch period (and / or an active period) of a vertical synchronization signal while displaying a specific image (e.g., the image (730) of FIG. 7). In addition, the display driving IC (230) can increase the effect of reducing power consumption by dynamically lowering the clock frequency (or clock count) of the clock signal (e.g., GB clock signal) within the porch period (and / or active period) of the vertical synchronization signal while displaying another image (e.g., image (710) of FIG. 7) in which the flickering is relatively less noticeable.

[0245] FIG. 9 illustrates an example of a graph showing changes in current consumption as transmission of a clock signal is controlled within a porch period of a vertical synchronization signal.

[0246] Fig. 9 illustrates an example of a graph (900) representing current consumption when controlling transmission of a clock signal within a porch period of a vertical synchronization signal. The horizontal axis of the graph (900) may represent time (unit: milliseconds (ms)), and the vertical axis of the graph (900) may represent current (unit: milliamps (mA)). As the current consumption increases, the power consumption may increase.

[0247] The graph (900) includes a first line (910) representing current consumed by controlling (or stopping) transmission of a clock signal at a start time of an active period of a vertical synchronization signal and a start time of a porch period of a vertical synchronization signal, as in FIG. 1B. The graph (900) includes a first reference value (921) and a second reference value (922). For example, the first reference value (921) may represent an average current value (about 5.0 mA) in an active period while performing the first scan. For example, the second reference value (922) may represent an average current value (about 1.0 mA) in an active period while performing the second scan.

[0248] Referring to the first line (910), the current consumed within the active section (911a) of the time section (911) of the vertical synchronization signal in which the first scan is performed may be a first reference value (921) (approximately 5.0 mA). The current consumed within the porch section (911b) of the time section (911) of the vertical synchronization signal in which the first scan is performed may be a value between about 0.5 and 0.8 mA, which is lower than the second reference value (922) (approximately 1.0 mA). The current consumed within the active section (912a) of the time section (912) of the vertical synchronization signal in which the second scan is performed may be a second reference value (922) (approximately 1.0 mA). The current consumed within the porch section (912b) of the time section (912) of the vertical synchronization signal during which the second scan is performed may be about 0.5 mA, which is lower than the second reference value (922) (about 1.0 mA).

[0249] In contrast, the second line (950) represents the current consumed by controlling (or stopping) the transmission of the clock signal at the start time of the active period of the vertical synchronization signal among the start time of the active period of the vertical synchronization signal and the start time of the porch period of the vertical synchronization signal, as in FIG. 1A. Referring to the second line (950), the current consumed within the active period (952a) of the time period (952) of the vertical synchronization signal during which the second scan is performed may be the second reference value (922) (about 1.0 mA). The current consumed within the porch period (952b) of the time period (952) of the vertical synchronization signal during which the second scan is performed may be about 0.8 mA, which is lower than the second reference value (922) (about 1.0 mA).

[0250] When comparing the time periods (912, 952) during which the second scan is performed, substantially the same value of current is consumed within the active periods (912a, 952a), but a different value of current may be consumed by the difference (930) within the porch periods (912b, 952b). More specifically, the amount of current consumed when controlling the transmission of the clock signal at both the start time of the active period of the vertical synchronization signal and the start time of the porch period of the vertical synchronization signal may be less than the amount of current consumed when controlling the transmission of the clock signal only at the start time of the active period of the vertical synchronization signal by the difference (930). The electronic device and method according to the present disclosure can reduce power consumption and increase the usage time (or DoU (day of usage)) of an electronic device (e.g., electronic device (200)) by controlling the transmission of the clock signal at both the start time of the active period of the vertical synchronization signal and the start time of the porch period of the vertical synchronization signal.

[0251] The effects that can be obtained from the present disclosure are not limited to the effects mentioned above, and other effects that are not mentioned can be clearly understood by a person having ordinary skill in the art to which the present disclosure belongs from the description below.

[0252] FIG. 10 is a block diagram of an electronic device within a network environment according to various embodiments.

[0253] Referring to FIG. 10, in a network environment (1000), an electronic device (1001) may communicate with an electronic device (1002) via a first network (1098) (e.g., a short-range wireless communication network), or may communicate with at least one of an electronic device (1004) or a server (1008) via a second network (1099) (e.g., a long-range wireless communication network). According to one embodiment, the electronic device (1001) may communicate with the electronic device (1004) via the server (1008). According to one embodiment, the electronic device (1001) may include a processor (1020), a memory (1030), an input module (1050), an audio output module (1055), a display module (1060), an audio module (1070), a sensor module (1076), an interface (1077), a connection terminal (1078), a haptic module (1079), a camera module (1080), a power management module (1088), a battery (1089), a communication module (1090), a subscriber identification module (1096), or an antenna module (1097). In some embodiments, the electronic device (1001) may omit at least one of these components (e.g., the connection terminal (1078)), or may have one or more other components added. In some embodiments, some of these components (e.g., sensor module (1076), camera module (1080), or antenna module (1097)) may be integrated into a single component (e.g., display module (1060)).

[0254] The processor (1020) may, for example, execute software (e.g., a program (1040)) to control at least one other component (e.g., a hardware or software component) of the electronic device (1001) connected to the processor (1020) and perform various data processing or operations. According to one embodiment, as at least a part of the data processing or operations, the processor (1020) may store commands or data received from other components (e.g., a sensor module (1076) or a communication module (1090)) in the volatile memory (1032), process the commands or data stored in the volatile memory (1032), and store result data in the non-volatile memory (1034). According to one embodiment, the processor (1020) may include a main processor (1021) (e.g., a central processing unit or an application processor) or a secondary processor (1023) (e.g., a graphics processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) that can operate independently or together with the main processor (1021). For example, when the electronic device (1001) includes the main processor (1021) and the secondary processor (1023), the secondary processor (1023) may be configured to use less power than the main processor (1021) or to be specialized for a given function. The secondary processor (1023) may be implemented separately from the main processor (1021) or as a part thereof.

[0255] The auxiliary processor (1023) may control at least a portion of functions or states associated with at least one component (e.g., the display module (1060), the sensor module (1076), or the communication module (1090)) of the electronic device (1001), for example, on behalf of the main processor (1021) while the main processor (1021) is in an inactive (e.g., sleep) state, or together with the main processor (1021) while the main processor (1021) is in an active (e.g., application execution) state. In one embodiment, the auxiliary processor (1023) (e.g., an image signal processor or a communication processor) may be implemented as a part of another functionally related component (e.g., a camera module (1080) or a communication module (1090)). In one embodiment, the auxiliary processor (1023) (e.g., a neural network processing unit) may include a hardware structure specialized for processing artificial intelligence models. The artificial intelligence models may be generated through machine learning. This learning can be performed, for example, on the electronic device (1001) itself where the artificial intelligence model is executed, or can be performed through a separate server (e.g., server (1008)). The learning algorithm can include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but is not limited to the examples described above. The artificial intelligence model can include multiple artificial neural network layers.The artificial neural network may be one of a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to, or alternatively to, a hardware structure, an artificial intelligence model may include a software structure.

[0256] The memory (1030) can store various data used by at least one component (e.g., the processor (1020) or the sensor module (1076)) of the electronic device (1001). The data can include, for example, software (e.g., the program (1040)) and input data or output data for commands related thereto. The memory (1030) can include volatile memory (1032) or non-volatile memory (1034).

[0257] The program (1040) may be stored as software in memory (1030) and may include, for example, an operating system (1042), middleware (1044), or an application (1046).

[0258] The input module (1050) can receive commands or data to be used in a component of the electronic device (1001) (e.g., a processor (1020)) from an external source (e.g., a user) of the electronic device (1001). The input module (1050) can include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0259] The audio output module (1055) can output audio signals to the outside of the electronic device (1001). The audio output module (1055) can include, for example, a speaker or a receiver. The speaker can be used for general purposes, such as multimedia playback or recording playback. The receiver can be used to receive incoming calls. In one embodiment, the receiver can be implemented separately from the speaker or as part of the speaker.

[0260] The display module (1060) can visually provide information to an external party (e.g., a user) of the electronic device (1001). The display module (1060) may include, for example, a display, a holographic device, or a projector and a control circuit for controlling the device. In one embodiment, the display module (1060) may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of a force generated by the touch.

[0261] The audio module (1070) can convert sound into an electrical signal, or vice versa, convert an electrical signal into sound. According to one embodiment, the audio module (1070) can acquire sound through the input module (1050), output sound through the sound output module (1055), or an external electronic device (e.g., electronic device (1002)) (e.g., speaker or headphone) directly or wirelessly connected to the electronic device (1001).

[0262] The sensor module (1076) can detect the operating status (e.g., power or temperature) of the electronic device (1001) or the external environmental status (e.g., user status) and generate an electrical signal or data value corresponding to the detected status. According to one embodiment, the sensor module (1076) can include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0263] The interface (1077) may support one or more designated protocols that may be used to directly or wirelessly connect the electronic device (1001) with an external electronic device (e.g., the electronic device (1002)). In one embodiment, the interface (1077) may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

[0264] The connection terminal (1078) may include a connector through which the electronic device (1001) may be physically connected to an external electronic device (e.g., the electronic device (1002)). According to one embodiment, the connection terminal (1078) may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0265] The haptic module (1079) can convert electrical signals into mechanical stimuli (e.g., vibration or movement) or electrical stimuli that a user can perceive through tactile or kinesthetic sensations. In one embodiment, the haptic module (1079) can include, for example, a motor, a piezoelectric element, or an electrical stimulation device.

[0266] The camera module (1080) can capture still images and videos. According to one embodiment, the camera module (1080) may include one or more lenses, image sensors, image signal processors, or flashes.

[0267] The power management module (1088) can manage power supplied to the electronic device (1001). According to one embodiment, the power management module (1088) can be implemented, for example, as at least a part of a power management integrated circuit (PMIC).

[0268] A battery (1089) may power at least one component of the electronic device (1001). In one embodiment, the battery (1089) may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0269] The communication module (1090) may support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device (1001) and an external electronic device (e.g., electronic device (1002), electronic device (1004), or server (1008)), and the performance of communication through the established communication channel. The communication module (1090) may operate independently from the processor (1020) (e.g., application processor) and may include one or more communication processors that support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module (1090) may include a wireless communication module (1092) (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module (1094) (e.g., a local area network (LAN) communication module, or a power line communication module). Among these communication modules, a corresponding communication module can communicate with an external electronic device (1004) via a first network (1098) (e.g., a short-range communication network such as Bluetooth, wireless fidelity (WiFi) direct, or infrared data association (IrDA)) or a second network (1099) (e.g., a long-range communication network such as a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or WAN)). These various types of communication modules can be integrated into a single component (e.g., a single chip) or implemented as multiple separate components (e.g., multiple chips). The wireless communication module (1092) can verify or authenticate the electronic device (1001) within a communication network such as the first network (1098) or the second network (1099) by using subscriber information (e.g., an international mobile subscriber identity (IMSI)) stored in the subscriber identification module (1096).

[0270] The wireless communication module (1092) can support 5G networks and next-generation communication technologies following the 4G network, such as NR access technology (new radio access technology). NR access technology can support high-speed transmission of high-capacity data (eMBB (enhanced mobile broadband)), minimizing terminal power and connecting multiple terminals (mMTC (massive machine type communications)), or high reliability and low latency (URLLC (ultra-reliable and low-latency communications)). The wireless communication module (1092) can support, for example, a high-frequency band (e.g., mmWave band) to achieve a high data transmission rate. The wireless communication module (1092) may support various technologies for securing performance in a high-frequency band, such as beamforming, massive multiple-input and multiple-output (MIMO), full dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large scale antenna. The wireless communication module (1092) may support various requirements specified in the electronic device (1001), an external electronic device (e.g., the electronic device (1004)), or a network system (e.g., the second network (1099)). According to one embodiment, the wireless communication module (1092) may support a peak data rate (e.g., 20 Gbps or more) for eMBB realization, a loss coverage (e.g., 164 dB or less) for mMTC realization, or a U-plane latency (e.g., 0.5 ms or less for downlink (DL) and uplink (UL) each, or 1 ms or less for round trip) for URLLC realization.

[0271] The antenna module (1097) can transmit or receive signals or power to or from an external device (e.g., an external electronic device). In one embodiment, the antenna module (1097) may include an antenna including a radiator formed of a conductor or a conductive pattern formed on a substrate (e.g., a PCB). In one embodiment, the antenna module (1097) may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network, such as the first network (1098) or the second network (1099), may be selected from the plurality of antennas by, for example, the communication module (1090). A signal or power may be transmitted or received between the communication module (1090) and an external electronic device through the at least one selected antenna. In some embodiments, in addition to the radiator, another component (e.g., a radio frequency integrated circuit (RFIC)) may be additionally formed as a part of the antenna module (1097).

[0272] According to various embodiments, the antenna module (1097) may form a mmWave antenna module. According to one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on or adjacent a first side (e.g., a bottom side) of the printed circuit board and capable of supporting a designated high frequency band (e.g., a mmWave band), and a plurality of antennas (e.g., an array antenna) disposed on or adjacent a second side (e.g., a top side or a side side) of the printed circuit board and capable of transmitting or receiving signals in the designated high frequency band.

[0273] At least some of the above components can be interconnected and exchange signals (e.g., commands or data) with each other via a communication method between peripheral devices (e.g., a bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface)).

[0274] According to one embodiment, commands or data may be transmitted or received between the electronic device (1001) and an external electronic device (1004) via a server (1008) connected to a second network (1099). Each of the external electronic devices (1002 or 104) may be the same or a different type of device as the electronic device (1001). According to one embodiment, all or part of the operations executed in the electronic device (1001) may be executed in one or more of the external electronic devices (1002, 104, or 108). For example, when the electronic device (1001) is to perform a certain function or service automatically or in response to a request from a user or another device, the electronic device (1001) may, instead of or in addition to executing the function or service itself, request one or more external electronic devices to perform the function or at least a part of the service. One or more external electronic devices that receive the request may execute at least a portion of the requested function or service, or an additional function or service related to the request, and transmit the result of the execution to the electronic device (1001). The electronic device (1001) may process the result as is or additionally and provide it as at least a portion of a response to the request. For this purpose, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used, for example. The electronic device (1001) may provide an ultra-low latency service by using distributed computing or mobile edge computing, for example. In another embodiment, the external electronic device (1004) may include an Internet of Things (IoT) device. The server (1008) may be an intelligent server utilizing machine learning and / or a neural network.According to one embodiment, an external electronic device (1004) or server (1008) may be included in the second network (1099). The electronic device (1001) may be applied to intelligent services (e.g., smart homes, smart cities, smart cars, or healthcare) based on 5G communication technology and IoT-related technology.

[0275] FIG. 11 is a block diagram of a display module according to various embodiments.

[0276] Referring to FIG. 11, a display module (1060) may include a display panel (1110) and a display driver IC (DDI) (1130) for controlling the same. The DDI (1130) may include an interface module (1131), a memory (1133) (e.g., a buffer memory), an image processing module (1135), or a mapping module (1137). The DDI (1130) may receive, for example, image data or image control signals corresponding to commands for controlling the image data, from other components of the electronic device (1001) through the interface module (1131). For example, according to one embodiment, image information may be received from a processor (1020) (e.g., a main processor (1021) (e.g., an application processor) or an auxiliary processor (1023) (e.g., a graphics processing unit) that operates independently of the function of the main processor (1021). The DDI (1130) may communicate with a touch circuit (1150) or a sensor module (1076) through the interface module (1131). In addition, the DDI (1130) may store at least a part of the received image information in the memory (1133), for example, in units of frames. The image processing module (1135) may, for example, perform preprocessing or postprocessing (e.g., resolution, brightness, or size adjustment) on at least a part of the image data based at least on the characteristics of the image data or the characteristics of the display panel (1110). The mapping module (1137) may output a voltage value corresponding to the image data preprocessed or postprocessed through the image processing module (1135). Alternatively, a current value may be generated. In one embodiment, the generation of the voltage value or current value may be performed at least in part based on, for example, the properties of the pixels of the display panel (1110), such as the arrangement of the pixels (RGB stripe or pentile structure), or the size of each sub-pixel.At least some pixels of the display panel (1110) may be driven based at least in part on, for example, the voltage value or current value, so that visual information (e.g., text, an image, or an icon) corresponding to the image data may be displayed through the display panel (1110).

[0277] According to one embodiment, the display module (1060) may further include a touch circuit (1150). The touch circuit (1150) may include a touch sensor (1151) and a touch sensor IC (1153) for controlling the same. The touch sensor IC (1153) may control the touch sensor (1151) to detect, for example, a touch input or a hovering input for a specific location of the display panel (1110). For example, the touch sensor IC (1153) may detect a touch input or a hovering input by measuring a change in a signal (e.g., voltage, light quantity, resistance, or charge quantity) for a specific location of the display panel (1110). The touch sensor IC (1153) may provide information (e.g., location, area, pressure, or time) regarding the detected touch input or hovering input to the processor (1020). According to one embodiment, at least a portion of the touch circuit (1150) (e.g., touch sensor IC (1153)) may be included as part of the display driver IC (1130), or as part of the display panel (1110), or as part of another component (e.g., auxiliary processor (1023)) disposed external to the display module (1060).

[0278] According to one embodiment, the display module (1060) may further include at least one sensor (e.g., a fingerprint sensor, an iris sensor, a pressure sensor, or an illuminance sensor) of the sensor module (1076), or a control circuit therefor. In this case, the at least one sensor or the control circuit therefor may be embedded in a part of the display module (1060) (e.g., the display panel (1110) or the DDI (1130)) or a part of the touch circuit (1150). For example, when the sensor module (1076) embedded in the display module (1060) includes a biometric sensor (e.g., a fingerprint sensor), the biometric sensor may obtain biometric information (e.g., a fingerprint image) associated with a touch input through a part of the display panel (1110). For another example, when the sensor module (1076) embedded in the display module (1060) includes a pressure sensor, the pressure sensor can obtain pressure information associated with a touch input through a part or the entire area of ​​the display panel (1110). According to one embodiment, the touch sensor (1151) or the sensor module (1076) can be placed between pixels of a pixel layer of the display panel (1110), or above or below the pixel layer.

[0279] The technical problems to be achieved in the present disclosure are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary knowledge in the technical field to which the present disclosure pertains.

[0280] As described above, the electronic device (200) may include a gate driver circuit (239). The electronic device (200) may include a display driving IC (230) (integrated circuitry). The electronic device (200) may include a display panel (210) including pixels. Each of the pixels may include sub-pixels. Each of the sub-pixels may include a light-emitting element; a storage capacitor configured to store a data voltage; and a transistor (301) configured to generate a current to be provided to the light-emitting element according to the data voltage stored in the storage capacitor, the transistor including a gate electrode, a source electrode, and a drain electrode connectable to an anode electrode of the light-emitting element, the transistor being configured to: The display driving IC (230) may be configured to transmit a clock signal for generating the scan signal to the gate driver circuit (239) within an active period of the vertical synchronization signal that transmits the scan signal to the gate electrode of the transistor (301) using the gate driver circuit (239). The display driving IC (230) may be configured to stop transmitting the clock signal for generating the scan signal to the gate driver circuit (239) within a porch period of the vertical synchronization signal that refrain from transmitting the scan signal to the gate electrode of the transistor (301) using the gate driver circuit (239).

[0281] According to one embodiment, the display driving IC (230) may include a source driver circuit (238). The display driving IC (230) may be configured to obtain, from the source driver circuit (238), a signal indicating the porch period of the vertical synchronization signal during which provision of the data voltage to each of the sub-pixels is to be stopped. The display driving IC (230) may be configured to stop transmitting the clock signal to the gate driver circuit (239) within the porch period of the vertical synchronization signal based on obtaining the signal indicating the porch period.

[0282] According to one embodiment, the display driving IC (230) may include a register circuit. The display driving IC (230) may be configured to transmit the clock signal for generating the scan signal to the gate driver circuit (239) within the active period of the vertical synchronization signal based on providing a first register value to the register circuit. The display driving IC (230) may be configured to stop transmitting the clock signal to the gate driver circuit (239) within the porch period of the vertical synchronization signal based on providing a second register value to the register circuit.

[0283] According to one embodiment, each of the first register value and the second register value may include first information indicating a period of the vertical synchronization signal related to the clock signal; and second information indicating whether to transmit the clock signal. The first register value may include the first information indicating the active period of the vertical synchronization signal and the second information indicating transmission of the clock signal. The second register value may include the first information indicating the porch period of the vertical synchronization signal and the second information indicating cessation of transmission of the clock signal.

[0284] According to one embodiment, each of the first register value and the second register value may further include at least one of: third information indicating a clock frequency of the clock signal; or, while transmitting the clock signal, fourth information indicating a voltage level of the clock signal.

[0285] According to one embodiment, the first information may indicate one of a value indicating that the section of the vertical synchronization signal is the active section, a value indicating that the section of the vertical synchronization signal is the porch section, and a value indicating that the section of the vertical synchronization signal is the active section and the porch section. The second information may indicate one of a value indicating transmission of the clock signal, and a value indicating cessation of transmission of the clock signal. The third information may indicate one candidate frequency value used as the clock frequency of the clock signal among a plurality of candidate frequency values. The fourth information may indicate one of a first voltage level, a second voltage level lower than the first voltage level, and a ground level while cessation of transmitting the clock signal.

[0286] According to one embodiment, each of the sub-pixels may further include a compensation transistor (303) including a drain electrode connected to the gate electrode of the transistor (301), a source electrode connected to the drain electrode of the transistor, and a gate electrode. The display driving IC (230) may be configured to transmit a clock signal for generating the compensation scan signal to the gate driver circuit (239) within the active period of the vertical synchronization signal that transmits the compensation scan signal to the gate electrode of the compensation transistor (303) using the gate driver circuit (239). The display driving IC (230) may be configured to stop transmitting the clock signal for generating the compensation scan signal to the gate driver circuit (239) within the porch period of the vertical synchronization signal that refrain from transmitting the compensation scan signal to the gate electrode of the compensation transistor (303) using the gate driver circuit (239).

[0287] According to one embodiment, the display driving IC (230) may be configured to perform a first scan, which includes transmitting the scan signal to the gate electrode of the transistor (301) using the gate driver circuit (239) within the active period of the vertical synchronization signal; and initializing the gate electrode of the transistor (301) based on transmitting the scan signal, providing the data voltage to the initialized gate electrode of the transistor (301), and providing current to the light-emitting element through the transistor (301) having the provided data voltage at the gate electrode of the transistor (301).

[0288] According to one embodiment, each of the sub-pixels may further include a bypass transistor (307) including a source electrode connected to the anode electrode of the light-emitting element, a drain electrode to which an initialization voltage is applied, and a gate electrode. The display driving IC (230) may be configured to transmit a clock signal for generating the bypass scan signal to the gate driver circuit (239) within the active period of the vertical synchronization signal that transmits the bypass scan signal to the gate electrode of the bypass transistor (307) using the gate driver circuit (239). The display driving IC (230) may be configured to stop transmitting the clock signal for generating the bypass scan signal to the gate driver circuit (239) within the porch period of the vertical synchronization signal that refrain from transmitting the bypass scan signal to the gate electrode of the bypass transistor (307) using the gate driver circuit (239).

[0289] According to one embodiment, the display driving IC (230) may be configured to stop transmitting the clock signal for generating the scan signal to the gate driver circuit (239) within the active period of another vertical synchronization signal that refrain from transmitting the scan signal to the gate electrode of the transistor (301) using the gate driver circuit (239) and the porch period of the other vertical synchronization signal. The display driving IC (230) may be configured to transmit the clock signal for generating the bypass scan signal to the gate driver circuit (239) within the active period of the other vertical synchronization signal that transmits the bypass scan signal to the gate electrode of the bypass transistor (307) using the gate driver circuit (239). The display driving IC (230) may be configured to stop transmitting the clock signal for generating the bypass scan signal to the gate driver circuit (239) within the porch period of the other vertical synchronization signal that refrain from transmitting the bypass scan signal to the gate electrode of the bypass transistor (307) using the gate driver circuit (239).

[0290] According to one embodiment, the display driving IC (230) may be configured to perform a second scan, including transmitting the bypass scan signal to the gate electrode of the bypass transistor (307) using the gate driver circuit (239) within the active period of the other vertical synchronization signal; and providing current to the light-emitting element through the transistor (301) while the data voltage according to the first scan is maintained by skipping initializing the gate electrode of the transistor (301), based on transmitting the bypass scan signal.

[0291] According to one embodiment, each of the sub-pixels may include a light-emitting transistor (306) including a source electrode connected to the drain electrode of the transistor (301), a drain electrode connected to the anode electrode of the light-emitting element, and a gate electrode. The display driving IC (230) may be configured to transmit a clock signal for generating the light-emitting scan signal to the gate driver circuit (239) within the active period of the vertical synchronization signal that transmits the light-emitting scan signal to the gate electrode of the light-emitting transistor (306) using the gate driver circuit (239). The display driving IC (230) may be configured to stop transmitting the clock signal for generating the light-emitting scan signal to the gate driver circuit (239) within the porch period of the vertical synchronization signal that refrain from transmitting the light-emitting scan signal to the gate electrode of the light-emitting transistor (306) using the gate driver circuit (239).

[0292] According to one embodiment, each of the sub-pixels may include an initialization transistor (304) including a drain electrode connected to the storage capacitor, a source electrode to which a different initialization voltage is applied, and a gate electrode. The display driving IC (230) may be configured to transmit a clock signal for generating the initialization scan signal to the gate driver circuit (239) within the active period of the vertical synchronization signal that transmits the initialization scan signal to the gate electrode of the initialization transistor (304) using the gate driver circuit (239). The display driving IC (230) may be configured to stop transmitting the clock signal for generating the initialization scan signal to the gate driver circuit (239) within the porch period of the vertical synchronization signal that refrain from transmitting the initialization scan signal to the gate electrode of the initialization transistor (304) using the gate driver circuit (239).

[0293] According to one embodiment, the display driving IC (230) may be configured to maintain the voltage level of the clock signal at a first voltage level while stopping transmitting the clock signal to the gate driver circuit (239) within the porch period of the vertical synchronization signal. The display driving IC (230) may be configured to maintain the voltage level of the clock signal at a second voltage level changed from the first voltage level while stopping transmitting the clock signal to the gate driver circuit (239) within an active period of another vertical synchronization signal that stops transmitting the scan signal to the gate electrode of the transistor (301) using the gate driver circuit (239).

[0294] According to one embodiment, each of the sub-pixels may further include a bypass transistor (307) including a source electrode connected to the anode electrode of the light-emitting element, a drain electrode to which an initialization voltage is applied, and a gate electrode. The display driving IC (230) may be configured to transmit a clock signal for generating the bypass scan signal to the gate driver circuit (239) within the active period of the vertical synchronization signal that transmits a bypass scan signal to the gate electrode of the bypass transistor (307) using the gate driver circuit (239). The display driving IC (230) may be configured to stop transmitting the clock signal for generating the bypass scan signal to the gate driver circuit (239) within the porch period of the vertical synchronization signal, or to transmit the clock signal for generating the bypass scan signal to the gate driver circuit (239). Within the active period of the vertical synchronization signal, the clock frequency of the clock signal for generating the bypass scan signal may be determined as a first clock frequency. Within the porch period of the vertical synchronization signal, the clock frequency of the clock signal for generating the bypass scan signal may be determined as a second clock frequency lower than the first clock frequency.

[0295] According to one embodiment, the display driving IC (230) may be configured to obtain an image to be displayed in the active period of the vertical synchronization signal. The display driving IC (230) may be configured to identify a brightness parameter of the display panel (210) for displaying the image. The display driving IC (230) may be configured to stop transmitting the clock signal for generating the bypass scan signal to the gate driver circuit (239) within the porch period of the vertical synchronization signal, which refrain from transmitting the bypass scan signal to the gate electrode of the bypass transistor (307) using the gate driver circuit (239), upon determining that the brightness parameter satisfies a first criterion. The display driving IC (230) may be configured to transmit the clock signal for generating the bypass scan signal to the gate driver circuit (239) within the porch section of the vertical synchronization signal that transmits the bypass scan signal to the gate electrode of the bypass transistor (307) by using the gate driver circuit (239) upon determining that the brightness parameter satisfies the second criterion.

[0296] According to one embodiment, the display driving IC (230) may be configured to transmit the clock signal for generating the bypass scan signal to the gate driver circuit (239) within the porch period of the vertical synchronization signal that transmits the bypass scan signal to the gate electrode of the bypass transistor (307) by using the gate driver circuit (239) upon determining that the brightness parameter satisfies a third criterion. When the brightness parameter satisfies the second criterion, the clock frequency of the clock signal for generating the bypass scan signal within the porch period of the vertical synchronization signal may be determined as the second clock frequency. When the brightness parameter satisfies the third criterion, the clock frequency of the clock signal for generating the bypass scan signal within the porch period of the vertical synchronization signal may be determined as a third clock frequency that is lower than the first clock frequency and higher than the second clock frequency.

[0297] According to one embodiment, the electronic device (200) may include a wearable device worn on a user's wrist. The display driving IC (230) may be configured to stop transmitting the clock signal for generating the scan signal to the gate driver circuit (239) within the porch period of the vertical synchronization signal, which refrain from transmitting the scan signal to the gate electrode of the transistor using the gate driver circuit (239), based on executing a mode for low power.

[0298] According to one embodiment, the length of the porch section of the vertical synchronization signal may be determined according to a refresh rate of the display panel (210). The display driving IC (230) may be configured to perform a first scan once, including initializing the gate electrode of the transistor (301), providing the data voltage to the initialized gate electrode of the transistor (301), and providing current to the light-emitting element through the transistor (301) having the provided data voltage at the gate electrode of the transistor (301), while the data voltage according to the first scan is maintained by skipping the initializing of the gate electrode of the transistor (301), and to perform a second scan M times, including providing current to the light-emitting element through the transistor (301). M may be a natural number greater than 1.

[0299] As described above, the electronic device (200) may include a gate driver circuit (239). The electronic device (200) may include a display driving IC (230) (integrated circuitry). The electronic device (200) may include a display panel (210) including pixels. Each of the pixels may include sub-pixels. Each of the sub-pixels may include a light-emitting element; a storage capacitor configured to store a data voltage; and a transistor (301) configured to generate a current to be provided to the light-emitting element according to the data voltage stored in the storage capacitor, the transistor including a gate electrode, a source electrode, and a drain electrode connectable to an anode electrode of the light-emitting element, the transistor being configured to: The display driving IC (230) may be configured to transmit first pulse signals to the gate driver circuit (239) within an active period of a vertical synchronization signal that transmits a scan signal to the gate electrode of the transistor (301) using the gate driver circuit (239). Each of the first pulse signals may have a first pulse width. The display driving IC (230) may be configured to transmit a second pulse signal having a second pulse width greater than the first pulse width to the gate driver circuit (239) within a porch period of the vertical synchronization signal that refrain from transmitting the scan signal to the gate electrode of the transistor (301) using the gate driver circuit (239). A length of the first pulse width may be shorter than a length of the active period of the vertical synchronization signal. A length of the second pulse width may be longer than or equal to a length of the porch period of the vertical synchronization signal.

[0300] Electronic devices according to the various embodiments disclosed in this document may take various forms. Electronic devices may include, for example, portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, or home appliances. Electronic devices according to the embodiments of this document are not limited to the aforementioned devices.

[0301] The various embodiments of this document and the terminology used therein are not intended to limit the technical features described in this document to specific embodiments, but should be understood to include various modifications, equivalents, or substitutes of the embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of the items, unless the context clearly indicates otherwise. In this document, each of the phrases "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" can include any one of the items listed together in the corresponding phrase among those phrases, or all possible combinations thereof. Terms such as "first," "second," or "first" or "second" may be used merely to distinguish one component from another, and do not limit the components in any other respect (e.g., importance or order). When a component (e.g., a first component) is referred to as "coupled" or "connected" to another component (e.g., a second component), with or without the terms "functionally" or "communicatively," it means that the component can be connected to the other component directly (e.g., wired), wirelessly, or through a third component.

[0302] The term "module" used in various embodiments of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit. A module may be an integral component, or a minimum unit or part of such a component that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0303] Various embodiments of the present document may be implemented as software (e.g., a program (1040)) including one or more instructions stored in a storage medium (e.g., an internal memory (1036) or an external memory (1038)) readable by a machine (e.g., an electronic device (1001)). For example, a processor (e.g., a processor (1020)) of the machine (e.g., an electronic device (1001)) may call at least one instruction among the one or more instructions stored from the storage medium and execute it. This enables the machine to operate to perform at least one function according to the at least one called instruction. The one or more instructions may include code generated by a compiler or code executable by an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. Here, 'non-transitory' simply means that the storage medium is a tangible device and does not contain signals (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently or temporarily on the storage medium.

[0304] According to one embodiment, the method according to various embodiments disclosed in the present document may be provided as included in a computer program product. The computer program product may be traded as a product between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., compact disc read-only memory (CD-ROM)), or may be distributed online (e.g., downloaded or uploaded) via an application store (e.g., Play Store™) or directly between two user devices (e.g., smart phones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily generated in a machine-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or an intermediary server.

[0305] According to various embodiments, each component (e.g., a module or a program) of the above-described components may include one or more entities, and some of the entities may be separated and placed in other components. According to various embodiments, one or more components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Alternatively or additionally, a plurality of components (e.g., a module or a program) may be integrated into a single component. In such a case, the integrated component may perform one or more functions of each of the plurality of components identically or similarly to those performed by the corresponding component among the plurality of components prior to the integration. According to various embodiments, the operations performed by a module, program, or other component may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

Claims

1. In an electronic device (200), Gate driver circuit (239); Display driving IC (230) (integrated circuitry); and It includes a display panel (210) containing pixels, Each of the above pixels includes sub-pixels, Each of the above sub-pixels: light emitting element; a storage capacitor configured to store a data voltage; and A transistor (301) is included, which includes a gate electrode connected to the storage capacitor, a source electrode, and a drain electrode connectable to the anode electrode of the light-emitting element, and is configured to generate a current to be provided to the light-emitting element according to the data voltage stored in the storage capacitor. The above display driving IC (230): Within the active period of the vertical synchronization signal that transmits the scan signal to the gate electrode of the transistor (301) using the gate driver circuit (239), a clock signal for generating the scan signal is transmitted to the gate driver circuit (239); and It is configured to stop transmitting the clock signal for generating the scan signal to the gate driver circuit (239) within the porch period of the vertical synchronization signal that refrain from transmitting the scan signal to the gate electrode of the transistor (301) using the gate driver circuit (239). Electronic device (200).

2. In claim 1, The above display driving IC (230) includes a source driver circuit (238), The above display driving IC (230): Obtaining a signal from the source driver circuit (238) indicating the porch section of the vertical synchronization signal at which the data voltage is to be stopped from being provided to each of the sub-pixels; and Based on obtaining the signal indicating the porch section, configured to stop transmitting the clock signal to the gate driver circuit (239) within the porch section of the vertical synchronization signal, Electronic device (200).

3. In claim 1, The above display driving IC (230) includes a register circuit, The above display driving IC (230): Based on providing a first register value to the register circuit, transmitting the clock signal for generating the scan signal to the gate driver circuit (239) within the active period of the vertical synchronization signal; and Based on providing a second register value to the register circuit, within the porch period of the vertical synchronization signal, the clock signal is configured to be stopped from being transmitted to the gate driver circuit (239). Electronic device (200).

4. In claim 3, Each of the first register value and the second register value: First information indicating a section of the vertical synchronization signal related to the clock signal; and Includes second information indicating whether to transmit the clock signal, The first register value includes the first information indicating the active period of the vertical synchronization signal and the second information indicating transmission of the clock signal, and The second register value includes the first information indicating the porch section of the vertical synchronization signal and the second information indicating the cessation of transmission of the clock signal. Electronic device (200).

5. In claim 4, Each of the first register value and the second register value: Third information indicating the clock frequency of the clock signal; or, While stopping transmitting the clock signal, further comprising at least one of the fourth pieces of information indicating a voltage level of the clock signal, Electronic device (200).

6. In claim 5, The above first information is: Indicates one of a value indicating that the section of the vertical synchronization signal is the active section, a value indicating that the section of the vertical synchronization signal is the porch section, and a value indicating that the section of the vertical synchronization signal is the active section and the porch section, The second information above is: Indicates one of a value indicating transmission of the clock signal and a value indicating cessation of transmission of the clock signal, The third information above is: Indicates one candidate frequency value among a plurality of candidate frequency values ​​to be used as the clock frequency of the clock signal, and The fourth information above is: While stopping transmitting the clock signal, one of a first voltage level, a second voltage level lower than the first voltage level, and a ground level is indicated. Electronic device (200).

7. In claim 1, Each of the above sub-pixels: Further comprising a compensation transistor (303) including a drain electrode connected to the gate electrode of the transistor (301), a source electrode connected to the drain electrode of the transistor, and a gate electrode; The above display driving IC (230): Transmitting a clock signal for generating the compensation scan signal to the gate driver circuit (239) within the active period of the vertical synchronization signal that transmits the compensation scan signal to the gate electrode of the compensation transistor (303) using the gate driver circuit (239); and It is configured to stop transmitting the clock signal for generating the compensation scan signal to the gate driver circuit (239) within the porch section of the vertical synchronization signal, which refrain from transmitting the compensation scan signal to the gate electrode of the compensation transistor (303) using the gate driver circuit (239). Electronic device (200).

8. In claim 1, The above display driving IC (230): Within the active period of the above vertical synchronization signal: Transmitting the scan signal to the gate electrode of the transistor (301) using the gate driver circuit (239); and Based on transmitting the scan signal, a first scan is performed, which includes initializing the gate electrode of the transistor (301), providing the data voltage to the initialized gate electrode of the transistor (301), and providing current to the light-emitting element through the transistor (301) having the provided data voltage at the gate electrode of the transistor (301). Electronic device (200).

9. In claim 8, Each of the above sub-pixels: It further includes a bypass transistor (307) including a source electrode connected to the anode electrode of the light emitting element, a drain electrode to which an initialization voltage is applied, and a gate electrode, The above display driving IC (230): Transmitting a clock signal for generating the bypass scan signal to the gate driver circuit (239) within the active period of the vertical synchronization signal that transmits a bypass scan signal to the gate electrode of the bypass transistor (307) using the gate driver circuit (239); and It is configured to stop transmitting the clock signal for generating the bypass scan signal to the gate driver circuit (239) within the porch section of the vertical synchronization signal, which refrain from transmitting the bypass scan signal to the gate electrode of the bypass transistor (307) using the gate driver circuit (239). Electronic device (200).

10. In claim 9, The above display driving IC (230): Within the active period of another vertical synchronization signal and the porch period of the other vertical synchronization signal, which refrain from transmitting the scan signal to the gate electrode of the transistor (301) using the gate driver circuit (239), the clock signal for generating the scan signal is stopped from being transmitted to the gate driver circuit (239); Transmitting the clock signal for generating the bypass scan signal to the gate driver circuit (239) within the active period of the other vertical synchronization signal that transmits the bypass scan signal to the gate electrode of the bypass transistor (307) using the gate driver circuit (239); and Within the porch section of the other vertical synchronization signal that refrain from transmitting the bypass scan signal to the gate electrode of the bypass transistor (307) using the gate driver circuit (239), the clock signal for generating the bypass scan signal is configured to be stopped from being transmitted to the gate driver circuit (239). Electronic device (200).

11. In claim 10, The above display driving IC (230): Within the active period of the above other vertical synchronization signal: Transmitting the bypass scan signal to the gate electrode of the bypass transistor (307) using the gate driver circuit (239); and Based on transmitting the bypass scan signal, a second scan is performed, which includes providing current to the light-emitting element through the transistor (301) while the data voltage according to the first scan is maintained by skipping initializing the gate electrode of the transistor (301). Electronic device (200).

12. In claim 1, Each of the above sub-pixels: A light emitting transistor (306) including a source electrode connected to the drain electrode of the transistor (301), a drain electrode connected to the anode electrode of the light emitting element, and a gate electrode, The above display driving IC (230): Transmitting a clock signal for generating the light emitting scan signal to the gate electrode of the light emitting transistor (306) within the active period of the vertical synchronization signal using the gate driver circuit (239); and It is configured to stop transmitting the clock signal for generating the light emitting scan signal to the gate driver circuit (239) within the porch section of the vertical synchronization signal that refrain from transmitting the light emitting scan signal to the gate electrode of the light emitting transistor (306) using the gate driver circuit (239). Electronic device (200).

13. In claim 1, Each of the above sub-pixels: An initialization transistor (304) including a drain electrode connected to the storage capacitor, a source electrode to which another initialization voltage is applied, and a gate electrode, The above display driving IC (230): Transmitting a clock signal for generating the initialization scan signal to the gate driver circuit (239) within the active period of the vertical synchronization signal that transmits the initialization scan signal to the gate electrode of the initialization transistor (304) using the gate driver circuit (239); and It is configured to stop transmitting the clock signal for generating the initialization scan signal to the gate driver circuit (239) within the porch period of the vertical synchronization signal while refraining from transmitting the initialization scan signal to the gate electrode of the initialization transistor (304) using the gate driver circuit (239). Electronic device (200).

14. In claim 1, The above display driving IC (230): While stopping transmitting the clock signal to the gate driver circuit (239) within the porch section of the vertical synchronization signal, the voltage level of the clock signal is maintained at the first voltage level; and It is configured to maintain the voltage level of the clock signal at a second voltage level changed from the first voltage level while stopping transmitting the clock signal to the gate driver circuit (239) within the active period of another vertical synchronization signal that stops transmitting the scan signal to the gate electrode of the transistor (301) using the gate driver circuit (239). Electronic device (200).

15. In claim 14, Each of the above sub-pixels: It further includes a bypass transistor (307) including a source electrode connected to the anode electrode of the light emitting element, a drain electrode to which an initialization voltage is applied, and a gate electrode, The above display driving IC (230): Transmitting a clock signal for generating the bypass scan signal to the gate driver circuit (239) within the active period of the vertical synchronization signal that transmits a bypass scan signal to the gate electrode of the bypass transistor (307) using the gate driver circuit (239); and Within the above porch interval of the above vertical synchronization signal: Stop transmitting the clock signal for generating the bypass scan signal to the gate driver circuit (239), or It is configured to transmit the clock signal for generating the bypass scan signal to the gate driver circuit (239), Within the active period of the vertical synchronization signal, the clock frequency of the clock signal for generating the bypass scan signal is determined as a first clock frequency, and Within the porch section of the vertical synchronization signal, the clock frequency of the clock signal for generating the bypass scan signal is determined as a second clock frequency lower than the first clock frequency. Electronic device (200).

Images