Systems and methods for assigning addresses to parallelly connected LED

Abstract

The present teaching relates to address programming in parallelly connected LEDs integrated with driver chips. Address assignment is achieved via a three-step process, including selecting a row, an individual parallelly connected LED in a row, and assigning a unique address to each selected LED. The selection of rows and individual LEDS is achieved by comparing two voltages supplied to each of an array of LEDs via respective signal supply networks according to the present teaching.

Description

SYSTEMS AND METHODS FOR ASSIGNING ADDRESSES TO PARALLELLYCONNECTED LEDCROSS REFERENCE

[0001] The present application claims priority to U.S. Provisional Patent Application No. 63 / 661,430, filed June 18, 2024 and U.S. Provisional Patent Application No. 63 / 679,390, filed August 5, 2024, the contents of which are incorporated herein in their entirety.BACKGROUND1. Technical Field

[0002] The present disclosure relates to LED (Light Emitting Diode). More specifically, the present teaching relates to systems and methods for addressing LEDs.2. Introduction

[0003] In modern LED technology, especially in transparent LED screens, LEDs and their corresponding driver chips are packaged together as a single pixel. These integrated driver- LED units simplify the overall circuit design and enable a finer pixel control. By embedding a driver chip within each LED module, such LED strings can operate with high precision, making them effective for applications where transparency, flexibility, and pixel density are critical.

[0004] LEDs in such systems can be connected either in series or in parallel. Although a serial connected LED string may be straightforward, it has limitations in terms of, e.g., reliability, because a single failure (or a failure of a few) may disrupt the operation of the entire string. On the other hand, a parallelly connected LED string may provide a greater degree of reliability and allow for a more compact design, leading to fewer pins required and reduced number of soldering needed that minimizes spacing between adjacent pixels and enhances manufacturing efficiency. With a parallel connection, driver chips in an array of parallelly-connected LEDs receive input data from the same input line. As such, each LED needs to know, based on address received with the pixel information, which data to take in. As such, an address for each LED needs to be recorded in the LED first, then compared against the address of the received data. In this manner, when the input is provided to all parallelly connected LEDs, each LED takes the data in when the accompanying address matches the previously recorded address.

[0005] Conventionally, addresses for parallelly connected individual LEDs in an array may be assigned during the soldering process, but this approach significantly reduces the production efficiency, as each driver chip needs to be soldered one by one. Additionally, soldering active (powered) driver chips poses risks (e.g., accidental shorts). Another conventional method involves modifying the external condition of a pixel when burning an address in the pixel, such as temperature or light exposure, using, e.g., built-in thermistors or photoresistors to enable selective address programming. However, due to the close spacing of LEDs, it is challenging to ensure that only one specific LED undergoes a controlled environmental change without affecting its neighbors. Moreover, fully automating this process would require specialized equipment capable of precisely altering conditions for each LED individually, adding complexity and cost to production.

[0006] Thus, an improved approach is needed to address the issues / deficiencies of the conventional methods to write addresses to parallelly connected LEDs.SUMMARY

[0007] The teachings disclosed herein relate to methods, systems, and programming for LED. More particularly, the present teaching relates to methods, systems, and programming related to assigning addresses for an array of parallelly connected LEDs:

[0008] In one example, a method, implemented on a machine is disclosed for assigning addresses for an array of parallelly connected LEDs each of which is integrated with a respective driver chip. Address assignment is achieved via a three-step process, including selecting a row, an individual parallelly connected LED in a row, and assigning a unique address to each selected LED. The selection of rows and individual LEDS is achieved by comparing two voltages supplied to each of an array of LEDs via respective signal supply networks according to the present teaching.

[0009] In a different example, a system is disclosed for assigning addresses for an array of parallelly connected LEDs. The system includes an addressable LED controller for controlling address assignment to multiple rows of LEDs through a first voltage and a second voltage supplied to the multiple rows of LEDs. Each of the multiple rows of LEDs includes parallelly connected LEDs, each of which is integrated with a respective driver chip configured to receive the first voltage and the second voltages, to compare the first and the second voltages, to determine whether the row that the driver chip is in is selected and / or whether the driver chip in a row of parallelly connected LED driver chips is selected, and tostore therein a unique address assigned thereto upon it being selected. The stored unique address is to be used to recognize data directed to the LED for display by matching the unique stored address with an address associated with the data.

[0010] Additional benefits and novel features will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and the accompanying drawings or may be learned by production or operation of the examples. The advantages of the present teachings may be realized and attained by practice or use of various aspects of the methodologies, instrumentalities and combinations set forth in the detailed examples discussed below.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The methods, systems and / or programming described herein are further described in terms of exemplary embodiments. These exemplary embodiments are described in detail with reference to the drawings. These embodiments are non-limiting exemplary embodiments, in which like reference numerals represent similar structures throughout the several views of the drawings, and wherein:

[0012] FIG. 1 A (prior art) illustrates a known example of an array of serially connected LED driver chips;

[0013] FIG. IB (prior art) illustrates a known example of an array of parallelly connected LED driver chips;

[0014] FIG. 2 illustrates an exemplary addressable LED controller connected to an array of parallelly connected LED driver chips for address assignment, according to an embodiment of the present teaching;

[0015] FIG. 3 illustrates an exemplary scheme of writing an address to an individual LED driver chip in an array of LED driver chips, according to an embodiment of the present teaching;

[0016] FIG. 4 illustrates an example internal architecture of a LED driver chip, according to an embodiment of the present teaching;

[0017] FIG. 5 A illustrates an exemplary scheme for selecting one row of LED driver chips from multiple rows of LED driver chips, according to an embodiment of the present teaching;

[0018] FIG. 5B illustrates exemplary data transmission paths within a driver chip during a row selection process, according to an embodiment of the present teaching;

[0019] FIG. 5C illustrates an exemplary flowchart of selecting one row of LED driver chips, according to an embodiment of the present teaching;

[0020] FIG. 6A illustrates an exemplary arrangement of power supplying wires to facilitate selecting individual LED driver chips in a row of multiple LED driver chips, according to an embodiment of the present teaching;

[0021] FIG. 6B illustrates exemplary data signal paths within a driver chip during a process of selecting an individual LED in a row, according to an embodiment of the present teaching;

[0022] FIG. 6C illustrates an exemplary flowchart for a process of selecting individual LED driver chips, according to an embodiment of the present teaching;

[0023] FIG. 6D illustrates another exemplary arrangement of power supplying wires to improve selection of individual LED driver chips in a row of multiple LED driver chips, according to an embodiment of the present teaching;

[0024] FIG. 7A illustrates an exemplary scheme for selecting individual LEDs driver chips in a row of LED driver chips, according to a different embodiment of the present teaching;

[0025] FIG. 7B illustrates another exemplary scheme for selecting individual LED driver chips in a row of LED driver chips, according to another different embodiment of the present teaching;

[0026] FIG. 7C illustrates an exemplary scheme for selecting individual LED driver chips in a row of LED driver chips, according to yet another different embodiment of the present teaching;

[0027] FIG. 8A illustrates an exemplary internal architecture of an addressable LED controller, according to an embodiment of the present teaching;

[0028] FIG. 8B illustrates an exemplary address programming scheme using an illustrated a 3x4 block of driver chips, according to an embodiment of the present teaching;

[0029] FIG. 8C illustrates exemplary data signal paths in a driver chip during a process of writing an address, according to different embodiments of the present teaching;

[0030] FIG. 8D illustrates an exemplary flowchart of writing an address to an individual LED driver chip, according to different embodiments of the present teaching;

[0031] FIG. 9 illustrates an exemplary scheme for automatically assigning addresses to LED driver chips in an LED display or a block thereof, according to an embodiment of the present teaching; and

[0032] FIG. 10 illustrates a diagram of an exemplary computing device architecture that may be used to realize a specialized system implementing the present teaching in accordance with various embodiments.DETAILED DESCRIPTION

[0033] In the following detailed description, numerous specific details are set forth by way of examples in order to facilitate a thorough understanding of the relevant teachings. However, it should be apparent to those skilled in the art that the present teachings may be practiced without such details. In other instances, well known methods, procedures, components, and / or system have been described at a relatively high-level, without detail, in order to avoid unnecessarily obscuring aspects of the present teachings.

[0034] The present teaching is provided to address the shortcomings of the traditional solutions in assigning (writing) addresses to parallelly connected LEDs that integrates driver chips with RGB lights commonly used in, e.g., transparent LED display. Specifically, the present teaching disclosed method, configuration, and systems to automate the process of programming addresses for an array of LEDs with rows having parallelly connected LEDs. Such address programming requires selection of each appropriate driver chip in a LED and then writing an address in the selected driver chip. As discussed herein, with a parallel connection configuration, all driver chips in a row sharing a common input data line receive the same data stream with addresses incorporated therein. Accordingly, each LED needs to store a unique address assigned thereto beforehand to identify and accept only the data with an address matching its stored address.

[0035] Conventional address assignment methods include writing an assigned address to each individual LED driver chip when soldering each driver chip, which is extremely inefficient. Another traditional method for address assignment is by selecting each individual LED via altering its external conditions such as temperature / light using built-in sensors. This approach faces great challenges due to tight pixel spacing and the need for expensive and complex equipment, driving up the production cost.

[0036] The present teaching discloses a three-step process of writing designated addresses to an array of LEDs with multiple rows of parallelly connected LEDs. The steps include: (1) selecting a row of LEDs, (2) selecting an individual LED from a row of parallelly connected LEDs, and (3) writing an assigned address to the selected individual LEDs. The three-step process may be carried out after all the LEDs with respective driver chips integrated thereto are mounted to a printed control board (PCB). As such, there is no need to writing addresses to each LED driver chip while placing and soldering the integrated LED with the driver chiponto the surface of the PCB, or changing the external conditions to isolate each LED, which improves the production efficiency and avoids the risk of soldering active driver chips.

[0037] In the first step of the three-step process, both row selection and selection of an individual LED in a row of parallelly connected LEDs are achieved by comparing different voltages supplied to the LEDs. To select a row of LEDs for address assignment, an Addressable LED Controller coupled to a plurality of rows of parallelly connected LEDs (integrated with respective driver chips) initially sends a command to all driver chips in all rows to enter into a row selection mode. To effectuate the selection of a row, the Addressable LED Controller sends a VDD voltage and an SDI voltage to the driver chips. The VDD voltage provided to all rows may be controlled at a substantially the same voltage, while the SDI voltage is supplied as a continuously rising voltage, starting from an initial voltage lower than the VDD voltage and gradually rising in time. With a certain SDI signal delivery mechanism according to the present teaching (will be disclosed below), at each moment, different rows receive different SDI voltages. In operation, driver chips in each row actively compares the received rising SDI voltage with the VDD voltage. When a driver chip in a particular row detects, via comparison, that the received SDI voltage exceeds the VDD voltage, this particularly row is selected. At this point, the driver chips that detect the condition via comparison may send a designated feedback signal to the Addressable LED Controller to notify that the particular row has been selected. In some embodiments, such driver chips may exit the row selection mode. That is, by controlling the difference between VDD voltage and the rising SDI voltage with respect to different rows at different points of time, the rows may be selected automatically at, e.g., different points of time.

[0038] The second step in the three-step process is to select a driver chip in a row of parallelly connected driver chips. This step may be performed in an individual driver chip selection mode and is achieved also via comparison of the rising SDI voltage and the VDD voltage. The VDD voltage sent from the Addressable LED Controller to the parallelly connected driver chips in each row may be delivered using a mechanism provided according to the present teaching to ensure that there is a distinguishable VDD voltage drop between neighboring parallelly connected driver chips. This may be done by driving a current through a VDD line used to supply the VDD voltage to different driver chips in a driver chip row. As will be disclosed below, in some embodiments, multiple VDD lines and / or multiple Addressable LED Controllers may be used to enhance the voltage drop between neighboring driver chips. To select a particular driver chip in a row, each driver chip compares the received rising SDI signal with the received VDD voltage. When the received rising SDIvoltage exceeds the received VDD voltage, the driver chip is selected. As each driver chip receives a different VDD voltage due to voltage drops between neighboring driver chips ensured by the VDD supplying mechanism of the present teaching, different driver chips in a row are selected at a different time instances.

[0039] The third step in the three-step process is to assign an address to the selected driver chip so that the selected driver chip can store the assigned address therein in the integrated LED. To do so, for each driver chip, once selected, it sends the specific SDI voltage and the specific VDD voltage at the time of the selection to the Addressable LED Controller, which then creates an address designated to the selected driver chip according to the specific SDI and VDD voltages and sends a designated address to the selected driver chip so that the designated address may be stored in the driver chip.

[0040] Through the three-step process as discussed herein, all parallelly connected LEDs on a LED display may store the respective addresses assigned thereto in their driver chips integrated with the RGB lights. Each of the LEDs can therefore be addressed and controlled to display the pictorial data associated with each pixel on the LED display.

[0041] The method and systems according to the present teaching not only eliminate the needs to manually assign addresses to LEDs during soldering or change environmental conditions (such as temperature or light to select a LED driver chip with complex equipment to isolate and control individual driver chips that are closely spaced). Because the three-step process is substantially automated, the process of assigning addresses to parallelly connected integrated LEDs in an entire LED display can be achieved with a significantly improved speed and cost.

[0042] To facilitate the three-step process for address programming, the driver chip integrated with each LED in each row of parallelly connected LEDs is provided to utilize the received voltage signals to carry out the selection of both a row and an individual LED. The driver chip in each LED according to the present teaching may include a comparator provided to compare a power supply VDD voltage with a signal SDI voltage received and self-selecting when the comparison result satisfies a certain condition. Upon the selfselection, the driver chip sends an output indicating either a row the driver chip is in or that the driver chip is selected. After a driver chip is selected, a unique address for the selected driver chip is created and sent to the driver chip. Upon receiving the address, the driver chip stores the address into its storage for subsequent addressing in a display operation. The driver chip may further include a controller that manages the comparator’s operation. The comparator and the controller work in coordination to enable the driver chip to operate indifferent operation modes, including precise voltage-based selection of rows or individual driver chips for address assignment. The driver chip according to the present teaching introduces a minimal change to the drive chip’s architecture, leading to minimum added cost.

[0043] FIG. 1 A illustrates a known example of serially connected multiple driver chips 110- 1, 110-2, 110-3 and 110-4 interconnected in series. A driver chip may include multiple ports, such as a VDD port for receiving a driving voltage, a Data Input (DI) port, a Secondary Data Input (DI2) port, a GND port connected to a ground, and a Data Output (DO) port. Each driver chip receives an input signal from the DI port, which is connected to the DO port of the adjacent (previous) driver chip in the upstream. In this serially connected example shown in FIG. 1 A, if driver chip 110-1 fails, the signal cannot pass through to driver chips 110-2, 110-3 and 110-4, causing the entire string fail.

[0044] FIG. IB illustrates a known example of parallelly connected multiple driver chips 120-1, 120-2, 120-3 and 120-4, which are shown to be interconnected in parallel. Input signal is provided to all driver chips at the same time. That is, each driver chip receives the same input signal at the same time from its DI port. In this example as shown in FIG. IB, each driver chip needs to, as discussed herein, store a unique address assigned thereto beforehand to identify and accept only the data matching its address.

[0045] FIG. 2 illustrates an exemplary configuration for address assignment operation with an addressable LED controller 200 connected to a row of parallelly connected LED driver chips 210, according to an embodiment of the present teaching. In operation, the LED addressable controller 200 sends a Voltage Drain Drain (VDD) signal via the VDD line 220 and a Serial Data Input (SDI) signal via a SDI line 230 to all driver chips 210-1, 210-2, 210- 3, 210-4, . . ., as shown in Fig. 2Each driver chip receives a first signal via its VDD port connected to the VDD line 220 and a second signal via its DI port connected to the SDI line 230. In some embodiments, the first and second signals may both be a voltage signal. As discussed herein, an individual LED driver chip in a row of parallelly connected driver chips may be self-selected based on a comparison of two signals. In the illustrated embodiment in FIG. 2, each driver chip is provided to compare the received first and second voltage signals. In some embodiments, the second signal from the SDI line 230 may be a digital signal, which may include various types of data. As an example, the digital signal may carry a command to control a module, such as a comparator, in a LED driver chip. As another example, the digital signal may also include an address (with coded value) associated with, e.g., a LED driver chip. As yet another example, the digital signal may include a grayscale value directed to a LED driver chip.

[0046] FIG. 3 illustrates an exemplary configuration of assigning addresses to different individual LED driver chips in an array of LED driver chips with multiple rows, according to an embodiment of the present teaching. An array of LEDs comprises multiple rows and multiple columns and each LED in this array may be located via (row, column). In Fig. 3, there are illustrated multiple rows 310, 20, 330, . . . , each of which includes multiple LED driver chips, located in different columns 340, 350, 360, 370, . . . , etc. For instance, row 310 has LED driver chips 310-1, 310-2, 310-3, 310-4, ... in columns 340, 350, 360, 370, ... ; row 320 has LED driver chips 320-1, 320-2, 320-3, 320-4, . . ., in these columns; row 330 has LED driver chips 330-1, 330-2, 330-3, 330-4, . . ., in these columns etc. In this illustration, the LED driver chips in each row are parallelly connected.

[0047] As discussed herein, according to the present teaching, the addresses for the LED driver chips in the illustrated array as shown in FIG. 3 are assigned to the LED driver chips in a three-step process. The first step corresponds to row selection, in which one row of the array may be selected at a time (such as the row shown in FIG. 2 with LED driver chips 320- 1, 320-2, 320-3 and 320-4) at each moment. The second step corresponds to column selection, in which individual LED driver chips in a selected tow are selected (e.g., the driver chip 320-3 is selected among the other driver chips in the row 320. Once a driver chip is selected, the third step corresponds to the process of assigning and writing a designated address to the selected LED driver chip. The address assigned to each selected LED is determined by the addressable LED controller 200 and is transmitted to the selected driver chip at a location determined by (row, column). Through this three-step process, each individual LED driver chip in the array of parallelly connected LED driver chips may be assigned an address. Details on each step will be discussed in connection with FIG. 5A - 5C, 6A - 6C, and 8A - 8C.

[0048] FIG. 4 illustrates an exemplary internal construct of a LED driver chip 410, according to an embodiment of the present teaching. The driver chip 410 may be configured to receive external power suppliers and digital signals. A driver chip is provided to drive a red, green, or blue lights in a LED. The exemplary driver chip 410 includes various circuitries for carrying out such designated functions to support both functions relating to address assignment and normal operation of driving the red, green, and blue lights of the LED. In operation, the driver chip 410 may receive inputs including a supply voltage (VDD), ground (GND), and a signal (DI) which may be an analog signal (such as a voltage signal) or a digital signal (such as a grayscale value). On the output side, the driver chip 410may provide an output current on OUT R, OUT G, and OUT B ports to drive a red, green, and blue lights of the LED, respectively.

[0049] At the core of the address assignment mechanism in the exemplary driver chip 410 is a Comparator 440. In operation, the Comparator 440 receives a VDD voltage and a DI voltage as inputs and compares the two voltages. The result of the comparison is transmitted to a Controller 450. The Controller 450 is provided to control the overall operation of the driver chip 410, including the enabling, in the three-step address assignment process, the Comparator 440 for comparison operation as well as the driver chip selection in subsequent address assignment to the selected driver chip. When the operating in a normal mode to drive the LED lights, the Controller 450 may disable the Comparator 440. A command is received by a Data Receiver 470 through the DI port and may be transmitted to the Controller 450. When the Comparator 440 is enabled, based on the received VDD and an input signal voltage from DI, the Comparator 440 compares the two and produces a comparison result. Based on the received command and the comparison result from the Comparator 440, the Controller 450 may set a selection flag 454. In some embodiments, the selection flag may indicate whether the driver chip 410 is self-selected so that it is ready to receive an address. In this way, the Comparator 440 and the Controller 450 work in coordination to enable the voltage-based self-selection of the driver chip 410 for the subsequent address assignment. In some embodiments, the Address Storage 460 may retain the assigned address after the power is off. In some embodiments, a default address value (e.g., zero) is initially stored in the Address Storage 460 of the driver chip 410 before receiving an input from the Controller 450. This default address value may be a factory setting of the driver chip 410.

[0050] The driver chip as depicted in FIG. 4 is capable of both address assignment associated with column selection as well as the normal operation to drive the RGB LED lights in one LED pixel. Once an address has been assigned by the addressable LED controller in the three-step address assignment process to the driver chip 410 and saved in the Address Storage 460, the driver chip 410 may operate in a normal operational mode. In the normal operational mode, the driver chip 410 may accept an incoming data stream from DI port, process the incoming data stream received at the DI port, identify whether the data is directed thereto by determining whether the address associated with the data matches the stored address in 460. If so, the data directed to the driver chip is used to control the output OUT R, OUT G, and OUT B to drive, respectively, the red, green, and blue lights according to the grayscale values and / or current gain values in the input data. In some embodiments, the input data may be transmitted by the Data Receiver 470 to the Controller 450. Then, theController 450 may determine whether the address of the input data matches the address stored in the Address Storage 460. If so, the Controller 450 may determine to transmit the input data including the grayscale values and / or current gain values to the corresponding Current Gain Buffer 480 and / or the Grayscale Data Buffer 490. In some other embodiments, the Current Gain Buffer 480 and / or the Grayscale Data Buffer 490, instead of directly receiving the input data from the Controller 450, may receive the input from the Data Receiver 470 after the Controller 450 determines that the address of the input data matches the address of the driver chip. For example, the Controller 450 may send a command to the Data Receiver 470 to transmit the data to the Current Gain Buffer 480 and / or the Grayscale Data Buffer 490.

[0051] As discussed herein, the input data may include other types of data that may be used to control the red, green and blue lights. As an example, each data frame may include RGB grayscale values for N parallelly connected driver chips, e.g., N sets of RGB grayscale values, each of which is for one of the parallelly connected driver chips. In some embodiments, a data frame may include fewer than N sets of RGB grayscale values. For example, when N1 equals to one, which means that all the driver chips receive the same RGB grayscale values, regardless of their individual addresses.

[0052] In some embodiments, N1 equals to N, which means the grayscale values are address-dependent and may be received by each driver chip according to the driver chip’s assigned address. For example, the data frame may be a sequence of N grayscale values. The first grayscale value may be provided to the driver chip with a first assigned address, the second to the driver chip with a second address, the third to the driver chip with a third address, and so on. As such, each driver chip parallelly connected in a string may respond only to the grayscale value that has an address matching its stored address in Address Storage 460. In some embodiments, for a driver chip with the default address value (e.g., zero), the driver chip may default to use the first grayscale value in the data frame. The Data Receiver 470 processes the received data frame and identifies the grayscale value directed thereto based on the address in the data frame and the address stored in 460. The grayscale value intended for the driver chip 410 is then stored in the Grayscale Data Buffer 490 for further processing. As illustrated in FIG. 4, the grayscale value stored in Grayscale Data Buffer 490 may be used by a Pulse Width Modulation (PWM) Controller 494, that may rely on a timing signal from an internal Clock 492, together with the grayscale value from storage 490, to convert the grayscale value to corresponding pulse width signals in R, G, and B channels, respectively.

[0053] On the other hand, the input data frame may also include N2 sets of RGB current gain values transmitted to the array of N parallelly connected driver chips. The RGB current gain values may be transmitted to a Current Gain Buffer 480. Similarly, when N2 equals to one, which means that all the driver chips receive the same RGB current gain values, regardless of their individual addresses. In some situations, N2 equals to N, which means the current gain values are address-dependent and may be taken as input by each driver chip according to the driver chip’s assigned address. The current gain value stored in the Current Gain Buffer 480 represents some set amplitudes in R, G, and B channels. A Current Driver 496 is provided for generating outputs to control the red, green, and blue lights based on both the pulse width signals in R, G, and B channels and the set amplitudes in R, G, B to modulate the output current for each of the output port OUT R, OUT G, and OUT B that drives, respectively, the red, green and blue LEDs, respectively.

[0054] Detailed operational scheme for selecting rows and individual parallelly connected driver chips in different rows is provided herein with reference to FIGs. 5 A - 8D. FIGs. 5A- 5C describe an exemplary scheme for row selection in the address assignment process and exemplary operation in driver chips. As discussed herein, the row selection is the first step of the three-step process for address assignment according to the present teaching. FIG. 5 A illustrates an exemplary configuration to facilitate selection of one row of LED drive chips from multiple rows of LED driver chips, according to an embodiment of the present teaching. In this illustrated embodiment, there are multiple rows (e.g., 510, 512, and 514) of parallelly connected driver chips. It is noted that the three rows as depicted herein is merely for illustration and there can be any number of rows in an LED. Each row is serially coupled to a respective resistor (e.g., row 510 is coupled to a first resister, row 512 is coupled to a second resister, and row 514 is coupled to a third resister) through a contact point (e.g., row 510 is coupled to the first resister via a first contact, row 512 is coupled to the second resister via a second contact, and row 514 is coupled to the third resister via a third contact). The contact point in each row can, for example, be a common contact point (e.g., an electrical node) for all parallelly connected driver chips in that row. For example, driver chips 510-1, 510-2 . . . 510-N along the row 510 are connected to the first resistor through the First Contact. Similarly, driver chips 512-2, 512-2 . . . 512-N along the row 512 are connected to a Second Resistor through the Second Contact, and driver chips 514-1, 514-2 . . . 514-N are connected to a Third Resistor through the Third Contact.

[0055] Notably, all driver chip rows in the multiple rows (e.g., the illustrated 510, 512 and 514) are linked, directly or indirectly, to a common Serial Data Input (SDI) port 502 of anAddressable LED Controller 500 through a respective path, such that the SDI line may be used to control multiple rows of driver chips. The illustrated configuration may be suitable for narrow LED display panels, which generally have a limited width and consequently a limited number of available SDI lines and / or connector pins. Rather than dedicating a separate data line to each driver chip row, the illustrated setup greatly reduces the number of control signals and required hardware ports. It should be appreciated that, although FIG. 5A illustrates a single SDI line controlling three driver chip rows 510, 512 and 514, more driver chip rows may be controlled by a single SDI line by the same principle. The Addressable LED Controller 500 may also supply VDD signals through a VDD port 504 and one or more VDD lines 520 to each driver chip along each of the driver chip row of the multiple rows. It should be appreciated that the DI voltage received by the driver chips are sometimes referred also as the SDI voltage since the voltage comes from the SDI port of the Addressable LED Controller and can be used interchangeably with the DI voltage to refer to the same voltage.

[0056] In the operation of a row selection process, different driver chip rows 510, 512 and 514 may receive different DI voltages because of the different resistors coupled thereto along a transmission path originated from the SDI 502. As illustrated in FIG. 5A, the original voltage may be provided to the second contact so that the driver chips parallelly connected in row 512 all receive the original voltage. The voltage also is transmitted to the second resistor and then to the first resistor before reaches the first contact, as well as to the third contact via the second resistor and the third resistor. The arrows in FIG. 5A between the SDI 502 to the respective contacts denote the directions of a current flow and the current causes voltage drops whenever it passes through a resistor. As such, the parallelly connected driver chips in row 510 receive, at their respective DI terminals, a DI voltage that is reduced from the SDI voltage from 502 due to a voltage drop from the Second and First Resistors along the current path. Similarly, the parallelly connected driver chips in row 514 also receive a DI voltage on their respective DI terminals which is reduced voltage due to a voltage drop caused by the Second and the Third Resistors along the current path.

[0057] Depending on the amount of voltage drop along different current paths, the driver chips in different rows receive different DI voltages, which may be leveraged for row selection, according to the present teaching. In some embodiments, a DI voltage difference of a certain amount may be adequate to distinguish different rows. For instance, a difference of around 300 mV may be sufficient to distinguish, which may be used to determine the resistors used along the current flow. For instance, the First / Second / Third Resistors may set to be 100 Q. In this case, if each driver chip draws a DI current of about 20 pA and each rowhas N=50 driver chips, the current drown by row 512 would be 2 mA and the current flowing into rows 510 and 514 would each be 1 mA because of the resistors. As such, the voltage drops between the row 512 and 510 / 514 would both be 100 * 2 mA + 1000 * 1 mA = 300 mV based on Ohm’s Law. In some embodiments, the First / Second / Third Resistors may take different values as long as the resulting DI voltages received by each driver chip row are distinguishable.

[0058] Given the distinguishable DI voltages received by different driver chip rows, the driver chips in different rows operate to react to the received DI voltage to facilitate the row selection. FIG. 5B shows how an illustrated driver chip 512-1 operates in row selection as well as exemplary data transmission paths during the row selection process, according to the teaching of FIG. 5 A. In this example, while the construct of different components remains the same as in FIG. 4, some of the components therein operate to facilitate row selection. As discussed herein, the SDI signal from the Addressable LED Controller 500 may include different information. For instance, the SDI signal may include a command, which may be a 32-bit signal to inform the driver chip to enter into a row selection mode. As shown in FIG. 5B, the driver chip 512-1 may receive the SDI signal on its DI terminal (connected to an SDI line 530). The Data Receiver 470, upon receiving the SDI signal, transmits the received command to the Controller 450 so that the driver chip enters into a row selection mode. In this manner, via the SDI signal, all driver chips along all rows controlled by the Addressable LED Controller 500 (e.g., rows 510, 512 and 514) enter into a row selection mode. Upon entering the row selection mode, the Controller 450 of each driver chip (e.g., 512-1) sets its internal Selection Flag 454 to a first state, indicative of a row selection mode. In some implementation, the Selection Flag 454 may correspond to a 1 -bit with a binary value (e.g., 0 as a first state indicating row selection mode and 1 as a second state).

[0059] Once all driver chips set in the row selection mode, the Addressable LED Controller 500 may send a DI voltage to all driver chips, starting from an initial DI voltage value and gradually increase the DI voltage. In some embodiments, the initial value of the DI voltage may be set to a value below a VDD voltage provided to all driver chips via the VDD port thereof. In the row selection mode, the Comparator 440 (e.g., in the exemplary driver chip 512-1 in FIG. 5B) may continuously compare the power supply voltage VDD with the ramping DI voltage from the Addressable LED Controller 500. The power supply voltage VDD voltage received by the driver chips is substantially identical as the current from the VDD port to each driver chip is minimal as compared with the current supplied in the normal current driving mode. At the beginning of the row selection process, the initial value of theDI voltage received from the DI port on each driver chip is below the VDD voltage received via the VDD port. In this situation, none of the driver chips triggers its associated Controller 450 and the Selection Flag 454 in each driver chip remains at a first state (signifying the row selection mode).

[0060] As the DI voltage received on the DI port continues to rise, it exceeds the VDD voltage received by some particular row of the driver chips. As discussed herein with reference to FIG. 5 A, the DI voltages received by different rows of driver chips differ due to the voltage drops along the current path due to resistors (i.e., First / Second / Third Resistors). In this exemplary configuration in FIG. 5A, as the SDI signal is provided from the SDI port 502 to the Second Contact directly (without any resistor), the DI voltage received by the driver chips in row 512 first exceeds the VDD voltage received by driver chips in row 512. In this case, the Comparator 450 sends a signal to the Controller 450, indicating the detected event. Upon receiving the result from the Comparator 540 that the DI voltage exceeds the VDD voltage, the Controller 450 operates to change its Selection Flag 454 from the first state to a second state, indicating that the row is selected as the row selection condition has been met. As discussed herein, the Selection Flag 454 may be a binary value with the first state representing a row selection mode and now the second state indicating that the row selection is completed for the associated row. On the other hand, as the DI voltage currently received by driver chips in other rows (e.g., 510 and 514) does not exceed the VDD voltage, the Selection Flags associated with driver chips in those rows remain at the first state and, thus, still subject to row selection.

[0061] In response to the flipped state of the Selection Flag 454, the Controller (e.g., 450) in each driver chip in the selected driver chip row 512 activates the Current Gain Buffer 480 and the Current Driver 496 to output a small reference current Ii (e.g., 1 mA) on a designated output channel, e.g., OUT R. For example, the Controller 450 may send a command to the Data Receiver 470 to send the small reference current Ii to the Current Gain Buffer 480. This output reference current Ii serves as a signaling current to the Addressable LED Controller 500 to indicate that the driver chip row 512 has been selected. The signaling current may be received by a VDD port of the Addressable LED Controller 500. When the Addressable LED Controller 500 detects a current increase of about, e.g., approximately 1 mA * N (where N is the number of driver chips in the selected row 512. Note that this current is provided as an illustration, instead of as a limitation. The level of the reference current Ii may vary with application needs. In addition, the level of the reference current may not need to be precise as the Addressable LED Controller 500 may provide some built-in level of tolerance.

[0062] In some embodiments, upon being notified of the row selection, the Addressable LED Controller 500 drives the DI voltage back down to a low voltage level to enable itself to transmit the next command to instruct all driver chips to enter an individual driver chip selection process or column selection process. In some situations, the Addressable LED Controller 500 may become disabled when sending a command during a row selection process if the DI voltage varies around a high voltage level corresponding to a high logic state. An exemplary the low voltage level may be between 0V and 0.8V. In some embodiments, the high voltage level may be between 3.3V and 5V.

[0063] Upon detecting that the DI voltage returns to the low voltage level, all driver chips exit the row selection mode. However, exiting the row selection mode does not change the respective Selection Flags in these driver chips, i.e., each driver chip retains whatever the flag state it has. Thus, the driver chips in a selected row (e.g., row 512) keep their Selection Flags at the second state, while driver chips in other rows (e.g., rows 510 and 514) remain at the first state. This indicates that selected driver chip row (512) is ready for address assignment, whereas other unselected driver chip rows (510 and 514) still need to be selected. In order to select another driver chip row (510 or 514), the DI line from SDI 502 may be re-routed from directly contacting the Second Contact to directly contacting the First Contact or the Third Contact. For example, when the DI line directly contacts the First Contact, the Addressable LED Controller 500 may select the driver chip row 510 in the same way as selecting the driver chip row 512.

[0064] In another embodiment, upon being notified of the row selection of a particular driver chip row, the Addressable LED Controller 500 may continue to drive the DI voltage to increase to select one or more rows. For example, the resistance of the First Resistor and the Third Resistor may set to be 100 Q and 200 Q, respectively, which leads to a smaller voltage drop in the driver chip row 510 compared to the voltage drop in the driver chip row 514. As illustrated in FIG. 5 A, the continuously increasing DI voltage in the driver chip row 510 may first reach a voltage value that exceeds the VDD in the driver chip row 510. As such, the driver chip row 510 is selected at a later time than the driver chip row 512. As the VDD voltage continues to increase, it eventually exceeds the VDD voltage in row 514, and the driver chip row 514 is selected after the driver chip row 510. As such, all the driver chip rows may be selected at different times in an automated manner. The Addressable LED Controller 500 may stop increasing the VDD voltage until the VDD voltage reaches a cap value. This cap value is determined by the number and resistance values of the resistors connected to themultiple driver chip rows. This cap value may be input to the Addressable LED Controller 500 prior to the start of the row selection process.

[0065] As an addition to the embodiment described above, the Addressable LED Controller 500 may pause for a time period after one driver chip row is selected, before continuing to drive the DI voltage to increase. During this time period, the Addressable LED Controller 500 may check if the driver chip row is selected successfully. As an example, the Addressable LED Controller 500 may send a command to the Data Receiver 470 of each driver chip of the selected driver chip row to send the small reference current h to the Current Gain Buffer 480. This output reference current Ii serves as a signaling current to the Addressable LED Controller 500 to indicate that the driver chip row has been selected.

[0066] FIG. 5C illustrates an exemplary flowchart of selecting one row of LED driver chips among multiple rows of parallelly connected LED driver chips, according to the teaching of FIG. 5A and 5B. At step 505, the Addressable LED Controller 500 sends a command to notify all driver chip rows to enter into a row selection mode. At step 515, the Controller 450 in each of the driver chips initializes their respective Selection Flag 454 to a first state. At Step 525, the Addressable LED Controller 500 sends both a VDD and a gradually increasing DI voltage to the multiple rows of parallelly connected driver chips. As discussed herein, the DI voltages received by different driver chips in different rows vary, depending on their respective row locations and the resistors deployed along the current path from the Addressable LED Controller 500 to these rows. At Step 535, the Comparator in each driver chip compares the received VDD voltage with the received DI voltage while the DI voltage continues to ramp up. When the Comparator detects that the DI voltage received exceeds the VDD voltage, it selects, at Step 545, the row that it is in and notifies the Controller that the driver chip row is selected. At step 555, upon receiving the result from a Comparator, the Controller in the driver chip in the selected driver chip row changes the Selection Flag 454 from the first state to a second state. Upon being selected, each driver chip in the selected row outputs, at Step 565, a reference current Ii indicating that a row has been selected. When the Addressable LED Controller 500 receives, at Step 575, a current increase with an approximate increase amount of Ii * N, where N is the number of parallelly connected driver chips in the selected row to notify that a row has been selected. At step 585, the Addressable LED Controller 500 resets the DI voltage to all driver chip rows (including both selected and unselected rows) to a low voltage level so that each driver chip is back to a state of taking an input (e.g., a command) for the next cycle. At step 595, the Controller in (e.g., 450) stores the Selection Flag 454 and exits the row selection mode.

[0067] Following the row selection process, the Addressable LED Controller 500 may proceed to select an individual driver chip within the selected driver chip row. This may be called column selection. This column selection process is further illustrated in FIGs. 6A-6C. Whereas row selection was made by comparing the DI voltage provided against the VDD voltage, individual driver chip selection at a particular column in a selected row is accomplished using a combination of DI voltage, VDD 520 voltage, and ground, according to the present teaching. In some embodiments, cement resistors may be used by the Addressable LED Controller 500 to create a controlled voltage gradient between neighboring driver chips along each row. Such controlled voltage gradient is leveraged by individual driver chips to determine when it is selected.

[0068] FIG. 6A illustrates an exemplary configuration for selecting an individual LED drive chip from a row of multiple parallelly connected LED driver chips, according to an embodiment of the present teaching. This illustration is provided with an Addressable LED Controller 500 connected with a driver chip row 610 with N driver chips 610-1, 610-2, . . . 610-N. The Addressable LED Controller 500 may supply three signals, VDD signal via connection 620, GND and SDI signals (not shown in FIG. 6A for illustration clarity) to each driver chip in the driver chip row 610. In some embodiments, the Addressable LED Controller 500 may route an SDI signal to all driver chips in different rows in the same manner as illustrated in FIG. 5A. In this illustrated configuration, the VDD signal is provided, via connection 620, to the driver chip row 610 from the Addressable LED Controller 500. The current path is denoted by the arrows in FIG. 6A so that when the VDD signal flows following the current path towards the ground through a Cement Resistor 612, it creates a controlled voltage gradient for neighboring driver chips along the driver chip row 610, as will be discussed below.

[0069] In the illustrated configuration, the VDD voltage is transmitted along two separate VDD lines 622-1 and 622-2 of, e.g., equal width. For example, a single 40-Mil-wide VDD line may be split into two 20-Mil-wide VDD lines. To enable voltage drop along the driver chip row, the two VDD lines 622-1 and 622-2 may be configured in a way to, e.g., ensure adequate voltage drops between neighboring chips. For instance, as seen in FIG. 6A, line 622-1 and line 622-2 may be serially connected and 622-1 may be connected to odd numbered driver chips while line 622-2 to even numbered driver chips. In this configuration, each of the two VDD lines 622-1 and 622-2 serves one half of the driver chips in each row. With this configuration of the VDD lines, the distance between the two neighboring driver chips along a single VDD line 622-1 / 622-2 is doubled, since each VDD line now onlyconnects to half of the driver chips along the same length of a single VDD line. For example, the distance between two neighboring driver chips 610-1 and 610-3 (not shown) is doubled, compared to the distance between two neighboring driver chips 610-1 and 610-2 if there is a single VDD line connecting all the driver chips. The increased distance together with the resistance doubling per unit length leads to a resistance that is four times of the original resistance between the neighboring odd numbered driver chips on the VDD line 622-1 and the neighboring even numbered driver chips on the VDD line 622-2, thereby magnifying the voltage drop between neighboring driver chips along a single VDD line.

[0070] The exemplary configuration as depicted in FIG. 6A may introduce a high driving current during the process of selecting an individual driver chip in a row to further increase the voltage drops between neighboring driver chips. For example, the Cement Resistor 612 may be selected to produce an appropriate amount of current, e.g., 2 A or any other value, through the VDD line 662-1 and 622-2. Assuming the VDD voltage on connection 620 is raised to 7V (e.g., from a normal operating voltage of 5V), and the total resistance of the path, including a 1.5Q Cement Resistor 612 and two 1-meter 20-Mil VDD lines with approximately IQ each, is around 3.5Q, a current of 2A can be achieved.

[0071] As an exemplary calculation of the voltage drop, the driver chip 610-1 located at the beginning of the VDD line 622-1 may see a VDD voltage of approximately 7 V. If N = 200, the driver chip 610-199 (N-l) located at the end of the VDD line 622-1 receives a voltage around 5V, i.e., a total of 2V voltage drop across the VDD line 622-1. As a result, the VDD voltage drop between neighboring chips spaced along the resistive VDD line 622-1 is about 2V / 100 = 20 mV.

[0072] FIG. 6B illustrates exemplary signal transmission paths within a driver chip during the process of selecting an individual LED driver chip from a selected row, according to an embodiment of the present teaching. Driver chip 610-1 is used here for illustration, which is similarly constructed as 410 (except that the Controller 450 in FIG. 6B now includes an additional Test Flag 654) but with a different signal flow for selecting an individual driver ship in a row of parallelly connected driver chips. To initiate the process, the Addressable LED Controller 500 transmits a command via an SDI signal from the SDI port to all driver chips in all rows. For example, when this command is received by a driver chip, e.g., driver chip 610-1 in a selected row 610, the Controller 450 in each driver chip in the same row (that receives the command via the Data Receiver 470 therein) controls the driver chip to enter into an individual driver chip selection mode (which corresponds to the second step in the three-step process and is distinct from the row selection mode which is the first step of thethree-step process). This may be done by setting an internal Test Flag 654 to a first state. In some implementations, the Test Flag may be binary with, e.g., the first state toggled with a second state.

[0073] While driver chips enter the individual driver chip selection mode, the Addressable LED Controller 500 may gradually increase the SDI voltage from an initial value, which may be set to a value below the VDD voltage. On the driver chip side, upon entering the individual driver chip selection mode, the Controller 450 turns on Comparator 440 in each driver chip to continuously compare the VDD voltage to the changing SDI voltage received on the DI port. It is noted that in this configuration, although the SDI signal is provided with a small current (e.g., < 20 pA per driver chip) that may cause a voltage drop, the drop due to this small current is negligible. As such, the SDI voltage received by different driver chips may be considered substantially uniform across all parallelly connected driver chips in the same driver chip row 610.

[0074] In operation, initially, the SDI voltage is below the VDD voltage for all the driver chips along a driver chip row so that the Test Flag in each driver chip stays at the first state. As the SDI voltage continues to rise, it eventually exceeds the VDD voltage in one driver chip. As discussed herein, to select an individual driver chip in a row (e.g., 610), the VDD is provided to different driver chips via one or more VDD lines 622 arranged to ensure that there is a sufficient voltage drop between neighboring driver chips. One exemplary arrangement of VDD lines 622-1 and 622-2 is shown in FIG. 6A. In such an exemplary configuration, each driver chip is to detect when the ramping SDI voltage will exceed the VDD voltage it receives. As each driver chip receives a different SDI voltage due to the voltage drop introduced because of the arrangement of VDD lines, each driver chip detects the condition that SDI voltage > VDD voltage at different timings.

[0075] The configuration as shown in FIG. 6A illustrates how to select a driver chip by detecting when the received SDI voltage exceeds the received VDD voltage. In this embodiment, because driver chip 610-2 is at the end of the second VDD line 622-2, it receives the lowest VDD voltage due to the arrangement of VDD lines 622-1 and 622-2. When Comparator 440 of driver chip 610-2 first detects that VDD voltage < SDI voltage, it signals the Controller 450 to change the Test Flag 654 from the first state to a second state, indicating that driver chip 610-2 is selected. In some embodiments, the second state may correspond to a binary value one. Meanwhile, the Test Flags of other driver chips in the driver chip row 610 remain at a first state because the VDD voltages they respectively receive from a VDD line (622-1 or 622-2) are still higher than the ramping SDI voltagereceived. However, with time, different driver chips in a row may detect that VDD voltage < SDI voltage at different time instances and it causes different driver chips in the same row to be selected at different times.

[0076] When the Test Flag 654 is set to the second state, the selected driver chip causes a reference signaling current H (e.g., approximately 1 mA) being output on a designated output channel to the Addressable LED Controller 500. In some embodiments, the red LED channel OUT R may be used as the designated output channel since, e.g., a red LED channel has the lowest forward voltage as compared with green and blue channels, making the red channel more likely to turn on reliably even when the VDD voltage is low. In the example in FIG. 6 A with driver chips 610-2, 610-4 . . ., because the VDD voltage received by driver chips towards the end of the VDD line 622-2 are relatively low because of the more substantial voltage drops from the input VDD voltage from the Addressable LED Controller 500, it is important to select a channel to ensure that the reference signaling current I2 can be reliably output.

[0077] The output reference signaling current I2 may signal the Addressable LED Controller 500 that an individual driver chip in a selected row has been selected so that when the Addressable LED Controller 500 detects it, it determines that a particular driver chip has been selected. As the actual value of I2 may vary in different implementations, the detection threshold used for detection may be provided with a tolerance range (e.g., ±0.3 mA). Additionally, upon determining that a driver chip (e.g., 610-2) has been selected, the SDI voltage and VDD voltage received by the driver chip at the time of the selection are also transmitted to the Addressable LED Controller 500 for storage, which is to be later used for the address assignment in the third step of the three-step process, as will be discussed in connection with FIG. 8A - 8C.

[0078] With the ramping SDI voltage, different driver chips in a row may be selected at different times via the same mechanism as discussed herein. When the ramping SDI voltage exceeds the initial VDD voltage (i.e., the highest SDI voltage across all driver chips in the same row), the Addressable LED Controller 500 controls to drive the SDI voltage back down to a low voltage level corresponding to a low logic state (e.g., between 0 and 0.8 V). This signals the end of the second step in the three-step process to select individual driver chips. Upon detecting that the SDI voltage returns the low voltage level, each driver chip exits the mode of selecting individual driver chips. While exiting this mode, the driver chips do not clear their respective Test Flags (654), i.e., each driver chip retains the value in the Test Flag 654 that it set during the comparison process. As discussed herein, a selected driver chip hasits Test Flag 654 set in the second state, making it eligible to receive an address in the subsequent third step in the three-step process for address assignment, in which a given address designated to the driver chip is to be programmed therein.

[0079] In the low logic state (associated with the low voltage level), the Addressable LED Controller 500 transmits another command to all driver chips instructing them to enter an address assignment process, corresponding to the third step in the three-step process for programming addresses in different driver chips. In some embodiments, during the individual driver chip selection process, the Addressable LED Controller 500 may be disabled so that it cannot send a command when it is at a high logic state as the SDI voltage varies around a high voltage level.

[0080] FIG. 6C illustrates an exemplary flowchart of the process of selecting an individual LED driver chip, according to the present teaching. As discussed with reference to FIGs. 6A - 6B, the Addressable LED Controller 500 sends, at Step 605, a command via the SDI port to each driver chip in each row of parallelly connected driver chips. However, only the driver chips along the previously selected row having the Selection Flag 454 in the second state may respond to the command to enter the individual driver chip selection mode. Upon receiving the command, the Controller 450 in each driver chip initializes, at Step 615, its Test Flag 654 to a first state. To proceed with the selection, the Addressable LED Controller 500 gradually increases, at Step 625, the SDI voltage to driver chips. At Step 635, the Comparator 440 in each driver chip continuously compares the rising SDI voltage with the received VDD voltage. When the Comparator 440 of a driver chip detects, at Step 645, that the SDI voltage exceeds the VDD voltage, the Comparator 440 transmits this detection result to the Controller 450 in the same driver chip. In response, the Controller 450 changes, at Step 655, the Test Flag 654 therein from the first state to the second state, signifying that this driver chip has been selected and causes, at Step 665, the driver chip outputs a signaling current L via a designated output port (e.g., approximately 1 mA through the red LED output OUT R) to the Addressable LED Controller 500.

[0081] When the Addressable LED Controller 500 detects the current I2 from the VDD port, it records, at Step 675, the current SDI voltage and the VDD voltage received by the driver chip at the moment of the selection. This information is stored in the Addressable LED Controller 500 for facilitating future address assignment. Then the Addressable LED Controller 500 pulls back, at Step 685, the SDI voltage to a low voltage level to instruct the driver chips to exit the driver chip selection mode. Upon receiving the low voltage level, individual driver chips exit the individual chip selection mode.

[0082] It should be appreciated that, although the individual driver chip selection process with reference to FIG. 6A - 6C is illustrated in connection with the row selection process in FIG. 5A - 5C, in some embodiments, the individual driver chip selection process may be performed without a preceding row selection process. In particular, some low-end applications, such as basic LED strips or low-resolution linear light bars, may use the individual driver chip selection process according to the present invention without a row selection process. In such implementations, all driver chips sharing the same SDI signal will all respond to the individual driver chip selection process. In such cases, addresses are assigned sequentially based on a comparison result based on the SDI voltage and its VDD voltage, as discussed herein. This approach may simplify the circuit and is suitable for use cases like decorative lighting, always-on LED strips, or scenarios where precise spatial control is not required.

[0083] In the exemplary embodiments shown in FIG. 6A, the VDD voltage drops between different pairs of neighboring driver chips may differ. For example, the VDD voltage drop between driver chip 610-1 and 610-2 may be the largest because driver chip 610-1 is connected to the starting end of VDD line 622-1 and driver chip 610-2 is connected to the end of VDD line 622-2. However, the VDD voltage drop between the last two driver chips in row 610 may be the smallest. In some embodiments, the connection of the VDD lines may be implemented to ensure that the enhanced VDD voltage drops between all neighboring driver chips remain relatively the same to ensure more consistent performance.

[0084] FIG. 6D illustrates another exemplary scheme of VDD supply lines to facilitate selection of individual LED drive chips in a row of multiple parallelly connected LED driver chips, according to an embodiment of the present teaching. Similar to the configuration of FIG. 6 A, each of the two VDD lines 622-1 and 622-2 supplies VDD voltage to one half of the driver chips in the row. In this arrangement, it can be seen that the VDD line 622-1 is provided to supply VDD voltage to odd numbered driver chips as what is in FIG. 6A. However, VDD line 622-1 and VDD line 622-2 are now connected differently, i.e., the end of VDD line 622-1 (providing VDD voltage to driver chip 610-(N-l)) is coupled with the end of VDD line 622-2 for providing VDD voltage to driver chip 610-2. As such, the voltage drops between the neighboring odd numbered driver chips and the neighboring even numbered driver chips are increased in a consistent manner because the distance in length of VDD supply line between any two neighboring driver chips is approximately the length of VDD line 622-1. If VDD 622-1 and VDD 622-2 have the same widths and lengths, then the distance of the VDD supply line between any two neighboring driver chips is consistently thelength of each VDD line and, hence, the VDD voltage drops is substantially increased. Importantly, this is true to all neighboring driver chips, eliminating the inconsistent VDD voltage drops between different neighboring driver chips, as a result from the scheme as shown in FIG. 6A.

[0085] Similarly, other alternative configurations may be constructed based on the same principle as illustrated in FIG. 6A and FIG. 6D. For example, a multiple-path VDD arrangement, e.g., a four-path VDD arrangement may be implemented by further expanding the arrangement of VDD lines in FIG. 6A and FIG. 6D. For example, the VDD voltage may be transmitted along more than two VDD lines of, e.g., K VDD lines of equal width. As such, each of the K VDD serves 1 / K of the driver chips in each row, creating a larger voltage drop between any two neighboring driver chips. As another configuration, the VDD lines, unlike receiving the driving voltage from the VDD port as illustrated in FIG. 6A and FIG. 6D, may receive the driving voltage from an external power source through a Cement Resistor. The Cement Resistor in this exemplary implementation may act as a controlled resistive load of the Addressable LED Controller. In this scheme, a multi meter may be employed to work together with the Cement Resistor to actively monitor the voltages along each of the VDD lines connected, thereby preventing damages to the driver chips due to potential voltage fluctuations.

[0086] FIGs. 7A -7C illustrate three additional alternative configurations that may also be used to facilitate the individual driver chip selection step of the three-step process, according to different embodiments of the present teaching. In each of the three alternative configurations shown in FIGs. 7A - 7C, a driver chip row, e.g., 710, is connected to two Addressable LED Controllers positioned at the opposite ends of a driver chip row to ensure unidirectional current flow while delivering VDD voltage from the first Addressable LED Controller to the second Addressable LED Controller. The first configuration is illustrated in FIG. 7A, where the first Addressable LED Controller 700 connecting to one end of a resistive VDD line 704 (supplying VDD voltage to the driver chip row 710) may be provided to supply a VDD voltage to individual driver chips during driver chip selection, while the second Addressable LED Controller 720 connecting to the other end of the resistive VDD line 704 serves as a load termination towards the ground. The two Addressable LED Controllers enable the power being supplied to driver chips in the driver chip row 710 along the resistive VDD line 704 with a VDD voltage gradient with distinguishable voltage drops between neighboring driver chips with enhanced resolution of voltage-based driver chip selection.

[0087] As shown in FIG. 7A, a VDD port 702 of the first Addressable LED Controller 700 is connected to the first end of the resistive VDD line 704. The Cement Resistor port 722 of the second Addressable LED Controller 720 is connected to the second end of the resistive VDD line 704 and the ground. The driver chip row 710, which includes multiple driver chips 710-1, 710-2, . . ., 710-N, with driver chip 710-1 coupled to the end of the resistive VDD line 704 near a VDD port 702 of the first Addressable LED Controller 700. Subsequent driver chips 710-2, 710-3, . . . 710-N are arranged along the resistive VDD line 704 as shown, and the last driver chip 710-N in the row is coupled to the end of the resistive VDD line 704 near the connection to the load resistor Cement Resistor port 722 of the second Addressable LED Controller 720. With this configuration, the VDD line 704 serves as a resistive conductor under load. With an appropriate level of resistance, the total voltage drop along the resistive VDD line 704 may be significant when a high current flows through the VDD line 704 (e.g., 2A), creating a voltage gradient, resulting in a voltage drop across neighboring driver chips. As such, the VDD voltage received by each driver chip decreases progressively along the direction of the current flow from 700 to 720 along the VDD line 704 so that the voltage drop between any two neighboring driver chips is large enough to enable the individual driver chip selection based on received VDD voltage according to the present teaching as described herein. For example, assuming a total resistance of 3.5 Q along the VDD line 704, the total voltage drop may reach 2V from the first driver chip 710-1 to the last driver chip 710-N, resulting in a 20mV difference between neighboring driver chips when N=100.

[0088] FIG. 7B illustrates a different alternative configuration to facilitate individual LED driver chip selection, according to an embodiment of the present teaching. In this configuration, two Addressable LED Controllers, 730 and 740reside at two ends of the driver chip row 710, as illustrated in FIG. 7B. In this configuration, the first Addressable LED Controller 730 includes two VDD ports, a first VDD port 732 and a second VDD port 736. The second Addressable LED Controller 740 includes two Cement Resistor ports, a first Cement Resistor port 742 and a second Cement Resistor port 744, both of which are connected to ground. Two separate VDD lines, 734 and 738, are employed in this configuration. The first VDD line 734 connects the first VDD port 732 to the first Cement Resistor port 742 and delivers the VDD from port 732 to odd numbed driver chips, e.g., the first, third, fifth, . . ., driver chips. The second VDD line 738 connects the second VDD port 736 to the second Cement Resistor port 744 and delivers the VDD from port 736 to even numbered driver chips, e.g., the second, the fourth, . . ., driver chips.

[0089] This dual-path configuration divides the driver chip row 710 into two parts, each of which is powered by a dedicated resistive VDD line. In the individual driver chip selection mode, the first Addressable LED Controller 730 may provide an initial voltage on both VDD ports 732 and 736 (e.g., 7V), and the second Addressable LED Controller 740 grounds both Cement Resistor ports 742 and 744 at a final voltage. In some embodiments, the initial voltage from the first Addressable LED Controller 730 may be set at 7V and the final voltage at the second Addressable LED Controller 740 at 3 V. In this case, each VDD line experiences a 4 V voltage drop, doubling the available drop as compared to that with a single- line configuration as shown in FIG. 7A (with a 2V drop). Consequently, the VDD voltage drops between neighboring driver chips using the configuration of FIG. 7B also double with increased current of approximately 40 mV, as compared to 20 mV in the single-line configuration as shown in FIG. 7A.

[0090] FIG. 7C illustrates yet another different alternative configuration facilitating individual driver chip selection, according to another embodiment of the present teaching. In this configuration, three VDD lines are employed. Similarly, the configuration in FIG. 7C includes two Addressable LED Controllers. A first Addressable LED Controller 750 is positioned on one end of the driver chip row 710 and a second Addressable LED Controller 760 is positioned on the opposite end. In this embodiment, the first Addressable LED Controller 750 includes three VDD ports — 752, 754, and 756 — each of which supplies power to a separate VDD line. The second Addressable LED Controller 760 includes three Cement Resistor ports — 762, 764, and 766 — each of which is connected to ground.

[0091] Correspondingly, there are three VDD lines, a first VDD line 753, a second VDD line 755, and a third VDD line 757 as shown in FIG. 7C. The first VDD line 753 connects the first VDD port 752 to the first Cement Resistor port 762; the second VDD line 755 connects the second VDD port 754 to the second Cement Resistor port 764; and the third VDD line 757 connects the third VDD port 756 to the third Cement Resistor port 766. The three VDD lines respectively provide VDD voltages to the driver chips in an alternate manner, e.g., the first VDD line 753 supplies VDD voltage to the first driver chip, the second VDD line 755 to the second driver chip, the third VDD line 757 to the third driver chip, and then the first VDD line 753 to the fourth driver chip, the second VDD line 755 to the fifth driver chip, the third VDD line 757 to the sixth driver chip, etc.

[0092] Compared to the dual-path configuration as illustrated in FIG. 7B, this three-path configuration creates an even larger voltage drop between neighboring driver chips, providing enhanced voltage gradient without increasing the physical spacing between chips.Each VDD line supplies a VDD voltage to only one-third of the total number of driver chips in a row with increased resistance between two neighboring driver chips on the same VDD line. As such, the VDD voltage drops between neighboring driver chips on the same VDD line is accordingly increased as compared with that using the two-path configuration shown in FIG. 7B. With a larger voltage drop between neighboring driver chips, this three-path configuration further improves the precision in detecting the selecting condition (VDD < SDI) within each driver chip, thereby enhancing the performance.

[0093] Other alternative configurations may also be implemented based on the same principle for increased VDD voltage drop between neighboring driver chips along each VDD line, as illustrated in FIGs. 7A - 7C. For example, a four-path or five-path VDD arrangements may be implemented by further expanding the configuration in FIG. 7C, to introduce even larger VDD drops between neighboring driver chips on the same VDD lines. While FIGs. 7A - 7C provide configurations with dual Addressable LED Controllers, in yet other embodiments, more than two Addressable LED Controllers may also be deployed to achieve the same result. For instance, one Addressable LED Controller may be positioned at one end of a driver chip row, with multiple VDD ports. Multiple additional Addressable LED Controllers may be provided at the other end of the driver chip row with a dedicated Cement Resistor port for receiving a respective VDD line from one of the multiple VDD ports of an Addressable LED Controller at the opposing end. Each VDD line may supply voltage to some selected driver chips and the multiple VDD lines provide the coverage to all driver chips in that driver chip row. Such arrangements maintain the unidirectional programming scheme while offering flexibility in routing to achieve desired voltage drops between neighboring driver chips on the same VDD line.

[0094] As discussed herein in connection with FIGs. 7A - 7C, one of the two Addressable LED Controllers may serve as a load termination at one end of the driver chip row to provide enhanced performance as compared to using a resistor as the load termination. In addition to acting as the load termination, an Addressable LED Controller serving as a load termination end may also be implemented to perform other tasks such as real-time monitoring and diagnostic feedback. In some embodiments, both Addressable LED Controllers may be utilized to, e.g., measure VDD voltages and currents to ensure correct operation and signal integrity. Hence, using an Addressable LED Controller to serve as a load termination end in place of a resistor may also provide the flexibility to perform new functions therein, such as bi-directional address programming or advanced fault detection.

[0095] As discussed herein, the three-step process includes row selection, individual driver chip selection (or column selection), and address assignment. It should be appreciated that the row selection process and the individual driver chip selection process may be performed using the same VDD voltage supply network as illustrated in FIGs. 6A, 6D, 7A - 7C, or any alternative configurations of VDD voltage supply network as discussed herein. Specifically, during the row selection step, the current from the VDD port to each driver chip row is minimal compared to the current supplied in the normal current driving mode. As a result, the VDD voltage received by each driver chip row is substantially the same despite the voltage drops induced by the VDD supply network. As such, the substantially same VDD voltages for different driver chip rows facilitates the row selection process based on different SDI voltages supplied to each driver chip row. On the other hand, in the individual driver chip selection step, the current from the VDD port is larger which may be, e.g., comparable to the current supplied in the normal current driving mode. This is for the purpose of inducing a voltage gradient along the supply line to introduce a larger voltage drop between neighboring driver chips in the driver chip row. As such, the VDD voltage gradients for different driver chip in the driver chip row facilitates the individual driver chip selection process based on different VDD voltages supplied to each driver chip.

[0096] Similarly, the row selection process and the individual driver chip selection process may be performed using the same SDI voltage supply network as illustrated in FIG. 5 A. Specifically, during the row selection process, the SDI voltage received by each driver chip row is different based on the resistors connected to each driver chip row. During the individual driver chip selection process, the process is performed within a single driver chip row. As such, the different SDI voltages between the different driver chip row do not affect the process performed within the single driver chip row.

[0097] Once both the row and individual driver chip selection for each selected row are made, the individually selected driver chips may be programmed with a uniquely assigned address in the third step for address assignment. Different aspects involved in address assignment operation are illustrated in FIGs. 8A-8C. In this step, the Addressable LED Controller 500 sends, via the SDI signal, an address to each selected individual driver chip, which, upon receiving the address, then saves the received address in the Address Storage 460 located in its controller 450 for future recognition of data directed thereto using the address.

[0098] FIG. 8A illustrates an exemplary internal construct of an Addressable LED Controller 500, according to an embodiment of the present teaching. As discussed herein, theAddressable LED Controller 500 is configured to facilitate the full three-step process for address assignment to selected LED driver chips, including (1) row selection, (2) individual driver chip selection, and (3) address assignment. As discussed in connection with FIGs. 5A- 5C and 6A-6C, the Addressable LED Controller 500 performs critical control and relevant functions in the first and second steps of the three-step process. It is also provided to control and execution of functions to facilitate the third step, i.e., assigning to and programming an address into a selected LED driver chip. The functionalities associated with the third step are described with reference to FIGs. 8A-8C.

[0099] As shown in FIG. 8A, the Addressable LED Controller 500 includes a Microcontroller Unit (MCU) 804, a Digital-to- Analog Converter (DAC) 806, a Current Meter 807, a Cement Resistor 809, and a Liquid Crystal Display (LCD) 802. The LCD 802 may be coupled with one or more physical buttons or a touchscreen interface, allowing users to monitor operation status, to input commands, or to adjust settings. The MCU 804 may serve as a central control unit for the Addressable LED Controller 500 for executing certain software routines, interfacing with some user input / output components (e.g., LCD 802), controlling the operation of the DAC 806, sending serial data frames and instructions via the SDI line, and monitoring feedback such as current readings from the Current Meter 807.

[0100] In this illustrated embodiment, the DAC 806 is connected to the SDI port 830 and is provided for generating analog voltage waveforms on the SDI line in each specific steps of the three-step process — such as in the row selection and individual driver chip selection steps — where precise voltage control is required for facilitating the selections. In some embodiments, the SDI port 830 may be configured to operate in two distinct modes: DAC mode and GPIO mode. In the DAC mode, the DAC 806 may control the voltage level on the SDI line, while the GPIO pin of the MCU 804 is placed in a high-impedance (Hi-Z) state. In the GPIO mode, the MCU 804 may directly drive the SDI signal to transmit digital instructions or data frames, while the DAC 806 is placed in a high-impedance state to avoid signal interference. This mode switching mechanism ensures that both analog voltages ramping and digital signaling can be executed on the same SDI line without interference or conflict.

[0101] The Current Meter 807 is electrically connected to a VDD0 port 820 and is used to measure current changes during the row selection and individual chip selection steps. For example, in the first step of row selection, the Current Meter 807 is configured to monitor the current change caused by Ii from a selected row; in the second step of individual driver chip selection step, it is configured to monitor the current change caused by L from a selecteddriver chip. In particular, the Current Meter 807 detects incremental current increases — such as a 1 mA step change — originating from a selected driver chip as an indication of a successful selection. The use of a dedicated VDDO port allows for stable and accurate current sensing without interference from the high-current path used for address selection.Separately, a Cement Resistor 809 is connected to the VDD1 port 822 to serve as a main high-current supply path during different steps of the three-step address assignment process. During the individual drive chip selection step, the Addressable LED Controller 500 may drive VDD1 to an elevated voltage level (e.g., 7 V), creating a current flow through the resistive VDD line and the Cement Resistor 809 to GND. This current induces a voltage gradient along a selected driver chip row, enabling internal comparators within each driver chip to detect whether the selection condition is met based on the received local VDD levels to achieve voltage-based driver chip selection. By isolating the high-current (VDD1) and low-current (VDDO) paths, the Addressable LED Controller 500 achieves both precise current monitoring and controlled voltage drop without signal interference.

[0102] The Addressable LED Controller 500 as discussed herein may send a designated address to the selected driver chip during the address assignment step, so that the designated address may be stored in the selected driver chip. In operation, the Addressable LED Controller receives, from each driver chip, a set of DI / VDD voltages. The different driver chips in different rows may be programmed with a uniquely assigned address by the Addressable LED Controller 500. The unique address for each driver chip is determined based on a combination of the driver chip row characteristics during the row selection process and the DI / VDD voltages of the selected driver chip during the individual driver chip selection process, which will be discussed further with reference to FIG. 8B.

[0103] FIG. 8B illustrates an exemplary address programming scheme with respect to a 3x4 block of driver chips, according to the present teaching. The 3x4 block of driver chips may be connected to the Addressable LED Controller 500 in a similar way as in FIG. 5A (The Addressable Controller 500, VDD and SDI lines are not depicted in FIG. 8B for illustration clarity). The 3x4 block of driver chips may reside on a larger section of LED display screen or a section having a MxN block of driver chips. The position of the 3x4 block of driver chips in the larger section may be denoted by (Xi, Yi). For example, the 3x4 block may be located at an upper-left comer of the MxN block and its position may be denoted by (Xi, Yi) = (0,0). Similarly, each driver chip in the 3x4 block is denoted by a set of unique coordinates. For example, driver chip 812-3 can be denoted by (Xi+2, Yi+3). As discussed in the row selection scheme, different driver chip rows Xi+1, Xi+2 and Xi+3 are distinguishablebased on different current transmission paths originated from the SDI port of the Addressable LED Controller 500. In some embodiments, the different driver chip rows may also be distinguished based on the time of when the Addressable LED Controller receives the signaling current II from the selected driver chip row. As such, different driver chip row may be assigned with a different parameter R. For example, the driver chip row Xi+2 which is the first selected row among the three driver chip rows may be assigned with a parameter R1. Then, as discussed in the individual driver chip selection scheme, different driver chips 812- 1, 812-2, 812-3 and 812-4 in the driver chip row Xi+2 are distinguishable based on different DI / VDD voltages upon being selected. For example, driver chip 812-4 is selected at DI2-4 and VDD2-4. As such, each driver chip in the driver chip row Xi+2 may be assigned with a parameter C, which may be expressed as a function of DI / VDD in the form of C = func (DI, VDD). It can be seen that the combination of parameters R and C uniquely identify an individual driver chip among the 3x4 block of driver chips. As such, the Addressable LED Controller may be able to program a unique address for the individual driver chip based on its parameters R and C, denoted by Address = Code (R, C).

[0104] In some embodiments, different driver chip rows may be connected to the same VDD lines. As such, different driver chips in the same column may be selected at the same DI / VDD voltages and are assigned with the same parameter C. For example, DI1-1 = DI2-1 = DI3-1 and VDDI-I=VDD2-I=VDD3-I. However, since each driver chip is located at different driver chip rows, their parameters R are different. Therefore, the address programming scheme as discussed herein is able to program a unique address for each individual driver chip in the 3x4 driver chip block.

[0105] Given the R and C parameter combinations that uniquely identifies an individual driver chip stored in the Addressable LED Controller 500, FIG. 8C illustrates exemplary signal transmission paths in an exemplary driver chip 810-1 during the third step of address assignment of the three-step process after the row and driver chip selection steps, according to different embodiments of the present teaching. Once an individual LED driver chip, e.g., 810-1, has been selected, the Addressable LED Controller 500 retrieves, from its internal memory (not shown), a list of DI voltage values and corresponding VDD voltages recorded associated with each driver chip during the prior individual driver chip selection process. To initiate the address assignment, the Addressable LED Controller 500 may be configured to set the voltage along the SDI line to a target level to ensure that the desired driver chips are selected. The target level of the SDI voltage may be determined in the following way. For example, assume there are N=21 driver chips along a driver chip row. As illustrated in FIG.6 A, the driver chip 610-1 located at the beginning of the VDD line may see the highest VDD voltage of 7V, and the VDD voltage for the driver chip 610-21 located at the end of the VDD line may see a voltage of 5V, resulting in a 2V / 20 = 0. IV voltage drop between neighboring chips. When the SDI voltage is set to be 6 V, the SDI voltage reaches the VDD voltage of the driver chip 610-11. As such, the driver chips from 610-11 to 610-21 having VDD voltages smaller than or equal to 6V are selected by this SDI voltage. If the SDI voltage is set to be 6. IV, one more driver chip 610-10 having a VDD voltage of 6. IV is further selected in addition to the driver chips 610-11 to 610-20. Due to potential fluctuations in the SDI voltage caused by ripples or noises, the SDI voltage that intends to select the driver chips from 610- 11 to 610-21 may be set to a value between 6V and 6.1V. As an example, the SDI voltage may set by averaging 6V and 6.1V, such that driver chips 610-11 to 610-21 are selected and the driver chip 610-10 is not selected.

[0106] After applying the desired DI voltage, the Addressable LED Controller 500 pulls the SDI line down to a low logic level (e.g., 0 V), causing all driver chips to exit the detection mode while retaining their internal Test Flags. The Addressable LED Controller 500 then sends a digital command via the SDI line to instruct the currently selected driver chip (whose Test Flag is now in the second state) to enter an address assignment mode. The Addressable LED Controller 500 transmits a digital address value to the SDI line received by the Address Storage 460 through the Data Receiver 470, and the selected driver chip 810-1 stores this address in the Address Storage 460 before automatically exiting the address assignment mode. As discussed herein, the digital address value is a uniquely assigned address of the driver chip based on its combination of R and C parameters.

[0107] In some embodiments, to confirm a successful address assignment, the Addressable LED Controller 500 may introduce a delay longer than the required write time and may perform a verification sequence. First, a data frame, which may be a command, from the Addressable LED Controller is transmitted to all the driver chips that is configured to turn off all LEDs, and the VDD current coming from the output ports of all the driver chips is measured. In a normal operation, the VDD current, upon receiving the data frame to turn off all LEDs, should be zero. If the detected VDD current by the Addressable LED Controller 500 is not zero, then there might be a failed communication between the Addressable LED Controller 500 and one or more of the driver chips. Then, the address assignment step may be paused for subsequent tests to identify the cause of the failed communication. In the normal operation, a second frame, which may be another command, from the Addressable is sent to the red LED of the chosen driver chip which is expected to generate a known signalingcurrent (e.g., approximately 1 mA) sent through the Current Gain Buffer 480 and Current Driver 496 to the VDD port. The Addressable LED Controller 500 measures the increase in VDD current and compares it to a valid range (e.g., 0.7 mA to 1.3 mA). If the increase falls within range, the address assignment is considered successful. Otherwise, if the increase is too small or too large — suggesting failure or unintended programming of multiple chips — an error is raised, and the process may pause for manual inspection.

[0108] Each driver chip starts with a default address value (e.g., 0), and only driver chips with the default address are permitted to receive new addresses. This ensures that in each cycle, only one unprogrammed driver chip is selected and written. For example, in the first pass, only driver chip 2 is selected and programmed with address 2. In the second pass, driver chips 2 and 4 are selected, and pixel 4 receives address 4. In the third pass, driver chips 2, 4, and 6 are selected, and driver chip 6 is assigned address 6. By separating driving chip detection and address assignment into two stages, the Addressable LED Controller 800 enables error checking based on SDI voltage and VDD current before finalizing address assignment. This improves robustness against environmental interference during factorylevel programming.

[0109] FIG. 8D illustrates an exemplary flowchart of assigning an address to an individual LED, according to different embodiments of the present teaching. At step 805, an input voltage DI is set to a level by averaging the previously recorded target value for a first driver chip and the next higher voltage value for its neighboring driver chip, such that the chip with the matching detection threshold is uniquely affected. At step 815, the driver chip with its Test Flag 654 in a second state detects the condition enters an address assignment mode, where it disables all current output channels and awaits a digital address. At step 825, the Addressable LED Controller 500 transmits a first address to the first driver chip via the SDI line. At step 835, the first chip stores the address internally and automatically exits the address assignment mode. At step 845, a first data frame is sent to all driver chips instructing them to turn off all LED output channels, including red, green, and blue, ensuring zero output current across the system. At step 855, a first current measurement IDD1 is recorded from the VDD line by the Current Meter 807 of the controller, establishing a current baseline. At step 865, a second data frame is transmitted to command only the chip with the newly written first address to output a known signaling current Ii, such as 1 mA, through a designated LED output (e.g., the red channel). At step 875, a second current measurement IDD2 is recorded from the VDD line.

[0110] At step 885, the controller compares IDD2 with IDD1 and determines whether the increase in current is approximately equal to the known current Ii, within a valid tolerance range (e.g., ± 0.3 mA). At step 895, if the increase in current is within the acceptable range, the Addressable LED Controller 800 determines that the first address has been successfully assigned to the intended driver chip. Otherwise, the process may indicate a failed write or an address conflict, and appropriate corrective actions such as error reporting or manual inspection may be initiated.

[0111] With the detailed disclosure provided herein about the three-step process to assigning addresses to different LED driver chips, the addresses for different individually selected LEDs in different rows may be assigned and programmed therein in an automated manner according to the present teaching. As discussed herein, the row selection scheme as disclosed herein allows different rows being selected automatically. Depending on the SDI voltages delivered to different rows through paths with resistors, different rows may be selected at a different time instant. For instance, as shown in FIG. 5A with three illustrated rows 510, 512, and 514, the SDI voltage is provided directly on the second contact to deliver the SDI voltage to driver chips parallelly connected in row 512. The same SDI voltage is delivered to row 510 and 514, via respective paths passing through corresponding first and third resistors. Due to the resistors, the SDI voltages delivered to the driver chips in row 510 and 512 are lower than that to row 512 at the same time instant. As such, rows 510 and 514 are selected later as compared with the selection of row 512. Given that, different individual driver chips in different rows may also happen at different times. Because of that, the addresses assignments to selected driver chips may also happen at different times.

[0112] The same operational scheme as discussed herein with respect to the 3x4 block of driver chips as shown in FIG. 5 A may be applied to a MxN block of LEDs, with M rows and N columns. In some embodiment, MxN may correspond to an entire LED display screen or a section thereof. This is shown in FIG. 9, where the MxN LED driver chips may be programmed with uniquely assigned addresses in an automated process using the three-step scheme as disclosed herein according to the present teaching. That is, each parallelly connected LED with integrated driver chip therein can be programmed with an assigned unique address continually and automatically without having to do so via individually soldering each driver chip in a sequential manner or by changing the local condition of each LED as what is done in the conventional solutions. As such, the address assigning / programming method and system according to the present teaching not only is capable ofcarrying out the task more efficiently but also is more reliable to deliver a satisfactory result in a cost-effective manner.

[0113] FIG. 10 is an illustrative diagram of an exemplary computing device architecture that may be used to realize a specialized system implementing the present teaching in accordance with various embodiments. Such a specialized system incorporating the present teaching has a functional block diagram illustration of a hardware platform, which includes user interface elements. The computer may be a general -purpose computer or a special purpose computer. Both can be used to implement a specialized system for the present teaching. This computer 1000 may be used to implement any component or aspect of the framework as disclosed herein. For example, the information analytical and management method and system as disclosed herein may be implemented on a computer such as computer 1000, via its hardware, software program, firmware, or a combination thereof. Although only one such computer is shown, for convenience, the computer functions relating to the present teaching as described herein may be implemented in a distributed fashion on a number of similar platforms, to distribute the processing load.

[0114] Computer 1000, for example, includes COM ports 1050 connected to and from a network connected thereto to facilitate data communications. Computer 1000 also includes a central processing unit (CPU) 1020, in the form of one or more processors, for executing program instructions. The exemplary computer platform includes an internal communication bus 1010, program storage and data storage of different forms (e.g., disk 1070, read only memory (ROM) 1030, or random-access memory (RAM) 1040), for various data files to be processed and / or communicated by computer 1000, as well as possibly program instructions to be executed by CPU 1020. Computer 1000 also includes an VO component 1060, supporting input / output flows between the computer and other components therein such as user interface elements 1080. Computer 1000 may also receive programming and data via network communications.

[0115] Hence, aspects of the methods of information analytics and management and / or other processes, as outlined above, may be embodied in programming. Program aspects of the technology may be thought of as “products” or “articles of manufacture” typically in the form of executable code and / or associated data that is carried on or embodied in a type of machine-readable medium. Tangible non-transitory “storage” type media include any or all of the memory or other storage for the computers, processors or the like, or associated modules thereof, such as various semiconductor memories, tape drives, disk drives and the like, which may provide storage at any time for the software programming.

[0116] All or portions of the software may at times be communicated through a network such as the Internet or various other telecommunication networks. Such communications, for example, may enable loading of the software from one computer or processor into another, for example, in connection with information analytics and management. Thus, another type of media that may bear the software elements includes optical, electrical, and electromagnetic waves, such as used across physical interfaces between local devices, through wired and optical landline networks and over various air-links. The physical elements that carry such waves, such as wired or wireless links, optical links, or the like, also may be considered as media bearing the software. As used herein, unless restricted to tangible “storage” media, terms such as computer or machine “readable medium” refer to any medium that participates in providing instructions to a processor for execution.

[0117] Hence, a machine-readable medium may take many forms, including but not limited to, a tangible storage medium, a carrier wave medium or physical transmission medium. Non-volatile storage media include, for example, optical or magnetic disks, such as any of the storage devices in any computer(s) or the like, which may be used to implement the system or any of its components as shown in the drawings. Volatile storage media include dynamic memory, such as a main memory of such a computer platform. Tangible transmission media include coaxial cables; copper wire and fiber optics, including the wires that form a bus within a computer system. Carrier-wave transmission media may take the form of electric or electromagnetic signals, or acoustic or light waves such as those generated during radio frequency (RF) and infrared (IR) data communications. Common forms of computer-readable media therefore include for example: a floppy disk, a flexible disk, hard disk, magnetic tape, any other magnetic medium, a CD-ROM, DVD or DVD-ROM, any other optical medium, punch cards paper tape, any other physical storage medium with patterns of holes, a RAM, a PROM and EPROM, a FLASH-EPROM, any other memory chip or cartridge, a carrier wave transporting data or instructions, cables or links transporting such a carrier wave, or any other medium from which a computer may read programming code and / or data. Many of these forms of computer readable media may be involved in carrying one or more sequences of one or more instructions to a physical processor for execution.

[0118] Those skilled in the art will recognize that the present teachings are amenable to a variety of modifications and / or enhancements. For example, although the implementation of various components described above may be embodied in a hardware device, it may also be implemented as a software only solution, e.g., an installation on an existing server. In addition, the techniques as disclosed herein may be implemented as a firmware,firmware / software combination, firmware / hardware combination, or a hardware / firmware / software combination.

[0119] While the foregoing has described what are considered to constitute the present teachings and / or other examples, it is understood that various modifications may be made thereto and that the subject matter disclosed herein may be implemented in various forms and examples, and that the teachings may be applied in numerous applications, only some of which have been described herein. It is intended by the following claims to claim any and all applications, modifications and variations that fall within the true scope of the present teachings.

Claims

WE CLAIM:

1. A light emitting diode (LED) control system, comprising: an addressable LED controller for controlling address assignment to multiple rows of LEDs through a first voltage supplied to the multiple rows of LEDs via a serial data input (SDI) port and a second voltage supplied to the multiple rows of LEDs via a voltage drain (VDD) supply port; each of the multiple rows of LEDs includes a plurality of parallelly connected LEDs, each of which is integrated with a respective driver chip configured to receive the first voltage and the second voltages via: a data input (DI) port operatively coupled to the SDI port for receiving the first voltage from the SDI port, a VDD port operatively coupled to the VDD supply port for receiving the second voltage from the VDD supply port; and the driver chip in each of the plurality of parallelly connected LEDs in each of the multiple rows comprises: a comparator for comparing the first voltage and the second voltage to generate a comparison result, a controller for controlling an operational state of the driver chip based on the comparison result and for reporting the operational state of the driver chip to the addressable LED controller, and an address storage for storing a unique address assigned to the LED by the addressable LED controller when the operational state of the driver chip satisfies a predetermined condition, wherein the unique address is to be used to recognize data directedto the LED for display by matching the unique address stored in the address storage of the driver chip in the LED with an address associated with the data.

2. The system of claim 1, wherein the predetermined condition associated with each of parallelly connected driver chips associated with the plurality of parallelly connected LEDs in each of the multiple rows specifies that: the row that the driver chip is located in the multiple rows is selected in a row selection mode; and a position that the driver chip is at in the row of parallelly connected LED driver chips is selected in an individual driver chip selection mode.

3. The system of claim 2, wherein the addressable LED controller is configured to control row selection by: sending a first control signal to parallelly connected LED driver chips in the multiple rows to enter the row selection mode; supplying a gradually rising SDI voltage as the first voltage via the SDI port to each of the multiple rows each of which has parallelly connected LED driver chips via a corresponding path with an associated level of resistance so that the multiple rows receive different rising SDI voltages at each time instant; and providing a VDD voltage as the second voltage via the VDD supply port to the multiple rows with parallelly connected LED driver chips.

4. The system of claim 3, wherein, in the row selection mode, each of the parallelly connected LED driver chips in each of the multiple rows is configured for:comparing, via the comparator, the received VDD voltage with the received rising SDI voltage to detect when the received rising SDI voltage exceeds the received VDD voltage; and based on a comparison result from the comparator in the row selection mode, the controller in the driver chip is configured for: setting a row selection flag to signal that the row that the driver chip is in is selected, and sending a first feedback signal to the addressable LED controller to report that the row is selected.

5. The system of claim 4, wherein the first feedback signal corresponds to a first signaling current flowing into the addressable LED controller; and the signaling current is sensed by the addressable LED controller in the row selection mode to detect that one of the multiple rows is selected in the row selection mode.

6. The system of claim 2, wherein the addressable LED controller is further configured for controlling individual driver chip selection in a row by: sending a second control signal to the parallelly connected LED driver chips in the row to enter the individual driver chip selection mode; supplying, in the individual driver chip selection mode, a gradually rising SDI voltage as the first voltage via the SDI port to each of the parallelly connected LED driver chips in the row; and providing, in the individual driver chip selection mode, a VDD voltage as the second voltage via the VDD supply port through a VDD line network to the parallelly connectedLED driver chips in the row, whereinthe VDD line network is constructed to introduce a distinguishable voltage drop between neighboring parallelly connected driver chips.

7. The system of claim 6, wherein, in the individual driver chip selection mode, the comparator in each of the parallelly connected LED driver chips is configured for comparing the received gradually rising SDI voltage with the VDD voltage received from the VDD line network to determine when the received gradually rising SDI voltage exceeds the received VDD voltage; and when a comparison result from a comparator in one of the parallelly connected driver chips indicates that the received gradually rising SDI voltage exceeds the received VDD voltage, the controller in the driver chip is configured for: setting a test flag therein to signal that the driver chip at a respective position is selected, and sending a second feedback signal to the addressable LED controller indicating that the driver chip is selected, wherein the second feedback signal includes a first value of the gradually rising SDI voltage and a second value of the VDD voltage received by the driver chip at the time of being selected.

8. The system of claim 7, wherein the second feedback signal further includes a second signaling current flowing into the addressable controller; and the second signaling current is sensed by the addressable LED controller in the individual driver chip selection mode to detect that one of the parallelly connected driver chips in one of the multiple rows is selected.

9. The system of claim 2, wherein the addressable LED controller is further configured for generating a unique address for each of the parallelly connected LED driver chips in each of the multiple rows by: recording the operational states reported from the controller of the driver chip during the row selection mode and the individua driver chip selection mode; creating the unique address for the driver chip based on the recorded operational states associated with the row selection and driver chip selection of the driver chip.

10. A method for an addressable light emitting diode (LED) controller, comprising: sending a first control signal to multiple rows of LEDs, each of which is integrated with a driver chip therein, wherein the first control signal instructs driver chips in the multiple rows of LEDs to enter a row selection mode; and in the row selection mode, supplying a first gradually rising voltage to the multiple rows, supplying a second voltage to the driver chips in the multiple rows, wherein the first gradually rising voltage and the second voltage are provided to the multiple rows to facilitate selecting one of the multiple rows based on the first gradually rising voltage and the second voltage, receiving a first feedback signal from one of the driver chips in one of the multiple rows to signal that the row has been selected.

11. The method of claim 10, further comprising: sending a second control signal to parallelly connected driver chips in one of the multiple rows to instruct the parallelly connected driver chips in a row to enter an individual driver chip selection mode; andin the individual driver chip selection mode, supplying a third gradually rising voltage to the parallelly connected driver chips in the row, supplying a fourth voltage to the parallelly connected driver chips through a supply line network constructed to ensure a distinguishable voltage drop between neighboring parallelly connected driver chips to facilitate selection of individual drivers from the parallelly connected driver chips, receiving a second feedback signal from an individual one of the parallelly connected driver chips signaling that the individual driver chip in the row is selected, wherein the second feedback signal includes a first value of the first gradually rising voltage and a second value of the second voltage received by the individual driver chip at the time of being selected.

12. The method of claim 11, further comprising: creating, based on the first and the second feedback signals, a unique address for the individual driver chip selected from the parallelly connected driver chips in a selected row; and sending the unique address to the selected individual driver chip for storing in the selected individual driver chip.

13. The method of claim 10, wherein the first gradually rising voltage corresponds to an SDI voltage with a gradually rising voltage level; and the second voltage corresponds to a VDD voltage.

14. The method of claim 10, whereinthe first feedback signal corresponds to a first signaling current flowing into the addressable LED controller; and the signaling current is sensed by the addressable LED controller in the row selection mode to detect that one of the multiple rows is selected in the row selection mode.

15. The method of claim 10, wherein the second feedback signal further includes a second signaling current flowing into the addressable controller; and the second signaling current is sensed by the addressable LED controller in the individual driver chip selection mode to detect that one of the parallelly connected driver chips in one of the multiple rows is selected.

16. The method of claim 10, wherein, in the row selection mode, each of the multiple rows receives the first gradually rising voltage via a corresponding resistive path with a different level of resistance; and each of the parallelly connected driver chips in each of the multiple rows: compares the first gradually rising voltage received via its corresponding resistive path with the second voltage, and generates the first feedback signal when the first gradually rising voltage received from its corresponding resistive path exceeds the second voltage.

17. The method of claim 11, wherein, in the individual driver chip selection mode, each of the parallelly connected driver chips in the selected row compares the first gradually rising voltage with the second voltage received from the supply line network; andgenerating the second feedback signal when the first gradually rising voltage exceeds the second voltage on the second voltage port.

18. A method for a driver chip integrated with a light emitting diode (LED) in one of multiple rows of parallelly connected LEDs to program therein an address assigned thereto, comprising: receiving a first control signal instructing the driver chip to enter a row selection mode; and upon entering the row selection mode, the driver chip: receiving a first gradually rising voltage and a second voltage, wherein the first gradually rising voltage received by the driver chip is via a resistive path, comparing the received first gradually rising voltage and the second voltage to detect when the first rising voltage exceeds the second voltage, signifying that a row that the driver chip is in is selected, and sending, upon detecting that the first gradually rising voltage exceeds the second voltage, a first feedback signal to signal that the row that the driver chip is in has been selected.

19. The method of claim 18, further comprising: receiving a second control signal instructing the driver chip to enter an individual driver chip selection mode; and upon entering the individual driver chip selection mode, receiving a first gradually rising voltage and a second voltage, wherein the second voltage is provided via a supply line network constructed to ensure a distinguishable voltage drop between the driver chip and a neighboring driver chip,comparing the received first gradually rising voltage and the second voltage from the supply line network to detect when the first rising voltage exceeds the second voltage from the supply line network, and sending, upon detecting that the first gradually rising voltage exceeds the second voltage, a second feedback signal to indicate that the driver chip is selected, wherein the second feedback signal includes a first value of the first gradually rising voltage and a second value of the second voltage received by the driver chip at the time of being selected.

20. The method of claim 19, further comprising: receiving the address assigned to the driver chip and created based on the first and the second feedback signals; receiving data with an associated address; buffering the data for driving the LED when the assigned address matches with the associated address of the data.

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