Back-contact solar cell, solar module and photovoltaic system

Abstract

The present application is applicable to the technical field of solar cells, and provides a back-contact solar cell, a solar module and a photovoltaic system. The back-contact solar cell comprises: a silicon substrate (1), which has a back surface (11) and a front surface (12) disposed opposite each other; a P-type doped polysilicon layer (2), which is located in a first region (111) of the back surface (11) of the silicon substrate (1); an N-type doped polysilicon layer (3), which is located in a second region (112) of the back surface (11) of the silicon substrate (1); a first metal electrode (6), which is disposed in the first region (111) and in contact with the P-type doped polysilicon layer (2); and a second metal electrode (7), which is disposed in the second region (112) and in contact with the N-type doped polysilicon layer (3), wherein the depth of a metal crystal of the first metal electrode (6) entering the P-type doped polysilicon layer (2) is greater than the depth of a metal crystal of the second metal electrode (7) entering the N-type doped polysilicon layer (3).

Description

A back-contact solar cell, battery module and photovoltaic system

[0001] This application claims priority to Chinese Patent Application No. 2024108214233, filed on June 24, 2024, entitled “A Back Contact Solar Cell, Battery Module and Photovoltaic System”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of solar cell technology, specifically to a back-contact solar cell, a cell module, and a photovoltaic system. Background Technology

[0003] Solar cell power generation is a sustainable and clean energy source. It utilizes the photovoltaic effect of semiconductors to convert sunlight into electrical energy, and conversion efficiency is a crucial indicator of solar cell performance. IBC (Interdigitated back contact) solar cells, also known as interdigitated back contact cells, have both positive and negative electrodes located on the back of the cell. This completely eliminates the shading caused by metal grid lines on the front surface, thus preventing optical losses and significantly improving conversion efficiency. Furthermore, the electrode-free design on the front of the cell results in a more aesthetically pleasing product, making it suitable for various applications.

[0004] In the prior art, the back side of the back contact solar cell forms staggered P-regions and N-regions. Typically, the depth of the metal electrode corresponding to the P-region into the P-type doped polycrystalline silicon layer is equal to the depth of the metal electrode corresponding to the N-region into the N-type doped polycrystalline silicon layer. Since the contact effect between the P-type doped polycrystalline silicon layer and the metal electrode is relatively poor, the conductivity between the P-type doped polycrystalline silicon layer and the metal electrode is poor, which affects the conversion efficiency of the cell. Technical issues

[0005] How to solve the problem of poor contact between the P-type doped polycrystalline silicon layer and the metal electrode in back-contact solar cells, which affects the cell conversion efficiency. Technical solutions

[0006] This application provides a back-contact solar cell, which aims to solve the problem of poor contact between the P-type doped polycrystalline silicon layer and the metal electrode in existing back-contact solar cells, thus affecting the cell conversion efficiency.

[0007] The back-contact solar cell provided in this application includes:

[0008] A silicon substrate having a back side and a front side disposed opposite to each other;

[0009] A P-type doped polycrystalline silicon layer is located in the first region on the back side of the silicon substrate;

[0010] An N-type doped polycrystalline silicon layer is located in a second region on the back side of the silicon substrate, and the first region is different from the second region;

[0011] A first metal electrode is disposed in the first region and in contact with the P-type doped polysilicon layer;

[0012] A second metal electrode is disposed in the second region and in contact with the N-type doped polysilicon layer;

[0013] Wherein, the depth to which the metal crystal of the first metal electrode penetrates the P-type doped polycrystalline silicon layer is greater than the depth to which the metal crystal of the second metal electrode penetrates the N-type doped polycrystalline silicon layer.

[0014] Optionally, the ratio of the depth of the metal crystal of the first metal electrode entering the P-type doped polysilicon layer to the depth of the metal crystal of the second metal electrode entering the N-type doped polysilicon layer is 1 to 4, and not equal to 1.

[0015] Optionally, the ratio of the depth of the metal crystal of the first metal electrode entering the P-type doped polysilicon layer to the depth of the metal crystal of the second metal electrode entering the N-type doped polysilicon layer is 1 to 2, and not equal to 1.

[0016] Optionally, the depth of the metal crystal of the first metal electrode penetrating the P-type doped polysilicon layer is 2~300nm; the depth of the metal crystal of the second metal electrode penetrating the N-type doped polysilicon layer is 1~200nm.

[0017] Optionally, both the first metal electrode and the second metal electrode comprise silver, glass frit, and organic materials, and the glass frit content in the first metal electrode is greater than the glass frit content in the second metal electrode.

[0018] Optionally, the refractive index of the P-type doped polycrystalline silicon layer is less than that of the N-type doped polycrystalline silicon layer.

[0019] Optionally, it also includes a back passivation film layer located on the back side of the P-type doped polysilicon layer and the back side of the N-type doped polysilicon layer, wherein the metal crystal of the first metal electrode passes through the back passivation film layer into the P-type doped polysilicon layer, and the metal crystal of the second metal electrode passes through the back passivation film layer into the N-type doped polysilicon layer.

[0020] Optionally, the average grain size of the P-type doped polysilicon layer is greater than the average grain size of the N-type doped polysilicon layer.

[0021] Optionally, the ratio of the average grain size of the P-type doped polysilicon layer to the average grain size of the N-type doped polysilicon layer is 1 to 4, and not equal to 1.

[0022] Optionally, the thickness of the N-type doped polysilicon layer is greater than the thickness of the P-type doped polysilicon layer.

[0023] Optionally, the ratio of the thickness of the N-type doped polycrystalline silicon layer to the thickness of the P-type doped polycrystalline silicon layer is 1 to 2, and not equal to 1.

[0024] This application also provides a battery assembly including any of the above-described back-contact solar cells.

[0025] This application also provides a photovoltaic system including the aforementioned battery module. Beneficial effects

[0026] The back-contact solar cell of this application sets the depth of the metal crystal of the first metal electrode into the P-type doped polycrystalline silicon layer to be greater than the depth of the metal crystal of the second metal electrode into the N-type doped polycrystalline silicon layer. While keeping the depth of the metal crystal of the second metal electrode into the N-type doped polycrystalline silicon layer unchanged, increasing the depth of the metal crystal of the first metal electrode into the P-type doped polycrystalline silicon layer can increase the contact area between the metal crystal of the first metal electrode and the P-type doped polycrystalline silicon layer, improve the contact effect between the first metal electrode and the P-type doped polycrystalline silicon layer, achieve good ohmic contact, improve the conductivity of the first metal electrode and the P-type doped polycrystalline silicon layer, and thus improve the cell conversion efficiency. Attached Figure Description

[0027] Figure 1 is a schematic diagram of a back-contact solar cell provided in an embodiment of this application;

[0028] Figure 2 is a schematic diagram of a back-contact solar cell structure provided in an embodiment of this application;

[0029] Figure 3 is a scanning electron microscope photograph of the metal crystal of the first metal electrode of a back-contact solar cell entering a P-type doped polycrystalline silicon layer, according to an embodiment of this application.

[0030] Figure 4 is a scanning electron microscope image of the metal crystal of the second metal electrode of a back-contact solar cell entering the N-type doped polycrystalline silicon layer, according to an embodiment of this application. Embodiments of the present invention

[0031] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this application and are not intended to limit this application.

[0032] In the description of this application, it should be understood that the terms "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0033] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0034] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0035] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0036] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0037] The back-contact solar cell provided in this application sets the depth of the metal crystal of the first metal electrode into the P-type doped polycrystalline silicon layer to be greater than the depth of the metal crystal of the second metal electrode into the N-type doped polycrystalline silicon layer. Compared with the second metal electrode, increasing the depth of the metal crystal of the first metal electrode into the P-type doped polycrystalline silicon layer can increase the contact area between the metal crystal of the first metal electrode and the P-type doped polycrystalline silicon layer, improve the contact effect between the first metal electrode and the P-type doped polycrystalline silicon layer, achieve good ohmic contact, improve the conductivity of the first metal electrode and the P-type doped polycrystalline silicon layer, and thus improve the cell conversion efficiency.

[0038] Please refer to Figure 1. An embodiment of this application provides a back-contact solar cell, comprising:

[0039] Silicon substrate 1, the silicon substrate 1 having a back side 11 and a front side 12 disposed opposite to each other;

[0040] P-type doped polycrystalline silicon layer 2 is located in the first region 111 on the back side 11 of silicon substrate 1;

[0041] The N-type doped polycrystalline silicon layer 3 is located in the second region 112 on the back side 11 of the silicon substrate 1, and the first region 111 is different from the second region 112.

[0042] A first metal electrode 6 is disposed in the first region 111 and in contact with the P-type doped polysilicon layer 2;

[0043] A second metal electrode 7 is disposed in the second region 112 and in contact with the N-type doped polysilicon layer 3;

[0044] The depth d3 of the metal crystal of the first metal electrode 6 entering the P-type doped polycrystalline silicon layer 2 is greater than the depth d4 of the metal crystal of the second metal electrode 7 entering the N-type doped polycrystalline silicon layer 3.

[0045] As shown in Figure 1, the back side 11 of the silicon substrate 1 is the bottom side, and the front side 12 is the top side. The dashed lines L1 and L2 are only used to distinguish the first region 111 and the second region 112, and do not represent the actual regions present in the back-contact solar cell. Referring to Figure 1, the region to the left of dashed line L1 is the first region 111, and the region to the right of dashed line L2 is the second region 112. The first region 111 and the second region 112 are different regions. The P-type doped polycrystalline silicon layer 2 is located in the first region 111 of the back side 11 of the silicon substrate 1, and the N-type doped polycrystalline silicon layer 3 is located in the second region 112 of the back side 11 of the silicon substrate 1. The P-type doped polycrystalline silicon layer 2 is located in the region to the left of dashed line L1 on the back side 11 of the silicon substrate 1; the N-type doped polycrystalline silicon layer 3 is located in the region to the right of dashed line L2 on the back side 11 of the silicon substrate 1.

[0046] In this embodiment of the application, a back-contact solar cell is provided by setting the depth d3 of the metal crystal of the first metal electrode 6 into the P-type doped polycrystalline silicon layer 2 to be greater than the depth d4 of the metal crystal of the second metal electrode 7 into the N-type doped polycrystalline silicon layer 3. Under the premise that the depth of the metal crystal of the second metal electrode 7 into the N-type doped polycrystalline silicon layer 3 remains unchanged, increasing the depth of the metal crystal of the first metal electrode 6 into the P-type doped polycrystalline silicon layer 3 can increase the contact area between the metal crystal of the first metal electrode 6 and the P-type doped polycrystalline silicon layer 2, improve the contact effect between the first metal electrode 6 and the P-type doped polycrystalline silicon layer 2, and thus improve the conductivity of the first metal electrode 6 and the P-type doped polycrystalline silicon layer 2, thereby improving the cell conversion efficiency. The depth d3 of the metal crystal of the first metal electrode 6 entering the P-type doped polysilicon layer 2 is set to be greater than the depth d4 of the metal crystal of the second metal electrode 7 entering the N-type doped polysilicon layer 3. This can be because the maximum depth of the metal crystal of the first metal electrode 6 entering the P-type doped polysilicon layer 2 is greater than the maximum depth of the metal crystal of the second metal electrode 7 entering the N-type doped polysilicon layer 3, or the average depth of the metal crystal of the first metal electrode 6 entering the P-type doped polysilicon layer 2 is greater than the average depth of the metal crystal of the second metal electrode 7 entering the N-type doped polysilicon layer 3.

[0047] In this embodiment, pastes with different burn-through capabilities can be used to print the first metal electrode 6 and the second metal electrode 7, thereby controlling the depth to which the metal crystals of the metal electrodes penetrate the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3. Specifically, the burn-through capability of the paste for the first metal electrode 6 is greater than that of the paste for the second metal electrode 7, which allows the metal crystals of the first metal electrode 6 to penetrate the P-type doped polysilicon layer 2 to a greater depth than the metal crystals of the second metal electrode 7 to penetrate the N-type doped polysilicon layer 3.

[0048] As an optional embodiment of this application, both the first metal electrode 6 and the second metal electrode 7 comprise a metal material, a glass frit, and an organic material, and the glass frit content in the first metal electrode 6 is greater than the glass frit content in the second metal electrode 7. The metal material may be silver or aluminum.

[0049] As an optional embodiment of this application, both the first metal electrode 6 and the second metal electrode 7 include silver, glass frit, and organic materials, and the glass frit content in the first metal electrode 6 is greater than the glass frit content in the second metal electrode 7.

[0050] In this embodiment, both the first metal electrode 6 and the second metal electrode 7 include silver, glass frit, and organic material components. The glass frit includes at least one of PbO, Bi2O3, ZnO, SiO2, and MgO. The glass frit content in the first metal electrode 6 is greater than that in the second metal electrode 7, which makes the burn-through capability of the paste of the first metal electrode 6 greater than that of the paste of the second metal electrode 7. This results in the metal crystal of the first metal electrode 6 penetrating to a greater depth in the P-type doped polycrystalline silicon layer 2 than the metal crystal of the second metal electrode 7 penetrating to a greater depth in the N-type doped polycrystalline silicon layer 3.

[0051] As an optional embodiment of this application, the depth d3 of the metal crystal of the first metal electrode 6 penetrating the P-type doped polysilicon layer 2 is 2~300 nm; the depth d4 of the metal crystal of the second metal electrode 7 penetrating the N-type doped polysilicon layer 3 is 1~200 nm. The depths d3 and d4 of the metal crystal of the first metal electrode 6 penetrating the P-type doped polysilicon layer 2 and the second metal electrode 7 penetrating the N-type doped polysilicon layer 3 can be flexibly set according to actual needs. Both the depths d3 and d4 of the metal crystal of the first metal electrode 6 penetrating the P-type doped polysilicon layer 2 and the second metal electrode 7 penetrating the N-type doped polysilicon layer 3 can be measured by scanning electron microscopy.

[0052] For example, the depth d3 of the metal crystal of the first metal electrode 6 penetrating the P-type doped polysilicon layer 2 can be 2 nm, or 10 nm, or 30 nm, or 50 nm, or 70 nm, or 90 nm, or 100 nm, or 110 nm, or 120 nm, or 140 nm, or 160 nm, or 200 nm, or 240 nm, or 260 nm, or 280 nm, or 300 nm. The depth d4 of the metal crystal of the second metal electrode 7 penetrating the N-type doped polysilicon layer 3 can be 1 nm, or 5 nm, or 20 nm, or 30 nm, or 50 nm, or 80 nm, or 90 nm, or 100 nm, or 120 nm, or 130 nm, or 150 nm, or 160 nm, or 180 nm, or 190 nm, or 200 nm.

[0053] As an optional embodiment of this application, the ratio of the depth d3 of the metal crystal of the first metal electrode 6 entering the P-type doped polysilicon layer 2 to the depth d4 of the metal crystal of the second metal electrode 7 entering the N-type doped polysilicon layer 3 is 1 to 4, and is not equal to 1.

[0054] In this embodiment, the ratio of the depth d3 of the metal crystal of the first metal electrode 6 entering the P-type doped polysilicon layer 2 to the depth d4 of the metal crystal of the second metal electrode 7 entering the N-type doped polysilicon layer 3 is greater than 1 and less than or equal to 4. This can reduce the metallization damage of the P-type doped polysilicon layer 2, reduce the sheet resistance of the P region, and improve the battery efficiency. It can also ensure good contact between the metal electrode and the P-type doped polysilicon layer 2, thereby improving the battery conversion efficiency.

[0055] For example, the ratio of the depth d3 of the metal crystal of the first metal electrode 6 penetrating the P-type doped polysilicon layer 2 to the depth d4 of the metal crystal of the second metal electrode 7 penetrating the N-type doped polysilicon layer 3 can be:

[0056] 1.01, or 1.05, or 1.1, or 1.15, or 1.2, or 1.25, or 1.3, or 1.35, or 1.4, or 1.45, or 1.5, or 1.55, or 1.6, or 1.65, or 1.7, or 1.75, or 1.8, or 1.85, or 1.9, or 1.92, or 2, or 2.2, or 2.5, or 2.7, or 2.8, or 3.0, or 3.3, or 3.5, or 4.0.

[0057] As an optional embodiment of this application, the ratio of the depth d3 of the metal crystal of the first metal electrode 6 entering the P-type doped polysilicon layer 2 to the depth d4 of the metal crystal of the second metal electrode 7 entering the N-type doped polysilicon layer 3 is 1 to 2, and is not equal to 1.

[0058] In this embodiment, the ratio of the depth d3 of the metal crystal of the first metal electrode 6 entering the P-type doped polysilicon layer 2 to the depth d4 of the metal crystal of the second metal electrode 7 entering the N-type doped polysilicon layer 3 is greater than 1 and less than or equal to 2. This ensures good contact between the metal electrode and the P-type doped polysilicon layer 2, and also facilitates the process control of the depth d3 of the metal crystal of the first metal electrode 6 entering the P-type doped polysilicon layer 2 and the depth d4 of the metal crystal of the second metal electrode 7 entering the N-type doped polysilicon layer 3.

[0059] As an optional embodiment of this application, the depth of the metal crystal of the first metal electrode 6 penetrating the P-type doped polysilicon layer 2 is 2~300 nm; the depth of the metal crystal of the second metal electrode 7 penetrating the N-type doped polysilicon layer 3 is 1~200 nm, to avoid the depths of the metal crystal of the first metal electrode 6 penetrating the P-type doped polysilicon layer 2 and the metal crystal of the second metal electrode 7 penetrating the N-type doped polysilicon layer 3 being too deep or too shallow. The depths d3 and d4 of the metal crystal of the first metal electrode 6 penetrating the P-type doped polysilicon layer 2 and the second metal electrode 7 penetrating the N-type doped polysilicon layer 3 can be flexibly set according to actual needs.

[0060] For example, the depth d3 of the metal crystal of the first metal electrode 6 penetrating the P-type doped polysilicon layer 2 can be 2 nm, or 10 nm, or 30 nm, or 50 nm, or 70 nm, or 90 nm, or 100 nm, or 110 nm, or 120 nm, or 140 nm, or 160 nm, or 200 nm, or 240 nm, or 260 nm, or 280 nm, or 300 nm. The depth d4 of the metal crystal of the second metal electrode 7 penetrating the N-type doped polysilicon layer 3 can be 1 nm, or 5 nm, or 20 nm, or 30 nm, or 50 nm, or 80 nm, or 90 nm, or 100 nm, or 120 nm, or 130 nm, or 150 nm, or 160 nm, or 180 nm, or 190 nm, or 200 nm.

[0061] For example, as shown in FIG3, the thickness d2 of the P-type doped polysilicon layer 2 is 105 nm, and the depth d3 of the metal crystal of the first metal electrode 6 entering the P-type doped polysilicon layer 2 is 55.6 nm; as shown in FIG4, the thickness of the N-type doped polysilicon layer 2 is 107 nm, and the depth d4 of the metal crystal of the second metal electrode 7 entering the N-type doped polysilicon layer 3 is 45.6 nm.

[0062] As an optional embodiment of this application, the thickness d1 of the N-type doped polysilicon layer 3 is greater than the thickness d2 of the P-type doped polysilicon layer 2.

[0063] In this embodiment, by setting the thickness d1 of the N-type doped polysilicon layer 3 to be greater than the thickness d2 of the P-type doped polysilicon layer 2, the thickness d2 of the P-type doped polysilicon layer 2 is reduced compared to the thickness d1 of the N-type doped polysilicon layer 3. This reduces the etching difficulty of the P-type doped polysilicon layer 2 and the patterning process, making it easier to pattern the P-type doped polysilicon layer. Moreover, reducing the thickness d2 of the P-type doped polysilicon layer 2 reduces the difficulty of boron diffusion, which is beneficial to the boron diffusion process and facilitates the preparation of a higher concentration of P-type doped polysilicon layer 2. Furthermore, since the thickness d1 of the N-type doped polysilicon layer 3 is greater than the thickness d2 of the P-type doped polysilicon layer 2, the N-type doped polysilicon layer 3 is thicker than the P-type doped polysilicon layer 2, which can enhance the passivation effect and improve the battery efficiency.

[0064] As an optional embodiment of this application, the ratio of the thickness d1 of the N-type doped polysilicon layer 3 to the thickness d2 of the P-type doped polysilicon layer 2 is 1 to 2, and is not equal to 1.

[0065] In this embodiment, the ratio of the thickness d1 of the N-type doped polysilicon layer 3 to the thickness d2 of the P-type doped polysilicon layer 2 is greater than 1 and less than or equal to 2. This reduces the etching difficulty of the P-type doped polysilicon layer 2, facilitates the patterning process of the P-type doped polysilicon layer 2, and is beneficial to the boron diffusion process, reducing the difficulty of boron diffusion and facilitating the preparation of a higher concentration of P-type doped polysilicon layer 2.

[0066] For example, the ratio of the thickness d1 of the N-type doped polysilicon layer 3 to the thickness d2 of the P-type doped polysilicon layer 2 can be:

[0067] 1.01, or 1.05, or 1.1, or 1.15, or 1.2, or 1.25, or 1.3, or 1.35, or 1.4, or 1.45, or 1.5, or 1.55, or 1.6, or 1.65, or 1.7, or 1.75, or 1.8, or 1.85, or 1.9, or 1.92, or 2.

[0068] Optionally, when the ratio of d1 to d2 is 1 to 2, the thickness d1 of the N-type doped polysilicon layer 3 is 100 nm to 600 nm, and the thickness d2 of the P-type doped polysilicon layer 2 can be 50 nm to 300 nm. Within the above ranges of d1 and d2, both the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 can easily achieve good doping effects, both exhibit good passivation effects, while ensuring minimal metallization damage and low contact resistance, and at a relatively low cost. Furthermore, it can reduce the etching difficulty of P-type doped polysilicon, facilitate patterning processes for P-type doped polysilicon, benefit the preparation of the N-type doped polysilicon layer 3, and facilitate the boron diffusion process, reducing the difficulty of boron diffusion and making it easier to prepare a high-concentration P-type doped polysilicon layer 2.

[0069] As an optional embodiment of this application, the refractive index of the P-type doped polycrystalline silicon layer 2 is less than that of the N-type doped polycrystalline silicon layer 3.

[0070] It is understandable that the refractive index of the N-type doped polycrystalline silicon layer 3 remains unchanged, while the refractive index of the P-type doped polycrystalline silicon layer 2 is reduced to be lower than that of the N-type doped polycrystalline silicon layer 3. This reduces the parasitic absorption effect in the P-region, thereby further improving the battery efficiency. The refractive indices of the P-type doped polycrystalline silicon layer 2 and the N-type doped polycrystalline silicon layer 3 can be flexibly set according to actual needs, as long as the refractive index of the P-type doped polycrystalline silicon layer 2 is lower than that of the N-type doped polycrystalline silicon layer 3.

[0071] As an optional embodiment of this application, the average grain size of the P-type doped polysilicon layer 2 is greater than the average grain size of the N-type doped polysilicon layer 3.

[0072] In this embodiment, the average grain size of the P-type doped polycrystalline silicon layer 2 and the average grain size of the N-type doped polycrystalline silicon layer 3 can be specifically measured using X-ray diffraction (XRD), scanning electron microscopy (SEM), or transmission electron microscopy (TEM). The average grain size of the P-type doped polycrystalline silicon layer 2 is greater than that of the N-type doped polycrystalline silicon layer 3. This can be understood as the average grain size of all grains in the P-type doped polycrystalline silicon layer 2 per unit area being greater than the average grain size of all grains in the N-type doped polycrystalline silicon layer 3 per unit area. In other words, the N-type doped polycrystalline silicon layer 3 has a greater number of grains per unit area, while the P-type doped polycrystalline silicon layer 2 has fewer grain boundaries per unit area compared to the N-type doped polycrystalline silicon layer 3. Therefore, this increases the density of the P-type doped polycrystalline silicon layer 2, reduces its sheet resistance, decreases current loss, and further improves battery efficiency. Moreover, the P-type doped polycrystalline silicon layer 2 has fewer grain boundaries, which can reduce the metallization damage to the P-type doped polycrystalline silicon layer 2 during the battery metallization process, and also helps to improve battery efficiency.

[0073] In practical applications, during the fabrication of the P-type doped polycrystalline silicon layer 2 and the N-type doped polycrystalline silicon layer 3, intrinsic amorphous silicon can be deposited first, followed by doping diffusion. High-temperature treatment is performed during the doping diffusion process. By controlling the diffusion temperature and diffusion time of the P-type doped polycrystalline silicon layer 2 and the N-type doped polycrystalline silicon layer 3, the average grain size of the two layers can be controlled. For example, a higher doping diffusion temperature and a longer diffusion time can be set for the P-type doped polycrystalline silicon layer 2, resulting in an average grain size larger than that of the N-type doped polycrystalline silicon layer 3.

[0074] As an optional embodiment of this application, the ratio of the average grain size of the P-type doped polysilicon layer 2 to the average grain size of the N-type doped polysilicon layer 3 is 1 to 4, and is not equal to 1.

[0075] In this embodiment, the ratio of the grain size of the P-type doped polysilicon layer 2 to the grain size of the N-type doped polysilicon layer 3 is greater than 1 and less than or equal to 4. This ensures that the average grain size of the P-type doped polysilicon layer 2 and the average grain size of the N-type doped polysilicon layer 3 are within a suitable range, which can reduce the sheet resistance of the P-region, improve the battery efficiency, and facilitate the fabrication of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3.

[0076] As an optional embodiment of this application, the average grain size of the P-type doped polysilicon layer 2 is 50~600 nm; the average grain size of the N-type doped polysilicon layer 3 is 10~400 nm, which facilitates the fabrication of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3.

[0077] Referring to Figure 2, as an optional embodiment of this application, there is a first height difference h1 between the surface of the P-type doped polysilicon layer 2 near the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 near the silicon substrate 1. The surface of the P-type doped polysilicon layer 2 near the silicon substrate 1 is further away from the front side 12 of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 near the silicon substrate 1.

[0078] In this embodiment, the surface of the silicon substrate 1 near the P-type doped polysilicon layer 2 and the surface near the N-type doped polysilicon layer 3 are not on the same plane. The surface of the P-type doped polysilicon layer 2 near the silicon substrate 1 is further away from the front side 12 of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 near the silicon substrate 1. There is a first height difference h1 between the surfaces of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 near the silicon substrate 1. The relative positions of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 are controlled more precisely, and the position reference is more accurate. Moreover, before the latter doped polysilicon layer is fabricated, the etchable parts of the first doped polysilicon layer are etched more cleanly. Furthermore, the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 in the gap between the first region 111 and the second region 112 are etched more cleanly, resulting in better electrical performance. The first height difference h1 can be flexibly set according to actual needs and is not limited here.

[0079] As an optional embodiment of this application, there is a second height difference h2 between the surface of the P-type doped polysilicon layer 2 near the silicon substrate 1 and the surface of the N-type doped polysilicon layer 3 away from the silicon substrate 1. The surface of the P-type doped polysilicon layer 2 near the silicon substrate 1 is further away from the front side 12 of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 away from the silicon substrate 1.

[0080] In this embodiment, the surface of the P-type doped polysilicon layer 2 away from the silicon substrate 1 is further away from the front side 12 of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 away from the silicon substrate 1. A second height difference h2 exists between the surfaces of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3, achieving good isolation between them. This results in good electrical isolation and a lower risk of short circuits or leakage. The second height difference h2 can be flexibly set according to actual needs and is not limited here.

[0081] As an optional embodiment of this application, the front side 12 of the silicon substrate 1 may also be provided with a textured structure (not shown). The textured structure can achieve a good light trapping effect and improve the conversion efficiency of the back contact solar cell.

[0082] As an optional embodiment of this application, the front side 12 of the back contact solar cell is also provided with a front passivation antireflection film layer 9 to further reduce light reflection and further improve the conversion efficiency of the back contact solar cell.

[0083] As an optional embodiment of this application, the back-contact solar cell further includes a back passivation film layer 5 located on the back side 11 of the P-type doped polycrystalline silicon layer 2 and the back side 11 of the N-type doped polycrystalline silicon layer 3. The metal crystal of the first metal electrode 6 passes through the back passivation film layer 5 into the P-type doped polycrystalline silicon layer 2, and the metal crystal of the second metal electrode 7 passes through the back passivation film layer 5 into the N-type doped polycrystalline silicon layer 3. By setting the back passivation film layer 5, the passivation effect of the back side 11 of the cell is further improved, thereby further improving the conversion efficiency of the back-contact solar cell.

[0084] As an optional embodiment of this application, the silicon substrate 1 further includes a trench 8 located between the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3. Using the trench 8 to physically isolate the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 can further improve the isolation effect between them, and further reduce the risk of short circuits or leakage. The width of the trench 8 can be flexibly set according to actual needs and is not limited here.

[0085] This application also provides a battery assembly, which includes the back-contact solar cell described in the above embodiments. It should be noted that the battery assembly and the back-contact solar cell have the same or similar beneficial effects, and the related aspects between them can be referred to each other; to avoid repetition, they will not be repeated here.

[0086] This application also provides a photovoltaic system, which includes the battery module described in the above embodiments. It should be noted that this photovoltaic system has the same or similar beneficial effects as a back-contact solar cell, and the related aspects between the two can be referred to each other; to avoid repetition, they will not be repeated here.

[0087] The above are merely optional embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A back-contact solar cell, characterized in that, include: A silicon substrate having a back side and a front side disposed opposite to each other; A P-type doped polycrystalline silicon layer is located in the first region on the back side of the silicon substrate; An N-type doped polycrystalline silicon layer is located in a second region on the back side of the silicon substrate, and the first region is different from the second region; A first metal electrode is disposed in the first region and in contact with the P-type doped polysilicon layer; A second metal electrode is disposed in the second region and in contact with the N-type doped polysilicon layer; Wherein, the depth to which the metal crystal of the first metal electrode penetrates the P-type doped polycrystalline silicon layer is greater than the depth to which the metal crystal of the second metal electrode penetrates the N-type doped polycrystalline silicon layer.

2. The back-contact solar cell according to claim 1, characterized in that, The ratio of the depth of the metal crystal of the first metal electrode entering the P-type doped polysilicon layer to the depth of the metal crystal of the second metal electrode entering the N-type doped polysilicon layer is 1 to 4, and not equal to 1.

3. The back-contact solar cell according to claim 1, characterized in that, The ratio of the depth of the metal crystal of the first metal electrode entering the P-type doped polysilicon layer to the depth of the metal crystal of the second metal electrode entering the N-type doped polysilicon layer is 1 to 2, and not equal to 1.

4. The back-contact solar cell according to claim 1, characterized in that, The depth of the metal crystal of the first metal electrode penetrating the P-type doped polycrystalline silicon layer is 2~300nm; the depth of the metal crystal of the second metal electrode penetrating the N-type doped polycrystalline silicon layer is 1~200nm.

5. The back-contact solar cell according to claim 1, characterized in that, Both the first metal electrode and the second metal electrode comprise silver, glass frit, and organic materials, and the glass frit content in the first metal electrode is greater than that in the second metal electrode.

6. The back-contact solar cell according to claim 1, characterized in that, The refractive index of the P-type doped polycrystalline silicon layer is less than that of the N-type doped polycrystalline silicon layer.

7. The back-contact solar cell according to claim 1, characterized in that, It also includes a back passivation film layer located on the back side of the P-type doped polysilicon layer and the back side of the N-type doped polysilicon layer, wherein the metal crystal of the first metal electrode passes through the back passivation film layer into the P-type doped polysilicon layer, and the metal crystal of the second metal electrode passes through the back passivation film layer into the N-type doped polysilicon layer.

8. The back-contact solar cell according to claim 1, characterized in that, The average grain size of the P-type doped polycrystalline silicon layer is greater than that of the N-type doped polycrystalline silicon layer.

9. The back-contact solar cell according to claim 8, characterized in that, The ratio of the average grain size of the P-type doped polycrystalline silicon layer to the average grain size of the N-type doped polycrystalline silicon layer is 1 to 4, and not equal to 1.

10. The back-contact solar cell according to claim 1, characterized in that, The thickness of the N-type doped polycrystalline silicon layer is greater than the thickness of the P-type doped polycrystalline silicon layer.

11. The back-contact solar cell according to claim 10, characterized in that, The ratio of the thickness of the N-type doped polycrystalline silicon layer to the thickness of the P-type doped polycrystalline silicon layer is 1 to 2, and is not equal to 1.

12. A battery assembly, characterized in that, Including the back-contact solar cell as described in any one of claims 1 to 11.

13. A photovoltaic system, characterized in that, Includes the battery assembly as described in claim 12.

Images