Semiconductor structure, and method for manufacturing semiconductor structure

Abstract

A semiconductor structure, and a method for manufacturing a semiconductor structure. The semiconductor structure comprises: a substrate; a stack structure, which is located on the substrate, wherein the stack structure comprises a plurality of stack units stacked in a direction perpendicular to a surface of the substrate, and each stack unit at least comprises a stack of one memory cell element and one isolation structure; and a stress adjustment layer, which is located between the stack structure and the substrate, wherein the stress adjustment layer comprises a first silicon germanium layer, the material of the first silicon germanium layer comprises germanium-doped silicon, the content of germanium is a first composition ratio, the first composition ratio is linearly correlated with the ratio of the thickness of the memory cell element or the thickness of the isolation structure to the thickness of the stack unit, and the direction of thickness is the direction perpendicular to the surface of the substrate. By means of the semiconductor structure, a semiconductor device in which the problem of warping is ameliorated can be obtained.

Description

Semiconductor structure and method for manufacturing semiconductor structure

[0001] The present application claims priority to the Chinese patent application No. 202410868782.4, filed on June 28, 2024, and entitled "Semiconductor structure and method for manufacturing semiconductor structure", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the semiconductor structure. BACKGROUND

[0003] The development of dynamic random access memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. With the miniaturization of semiconductor device structures, the technical barriers encountered by existing structures are becoming more and more obvious. Therefore, developing more novel structures on the basis of existing structures is a favorable means to break through the existing technical barriers.

[0004] The emergence of three-dimensional dynamic random access memory (3D DRAM), especially 3D DRAM including multilayer horizontal cells (MHC), generally includes multiple transistors stacked on a substrate, which meets the above-mentioned requirements.

[0005] However, the manufacturing process of the multilayer stacked transistors and capacitors is complex, especially in the process of manufacturing the stacked transistors or capacitors, the wafer warpage is large during the formation of the stack, the process is difficult to control, the process flow needs to be optimized, and the device yield needs to be improved. SUMMARY

[0006] According to a first aspect of embodiments of the present disclosure, a semiconductor structure is provided, comprising:

[0007] a substrate;

[0008] a stack structure located on the substrate, the stack structure comprising a plurality of stack units stacked in a direction perpendicular to a surface of the substrate, each of the stack units comprising a stack of at least one storage cell element and one isolation structure;

[0009] a stress adjustment layer located between the stack structure and the substrate, the stress adjustment layer comprising a first silicon germanium layer;

[0010] The material of the first silicon germanium layer comprises silicon doped with germanium, wherein the content of germanium is a first component ratio, the first component ratio is linearly related to a proportion of a thickness of the storage cell element or a thickness of the isolation structure to a thickness of the stack unit, and the thickness is in a direction perpendicular to the surface of the substrate.

[0011] In some embodiments, the first composition ratio ranges from 3% to 20%.

[0012] In some embodiments, the first silicon germanium layer has a thickness greater than or equal to 3 microns.

[0013] In some embodiments, the stress adjustment layer further comprises a germanium-based layer, the germanium-based layer being located between the substrate and the first silicon germanium layer.

[0014] In some embodiments, the material of the germanium-based layer comprises silicon-doped germanium, wherein the content of germanium ranges from 50% to 100%.

[0015] In some embodiments, the germanium-based layer has a thickness ranging from 5 to 100 nanometers, and the first silicon germanium layer has a thickness ranging from 100 to 500 nanometers.

[0016] In some embodiments, the stack structure further comprises a second silicon germanium layer, the second silicon germanium layer being located in the stack unit closest to the substrate in the stack structure.

[0017] In some embodiments, the material of the second silicon germanium layer comprises silicon-doped germanium, wherein the content of germanium is a second composition ratio, the second composition ratio being greater than the first composition ratio, and the first composition ratio and the second composition ratio are linearly related.

[0018] In some embodiments, the second composition ratio ranges from 3.2% to 30%.

[0019] In some embodiments, the storage unit element is a capacitor structure, and the semiconductor structure further comprises: a transistor structure located at one end of the stack structure, a first source-drain region of the transistor structure being connected to the capacitor structure in one-to-one correspondence; a word line structure connected to a channel region of the transistor structure; a bit line structure connected to a second source-drain region of the transistor structure; or, the storage unit element is a bit line structure, and the semiconductor structure further comprises: a transistor structure located at one end of the stack structure, a second source-drain region of the transistor structure being connected to the bit line structure; a word line structure connected to a channel region of the transistor structure; a capacitor structure connected to a first source-drain region of the transistor structure in one-to-one correspondence.

[0020] According to a second aspect of the embodiments of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising:

[0021] providing a substrate;

[0022] forming a stress adjustment layer on the substrate, the stress adjustment layer comprising a first silicon germanium layer;

[0023] forming an initial stack structure on the stress adjustment layer, the initial stack structure comprising a plurality of initial stack units stacked in a direction perpendicular to a surface of the substrate, each of the initial stack units comprising at least a stack of one of the silicon layers and one of the second silicon germanium layers;

[0024] replacing the second silicon germanium layers in the initial stack structure with isolation structures, and replacing part of the silicon layers with memory cell elements to form a stack structure, the stack structure comprising a plurality of stack units stacked in a direction perpendicular to a surface of the substrate, each of the stack units comprising at least a stack of one of the memory cell elements and one of the isolation structures;

[0025] wherein a material of the first silicon germanium layer comprises silicon doped with germanium, a content of the germanium being a first composition ratio, the first composition ratio being linearly related to a proportion of a thickness of the memory cell element or a thickness of the isolation structure to a thickness of the stack unit, the thickness being in the direction perpendicular to the surface of the substrate.

[0026] In some embodiments, forming a stress adjustment layer on the substrate, the stress adjustment layer comprising a first silicon germanium layer, comprises: growing the first silicon germanium layer on a surface of the substrate by an epitaxial growth method; wherein the first silicon germanium layer has a thickness greater than 3 micrometers, and the first composition ratio is in a range of 3% to 20%.

[0027] In some embodiments, forming a stress adjustment layer on the substrate, the stress adjustment layer comprising a first silicon germanium layer and a germanium-based layer, comprises: growing the germanium-based layer on a surface of the substrate by an epitaxial growth method, and growing the first silicon germanium layer on a surface of the germanium-based layer by an epitaxial growth method; wherein a material of the germanium-based layer comprises germanium doped with silicon, a content of the germanium being in a range of 50% to 100%, the germanium-based layer has a thickness in a range of 5 to 100 nanometers, and the first silicon germanium layer has a thickness in a range of 100 to 500 nanometers.

[0028] In some embodiments, forming an initial stack structure on the stress adjustment layer comprises: alternately growing a plurality of the silicon layers and a plurality of the second silicon germanium layers on a surface of the first silicon germanium layer by an epitaxial growth method to form a plurality of the initial stack units stacked in a direction perpendicular to a surface of the substrate, each of the initial stack units comprising at least a stack of one of the silicon layers and one of the second silicon germanium layers; wherein a material of the second silicon germanium layer comprises silicon doped with germanium, a content of the germanium being a second composition ratio, the second composition ratio being greater than the first composition ratio, and the first composition ratio is linearly related to the second composition ratio, the second composition ratio being in a range of 3.2% to 30%.

[0029] In some embodiments, the storage unit element is a capacitor structure, and the method for manufacturing the semiconductor structure further comprises: forming a transistor structure at one end of the initial stack structure or the stack structure, a first source-drain region of the transistor structure being connected to the capacitor structure in a one-to-one correspondence; forming a word line structure connected to a channel region of the transistor structure; forming a bit line structure connected to a second source-drain region of the transistor structure; or, the storage unit element is a bit line structure, and the method for manufacturing the semiconductor structure further comprises: forming a transistor structure at one end of the stack structure, a second source-drain region of the transistor structure being connected to the bit line structure; forming a word line structure connected to a channel region of the transistor structure; and forming a capacitor structure connected to a first source-drain region of the transistor structure in a one-to-one correspondence. BRIEF DESCRIPTION OF DRAWINGS

[0030] FIGS. 1-7 are schematic diagrams of steps of forming a stacked semiconductor structure according to the related art;

[0031] FIGS. 8-14 are schematic diagrams of forming a semiconductor structure according to an exemplary embodiment;

[0032] FIGS. 15-21 are schematic diagrams of forming a semiconductor structure according to another exemplary embodiment;

[0033] FIG. 22 is a schematic diagram of forming a storage unit element according to an exemplary embodiment;

[0034] FIG. 23 is a schematic diagram of forming a storage unit element according to another exemplary embodiment;

[0035] FIG. 24 is a schematic diagram of forming a 3D DRAM according to an exemplary embodiment;

[0036] FIG. 25 is a schematic diagram of forming a 3D DRAM according to another exemplary embodiment. DETAILED DESCRIPTION

[0037] The technical solutions of the present disclosure will be described in further detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described herein. On the contrary, these implementation methods are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0038] The present disclosure will be described with respect to the following examples in conjunction with the accompanying drawings. The advantages and features of the present disclosure will become clear to those skilled in the art from the following description and claims. It should be noted that the drawings are in simplified form and are not drawn to precise scale. They are merely intended to facilitate the description of the present disclosure.

[0039] It can be understood that the meanings of "on", "over", and "above" of the present disclosure should be interpreted in the broadest way, so that the meaning of "on" not only means the meaning of "on" something with no intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of "on" something with intervening features or layers therebetween.

[0040] In the embodiments of the present disclosure, the terms "first", "second", "third", and the like are used to distinguish similar objects, and do not necessarily have to describe a particular order or sequence.

[0041] In the embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entirety of the underlying or overlying structure, or can have a scope that is less than the scope of the underlying or overlying structure. Further, the layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure, or the layer can be between any horizontal pair of planes at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface. The layer can include a plurality of sub-layers.

[0042] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0043] In the related art, the process flow of a 3D memory structure usually needs to first form a stack of sacrificial materials, then remove the sacrificial materials in the stack by lateral etching through the opening or groove in the middle or side of the stack, and then fill the target material as a replacement. In order to ensure the high performance requirement of the device, the method of epitaxial growth is usually used to form a stack of sacrificial materials on a wafer. However, the inventors of the present application have found that as the number of layers of the stack increases, due to the difference in crystal lattice between the sacrificial material and the material of the wafer itself, the wafer warping problem becomes increasingly apparent, which easily causes process instability, and even causes wafer chipping, product scrap, and other problems.

[0044] A solution to the wafer warping problem is provided in the related art, as shown in FIGS. 1-7. A warping compensation layer 101 (typically made of silicon nitride) is first attached to the back side of a wafer 100. A stack structure 102 including a sacrificial layer 1021 and a functional layer 1022 is then formed on the front side of the wafer 100 by epitaxial growth. A first mask 1031 is then formed on the top surface of the stack structure 102. A trench is formed in the stack structure 102 through the first mask 1031. Part of the sacrificial layer 1021 is removed through the trench. Replacement material 104 is then filled in the trench. The first mask 1031 is removed at the same time as part of the warping compensation layer 101 on the back side of the wafer 100 is removed, leaving part of the warping compensation layer 101'. A second mask 1032 is then formed on the top surface of the stack structure 102. A trench is formed in the stack structure 102 through the second mask 1032. The remaining part of the sacrificial layer 1021 is removed. Replacement material 104 is then filled in the trench. The second mask 1032 is removed at the same time as the remaining part of the warping compensation layer 101' on the back side of the wafer 100 is removed. Subsequently, a desired semiconductor structure is formed. The inventors of the present application have found that the method of forming a warping compensation layer on the back side of a wafer and then removing it involves multiple back side processing, wafer flipping, and other issues. The process is complicated, difficult, and costly.

[0045] To address the above technical problems, the present disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure. An example of the semiconductor structure and the method for manufacturing the semiconductor structure will be described below with reference to FIGS. 8-25. FIGS. 8-14 are schematic diagrams of steps and structures of a method for manufacturing a semiconductor structure according to an example embodiment of the present disclosure. FIGS. 15-21 are schematic diagrams of steps and structures of a method for manufacturing a semiconductor structure according to another example embodiment of the present disclosure. FIGS. 23 and 24 are schematic diagrams of forming a memory cell structure according to example embodiments of the present disclosure. FIGS. 24 and 25 are schematic diagrams of a 3D DRAM structure according to example embodiments of the present disclosure.

[0046] In an example embodiment of the present disclosure, as shown in FIG. 8, a substrate 200 is provided.

[0047] The material of the substrate 200 can be at least one of the following semiconductor materials or III-V materials: silicon, germanium, silicon germanium (SiGe), silicon on insulator (SOI), silicon on stacked silicon (SSOI), silicon on stacked silicon germanium (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc. In an example embodiment of the present disclosure, the material of the substrate 200 is single crystal silicon.

[0048] Referring to FIG. 9, a stress adjustment layer is formed on the substrate 200. In an exemplary embodiment of the present disclosure, the stress adjustment layer includes a first silicon germanium layer 201.

[0049] The material of the first silicon germanium layer 201 includes silicon doped with germanium, in which the germanium content is a first composition ratio Y. In some embodiments, the first composition ratio Y ranges from 3% to 20%. It should be noted that the germanium content described herein as a first composition ratio should be understood as the ratio of the number of germanium atoms in the silicon germanium layer to the total number of atoms (mainly silicon atoms and germanium atoms) in the silicon germanium layer.

[0050] The first silicon germanium layer 201 is formed on the front surface of the substrate 200. In some embodiments, the thickness of the first silicon germanium layer 201 is not less than 3 μm (micrometers). In other embodiments, the thickness of the first silicon germanium layer 201 is greater than 3 μm and less than or equal to 10 μm. The thickness of the first silicon germanium layer 201 should not be too thin, otherwise the effect of adjusting the warping will be poor, and it should not be too thick, otherwise the effect of adjusting the warping will be overcorrected. It should be noted that the front surface described herein is the functional surface of the wafer, and the required functional device will be formed on the functional surface subsequently.

[0051] In an exemplary embodiment of the present disclosure, the first silicon germanium layer 201 is formed on the front surface of the substrate 200 by an epitaxial growth method. Specifically, the process conditions of the epitaxial growth are as follows: the temperature range is controlled to be 600-700°C, the pressure range is controlled to be 5-50 torr, and the substrate 200 is supplied with a silicon source gas and a germanium source gas. In some embodiments, the silicon source gas is dichlorosilane (SiH2Cl2) and the germanium source gas is germane (GeH4). In other embodiments, the silicon source gas is monosilane (SiH4) and the germanium source gas is germane (GeH4). The flow rate of the silicon source gas and the germanium source gas ranges from 20 to 200 sccm (standard cubic centimeters per minute).

[0052] In an exemplary embodiment of the present disclosure, after the first silicon germanium layer 201 is epitaxially grown from the substrate 200, high-temperature annealing is performed to press the crystal dislocation between the first silicon germanium layer 201 and the substrate 200 at the interface, and to completely release the stress in the first silicon germanium layer 201. In some embodiments, the temperature range of the high-temperature annealing is 950-1050°C, and the time range of the high-temperature annealing is 3-10 minutes.

[0053] In an exemplary embodiment of the present disclosure, referring to FIG. 10, an initial stack structure 202 is formed on the stress adjustment layer.

[0054] In an example embodiment of the present disclosure, the method of forming the initial stack structure 202 includes using a silicon germanium (SiGe) surface of the first SiGe layer 201 as an initial base layer, and using an epitaxial growth method to grow the initial stack structure 202 of the Si-SiGe alternating stack on the first SiGe layer 201, with the stacking direction being along a direction perpendicular to the surface of the substrate 200. In this process, a second SiGe layer can be formed by adding a germanium source gas during the epitaxial growth of the silicon layer. The initial stack structure 202 includes a plurality of initial stack units 2020, each of which includes at least one silicon layer 2022 and one second SiGe layer 2021.

[0055] In some embodiments, the number of layers of the second SiGe layer 2021 in the initial stack structure 202 is the same as the number of layers of the silicon layer 2022, and is greater than or equal to 5. In other embodiments, the number of layers of the second SiGe layer 2021 in the initial stack structure 202 is one more than the number of layers of the silicon layer 2022.

[0056] In some embodiments, the top layer of the initial stack structure 202, i.e., the layer farthest from the first SiGe layer 201 in the initial stack structure 202, is the second SiGe layer 2021, which can be used to protect the underlying silicon layer 2022 and the subsequently formed memory cell element from damage during subsequent manufacturing process flows after being replaced with an insulating material. In some embodiments, the top layer of the initial stack structure 202, i.e., the layer farthest from the first SiGe layer 201 in the initial stack structure 202, can also be the silicon layer 2022, but the protection can also be provided by the subsequently formed mask layer covering the top layer.

[0057] In some embodiments, the material of the second SiGe layer 2021 in the initial stack structure 202 includes silicon doped with germanium, where the germanium content is a second composition ratio X. During the epitaxial growth of the second SiGe layer 2021, the germanium content in the second SiGe layer 2021, i.e., the second composition ratio X, can be controlled by controlling the supply ratio of the silicon source gas and the germanium source gas, and thus the range of the second composition ratio X is 3.2% - 30%. In some embodiments, the germanium content (the second composition ratio X) in the second SiGe layer 2021 is greater than the germanium content (the first composition ratio Y) in the first SiGe layer 201, and the first composition ratio Y is linearly related to the second composition ratio X. It should be noted that the description of the germanium content in the second SiGe layer 2021 as the second composition ratio X described herein is understood to be similar to the description of the germanium content in the first SiGe layer 201 as the first composition ratio Y described above, and thus is not repeated here.

[0058] In some embodiments, only a single second silicon germanium layer 2021 and a single silicon layer 2022 are included in one initial stack unit 2020 of the initial stack structure 202, wherein the thickness of the single second silicon germanium layer 2021 is A, the thickness of the single silicon layer 2022 is B, and A or B ranges from 50-150 nm. The germanium content (first composition ratio Y) in the first silicon germanium layer 201 is linearly correlated with the proportion of the thickness A of the second silicon germanium layer 2021 or the thickness B of the single silicon layer 2022 to the thickness of the initial stack unit 2020. In some embodiments, the germanium content (first composition ratio Y) in the first silicon germanium layer 201 is linearly positively correlated with the proportion of the thickness A of the second silicon germanium layer 2021 to the thickness of the initial stack unit 2020. In an exemplary embodiment of the present disclosure, the first composition ratio Y and the second composition ratio X, as well as the thickness A of the single second silicon germanium layer 2021 and the thickness B of the single silicon layer 2022 satisfy the following relationship:

[0059] It should be noted that the thickness direction described herein should be understood as the direction perpendicular to the surface of the substrate 200. The first silicon germanium layer 201 satisfying the above relationship can be in a partially or completely relaxed state, and in some embodiments, after the initial stack structure 202 is epitaxially grown on the first silicon germanium layer 201 under substantially the same process conditions, the warpage of the wafer as a whole changes by less than 10 μm, and the warpage change rate is lower than 50% as the number of epitaxial layers increases.

[0060] In an exemplary embodiment of the present disclosure, after the initial stack structure 202 is formed on the first silicon germanium layer 201, a trench 204 is formed in the initial stack structure 202, as shown in FIG. 11, and the trench 204 penetrates through the initial stack structure 202. In some embodiments, the bottom of the trench 204 stops in the first silicon germanium layer 201.

[0061] Specifically, in some embodiments, the step of forming the trench 204 includes: first forming a first mask layer 2031 on the top layer of the initial stack structure 202, and patterning the first mask layer 2031 to form an opening, the bottom of the opening exposing part of the top surface of the initial stack structure 202 as an etching region to be etched, and then etching the initial stack structure 202 along the opening and penetrating through the entire initial stack structure 202. In some embodiments, the etching method can adopt at least one of the following etching methods: plasma dry etching, ion beam etching (IBE), and reactive ion etching (RIE). In some embodiments, an etching endpoint detection method (EPD) is used to make the bottom of the trench 204 obtained by etching stop in the first silicon germanium layer 201.

[0062] In some embodiments, the material of the first mask layer 2031 can be a combination of one or more of photoresist, spin-on hard mask (SOH), spin-on carbon (SOC), amorphous carbon, polysilicon, silicon nitride, silicon oxynitride, silicon carbon nitride.

[0063] In an exemplary embodiment of the present disclosure, after forming the trench 204 through the initial stack structure 202, a protective layer 205 is formed at the bottom of the trench 204.

[0064] In some embodiments, the top surface of the protective layer 205 is not lower than the top surface of the second silicon germanium layer 2021 of the bottom layer (i.e., the single layer closest to the substrate 200) in the initial stack structure 202, and the top surface of the protective layer 205 is lower than the top surface of the second silicon germanium layer 2021 of the bottom layer upwardly closest to the bottom layer (i.e., the single layer second closest to the substrate 200) in the initial stack structure 202.

[0065] In an exemplary embodiment of the present disclosure, after forming the trench 204 and the protective layer 205, referring to FIG. 12, the end surface of the second silicon germanium layer 2021 in the initial stack structure 202 exposed by the trench 204, the second silicon germanium layer 2021 is subjected to a lateral etch, selectively removing part of the second silicon germanium layer 2021 in the initial stack structure 202 and forming a gap between the adjacent silicon layers 2022 remaining, and the lateral etch direction extends from close to the trench 204 to away from the trench 204.

[0066] In some embodiments, the second silicon germanium layer 2021 is subjected to a lateral etch using a silicon germanium etching solution. Specifically, the silicon germanium etching solution can include a mixed solution of hydrofluoric acid (HF), hydrogen peroxide (H2O2), and a silicon corrosion inhibitor.

[0067] In some embodiments, during the lateral etch, because the protective layer 205 has a low etching selectivity to the second silicon germanium layer 2021 and covers the end surface of the second silicon germanium layer 2021 of the bottom layer (i.e., the single layer closest to the substrate 200) in the initial stack structure 202, the second silicon germanium layer 2021 of the bottom layer is not in contact with the etching solution and thus is not etched.

[0068] In an exemplary embodiment of the present disclosure, after removing part of the second silicon germanium layer 2021, as shown in FIG. 13, the trench 204 is filled with an isolation material 206, and the isolation material 206 fills the trench 204 and the gap between the adjacent silicon layers 2022 after the aforementioned lateral etch.

[0069] In some embodiments, the isolation material 206 can be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, silicon carbon oxynitride. In an exemplary embodiment of the present disclosure, the isolation material 206 uses silicon oxide.

[0070] In an exemplary embodiment of the present disclosure, after the isolation material 206 fills up the trench 204 and the remaining space between the adjacent silicon layers 2022 after the aforementioned etching, other trenches (not shown, only different from the location of the trench 204) are formed in other locations of the initial stack structure 202, and the remaining portion of the second silicon germanium layer 2021 is removed through the other trenches. Specifically, as shown in FIG. 14, a second mask layer 2032 is formed, the material of the second mask layer 2032 can be the same as that of the first mask layer 2031, the second mask layer 2032 is patterned to form an opening, the bottom of the opening exposes part of the top surface of the initial stack structure 202 as the etching area, and the initial stack structure 202 is etched along the opening to form other trenches (not shown) and penetrate the entire initial stack structure 202. The protection layer 205 is also formed at the bottom of the other trenches (not shown), and the end surface of the second silicon germanium layer 2021 exposed by the other trenches (not shown) in the initial stack structure 202, the second silicon germanium layer 2021 is etched, the remaining portion of the second silicon germanium layer 2021 in the initial stack structure 202 is selectively removed and the remaining space between the adjacent silicon layers 2022 is formed, and the etching direction extends from the other trenches (not shown) to the other trenches (not shown). After removing the remaining portion of the second silicon germanium layer 2021, the isolation material 206 is filled in the other trenches (not shown), and the isolation material 206 fills up the other trenches (not shown) and the remaining space between the adjacent silicon layers 2022 after the aforementioned etching.

[0071] In some embodiments, the trench 204 and other trenches (not shown) can be formed in the same etching step, i.e., the first mask layer 2031 and the second mask layer 2032 are the same mask layer, which is patterned to form a plurality of openings, the bottoms of the plurality of openings expose the top surface of the initial stack structure 202 to serve as the etching region of the trench 204 and other trenches (not shown), and then the trench 204 and other trenches (not shown) are etched along the plurality of openings. It can be understood that, in some embodiments, the subsequent selective removal of the second silicon germanium layer 2021 in the initial stack structure 202 through the trench 204 and other trenches (not shown) can also be formed in the same etching step, and in some embodiments, the subsequent filling of the isolation material 206 can also be formed in the same filling step. In the above-mentioned embodiments, it is not necessary to remove the first mask layer 2031 formed on the top layer of the initial stack structure 202 after the first mask layer 2031 is patterned, to form the second mask layer 2032 on the top layer of the initial stack structure 202, and then to pattern the second mask layer 2032, which reduces the number of photolithography steps, and the subsequent selective removal of the second silicon germanium layer 2021 and the filling of the isolation material 206 also saves similar process steps, thereby greatly saving the process cost, reducing the process difficulty, and reducing the damage to the surface of the top layer of the initial stack structure 202 in the process of removing the first mask layer 2031 and the second mask layer 2032, and the corrosion and consumption of the etching liquid to the silicon layer 2022 in the multi-step etching process.

[0072] In another example embodiment of the present disclosure, referring to FIG. 15, a substrate 300 is provided.

[0073] The material of the substrate 300 can be at least one of the following semiconductor materials or III-V materials: silicon, germanium, silicon germanium (SiGe), silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). In an example embodiment of the present disclosure, the material of the substrate 300 is monocrystalline silicon.

[0074] Referring to FIG. 16, a stress adjustment layer is formed on the substrate 300. In an example embodiment of the present disclosure, the stress adjustment layer includes a first silicon germanium layer 301 and a germanium-based layer 3010.

[0075] The material of the first silicon germanium layer 301 includes silicon doped with germanium, and the germanium content is a first composition ratio Y. In some embodiments, the first composition ratio Y ranges from 3% to 20%. It should be noted that the germanium content described herein as the first composition ratio should be understood as the ratio of the number of germanium atoms in the silicon germanium layer to the total number of atoms (mainly silicon atoms and germanium atoms) in the silicon germanium layer.

[0076] The material of the germanium-based layer 3010 includes silicon-doped germanium, in which the content of germanium is a third composition ratio Z. In some embodiments, the third composition ratio Z ranges from 50% to 100%. The content of germanium in the germanium-based layer 3010 described herein as the third composition ratio Y should be understood as similar to the description of the content of germanium in the first silicon-germanium layer 301 as the first composition ratio Y in the above-described embodiments, which will not be repeated here.

[0077] The germanium-based layer 3010 is formed on the front surface of the substrate 300, and the first silicon-germanium layer 301 is formed on the germanium-based layer 3010. In some embodiments, the thickness of the germanium-based layer 3010 ranges from 5 nm to 100 nm, and the thickness of the first silicon-germanium layer 301 ranges from 100 nm to 500 nm. The thickness of the first silicon-germanium layer 301 should not be too thin, otherwise the effect of adjusting the warping will be poor, and should not be too thick, otherwise the effect of adjusting the warping will be overcorrected. It should be noted that the front surface described herein, i.e., the functional surface of the wafer, will subsequently form the required functional devices on the functional surface.

[0078] In another exemplary embodiment of the present disclosure, the germanium-based layer 3010 is formed on the surface of the substrate 300 by an epitaxial growth method. Specifically, the process conditions of the epitaxial growth are as follows: the temperature range is controlled to be 300-650°C, the pressure range is controlled to be 5-50 torr, and the substrate 300 is supplied with a silicon source gas and a germanium source gas. In some embodiments, the silicon source gas is silane (SiH4), and the germanium source gas is germane (GeH4). The flow rate of the silicon source gas and the germanium source gas ranges from 20 sccm to 200 sccm (standard cubic centimeters per minute).

[0079] In another exemplary embodiment of the present disclosure, the first silicon-germanium layer 301 is formed on the surface of the germanium-based layer 3010 by an epitaxial growth method. Specifically, the process conditions of the epitaxial growth are as follows: the temperature range is controlled to be 600-700°C, the pressure range is controlled to be 5-50 torr, and the substrate 300 is supplied with a silicon source gas and a germanium source gas. In some embodiments, the silicon source gas is dichlorosilane (SiH2Cl2), and the germanium source gas is germane (GeH4). In other embodiments, the silicon source gas is silane (SiH4), and the germanium source gas is germane (GeH4). The flow rate of the silicon source gas and the germanium source gas ranges from 20 sccm to 200 sccm (standard cubic centimeters per minute).

[0080] Compared with the foregoing embodiments, the thickness of the combination of the first silicon-germanium layer 301 and the germanium-based layer 3010 is much smaller than the thickness of the first silicon-germanium layer 201 in the foregoing embodiments, thereby reducing the epitaxial cost, and the overall thickness of the wafer after the subsequent epitaxial growth of the stacked structure is reduced, and the warping problem is greatly improved.

[0081] In another exemplary embodiment of the present disclosure, after epitaxial growth of the germanium-based layer 3010 and the first silicon-germanium layer 301 from the substrate 300, a high-temperature annealing is performed to compress the crystal dislocations between the first silicon-germanium layer 301 and the germanium-based layer 3010 and between the germanium-based layer 3010 and the substrate 300 at the interface and to completely release the stress in the first silicon-germanium layer 301 and the germanium-based layer 3010. In some embodiments, the high-temperature annealing is performed at a temperature ranging from 950-1050°C for a time ranging from 3-10 minutes.

[0082] In another exemplary embodiment of the present disclosure, referring to FIG. 17, the initial stack structure 302 is formed on the stress adjustment layer.

[0083] In another exemplary embodiment of the present disclosure, the method of forming the initial stack structure 302 includes using the silicon-germanium (SiGe) surface of the first silicon-germanium layer 301 as an initial base layer and growing the initial stack structure 302 of the silicon-germanium (SiGe) surface of the first silicon-germanium layer 301 in an epitaxial growth method, with the stacking direction being along a direction perpendicular to the surface of the substrate 300. In this embodiment, the second silicon-germanium layer can be formed by adding a germanium source gas during epitaxial growth of the silicon layer. The initial stack structure 302 includes a plurality of initial stack units 3020, each of which includes at least one silicon layer 3022 and one second silicon-germanium layer 3021.

[0084] In some embodiments, the number of layers of the second silicon-germanium layer 3021 and the number of layers of the silicon layer 3022 in the initial stack structure 302 are the same, and both are greater than or equal to 5. In other embodiments, the number of layers of the second silicon-germanium layer 3021 in the initial stack structure 302 is one more than the number of layers of the silicon layer 3022.

[0085] In some embodiments, the top layer of the initial stack structure 302, i.e., the layer farthest from the first silicon-germanium layer 301 in the initial stack structure 302, is the second silicon-germanium layer 3021, which can be used to protect the underlying silicon layer 3022 and the subsequently formed memory cell element from damage in subsequent manufacturing process flows after being replaced with an insulating material. In some embodiments, the top layer of the initial stack structure 302, i.e., the layer farthest from the first silicon-germanium layer 301 in the initial stack structure 302, can also be the silicon layer 3022, but the protection can also be provided by the subsequently formed mask layer covering the top layer.

[0086] In some embodiments, the material of the second silicon germanium layer 3021 in the initial stack structure 302 includes silicon doped with germanium, where the germanium content is a second composition ratio X. During the epitaxial growth to form the second silicon germanium layer 3021, the germanium content in the second silicon germanium layer 3021, i.e., the second composition ratio X, can be controlled by controlling the supply ratio of the silicon source gas and the germanium source gas, and the range of the second composition ratio X is 3.2% - 30%. In some embodiments, the germanium content in the second silicon germanium layer 3021 (the second composition ratio X) is greater than the germanium content in the first silicon germanium layer 301 (the first composition ratio Y), and the first composition ratio Y is linearly related to the second composition ratio X. It should be noted that the description of the germanium content in the second silicon germanium layer 3021 as the second composition ratio X herein is understood similarly to the description of the germanium content in the first silicon germanium layer 301 as the first composition ratio Y in the above-described embodiments, and the description is not repeated herein.

[0087] In some embodiments, only a single second silicon germanium layer 3021 and a single silicon layer 3022 are included in a single initial stack unit 3020 of the initial stack structure 302, where the thickness of the single second silicon germanium layer 3021 is A, and the thickness of the single silicon layer 3022 is B, and A or B ranges from 50 nm to 150 nm. The germanium content in the first silicon germanium layer 301 (the first composition ratio Y) is linearly related to the proportion of the thickness of the single second silicon germanium layer 3021 or the thickness of the single silicon layer 3022 to the thickness of the initial stack unit 3020. In some embodiments, the germanium content in the first silicon germanium layer 301 (the first composition ratio Y) is linearly positively related to the proportion of the thickness of the single second silicon germanium layer 3021 to the thickness of the single initial stack unit 3020. In an exemplary embodiment of the present disclosure, the first composition ratio Y and the second composition ratio X, as well as the thickness A of the single second silicon germanium layer 3021 and the thickness B of the single silicon layer 3022, satisfy the following relationship:

[0088] It should be noted that the thickness direction described herein is understood as the direction perpendicular to the surface of the substrate 300. The first silicon germanium layer 301 satisfying the above relationship can be in a partially or completely relaxed state, and in some embodiments, after the initial stack structure 302 epitaxially grown on the above-described first silicon germanium layer 301 under substantially the same process conditions, the warpage of the wafer as a whole changes by less than 10 μm, and the warpage change rate is lower than 50% as the number of epitaxial layers increases.

[0089] In another exemplary embodiment of the present disclosure, after the initial stack structure 302 is formed on the first silicon germanium layer 301, as shown in FIG. 18, a trench 304 is formed in the initial stack structure 302, and the trench 304 penetrates through the initial stack structure 302, and in some embodiments, the bottom of the trench 304 stops in the first silicon germanium layer 301.

[0090] Specifically, in some embodiments, the step of forming the trench 304 includes: first forming a first mask layer 3031 on the top layer of the initial stack structure 202, patterning the first mask layer 3031 to form an opening, the bottom of the opening exposing part of the top surface of the initial stack structure 302 as an area to be etched, etching the initial stack structure 302 along the opening, and penetrating through the entire initial stack structure 302. In some embodiments, the etching method can adopt at least one of the following etching methods: plasma dry etching, ion beam etching (IBE), reactive ion etching (RIE). In some embodiments, an etching endpoint detection (EPD) method is used to stop the etching of the trench 304 at the first silicon germanium layer 301.

[0091] In some embodiments, the material of the first mask layer 3031 can be a combination of one or more of the following: photoresist, spin-on hard mask (SOH), spin-on carbon (SOC), amorphous carbon, polysilicon, silicon nitride, silicon oxynitride, silicon carbon nitride.

[0092] In another exemplary embodiment of the present disclosure, after forming the trench 304 penetrating through the initial stack structure 302, a protective layer 305 is formed at the bottom of the trench 304.

[0093] In some embodiments, the top surface of the protective layer 305 is not lower than the top surface of the second silicon germanium layer 3021 which is the bottom layer (i.e., the single layer closest to the substrate 300) in the initial stack structure 302, and the top surface of the protective layer 305 needs to be lower than the top surface of the second silicon germanium layer 3021 which is the bottom layer upwardly closest to the bottom layer (i.e., the single layer second closest to the substrate 300) in the initial stack structure 302.

[0094] In another exemplary embodiment of the present disclosure, after forming the trench 304 and the protective layer 305, referring to FIG. 19, the end surface of the second silicon germanium layer 3021 in the initial stack structure 302 exposed by the trench 304 is subjected to lateral etching to selectively remove part of the second silicon germanium layer 3021 in the initial stack structure 302 and form voids between the adjacent silicon layers 3022 remaining, and the lateral etching direction extends from close to the trench 304 to away from the trench 304.

[0095] In some embodiments, the second silicon germanium layer 3021 is subjected to lateral etching using a silicon germanium etching solution. Specifically, the silicon germanium etching solution can include a mixed solution of hydrofluoric acid (HF), hydrogen peroxide (H2O2), and a silicon corrosion inhibitor, etc.

[0096] In some embodiments, during the side etching process, the bottom layer of the second silicon germanium layer 3021 is not exposed to the etching solution and thus is not etched because the protective layer 305 has a low etching selectivity to the second silicon germanium layer 3021 and covers the end surface of the second silicon germanium layer 3021 of the bottom layer (i.e., the single layer closest to the substrate 300) in the initial stack structure 302.

[0097] In another exemplary embodiment of the present disclosure, after removing the portion of the second silicon germanium layer 3021, the isolation material 306 is filled in the trench 304, and the isolation material 306 fills the trench 304 and the gap between the adjacent silicon layers 3022 after the aforementioned side etching.

[0098] In some embodiments, the isolation material 306 can be at least one or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride. In an exemplary embodiment of the present disclosure, the isolation material 306 is silicon oxide.

[0099] In another exemplary embodiment of the present disclosure, after the isolation material 306 fills the trench 304 and the gap between the adjacent silicon layers 3022 after the aforementioned side etching, other trenches (not shown, only different from the location of the trench 304) are formed in other locations of the initial stack structure 302, and the remaining portion of the second silicon germanium layer 3021 is removed through the other trenches. Specifically, as shown in FIG. 21, the second mask layer 3032 is formed, the material of the second mask layer 3032 can be the same as that of the first mask layer 3031, the second mask layer 3032 is patterned to form an opening, the bottom of the opening exposes a portion of the top surface of the initial stack structure 302 as an etching area to be etched, and the initial stack structure 302 is etched along the opening to form other trenches (not shown) and penetrate the entire initial stack structure 302. The protective layer 305 is also formed at the bottom of the other trenches (not shown), and the end surface of the second silicon germanium layer 3021 exposed through the other trenches (not shown) in the initial stack structure 302 is subjected to side etching, selectively removing the remaining portion of the second silicon germanium layer 3021 in the initial stack structure 302 and forming a remaining gap between the adjacent silicon layers 3022 remaining, and the side etching direction extends from the direction close to the other trenches (not shown) to the direction away from the other trenches (not shown). After removing the remaining portion of the second silicon germanium layer 3021, the isolation material 306 is filled in the other trenches (not shown), and the isolation material 306 fills the other trenches (not shown) and the remaining gap between the adjacent silicon layers 3022 after the aforementioned side etching.

[0100] In some embodiments, the trench 304 and other trenches (not shown) can be formed in the same etching step, i.e., the first mask layer 3031 and the second mask layer 3032 are the same mask layer, which is patterned to form a plurality of openings, the bottoms of the plurality of openings expose the top surface of the initial stack structure 302 to serve as the etching region of the trench 304 and other trenches (not shown), and then the trench 304 and other trenches (not shown) are etched along the plurality of openings. It can be understood that, in some embodiments, the subsequent selective removal of the second silicon germanium layer 3021 in the initial stack structure 302 through the trench 304 and other trenches (not shown) can also be formed in the same etching step, and in some embodiments, the subsequent filling of the isolation material 306 can also be formed in the same filling step. In the above-mentioned embodiments, it is not necessary to remove the first mask layer 3031 formed on the top layer of the initial stack structure 302 after the first mask layer 3031 is patterned, to form the second mask layer 3032 on the top layer of the initial stack structure 302, and then to pattern the second mask layer 3032, which reduces the number of photolithography steps, and the subsequent selective removal of the second silicon germanium layer 3021 and the filling of the isolation material 306 also saves similar process steps, thereby greatly saving the process cost, reducing the process difficulty, and reducing the damage to the surface of the top layer of the initial stack structure 302 in the process of removing the first mask layer 3031 and the second mask layer 3032, and the corrosion and consumption of the etching liquid to the silicon layer 3022 in the multi-step etching process.

[0101] In an exemplary embodiment of the present disclosure, referring to FIG. 22 or FIG. 23, after the second silicon germanium layer 2021 / 3021 in the initial stack structure 202 / 302 in the foregoing embodiments is replaced by the isolation material 206 / 306, the silicon layer 2022 / 3022 in the initial stack structure 202 / 302 is partially replaced by a storage unit element to form a stack structure 402.

[0102] In an exemplary embodiment of the present disclosure, as shown in FIG. 22, a stress adjustment layer 401 is formed on a substrate 400, and the stress adjustment layer 401 can be the same as the stress adjustment layer in any of the foregoing embodiments. The stack structure 402 is formed on the stress adjustment layer 401. The stack structure 402 includes a plurality of stack units 4020, and each stack unit 4020 includes at least one storage unit element 407 and one isolation structure 4023. The storage unit element 407 is a bit line structure and is formed at one end of a silicon layer 4022 in the stack structure 402. The isolation material 406 is located at the end of the storage unit element 407 away from the silicon layer 4022, fills the stack structure 402, and is integrated with the isolation structure 4023 between the adjacent silicon layers 4022. In some embodiments, the stress adjustment layer 401 can be any of the stress adjustment layers in the foregoing embodiments, which satisfy the corresponding same relationship in the foregoing embodiments, and the description is not repeated here.

[0103] In some embodiments, the forming method of the bit line structure of the storage unit element 407 can include, partially etching one end of the silicon layer 2022 / 3022 in the initial stack structure 202 / 302 in the foregoing embodiments such as Figure 14 or Figure 21, and then forming the bit line structure by metal deposition. In some embodiments, the extending direction of the bit line structure is parallel to the surface of the substrate 400 and perpendicular to the extending direction of the silicon layer 2022 / 3022. In some embodiments, the forming method of the semiconductor structure provided by the present disclosure further includes, forming a transistor structure at one end of the stack structure 402, the second source-drain region of the transistor structure is connected with the bit line structure; forming a word line structure, the word line structure is connected with the channel region of the transistor structure; forming a capacitor structure, the capacitor structure is connected with the first source-drain region of the transistor structure one by one.

[0104] In another exemplary embodiment of the present disclosure, as shown in Figure 23, a stress adjustment layer 501 is formed on the substrate 500, which can be the same as the stress adjustment layer in any of the foregoing embodiments, and a stack structure 502 is formed on the stress adjustment layer 501. The stack structure 502 includes a plurality of stack units 5020, each of which includes at least one storage unit element 507 and one isolation structure 5023. In some embodiments, the storage unit element 507 is a capacitor structure formed at one end of a silicon layer 5022 in the stack structure 502. The electrode material 506 is located at the end of the storage unit element 507 away from the silicon layer 5022, filled in the stack structure 502, and integrated with the upper electrode (not shown) in the capacitor structure. In other embodiments, the storage unit element 507 is a bit line contact structure formed at one end of the silicon layer 5022 in the stack structure 502. The bit line 506 is located at the end of the storage unit element 507 away from the silicon layer 5022, formed in the stack structure 502, and integrated with the bit line contact structure in the same column in the vertical direction (perpendicular to the surface direction of the substrate 500). In some embodiments, the stress adjustment layer 501 can be any of the stress adjustment layers in the foregoing embodiments, which satisfy the same relationship as in the foregoing embodiments, which are not repeated here.

[0105] In some embodiments, the method for forming the capacitor structure of the memory cell 507 can include, by the side etching of one end of the silicon layer 2022 / 3022 in the initial stack structure 202 / 302 of the aforementioned embodiments such as FIG. 14 or FIG. 21, and then forming the capacitor structure by deposition, including forming a stack of lower electrode-dielectric-upper electrode. In some embodiments, the extending direction of the capacitor structure is parallel to the surface of the substrate 500 and parallel to the extending direction of the silicon layer 2022 / 3022. In some embodiments, the method for forming the semiconductor structure provided by the present disclosure further includes, forming a transistor structure at one end of the stack structure 502, the first source / drain region of the transistor structure is connected to the capacitor structure one by one; forming a word line structure connected to the channel region of the transistor structure; forming a bit line structure connected to the second source / drain region of the transistor structure.

[0106] In other embodiments, the method for forming the bit line contact structure of the memory cell 507 can include, by exposing one end of the silicon layer 2022 / 3022 in the initial stack structure 202 / 302 of the aforementioned embodiments such as FIG. 14 or FIG. 21, and then forming the bit line contact structure by metallization, and then forming the bit line structure 506 connected to the bit line contact structure in the same column in the vertical direction (perpendicular to the surface direction of the substrate 500). In some embodiments, the method for forming the semiconductor structure provided by the present disclosure further includes, forming a transistor structure at one end of the stack structure 502, the second source / drain region of the transistor structure is connected to the bit line structure through the bit line contact structure; forming a word line structure connected to the channel region of the transistor structure; forming a capacitor structure connected to the first source / drain region of the transistor structure one by one.

[0107] In some embodiments, the side etching of the silicon layer 2022 / 3022 is performed by wet chemical etching using a silicon etching solution to remove part of the silicon layer 2022 / 3022 which is monocrystalline silicon. Specifically, the silicon etching solution uses ammonium hydroxide deionized water mixture (ADM) or tetramethylammonium hydroxide (TMAH) as the etching solution for selective etching of the silicon layer 2022 / 3022.

[0108] In some embodiments, the deposition method of the capacitor structure or the bit line structure can use at least one of the following deposition methods: chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultrahigh vacuum chemical vapor deposition (UHVCVD), flowable chemical vapor deposition (FCVD), direct liquid injection chemical vapor deposition (DLICVD), rapid thermal chemical vapor deposition (RTCVD), microwave plasma assisted chemical vapor deposition (MPCVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and electroplating sputtering.

[0109] The preparation method of the semiconductor structure provided by the present disclosure includes: forming a stress adjustment layer by epitaxy before forming an initial stack structure on a substrate by epitaxy, wherein a first silicon germanium layer in the stress adjustment layer has a germanium content linearly related to a proportion of a single layer in a stack unit in a subsequent initial stack structure, so that the warping problem of the wafer as a whole is greatly improved with the increase of the number of layers grown by epitaxy, the device reliability is improved, and the defects and disadvantages caused by forming a compensation layer on the back of the wafer in the related art are avoided, the process feasibility is improved, the process cost is saved, the process difficulty is reduced, and thus the process reliability is greatly improved.

[0110] Based on the above preparation method of the semiconductor structure, the present disclosure further provides a semiconductor structure, as shown in FIG. 24 or FIG. 25, which at least includes: a substrate 600 / 700; a stack structure 602 / 702 located on the substrate 600 / 700, the stack structure 602 / 702 including a plurality of stack units 6020 / 7020 stacked in a direction perpendicular to the surface of the substrate 600 / 700, each stack unit 6020 / 7020 including at least one storage unit element and one isolation structure 6023 / 7023; and a stress adjustment layer 601 / 701 located between the stack structure 602 / 702 and the substrate 600 / 700. In some embodiments, the storage unit element can be a bit line structure 608 and / or a bit line contact structure 610 / 710. In other embodiments, the storage unit element can be a capacitor structure 607 / 707.

[0111] In some embodiments, the first silicon germanium layer in the stress adjustment layer 601 / 701 includes a first silicon germanium layer with a germanium content of a first composition ratio Y. In some embodiments, the first composition ratio Y is in a range of 3% to 20%. In some embodiments, the bottom layer of the stack structure 602 / 702 includes a second silicon germanium layer 6021 / 7021 with a germanium content of a second composition ratio X. In some embodiments, the second composition ratio X is in a range of 3.2% to 30%. In some embodiments, the germanium content (the second composition ratio X) in the second silicon germanium layer 6021 / 7021 is greater than the germanium content (the first composition ratio Y) in the first silicon germanium layer, and the first composition ratio Y is linearly related to the second composition ratio X. In some embodiments, only a single memory cell element and a single isolation structure 6023 / 7023 are included in one stack unit 6020 / 7020 of the stack structure 602 / 702, where the thickness of the single isolation structure 6023 / 7023 is A, and the thickness of the single memory cell element is B, and A or B is in a range of 50 to 150 nm. The germanium content (the first composition ratio Y) in the first silicon germanium layer is linearly related to the proportion of the thickness of the single isolation structure 6023 / 7023 or the thickness of the single memory cell element to the thickness of the stack unit 6020 / 7020. In some embodiments, the germanium content (the first composition ratio Y) in the first silicon germanium layer is linearly and positively related to the proportion of the thickness of the single isolation structure 6023 / 7023 to the thickness of the single stack unit 6020 / 7020. In an exemplary embodiment of the present disclosure, the first composition ratio Y, the second composition ratio X, the thickness A of the single isolation structure 6023 / 7023, and the thickness B of the single memory cell element satisfy the following relationship:

[0112] It should be noted that the germanium content described herein should be understood as the ratio of the number of germanium atoms in the silicon germanium layer to the total number of atoms (mainly silicon atoms and germanium atoms) in the silicon germanium layer, and the thickness direction described herein should be understood as the direction perpendicular to the surface of the substrate 600 / 700. The first silicon germanium layer in the stress adjustment layer satisfying the above relationship can be in a partially or completely relaxed state. In some embodiments, after an initial stack structure is epitaxially grown on the first silicon germanium layer under substantially the same process conditions, the overall warpage of the wafer changes by less than 10 μm, and the warpage change rate is lower than 50% as the number of epitaxial layers increases.

[0113] In some embodiments, the semiconductor structure provided by the present disclosure further includes a protective layer 605 / 705, the top surface of the protective layer 605 / 705 is not lower than the top surface of the second silicon germanium layer 6021 / 7021 in the bottom layer (i.e., the single layer closest to the substrate 600 / 700) of the stack structure 602 / 702, and the top surface of the protective layer 605 / 705 is lower than the top surface of the silicon layer 6022 / 7022 in the bottom layer of the stack structure 602 / 702.

[0114] In some embodiments, the semiconductor structure provided by the present disclosure further comprises a plurality of capacitor structures 607 / 707, the capacitor structures 607 / 707 extend in a direction parallel to the surface of the substrate 600 / 700 and parallel to the silicon layer 6022 / 7022, the capacitor structures 607 / 707 comprise a stack of lower electrode-dielectric-upper electrode, and the upper electrodes of the plurality of capacitor structures 607 / 707 are connected to the electrode material layer 606 / 706.

[0115] In some embodiments, the semiconductor structure provided by the present disclosure further comprises a plurality of transistor structures 6024 / 7024. In some embodiments, the plurality of transistor structures 6024 / 7024 are arranged in an array in a cross-sectional direction perpendicular to the silicon layer 6021 / 7021, i.e. not only in a direction perpendicular to the substrate 600 / 700, but also in the same horizontal layer, the plurality of transistor structures 6024 / 7024 are regularly spaced. In some embodiments, the transistor structures 6024 / 7024 can be formed from the silicon layer in the initial stack structure in the foregoing embodiments. In some embodiments, the capacitor structures 607 / 707 are connected to the first source / drain regions (not shown) of the transistor structures 6024 / 7024 one-to-one for storing or releasing induced charges. In some embodiments, the capacitor structures 607 / 707 are connected to the first source / drain regions through the capacitor contact structures 604 / 704.

[0116] In an exemplary embodiment of the present disclosure, as shown in FIG. 24, the semiconductor structure provided by the present disclosure further comprises a bit line structure 608 and a word line structure 609; the bit line structure 608 extends in a direction parallel to the surface of the substrate 600 and perpendicular to the silicon layer 6021, the bit line structure 608 is connected to the second source / drain regions (not shown) of the transistor structures 6024 for providing or sensing the storage charges in the plurality of capacitor structures 607 in the same row; the word line structure 609 extends in a direction perpendicular to the surface of the substrate 600, the word line structure 609 is connected to the channel regions (not shown) of the transistor structures 6024 for controlling the opening or closing of the storage transistors in the same column. In some embodiments, the second source / drain regions are connected to the bit line structure 608 through the bit line contact structures 610. In some embodiments, the storage unit element in the semiconductor structure provided by the present disclosure can be the bit line structure 608, the bit line contact structure 610 or the capacitor structure 607.

[0117] In an example embodiment of the present disclosure, as shown in FIG. 25, the semiconductor structure provided by the present disclosure further comprises a bit line structure 708 and a word line structure 709; the bit line structure 708 extends in the same direction as the surface of the substrate 700, and is connected to the second source / drain region (not shown) of the transistor structure 7024 for providing or sensing the storage charge in the plurality of capacitor structures 707 of the column; the word line structure 709 extends in parallel to the surface of the substrate 700 and perpendicular to the extension direction of the silicon layer 7021, and is connected to the channel region (not shown) of the transistor structure 7024 for controlling the turn-on or turn-off of the plurality of transistor structures 7024 in the row. In some embodiments, the bit line structure 708 is connected to the second source / drain region through a bit line contact structure 710. In some embodiments, the storage unit in the semiconductor structure provided by the present disclosure can be the bit line contact structure 710 or the capacitor structure 707.

[0118] In some embodiments, the material of the transistor structure 6024 / 7024 can be at least one or any combination of the following materials: silicon, germanium, silicon germanium (SiGe), III-V group material, indium gallium zinc oxide (IGZO), two-dimensional material. In an example embodiment of the present disclosure, the material of the transistor structure 6024 / 7024 is doped monocrystalline silicon.

[0119] In some embodiments, the material of the bit line contact structure 610 / 710 and the capacitor contact structure 604 / 704 can be any one or more of the following metal silicide materials: cobalt silicide (CoSi), nickel silicide (NiSi), tungsten silicide (WSi), molybdenum silicide (MoSi), titanium silicide (Ti), tantalum silicide (TaSi), ruthenium silicide (RuSi), platinum silicide (PtSi).

[0120] In some embodiments, the material of the bit line structure 608 / 708 and the word line structure 609 / 709 can be any one or more of the following metal or metal nitride materials: tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), molybdenum nitride (MoN), ruthenium (Ru), ruthenium nitride (RuN).

[0121] In some embodiments, the material of the lower electrode and the upper electrode of the capacitor structure 607 / 707 can be at least one or more of the following: titanium nitride, tantalum nitride, or tungsten nitride, and the material of the dielectric can be at least one or more of the following: silicon oxide (SiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), barium strontium titanate (BST), strontium titanate (STO), lead titanate (PZT).

[0122] In some embodiments, the isolation structure 6023 / 7023 can be at least one of or any combination of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride. In an exemplary embodiment of the present disclosure, the isolation structure 6023 / 7023 employs silicon oxide.

[0123] The semiconductor structure provided by the present disclosure includes a stress adjustment layer formed between a substrate and a stack structure, so that the warping problem of the wafer as a whole is greatly improved, and the related device made of the semiconductor structure has good device reliability and storage performance.

[0124] It should be noted that the semiconductor structure in the embodiments of the present disclosure can be used to manufacture 3D DRAM devices, and can also be used to manufacture other 3D devices that require lateral etching of the sacrificial layer in the stack structure, which is not limited here.

[0125] The various semiconductor structures shown in the specific embodiments can be used in electronic devices with storage functions. The electronic device can be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (PC), a server, a workstation, etc. The storage function in the electronic device can be realized by a memory such as a dynamic random access memory (DRAM), a ferroelectric random access memory (FRAM), a phase change memory (PCM), a magnetic random access memory (MRAM), or a resistive random access memory (RRAM).

[0126] The above merely provides a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present disclosure, which should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, comprising: Substrates (200, 300, 400, 500, 600, 700); A stacked structure (402, 502, 602, 702) is located on the substrate, the stacked structure comprising a plurality of stacked units (4020, 5020, 6020, 7020) stacked in a direction perpendicular to the surface of the substrate, each of the stacked units comprising at least a stack of a storage unit (407, 507) and an isolation structure (4023, 5023, 6023, 7023); A stress adjustment layer (401, 501, 601, 701) is located between the stacked structure and the substrate, and the stress adjustment layer includes a first silicon-germanium layer (201, 301). The material of the first silicon-germanium layer includes germanium-doped silicon, wherein the germanium content is a first component ratio, the first component ratio being linearly related to the ratio of the thickness of the memory cell or the thickness of the isolation structure to the thickness of the stacked cell, and the direction of the thickness being along a direction perpendicular to the surface of the substrate.

2. The semiconductor structure according to claim 1, wherein, The first component ratio ranges from 3% to 20%.

3. The semiconductor structure according to claim 1, wherein, The thickness of the first silicon-germanium layer is greater than or equal to 3 micrometers.

4. The semiconductor structure according to claim 1, wherein, The stress adjustment layer further includes a germanium substrate (3010) located between the substrate and the first silicon-germanium layer.

5. The semiconductor structure according to claim 4, wherein, The germanium substrate material comprises silicon-doped germanium, wherein the germanium content ranges from 50% to 100%.

6. The semiconductor structure according to claim 5, wherein, The thickness of the germanium base layer ranges from 5 to 100 nanometers, and the thickness of the first silicon-germanium layer ranges from 100 to 500 nanometers.

7. The semiconductor structure according to claim 1, wherein, The stacked structure further includes a second silicon-germanium layer (4021, 5021, 6021, 7021), which is located in the stacked unit closest to the substrate in the stacked structure.

8. The semiconductor structure according to claim 7, wherein, The material of the second silicon-germanium layer (4021, 5021, 6021, 7021) includes germanium-doped silicon, wherein the germanium content is a second component ratio, the second component ratio is greater than the first component ratio, and the first component ratio is linearly related to the second component ratio.

9. The semiconductor structure according to claim 8, wherein, The range of the second component ratio is 3.2%-30%.

10. The semiconductor structure according to any one of claims 1 to 9, wherein, The storage cell is a capacitor structure (607, 707), and the semiconductor structure further includes: Transistor structures (6024, 7024) are located at one end of the stacked structure, and the first source and drain regions of the transistor structure are connected to the capacitor structure in a one-to-one correspondence. Word line structures (609, 709) are connected to the channel region of the transistor structure; Bit line structures (608, 708) are connected to the second source / drain regions of the transistor structure; Alternatively, the memory cell may be a bit line structure (608, 708), and the semiconductor structure may further include: A transistor structure (6024, 7024) is located at one end of the stacked structure, and the second source / drain region of the transistor structure is connected to the bit line structure; Word line structures (609, 709) are connected to the channel region of the transistor structure; The capacitor structure (607, 707) is connected one-to-one with the first source and drain regions of the transistor structure.

11. A method for fabricating a semiconductor structure, comprising: Substrates are available in (200, 300, 400, 500, 600, 700); A stress adjustment layer (401, 501, 601, 701) is formed on the substrate, the stress adjustment layer including a first silicon-germanium layer (201, 301); An initial stack structure (202, 302) is formed on the stress adjustment layer. The initial stack structure includes a plurality of initial stack units (2020, 3020) stacked in a direction perpendicular to the surface of the substrate. Each initial stack unit includes at least a stack of a silicon layer (2022, 3022) and a second silicon-germanium layer (2021, 3021). The second silicon-germanium layer in the initial stacked structure is replaced with an isolation structure (2023, 3023, 4023, 5023), and a portion of the silicon layer is replaced with memory cells (407, 507) to form a stacked structure (402, 502, 602, 702). The stacked structure includes a plurality of stacked cells (4020, 5020, 6020, 7020) stacked in a direction perpendicular to the surface of the substrate. Each stacked cell includes at least one memory cell and one isolation structure stack. The material of the first silicon-germanium layer includes germanium-doped silicon, wherein the germanium content is a first component ratio, and the first component ratio is linearly related to the ratio of the thickness of the memory cell or the thickness of the isolation structure to the thickness of the stacked cell, wherein the direction of the thickness is along a direction perpendicular to the surface of the substrate.

12. The method for fabricating a semiconductor structure according to claim 11, wherein, A stress adjustment layer (401, 501, 601, 701) is formed on the substrate, the stress adjustment layer including a first silicon-germanium layer (201, 301), comprising: The first silicon-germanium layer is grown on the surface of the substrate by epitaxial growth. The thickness of the first silicon-germanium layer is greater than 3 micrometers, and the first component ratio ranges from 3% to 20%.

13. The method for fabricating a semiconductor structure according to claim 11, wherein, A stress adjustment layer (401, 501, 601, 701) is formed on the substrate. The stress adjustment layer includes a first silicon-germanium layer (201, 301) and a germanium base layer (3010), comprising: The germanium substrate is grown on the surface of the substrate by epitaxial growth, and then the first silicon-germanium layer is grown on the surface of the germanium substrate by epitaxial growth. The germanium base layer is made of silicon-doped germanium, with a germanium content ranging from 50% to 100%, a thickness ranging from 5 to 100 nanometers, and a thickness ranging from 100 to 500 nanometers for the first silicon-germanium layer.

14. The method for fabricating a semiconductor structure according to claim 11, wherein, An initial stacked structure (202, 302) is formed on the stress adjustment layer, comprising: By means of epitaxial growth, a plurality of silicon layers and a plurality of second silicon-germanium layers are alternately grown on the surface of the first silicon-germanium layer to form a plurality of initial stacked units stacked in a direction perpendicular to the surface of the substrate, each initial stacked unit comprising at least one stack of the silicon layer and one stack of the second silicon-germanium layer; The material of the second silicon-germanium layer includes silicon doped with germanium, wherein the germanium content is a second component ratio, the second component ratio is greater than the first component ratio, and the first component ratio is linearly related to the second component ratio, and the range of the second component ratio is 3.2%-30%.

15. The method for fabricating a semiconductor structure according to any one of claims 11 to 14, wherein, The storage cell is a capacitor structure (607, 707), and the method for fabricating the semiconductor structure further includes: A transistor structure (6024, 7024) is formed, located at one end of the initial stacked structure or the stacked structure, and the first source and drain regions of the transistor structure are connected to the capacitor structure in a one-to-one correspondence. A word line structure (609, 709) is formed, wherein the word line structure is connected to the channel region of the transistor structure; A bit line structure (608, 708) is formed, wherein the bit line structure is connected to the second source-drain region of the transistor structure; Alternatively, the memory cell may be a bit line structure (608, 708), and the method for fabricating the semiconductor structure may further include: A transistor structure (6024, 7024) is formed at one end of the stacked structure, and the second source / drain region of the transistor structure is connected to the bit line structure; A word line structure (609, 709) is formed, wherein the word line structure is connected to the channel region of the transistor structure; A capacitor structure (607, 707) is formed, and the capacitor structure is connected one-to-one with the first source and drain regions of the transistor structure.

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