Chip packaging structure and manufacturing method therefor, and electronic device

Abstract

Embodiments of the present application relate to the technical field of chip packaging, and provide a chip packaging structure and a manufacturing method therefor, and an electronic device, aiming to improve the internal communication efficiency of the chip packaging structure. The chip packaging structure comprises a first chip, a second chip, a first filling layer wrapped around the periphery of the first chip, a first metallized via passing through the first filling layer, a first redistribution layer, and a second redistribution layer. The first redistribution layer is stacked on one side of the first chip and the first filling layer, and is connected to the first chip and the first metallized via, so that the first chip can be electrically connected to the first metallized via. The second redistribution layer is stacked on one side of the first chip and the first filling layer, and is connected to the first redistribution layer. The second chip is located on the side of the second redistribution layer away from the first chip, and is connected to the second redistribution layer and the first metallized via. By using the first metallized via, the first redistribution layer and the second redistribution layer, the number of electrical channels can be increased, improving the communication efficiency.

Description

A chip packaging structure and its fabrication method, and an electronic device.

[0001] This application claims priority to Chinese Patent Application No. 202410878642.5, filed on June 28, 2024, entitled "A Chip Packaging Structure and Its Manufacturing Method, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of chip packaging technology, and in particular to a chip packaging structure and its manufacturing method, as well as electronic devices. Background Technology

[0003] The development and application of semiconductor integrated circuit technology have brought about tremendous changes in many fields. The rapid development of these fields, in turn, has placed higher demands on the design and manufacturing processes of semiconductor integrated circuits, requiring semiconductor chips to integrate more transistors in the smallest possible area to achieve the highest possible performance while ensuring functional reliability. Special designs for chip packaging structures, such as the introduction of 3D or 2.5D packaging methods, can increase chip packaging density, enabling the chip packaging structure to provide higher performance within the same size. However, in some application scenarios, although chip packaging density is improved, crosstalk may occur in signal transmission within the chip packaging structure. This not only reduces the reliability of chip functionality but may also lead to a significant increase in signal delay due to communication path congestion, resulting in low internal communication efficiency within the chip packaging structure.

[0004] Therefore, how to balance the packaging density of chip packaging structure and internal communication efficiency is a key issue that continues to be studied by those skilled in the art. Summary of the Invention

[0005] This application provides a chip packaging structure and its manufacturing method, as well as an electronic device, with the main purpose of balancing the packaging density and internal communication efficiency of the chip packaging structure.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] In a first aspect, a chip packaging structure is provided, comprising a first chip, a second chip, a first fill layer, a first metallized via, a first redistribution layer, and a second redistribution layer. The first fill layer surrounds the first chip. The first metallized via penetrates the first fill layer along its thickness direction to achieve electrical conduction in the thickness direction of the first fill layer. Furthermore, the first redistribution layer is stacked on one side of the first chip and the first fill layer and is connected to the first chip and the first metallized via, thereby enabling electrical connection between the first chip and the first metallized via, thus increasing the electrical channels for connection to the first chip. Additionally, the second redistribution layer is stacked on one side of the first chip and the first fill layer and is connected to the first redistribution layer. The second chip is located on the side of the second redistribution layer away from the first chip and is connected to the second redistribution layer and the first metallized via, thereby increasing the electrical channels for connection to the second chip.

[0008] The chip packaging structure provided by the first aspect of the above-described embodiment increases lateral electrical channels through the first and second redistribution layers, and utilizes the first metallized via in the first filling layer to increase the electrical channels of the first chip and the second chip in the stacking direction, i.e., the vertical electrical channels. This increases the communication paths between the first and second chips, and between the first or second chip and other electronic components, thereby improving the vertical and lateral communication capabilities within the chip packaging structure. On one hand, the stacking of the first and second chips increases the packaging density of the chip packaging structure. On the other hand, the expansion of electrical channels helps to rationally allocate communication paths, making the communication paths of some signals shorter, reducing signal delay in the chip packaging structure, and improving the internal communication efficiency of the chip packaging structure. Furthermore, expanding electrical channels and rationally allocating communication paths can also reduce signal crosstalk and ensure the reliability of the chip packaging structure while having higher interconnect density and interconnect bandwidth.

[0009] In conjunction with the first aspect, in one possible implementation, the chip package structure further includes a third chip and a fourth chip. A first filling layer surrounds the third chip, and the fourth chip is disposed on the same layer as the second chip. This expands the lateral topology of the chip package structure, improving its packaging density and overall performance. A first redistribution layer extends to one side of the third chip and is connected to it. A second redistribution layer extends to one side of the fourth chip, and the fourth chip is connected to the second redistribution layer and the first metallized via. Therefore, not only is the interconnection performance between the third and fourth chips improved, but the lateral communication capability of the entire chip package structure is also enhanced.

[0010] In conjunction with the first aspect, in one possible implementation, the first and second chips are of the type of input / output (I / O) chips, thereby implementing signal input / output processing. Alternatively, the first and second chips are of the type of computing chips, thereby implementing signal computation processing.

[0011] In conjunction with the first aspect, in one possible implementation, the third and fourth chips may be high-speed interconnect chips, thereby cooperating with the first and second chips to achieve input / output processing of signals on the same layer within the chip package structure. Alternatively, the third and fourth chips may be computing chips, thereby cooperating with the first and second chips to achieve computational processing of signals on the same layer within the chip package structure.

[0012] In conjunction with the first aspect, in one possible implementation, the first chip includes a chip redistribution layer, a transistor layer, and a power supply network layer. The chip redistribution layer is located on the side of the transistor layer facing the first redistribution layer and is connected to the transistor layer. This allows the chip redistribution layer to be connected to the first redistribution layer through redistribution, thereby achieving the connection between the first redistribution layer and the first chip. The power supply network layer is located on the side of the transistor layer away from the first redistribution layer and is connected to the transistor layer. This allows the power supply network layer to serve as the back power supply network for the transistor layer, achieving back power supply for the chip.

[0013] In conjunction with the first aspect, in one possible implementation, the first chip further includes a substrate and a second metallized via. The substrate is located between the transistor layer and the power supply network layer, and the second metallized via penetrates the substrate along its thickness direction to achieve electrical conduction of the substrate in the thickness direction. The transistor layer includes a field-effect transistor (MOFET), and the power supply network layer is connected to the MOFET through the second metallized via. By turning the MOFET on or off, the back power supply of the transistor layer can be controlled, and signal transmission can also be controlled accordingly.

[0014] In conjunction with the first aspect, in one possible implementation, the second redistribution layer is located on the side of the first chip and the first fill layer away from the first redistribution layer, and is connected to the first redistribution layer through a first metallized via. The chip package structure also includes an adapter layer and a packaged redistribution layer. The adapter layer is located on the side of the first redistribution layer away from the second redistribution layer and is connected to the first redistribution layer. The packaged redistribution layer is located on the side of the adapter layer away from the first redistribution layer and is connected to the adapter layer. In this implementation, the adapter layer is located on one side of the stacked first and second chips. The adapter layer facilitates signal transfer between the first and second chips via the first redistribution layer, enabling unified signal processing. The packaged redistribution layer not only enables signal transmission but also encapsulates one side of the chip package structure.

[0015] In conjunction with the first aspect, in one possible implementation, the second redistribution layer is located on the side of the first redistribution layer away from the first chip and the first fill layer. The chip package structure further includes: an adapter layer and a packaged redistribution layer. The adapter layer is located between the first and second redistribution layers, and the first redistribution layer is connected to the second redistribution layer via the adapter layer. The packaged redistribution layer is located on the side of the second chip and the first fill layer away from the second redistribution layer, and is connected to the second chip. The packaged redistribution layer is connected to the second redistribution layer via a first metallized via. In this implementation, the adapter layer is located between the stacked first and second chips, and the adapter layer relays signals in the first and second redistribution layers respectively, which helps to reduce voltage drop across the circuits in the chip package structure.

[0016] In conjunction with the first aspect, in one possible implementation, the chip package structure further includes a second fill layer, a third metallized via, a third redistribution layer, and a fifth chip. The second fill layer surrounds the second chip. The third metallized via penetrates the second fill layer along its thickness direction. The third redistribution layer is located on the side of the second chip and the second fill layer away from the second redistribution layer, and is connected to the second chip. The fifth chip is located on the side of the third redistribution layer away from the second chip, and is connected to the third redistribution layer and the third metallized via. In this implementation, the fifth chip, stacked with the first and second chips, increases the number of chip layers in the chip package structure, which helps to improve the chip's packaging density and performance.

[0017] In conjunction with the first aspect, in one possible implementation, the first chip is connected to the first redistribution layer by bonding, or the second chip is connected to the second redistribution layer by bonding, or the first chip is connected to the second redistribution layer by redistribution. In this way, the first chip is connected to the first redistribution layer and the second redistribution layer located on opposite sides of the first chip by bonding and redistribution, which helps to improve the efficiency of chip packaging.

[0018] Secondly, a method for fabricating a chip package structure is provided, the method comprising: fabricating a first redistribution layer; fabricating a first chip, a first fill layer, and a first metallized via stacked on the first redistribution layer; the first metallized via penetrating the first fill layer along its thickness direction; and the first redistribution layer being connected to the first chip and the first metallized via; wherein the first fill layer surrounds the first chip; fabricating a second redistribution layer stacked on the first chip and the first fill layer, and the second redistribution layer being connected to the first redistribution layer; and fabricating a second chip on the side of the second redistribution layer away from the first chip, and the second chip being connected to the second redistribution layer and the first metallized via.

[0019] Thirdly, an electronic device is provided, comprising: a circuit board and a chip package structure. The chip package structure is the chip package structure of any of the above embodiments or is manufactured using the manufacturing method of the chip package structure as described in the above embodiments. The chip package structure is connected to the circuit board.

[0020] The technical effects of any of the design methods in the second or third aspect can be found in the technical effects of the different design methods in the first aspect, and will not be repeated here. Attached Figure Description

[0021] Figure 1 is a schematic diagram of a chip packaging structure in the related technology;

[0022] Figure 2 is a perspective view of an electronic device provided in an embodiment of this application;

[0023] Figure 3 is an exploded view of an electronic device provided in an embodiment of this application;

[0024] Figure 4 is a schematic diagram of a chip packaging structure and a motherboard in an electronic device provided in an embodiment of this application;

[0025] Figure 5 is a schematic diagram of a chip packaging structure provided in an embodiment of this application;

[0026] Figure 6 is a schematic diagram of the transverse topology of a chip packaging structure provided in an embodiment of this application;

[0027] Figure 7 is a schematic diagram of the transverse topology of another chip packaging structure provided in the embodiment of this application;

[0028] Figure 8 is a schematic diagram of the lateral topology of another chip packaging structure provided in an embodiment of this application;

[0029] Figure 9 is a schematic diagram of another chip packaging structure provided in an embodiment of this application;

[0030] Figure 10 is a schematic diagram of another chip packaging structure provided in an embodiment of this application;

[0031] Figure 11 is a schematic diagram of another chip packaging structure provided in an embodiment of this application;

[0032] Figure 12 is a schematic diagram of another chip packaging structure provided in an embodiment of this application;

[0033] Figure 13 is a schematic diagram of another chip packaging structure provided in an embodiment of this application;

[0034] Figure 14 is a schematic diagram of another chip packaging structure provided in an embodiment of this application;

[0035] Figure 15 is a schematic diagram of another chip packaging structure provided in an embodiment of this application;

[0036] Figure 16 is a schematic diagram of another chip packaging structure provided in an embodiment of this application;

[0037] Figure 17 is a schematic diagram of another chip packaging structure provided in an embodiment of this application;

[0038] Figure 18 is a schematic diagram of another chip packaging structure provided in an embodiment of this application;

[0039] Figure 19 is a flowchart of the steps of a chip packaging structure fabrication method provided in an embodiment of this application;

[0040] Figure 20 is a process diagram of the fabrication of a chip packaging structure provided in an embodiment of this application;

[0041] Figure 21 is a process diagram of another chip packaging structure provided in an embodiment of this application;

[0042] Figure 22 is a process diagram of the fabrication of another chip packaging structure provided in the embodiment of this application;

[0043] Figures 23A-23L are process diagrams illustrating the fabrication of another chip packaging structure provided in the embodiments of this application. Detailed Implementation

[0044] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0045] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more. "At least one" or similar expressions refer to any combination of these items, including any combination of a single item or a plurality of items. For example, at least one of a, b, and c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple. "a and / or b" includes the following three combinations: only a, only b, and a combination of a and b.

[0046] Furthermore, to facilitate a clear description of the technical solutions in the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that "first" and "second" are not necessarily different. Meanwhile, in the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is being used as an example, illustration, or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of terms such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding.

[0047] In describing some embodiments, the term "connection" and its derivative expressions are used. The term "connection" should be interpreted broadly; for example, "connection" can be an electrical connection based on a conductor. Of course, the understanding of "connection" also includes, but is not limited to, a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0048] As used in this article, "same layer" refers to the positional relationship between multiple film layers in the same layer in a multilayer structure that is stacked on top of each other. The film formation processes of "same layer" film layers can be different or the same, the patterns of each film layer can be continuous or discontinuous, and these patterns may also have different thicknesses.

[0049] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0050] In this application embodiment, the terms "upper," "lower," "left," and "right" are not limited to the orientation of the components schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts used for description and clarification, and can vary accordingly depending on the orientation of the components in the accompanying drawings. In the drawings, for clarity, the thickness of layers and regions is exaggerated, and the dimensional proportions between the parts in the illustrations do not reflect actual dimensional proportions. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, exemplary embodiments should not be construed as being limited to the shapes of the areas shown in this application, but rather include shape deviations due to, for example, manufacturing. For example, an etched area shown as rectangular would typically have a curved feature. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0051] Furthermore, the architecture and scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of architecture and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0052] As chip manufacturing processes approach their physical size limits, 3D packaging technology has become a crucial technology for improving chip integration and performance. In 3D packaging, conventional microbump vertical interconnects pose significant challenges to manufacturing processes when the pitch is reduced to below 10μm. Therefore, for chip packaging applications with pitches of 10μm and below, hybrid bonding (HB) is a more suitable vertical interconnect solution because it avoids the use of bumps and employs smaller copper / copper interconnect structures to achieve direct electrical connections between chips, resulting in higher interconnect density. For this reason, hybrid bonding is considered a key technology for achieving high-density 3D stacked packaging and integrated architecture design.

[0053] The development of hybrid bonding technology helps improve the performance of chip packaging structures in various aspects. The development trends of hybrid bonding technology can be broadly categorized into the following directions: First, improvements based on underlying principles, such as pad patterns and shapes. Second, integration with 3D structure applications, such as face-to-face (F2F) stacking, face-to-back (F2B) stacking, and through-deposition via (TDV) connections. Third, integration with other architecture applications, such as 2.5D packaging, fan-out (FO) packaging, 2D packaging, and wire bonding (WB). Fourth, integration with electronic components, such as capacitors, inductors, sensors, and optical ports. Fifth, improvements in equipment and process flows.

[0054] However, in some chip packaging structures proposed by related technologies, the power supply and signal lines are densely packed. This can lead to a significant increase in signal delay due to communication path congestion. Furthermore, the communication paths occupy a large area of ​​the chip, which also increases the chip's manufacturing cost. Therefore, it is difficult for those skilled in the art to balance the packaging density and internal communication efficiency of a chip packaging structure.

[0055] In view of this, embodiments of this application provide a chip packaging structure and an electronic device including the chip packaging structure. In some application scenarios, the chip packaging structure can be a chip obtained by packaging a bare chip, or a semiconductor structure obtained by packaging multiple chips, such as a multi-chip module (MCM) or a system-in-a-package (SIP) structure. This chip packaging structure expands the internal vertical and horizontal communication paths, reduces internal signal delay, reduces signal crosstalk, and balances packaging density and internal communication efficiency.

[0056] This application provides an electronic device, which includes a circuit board and a chip package structure. The chip package structure is the chip package structure described in any of the above embodiments or is manufactured using the manufacturing method described in the above embodiments. The chip package structure is connected to the circuit board.

[0057] The aforementioned electronic devices include, but are not limited to, electronic devices in the fields of information technology (IT) and communications technology (CT), such as supercomputing devices, artificial intelligence devices, servers, optical communication devices, mobile phones, tablet personal computers, laptop computers, personal digital assistants (PDAs), cameras, personal computers, laptops, in-vehicle devices, wearable devices, augmented reality (AR) glasses, AR headsets, virtual reality (VR) glasses, or VR headsets, and other devices that require data processing / storage / transmission / reception. This application does not impose any special limitations on the specific form of the aforementioned electronic devices. For ease of explanation, the following description uses the mobile phone shown in Figure 2 as an example.

[0058] Figure 1 is a perspective view of an electronic device provided in some embodiments of this application, and Figure 2 is an exploded view of the electronic device shown in Figure 1. Referring to Figure 1, the electronic device 1000 can be a mobile phone. Taking this as an example, the electronic device 1000 may include a chip package structure 100, a screen 200, a mid-frame 300, a back cover 400, and a motherboard 500 fixed on the mid-frame 300, as shown in Figure 2.

[0059] It is understood that Figures 1 and 2 only exemplarily illustrate some components included in the electronic device 1000, and the actual shape, size, location, and construction of these components are not limited to Figures 1 and 2. For example, in some other examples, the electronic device 1000 may not include the screen 200 shown in Figure 2, or the electronic device 1000 may also include the camera 600 shown in Figure 2.

[0060] In this embodiment, the chip package structure can also be referred to as an integrated circuit. As shown in FIG3, the chip package structure 100 is disposed on the motherboard 500 and electrically connected to the motherboard 500. For example, the chip package structure 100 can be electrically connected to the motherboard 500 through a ball grid array (BGA) or multiple arrays of copper pillar bumps (CPB) on the chip package structure 100, thereby enabling the chip package structure 100 to transmit signals with other devices or device stacks on the motherboard 500.

[0061] The aforementioned motherboard 500 can be a printed circuit board (PCB). The number of chip package structures 100 on the motherboard 500 can be one, two, or more, and this application does not impose any restrictions.

[0062] For ease of description below, a three-dimensional spatial coordinate system, namely the X, Y, and Z coordinate system, is shown in some of the accompanying drawings of the embodiments of this application. Referring to Figure 3, the plane containing the motherboard 500 is the XY plane. Taking the motherboard 500 shown in Figure 3 as a rectangle as an example, the X-axis can be the length direction of the motherboard 500, the Y-axis can be the width direction of the motherboard 500, and the Z-axis is a direction perpendicular to or approximately perpendicular to the motherboard 500 within the manufacturing tolerance range. It is understood that the width of the motherboard 500 is smaller than its length.

[0063] It should be noted that Figures 1 to 3 are merely examples of application scenarios for the chip packaging structure provided in the embodiments of this application, specifically illustrating how the chip packaging structure is integrated into an electronic device. In fact, the chip packaging structure provided in the embodiments of this application can also be used independently of the electronic device; specific implementation methods will be described in detail below.

[0064] Referring to Figure 4, in some chip packaging structures 100 provided in this application embodiment, different chips 1 mainly communicate through the traces inside the adapter board 2 and the through silicon vias (TSVs) 3 inside the chips. The arrows in Figure 4 schematically show the communication path. Different chips 1 are interconnected through the communication path formed by the TSVs 3 and the adapter board 2. Although multi-layer chip packaging and interconnection are achieved, the power supply lines and signal lines need to be transmitted through the TSVs inside the chips in the direction of chip stacking. The dense power supply lines and signal lines not only easily cause power noise generated by the power supply lines to interfere with the high-frequency signals in the signal lines, reducing the reliability of chip functions, but may also cause a significant increase in signal delay of the chip packaging structure due to communication path congestion. Therefore, the chip packaging structure 100 shown in Figure 4 still has the problems of long communication paths, high delay, high power consumption, and low communication efficiency, which need to be further improved.

[0065] The chip packaging structure 100 shown in Figure 5 is a further improvement on the above embodiment. Referring to Figure 5, this application embodiment also provides a chip packaging structure 100, which includes a first chip 4, a second chip 5, a first filling layer 6, a first redistribution layer 7, a second redistribution layer 8, and a first metallization via 9.

[0066] In this embodiment, the chip packaging structure 100 can package multiple chips, including the first chip 4 and the second chip 5. Specifically, in some embodiments, the types of chips include, but are not limited to, at least one of the following: a center processing unit (CPU) chip on a PCB, a dynamic random access memory (DRAM) chip, a radio frequency (RF) chip, a power amplifier (PA) chip, a system-on-a-chip (SOC), a power management integrated circuit (PMIC), a memory chip, an audio processor chip, a touch screen control chip, NAND flash memory, and an image sensor chip. Among these, memory chips include, for example, high bandwidth memory (HBM).

[0067] In this embodiment, the first chip 4, the second chip 5, the first redistribution layer 7, and the second redistribution layer 8 may be stacked on top of each other. The first fill layer 6 may be on the same layer as the first chip 4 and surround the first chip 4.

[0068] In some alternative embodiments, the material of the first filler layer 6 may have electrical insulating properties and may include, but is not limited to, silicon oxide, silicon nitride, and polymer compounds. The polymer compound may include plastics, specifically, for example, resin materials. The first filler layer 6 may encapsulate the first chip 4.

[0069] In this embodiment, the first metallized hole 9 penetrates the first filling layer 6 along the thickness direction of the first filling layer 6, thereby enabling the first filling layer 6 to be electrically conductive in the thickness direction.

[0070] In the embodiments of this application, unless otherwise specified, the thickness direction of any structure may refer to the stacking direction of the chip stacking structure.

[0071] In the embodiments of this application, the metallized holes, including the first metallized hole 9, are also collectively referred to as vias. Vias can be obtained by through-hole metallization. For example, by using chemical plating or electroplating in the through-hole of insulating material, a layer of conductive metal can be plated on the insulating hole wall, thereby electrically connecting the conductors located on both sides of the thickness direction of the first filling layer.

[0072] In this embodiment, the first redistribution layer 7 is stacked on one side of the first chip 4 and the first filling layer 6, and is connected to the first chip 4 and the first metallization hole 9, so that the first chip 4 can be electrically connected to the first metallization hole 9, thereby increasing the number of electrical channels connected to the first chip 4.

[0073] Please refer to Figure 5. In this embodiment, the chip may specifically include a first chip 4, a second chip 5, a third chip 10, and so on. The redistribution layer may include a first redistribution layer 7, a second redistribution layer 8, etc., outside the chip, and so on. It may also include a chip redistribution layer inside the chip, and a package redistribution layer outside the chip.

[0074] In some alternative embodiments, the chip in the chip package structure 100 may include a chip redistribution layer, thereby enabling connection to the redistribution layer via redistribution. In still other alternative embodiments, the chip package structure 100 may further include a bonding layer, thereby enabling connection of the chip to the redistribution layer via bonding. The type of bonding layer may include a hybrid bonding layer.

[0075] Referring to Figure 5, specifically, in some optional embodiments, the chip package structure 100 may further include a redistribution bonding layer 23, which is located between the first chip 4 and the first redistribution layer 7. The first chip 4 may further include a chip bonding layer 46, which connects the first chip 4 to the first redistribution layer 7 through bonding between the chip bonding layer 46 and the redistribution bonding layer 23.

[0076] In this embodiment, the second redistribution layer 8 is stacked on one side of the first chip 4 and the first filling layer 6, and is connected to the first redistribution layer 7. The second chip 5 is located on the side of the second redistribution layer 8 away from the first chip 4, and is connected to the second redistribution layer 8 and the first metallized via 9, thereby increasing the number of electrical channels connected to the second chip 5.

[0077] Referring to Figure 5, in some examples, the first chip 4 can be connected to the second redistribution layer 8 via redistribution. In this embodiment, the same chip can be connected to different redistribution layers, which not only facilitates increasing the number of electrical channels connected to the chip, but also adapts to the structural characteristics of the chip and the redistribution layer by using different connection methods, thus helping to improve the efficiency of chip packaging. Correspondingly, in some other examples, the second chip 5 can also be connected to the second redistribution layer 8 via bonding.

[0078] Referring to Figure 5, in some optional embodiments, the redistribution bonding layer 23 may also be located between the second chip 5 and the second redistribution layer 8. The second chip 5 may also include a chip bonding layer 46, and the second chip 5 and the second redistribution layer 8 can be connected through the bonding connection between the chip bonding layer 46 and the redistribution bonding layer 23.

[0079] In the embodiments of this application, the rewiring method can refer to the electrical connection of the device stack structure through two rewiring layers, for example, through the metal exposed on one side of the rewiring layer inside the chip (the first chip rewiring layer 41 in Figure 5) and the metal exposed on one side of the rewiring layer outside the chip (the first rewiring layer 7 in Figure 5).

[0080] Referring to Figure 5, in this embodiment, the first chip 4 can be directly electrically connected to the second chip 5 via wires in the second redistribution layer 8, and can also be electrically connected to the second chip 5 sequentially via wires in the first redistribution layer 7, the first metallized via 9, and the second redistribution layer 8, thereby expanding the electrical channels. Thus, a redistribution layer is added at each chip layer as a lateral interconnection channel, and the redistribution layer has both vertical and lateral communication capabilities, increasing the communication paths between chips. Furthermore, combined with higher density HB pins and the externally located first metallized via 9 on the chip, higher interconnection density and shorter communication paths can be achieved, reducing latency and increasing bandwidth within the chip package structure, thereby improving communication efficiency.

[0081] Through the above embodiments, the chip package structure 100 increases lateral electrical channels through the first redistribution layer 7 and the second redistribution layer 8, and increases electrical channels in the stacking direction of the first chip 4 and the second chip 5, as well as vertical electrical channels, using the first metallization via 9 in the first filling layer 6. This increases the communication paths between the first chip 4 and the second chip 5, and between the first chip 4 or the second chip 5 and other electronic devices, improving the vertical and lateral communication capabilities within the chip package structure 100. Signals between chips can be transmitted vertically through the first metallization via 9 and horizontally through the first redistribution layer 7 and the second redistribution layer 8, improving signal transmission efficiency and reducing signal delay. Therefore, not only does the stacking of the first chip 4 and the second chip 5 increase the packaging density of the chip package structure, but the first redistribution layer 7, the second redistribution layer 8, and the first metallization via 9 also expand the electrical channels, improving the internal communication efficiency of the chip package structure, reducing signal crosstalk, and ensuring the reliability of the chip package structure.

[0082] Referring to Figure 5, and in conjunction with the above embodiments, in some optional implementations, the chip package structure 100 further includes a third chip 10 and a fourth chip 11. The third chip 10 is disposed on the same layer as the first chip 4, and the first filler layer 6 further surrounds the third chip 10. The fourth chip 11 is disposed on the same layer as the second chip 5. A first redistribution layer 7 is also located on one side of the third chip 10 and connected to it. A second redistribution layer 8 is also located on one side of the fourth chip 11, and the fourth chip 11 is connected to the second redistribution layer 8 and the first metallized via 9.

[0083] Through the above embodiments, the lateral topology of the chip packaging structure 100 can be expanded by using the third chip 10 and the fourth chip 11, thereby improving the packaging density and overall performance of the chip packaging structure. Furthermore, the interconnection relationship between the third chip 10 and the fourth chip 11 can refer to the first chip 4 and the second chip 5, which can further enhance the lateral communication capability of the chip packaging structure 100.

[0084] Referring to Figure 5, and in conjunction with the above embodiments, in some optional implementations, the first chip 4 and the second chip 5 may be high-speed interconnect chips to achieve signal input / output processing. Alternatively, the first chip 4 and the second chip 5 may be computing chips to achieve signal computation processing.

[0085] Among them, computing chips can use integrated transistors to perform signal processing and can also be called logic chips. High-speed interconnect chips can perform input / output processing of signals and can also be called input / output chips.

[0086] Referring to Figure 5, and in conjunction with the above embodiments, in some optional implementations, the third chip 10 and the fourth chip 11 may be high-speed interconnect chips, thereby cooperating with the first chip 4 and the second chip 5 to realize input / output processing of signals on the same layer within the chip package structure 100. Alternatively, the third chip 10 and the fourth chip 11 may be computing chips, thereby cooperating with the first chip 4 and the second chip 5 to realize computational processing of signals on the same layer within the chip package structure.

[0087] In some examples, the first chip 4 and the second chip 5 are computing chips, and the third chip 10 and the fourth chip 11 are high-speed interconnect chips, in order to achieve computational processing and input / output processing of signals on the same layer.

[0088] In some alternative embodiments, the computing chip and the high-speed interconnect chip are manufactured using different process technologies. For example, the computing chip may have a higher process node to accommodate a larger number of transistors, while the high-speed interconnect chip may have a lower process node to reduce the overall cost of the chip package.

[0089] Through the above embodiments, the chip package structure 100 delegates signal input / output processing to the high-speed interconnect chip and signal computation processing to the computing chip. Computing chips are often expensive to manufacture. Separating some power and signal circuits from the computing chip, and using metallized vias for power supply and high-speed interconnect chips for signal transmission, reduces the area wasted by the computing chip due to power supply or communication requirements, thereby improving area utilization efficiency and correspondingly reducing chip manufacturing costs.

[0090] Figures 6-8 illustrate some lateral topological diagrams of the chip package structure 100 provided in the embodiments of this application. Referring to Figures 6-8, and in conjunction with the above embodiments, in some optional implementations, along the XY plane, the chip package structure 100 includes a computing chip region 101, a high-speed interconnect chip region 102, a metallized via region 103, and a package region 104.

[0091] Referring to Figures 5-8, in some embodiments, the first chip 4 and the second chip 5 can be disposed in the computing chip region 101, the third chip 10 and the fourth chip 11 can be disposed in the high-speed interconnect chip region 102, the first metallized via 9 can be disposed in the metallized via region 103, and the first redistribution layer 7, the second redistribution layer 8, the carrier layer 20, the dielectric layer 21, and the first solder ball 22 can be located in the first packaging region 104. The carrier layer 20 and the dielectric layer 21 can be dummy wafers.

[0092] The arrows shown in Figures 6-8 schematically illustrate the electrical connection relationships between the structures of each region in the chip package structure 100.

[0093] Referring to Figures 5-8, in some optional embodiments, the first chip 4 and the third chip 10 are electrically connected and can be used for signal transmission. The first metallized via 9 is electrically connected to the first chip 4 through the first redistribution layer 7 or the second redistribution layer 8 and can be used to supply power to the first chip 4. The first chip 4 and the second chip 5 are directly electrically connected through the second redistribution layer 8 and can be used for both signal transmission and power supply. This allows for the division of signal transmission and power supply areas, reducing crosstalk, such as reducing power supply noise interference with high-frequency signals.

[0094] Furthermore, referring to Figures 5-8 and the above embodiments, in some optional implementations, along the XY plane, the chip can be divided into different regions according to the electrical connection type of the communication path to further reduce signal crosstalk. For example, the chip regions can be divided for accessing power supply lines and signal transmission lines respectively. In some further optional implementations, the region of the first chip 4 near the second chip 5 can also be used for accessing signal transmission lines, and the region of the first chip 4 near the first metallized via 9 can be used for accessing power supply lines.

[0095] Referring to Figures 5-8, in some optional embodiments, the number of first chips 4 can be multiple, and multiple first chips 4 are arranged on the same layer. For example, the number of first chips 4 can be two or four.

[0096] Referring to Figures 5 and 6, in some optional embodiments, the second chip 5 can be located on one side of multiple first chips 4 and the distance between it and each first chip 4 is equal, so that the communication paths are equal or similar, thereby maximizing communication efficiency.

[0097] In some alternative implementations, the second chip 5 may be located on one side of a plurality of first chips 4, and the spacing between the second chip 5 and each of the first chips 4 may be unequal.

[0098] Referring to Figures 5 and 7, in some alternative embodiments, the number of first chips 4 can be four. The first chips 4 can also be located in pairs on opposite sides of the second chips 5, and the distance between any one first chip 4 and each second chip 5 is equal, so that the communication paths are equal or similar, thereby maximizing communication efficiency.

[0099] In some alternative implementations, the first chip 4 can be located on opposite sides of the second chip 5 in pairs, and the spacing between each first chip 4 and the first chip 4 can also be unequal.

[0100] Referring to Figures 5 and 8, in some alternative embodiments, every two first chips 4, one second chip 5, and the first metallization holes 9 located on opposite sides of the two first chips 4 form a chipset, and the chip package structure 100 may also include multiple chipsets.

[0101] Please refer to Figure 5. It can be understood that the number of the second chip 5 can correspond to the number of the first chip 4, and the number of the fourth chip 11 can correspond to the number of the third chip 10.

[0102] Referring to Figure 5, further, in some optional embodiments, at least a portion of the orthographic projection of the second chip 5 on the first transition layer 12 overlaps with the orthographic projection of the first chip 4 on the first transition layer 12; or, at least a portion of the orthographic projection of the fourth chip 11 on the first transition layer 12 overlaps with the orthographic projection of the third chip 10 on the first transition layer 12. This increases the area of ​​direct electrical connection between the first chip 4 and the second chip 5, as well as the area of ​​direct electrical connection between the third chip 10 and the fourth chip 11, reducing the length of the communication path and improving communication efficiency.

[0103] Referring to Figures 5-8, in some optional embodiments, the first metallized hole 9 located in the metallized hole region 103 may be located on at least one side of the first chip 4. For example, the first metallized hole 9 may be located on the side of the first chip 4 away from the third chip 10, or it may be located on the side of the third chip 10 away from the first chip 4, in order to minimize the length of the lateral communication path and improve communication efficiency.

[0104] In this embodiment, the power supply lines and signal lines can be separated and centrally distributed. Noise generated by the power supply lines will not affect the communication of the signal lines, thereby avoiding signal distortion. For example, the first metallized via 9 in Figure 5 can be responsible for power supply and is distributed in the edge region of the chip package structure 100 (refer to the metallized via region 103 in Figures 6-8). The third and fourth chips responsible for vertical communication can have metallized through-silicon vias (TSVs) and can act as high-speed interconnect chips to collect signals from the current layer and then transmit signals upward or downward through the metallized TSVs. Furthermore, since the main power supply lines are distributed outside the chip and connected through the metallized vias, the diameter of the metallized vias can be designed to be larger, thereby reducing the impedance of the vertical circuit.

[0105] In this embodiment, the chip packaging structure may have multiple transistor layers, including a first transistor layer, a second transistor layer, a third transistor layer, and so on.

[0106] Referring to Figure 5, and in conjunction with the above embodiments, in some optional implementations, the first chip 4 includes a first chip redistribution layer 41, a first transistor layer 42, and a power supply network layer 43. The first chip redistribution layer 41 is located on the side of the first transistor layer 42 facing the first redistribution layer 7, and is connected to the first transistor layer 42. Thus, the first chip redistribution layer 41 and the first redistribution layer 7 can be connected through redistribution, thereby realizing the connection between the first redistribution layer 7 and the first chip 4.

[0107] The power supply network layer 43 is located on the side of the first transistor layer 42 away from the first redistribution layer 7 and is connected to the first transistor layer 42. This allows the power supply network layer 43 to provide back power to the first transistor layer 42, thus enabling back power supply to the first chip 4. Therefore, the power supply network layer can also be called a Backside Power Delivery Network (BSPDN).

[0108] In some alternative embodiments, the power supply network layer 43 may include an insulating layer and multiple layers of metal wires disposed within the insulating layer. In still other alternative embodiments, the power supply network layer 43 may also include, but is not limited to, electronic devices such as capacitors and inductors.

[0109] In the above embodiments, the chip closer to the carrier layer 20 requires fewer electrical channels compared to other chips, so a back power supply network is not required. For example, in the three-layer chip packaging structure shown in Figure 12, the first chip 4 and the second chip 5 can have a power supply network layer, while the fifth chip 17 can be without a power supply network layer.

[0110] In the above embodiments, the use of a back-side power supply network significantly reduces the IR-Drop phenomenon. Furthermore, back-side power supply enables lower power grid density, further reducing impedance and IR-Drop, and improving the energy utilization efficiency of the chip package structure. Moreover, combined with the use of metallized vias and redistribution layers in the above embodiments, the back-side power supply network allows power / ground lines to bypass the back-end of line (BEOL) layer, significantly reducing the length of metal lines used for power supply in the chip package structure, thereby reducing power consumption and the number of buffers. Furthermore, combined with the use of metallized vias and redistribution layers in the above embodiments, the back-side power supply network can significantly reduce Design Rule Check (DRC) violations and timing congestion, improve chip area utilization, and enhance the overall physical design of the chip package structure.

[0111] Through the above embodiments, the first chip 4 and other computing chips can have a back power supply network. As a computing chip, the field-effect transistors in the first transistor layer 42 can be directly powered through the second metallization hole 45 in the substrate 44 on the back of the chip. Therefore, in conjunction with the above embodiments, for the computing chip, the power layer and the corresponding power supply lines are separated from the signal layer and the corresponding signal lines.

[0112] Referring to Figure 5, and in conjunction with the above embodiments, in some optional implementations, the first chip 4 further includes a substrate 44 and a second metallized via 45. The substrate 44 can serve as the substrate of the first chip 4.

[0113] The material of substrate 44 may be electrically insulating. Specifically, the material of substrate 44 may include, but is not limited to, inorganic and organic materials. For example, inorganic materials may include ceramics, such as silicon nitride (Si3N4), and organic materials may include plexiglass.

[0114] The substrate 44 is located between the first transistor layer 42 and the power supply network layer 43. The second metallization hole 45 penetrates the substrate 44 along the thickness direction of the substrate 44. The second metallization hole 45 can be electrically connected to the first transistor layer 42 and the power supply network layer 43 to realize the electrical conduction of the substrate 44 in the thickness direction.

[0115] Specifically, in some optional embodiments, the first transistor layer 42 includes a field-effect transistor (not shown in the figure), and the power supply network layer 43 is connected to the field-effect transistor through a second metallization via 45. By turning the field-effect transistor on or off, the back power supply control of the first transistor layer 42 can be realized, and the transmission of signals can also be controlled in this way.

[0116] Referring to Figures 5 and 9, in some optional embodiments, the chip package structure 100 further includes a first transition layer 12 and a first package redistribution layer 13. The first transition layer 12 is located on the side of the first redistribution layer 7 away from the second redistribution layer 8 and is connected to the first redistribution layer 7. The first package redistribution layer 13 is located on the side of the first transition layer 12 away from the first redistribution layer 7 and is connected to the first transition layer 12. Thus, signal switching processing, redistribution processing, and packaging of the chip can be realized.

[0117] In this embodiment, the adapter layer connected to the first package redistribution layer 13 can be referred to as the first adapter layer 12, and the package redistribution layer connected to the first adapter layer 12 can be referred to as the first package redistribution layer 13. The first adapter layer 12 can function as a signal adapter, and the first package redistribution layer 13 can function as a signal fan-out.

[0118] Referring to Figures 5 and 9, in some optional embodiments, the first transition layer 12 may specifically include a second transistor layer 121, a first base layer 122, and a first transition metallization via 123. The first transition metallization via 123 penetrates the first base layer 122 along its thickness direction. The second transistor layer 121 is disposed on the side of the first transition layer 12 near the first redistribution layer 7 and is electrically connected to the first redistribution layer 7. The second transistor layer 121 is also electrically connected to the first transition metallization via 123, thereby electrically connecting to the first package redistribution layer 13 through the first transition metallization via 123.

[0119] Figure 5 also shows the case where the first chip 4 and the second chip 5 are located on the same side of the first transition layer 12. Referring to Figure 5, in conjunction with the above embodiments, in some optional embodiments, the second redistribution layer 8 is located on the side of the first chip 4 and the first fill layer 6 away from the first redistribution layer 7, and is connected to the first redistribution layer 7 through the first metallization via 9.

[0120] In the above embodiments, the stacked first chip 4 and second chip 5 are located on the same side of the first transition layer 12. The first transition layer 12 realizes the signal transfer between the first chip 4 and the second chip 5 through the first redistribution layer 7, which facilitates the unified processing of signals. The first packaging redistribution layer 13 can not only realize signal transmission, but also encapsulate one side of the chip packaging structure 100.

[0121] Figure 9 shows the first chip 4 and the second chip 5 located on opposite sides of the first interfacing layer 12. Referring to Figure 9, and in conjunction with the above embodiments, in some optional implementations, the second redistribution layer 8 is located on the side of the first redistribution layer 7 away from the first chip 4 and the first filling layer 6. The chip package structure 100 further includes: a first interfacing layer 12 and a first package redistribution layer 13. The first interfacing layer 12 is located between the first redistribution layer 7 and the second redistribution layer 8, and the first redistribution layer 7 is connected to the second redistribution layer 8 through the first interfacing layer 12. The first package redistribution layer 13 is located on the side of the second chip 5 and the first filling layer 6 away from the second redistribution layer 8, and is connected to the second chip 5. The first package redistribution layer 13 is connected to the second redistribution layer 8 through a first metallized via 9. In the above embodiments, the stacked first chip 4 and the second chip 5 are located on opposite sides of the first transition layer 12, and are electrically connected to the first transition layer 12 through the first redistribution layer 7 and the second redistribution layer 8, respectively. The first transition layer 12 transfers the signals in the first redistribution layer 7 and the second redistribution layer 8, respectively. Since the spacing between the first chip 4 and the second chip 5 and the first transition layer 12 in the chip stacking direction (i.e., the Z direction) is equal or similar, the signal transfer paths are also equal or similar, which helps to further reduce the voltage drop phenomenon of the lines in the chip package structure 100.

[0122] The above embodiments mainly describe the case where a chip package structure contains two stacked chips. Figure 10 shows one case where a chip package structure contains multiple stacked chips. Referring to Figure 10, the chip package structure 100 can also package three or more stacked chips. For example, the chip package structure can package five or ten layers of chips.

[0123] Figure 11 illustrates another scenario where a chip package structure contains multiple stacked chips. Referring to Figure 11, when the chip package structure encapsulates multiple stacked chips, and the thickness of the chip package structure is sufficient, the carrier layer 20 and dielectric layer 21 shown in Figure 10 can be omitted as support. The chip furthest from the first solder ball 22 can be protected by its own substrate and the filling layer encapsulating the chip. Taking Figure 11 as an example, assuming a three-layer chip package, the sixth chip 18 can be protected by its own substrate 44 and the third filling layer 19 encapsulating the sixth chip 18.

[0124] Figures 12 and 13 illustrate a chip package structure with three stacked chips. Referring to Figures 12 and 13, and in conjunction with the above embodiments, in some optional implementations, the chip package structure 100 further includes a second fill layer 14, a third metallized via 15, a third redistribution layer 16, and a fifth chip 17. The second fill layer 14 is on the same layer as the second chip 5 and surrounds the periphery of the second chip 5. The third metallized via 15 penetrates the second fill layer 14 along its thickness direction. The third redistribution layer 16 is located on the side of the second chip 5 and the second fill layer 14 away from the second redistribution layer 8, and is connected to the second chip 5. The fifth chip 17 is located on the side of the third redistribution layer 16 away from the second chip 5, and is connected to the third redistribution layer 16 and the third metallized via 15.

[0125] Referring to Figures 12 and 13, in some optional embodiments, the second chip 5 can be directly connected to the fifth chip 17 via a conductor in the third redistribution layer 16, or it can be connected to the fifth chip 17 sequentially via the second redistribution layer 8, the third metallized via 15, and the third redistribution layer 16. In some optional embodiments, the second chip 5 can be directly connected to the first chip 4 via a conductor in the second redistribution layer 8, or it can be connected to the first chip 4 sequentially via the second redistribution layer 8, the first metallized via 9, and the first redistribution layer 7.

[0126] By providing a fifth chip 17 stacked with the first chip 4 and the second chip 5 through the above embodiments, the number of chip layers in the chip packaging structure 100 is increased, which helps to improve the chip packaging density and performance.

[0127] Please refer to Figures 12 and 13. In conjunction with the above embodiments, in some optional implementations, the chip package structure 100 may further include a sixth chip 18, which is disposed on the same layer as the fifth chip 17 and connected to the third redistribution layer 16.

[0128] In conjunction with the above embodiments, in some optional implementations, the chip package structure 100 may further include a third filling layer 19, which is disposed on the same layer as the fifth chip 17 and wraps around the periphery of the fifth chip 17 or the sixth chip 18.

[0129] In conjunction with the above embodiments, in some optional implementations, the material of the second filling layer 14 or the third filling layer 19 can be the same as the material of the first filling layer 6, so as to facilitate manufacturing and reduce manufacturing costs.

[0130] Referring to Figure 5, in some optional embodiments, the chip package structure 100 may further include a carrier layer 20 and a dielectric layer 21, with the dielectric layer 21 located on the side of the second chip 5 and the second fill layer 14 away from the second redistribution layer 8, and the carrier layer 20 located on the side of the dielectric layer 21 away from the second chip 5 and the second fill layer 14.

[0131] In some alternative embodiments, the material of the carrier layer 20 may include, but is not limited to, inorganic and organic materials. For example, inorganic materials may include ceramics, such as silicon nitride (Si3N4), and organic materials may include plexiglass. Further, the material of the carrier layer 20 may be the same as the material of the substrate.

[0132] In some alternative embodiments, the material of the dielectric layer 21 may include, but is not limited to, silicon oxide (SiO2) and silicon nitride (SiN). x One of the following: , and aluminum oxide (Al2O3).

[0133] Please refer to Figure 5. In some optional embodiments, the chip package structure 100 may further include a first solder ball 22, which is electrically connected to the first package redistribution layer 13.

[0134] Referring to Figure 14, in some alternative embodiments, the first solder ball 22 can be electrically connected to the motherboard 500. Furthermore, multiple chip package structures 100 can be electrically connected to the same motherboard 500.

[0135] In some optional embodiments, the motherboard 500 may include the second transition layer 501 shown in FIG. 15, which can serve as a signal transition layer. Specifically, the second transition layer 501 may include a third transistor layer 5011 and a second base layer 5012. The second base layer 5012 can serve as a substrate. The second transition layer 501 may also include a second transition metallization via 5013, which penetrates the thickness direction of the second base layer 5012. The motherboard 500 may also include a second packaging redistribution layer 502 shown in FIG. 15, which can serve as a signal fan-out layer.

[0136] Please refer to Figure 15. In some optional embodiments, the chip packaging structure 100 in the above embodiments can also be integrated into a 2.5D packaging structure. Specifically, the chip packaging structure 100 may also include an HBM chip 511, a molding layer 512, a second transition layer 501, a second packaging redistribution layer 502, and a second solder ball 513.

[0137] The molding layer 512 is used to mold the HBM chip 511. The HBM chip 511 and the first redistribution layer 7 are electrically connected to the second transition layer 501 through the first solder ball 22, and the second encapsulation redistribution layer 502 is electrically connected to the second solder ball 513.

[0138] Referring to Figure 16, in some optional embodiments, the bonding method between the chip and the redistribution layer includes, but is not limited to, at least one of hybrid bonding or microbump bonding. The fifth chip 17 in Figure 16 includes a first metal microbump structure 171, and the third redistribution layer 16 includes a second metal microstructure 161. The bonding between the first metal microbump structure 171 and the second metal microstructure 161 enables the fifth chip 17 and the third redistribution layer 16 to be connected. The sixth chip 18, which is in the same layer as the fifth chip 17, can also be bonded to the third redistribution layer 16 using the same bonding method. The remaining chips can be connected to the redistribution layer using a hybrid bonding method.

[0139] Referring to Figure 16, in some optional embodiments, the chip package structure 100 may further include a wafer dummy 24 located on the side of a portion of the first metal microbump structure 171 away from the second metal microstructure 161, in order to facilitate the implementation of the microbump bonding process in the chip package structure 100.

[0140] Referring to Figures 17 and 18, in some optional embodiments, the chip package structure 100 may further include an electronic device 514 and a third packaging redistribution layer 25. The third packaging redistribution layer 25 may be located on the side of the second chip 5 and the second fill layer 14 away from the second redistribution layer 8. The electronic device 514 may be electrically connected to the third packaging redistribution layer 25. Taking a two-layer chip package structure 100 as an example, the third packaging redistribution layer 25 may be electrically connected to the second redistribution layer 8 through a third metallized via 15.

[0141] Referring to Figure 17, in some optional embodiments, the electronic device 514 can be electrically connected to the third package redistribution layer 25 via wire bonding, thereby being electrically connected to the chip. In conjunction with these embodiments, in some cases, the type of the electronic device 514 may include, but is not limited to, a sensor, an antenna, or a capacitor.

[0142] Referring to Figure 18, in some alternative embodiments, the electronic device 514 can be electrically connected to the third package redistribution layer 25 via a pin, thereby being electrically connected to the chip. In conjunction with these embodiments, in some cases, the type of the electronic device 514 may include, but is not limited to, a sensor, capacitor, LED, and inductor.

[0143] Referring to Figure 19, in some optional embodiments, this application also provides a method for manufacturing the above-described chip packaging structure, the method comprising:

[0144] Step S701: Create the first rewiring layer.

[0145] Step S702: Fabricate a first chip, a first fill layer, and a first metallized via stacked on the first redistribution layer. The first metallized via penetrates the first fill layer along its thickness direction, and the first redistribution layer is connected to the first chip and the first metallized via. The first fill layer surrounds the first chip.

[0146] Step S703: Fabricate a second redistribution layer stacked on the first chip and the first fill layer, and connect the second redistribution layer to the first redistribution layer.

[0147] In step S704, a second chip is fabricated on the side of the second redistribution layer away from the first chip, and the second chip is connected to the second redistribution layer and the first metallization via.

[0148] Furthermore, taking the fabrication of the first chip 4 in Figure 5 or Figure 12 as an example, this application embodiment also provides a chip fabrication method. Please refer to Figure 20. The fabrication method specifically includes:

[0149] Step S711: A wafer 44' is provided, including an unthinned second metallized via 45'. A transistor layer 42 and a first chip redistribution layer 41 are fabricated on the wafer 44' to obtain a first die 401. The transistor layer 42 includes a plurality of transistors. Exemplarily, the transistors may include field-effect transistors. Specifically, the first chip redistribution layer 41 includes metal lines.

[0150] In step S712, the first die 401 is bonded to the dummy wafer 24 using a wafer-to-wafer (W2W) bonding process to obtain the second die 402. In some embodiments, a dielectric layer 21 may also be provided between the first die 401 and the dummy wafer 24. In some examples, the dummy wafer 24 may not have circuitry, and the specific type may include a silicon wafer.

[0151] In step S713, the wafer 44' in the second core 402 is thinned to obtain a substrate 44 and a second metallized hole 45, and a wafer dummy 24 is used as a support for the thinned second core 402 to obtain a third core 403. Exemplarily, the wafer can be thinned until the thickness of the substrate 44 is <10 μm.

[0152] In step S714, a power supply network layer 43 is fabricated on the side of the third chip 403 where the substrate 44 and the second metallization via 45 are located, resulting in a fourth chip 404. The power supply network layer 43 includes multiple layers of metal lines, which can be electrically connected to transistors in the transistor layer 42 through the second metallization via 45.

[0153] In step S715, a chip bonding layer 46 is fabricated on the side surface of the fourth chip 404 where the power supply network layer 43 is located, to obtain the fifth chip 405. Specifically, the chip bonding layer 46 can be a hybrid bonding layer, which may include inorganic dielectrics (such as SiO2, SiN, SiCN) and metal pads (such as Cu, Au).

[0154] Step S716: The dummy wafer in the fifth core 405 is thinned to obtain the sixth core 406. For example, the dummy wafer, which serves as a support, can be thinned until the thickness is <200μm.

[0155] In step S717, multiple sixth cores 406 can be fabricated on the same dummy wafer. Individual cores can be obtained by cutting the wafer. Exemplarily, the cutting method may include, but is not limited to, wheel cutting, plasma cutting, laser cutting, stealth cutting, etc.

[0156] Taking the second chip 5, the third chip 10 and the fourth chip 11 in Figure 5 as examples, it is not necessary to make a power supply network layer. Please refer to Figure 21. The manufacturing method of these chips can be obtained by referring to the above steps S711 to obtain chip 521, referring to step S715 to obtain chip 522, referring to step S716 to thin the wafer 44' to obtain chip 523, and referring to step S717 to cut the chip.

[0157] Taking the fabrication of the first transition layer 12 and the first redistribution layer 7 in Figure 5 as an example, the fabrication of the chip described above can also be referred to. Please refer to Figure 22. Specifically, the chip 1201 can be obtained by referring to step S711 and the chip 1202 can be obtained by referring to step S715.

[0158] Please refer to Figures 23A-23L. This application also provides a method for manufacturing the above-described chip packaging structure, the method specifically including:

[0159] Step S731, referring to Figure 23A, provides the original die 4' of the first chip, the original die 10' of the third chip, the original layer 12' of the first interfacing layer, and the first redistribution layer 7. The first redistribution layer 7 is mounted to one side of the original layer 12' of the first interfacing layer. Then, using chip-to-wafer (C2W) bonding, the original die 4' of the first chip and the original die 10' of the third chip are mounted to the side of the first redistribution layer 7 away from the original layer 12' of the first interfacing layer.

[0160] In step S732, referring to Figure 23B, the gap between the original die 4' of the first chip and the original die 10' of the third chip is filled with filling material 6'. The filling material 6' may include, but is not limited to, at least one of inorganic materials such as silicon oxide (SiO2) and silicon nitride (SiN), and may also include, but is not limited to, at least one of organic materials such as polyimide (PI) and benzocyclobutene (BCB). The filling process may include, but is not limited to, chemical vapor deposition (CVD) and spin coating. Chemical vapor deposition, for example, is plasma-enhanced chemical vapor deposition (PECVD).

[0161] In step S733, referring to Figure 23C, the surfaces of the filler material 6', the original die 4' of the first chip, and the original die 10' of the third chip away from the first redistribution layer 7 are planarized to obtain the first chip 4, the third chip 10, and the first filler layer 6. Exemplarily, processes such as backside gridding (BG) and chemical-mechanical planarization (CMP) can be used to thin the die and filler material.

[0162] Step S734, referring to Figure 23D, fabricate the interconnect. The interconnect includes a first metallized via 9 for vertical interconnection and a second redistribution layer 8 for horizontal interconnection. In some examples, the first metallized via 9 may be obtained by metallization using through-silicon vias (TSVs), and the second redistribution layer 8 may include metal lines.

[0163] In step S735, please refer to Figure 23E to fabricate a rerouting bonding layer 23 on the second rerouting layer 8. For details, please refer to step S715 above.

[0164] Step S736, referring to Figures 23F-23I, depending on the number of chip layers to be fabricated, steps S731-S735 can be iteratively referenced to obtain multi-layer chips and related structures. For example, using the original die 5' of the second chip and the original die 11' of the third chip in Figure 23F, the second chip 5 and the fourth chip 11 in Figure 23G can be obtained respectively. Taking the fabrication of a chip package structure containing three layers as an example, after referring to steps S731-S735 twice, and then referring to steps S731-S733, using the original die 17' of the third chip and the original die 18' of the fourth chip in Figure 23H, the fifth chip 17 and the sixth chip 18 in Figure 23I can be obtained respectively.

[0165] In step S737, referring to Figure 23J, a carrier layer 20 and a dielectric layer 21 are fabricated on one side of the structure obtained in step S736. Specifically, refer to steps S712 and S716. For example, the carrier layer 20 and the dielectric layer 21 can be wafer dummy wafers, which serve as supports and can be thinned to a thickness of <100μm.

[0166] Step S738, please refer to Figure 23K, thin the original layer 12' of the first transition layer to obtain the first transition layer 12.

[0167] In step S739, referring to Figure 23L, a packaged redistribution layer 13 is fabricated on the side of the first transition layer 12 away from the first redistribution layer 7. The packaged redistribution layer 13 may include metal wires and the dielectric between the wires. The dielectric material may include, but is not limited to, inorganic materials such as SiO2, SiN, SiCN, and GaN, or organic materials such as PI and BCB.

[0168] In step S740, please refer to Figure 23L to create metal microbumps or solder balls on the side of the package redistribution layer 13 away from the first transition layer 12.

[0169] Step S741: The above structure is divided into multiple individual chips by cutting, as detailed in step S717 above.

[0170] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip packaging structure, characterized in that, The chip packaging structure includes: First chip; The first filling layer surrounds the first chip; The first metallized hole penetrates the first filler layer along the thickness direction of the first filler layer; A first redistribution layer is stacked on one side of the first chip and the first fill layer, and is connected to the first chip and the first metallization via. The second redistribution layer is stacked on one side of the first chip and the first fill layer, and is connected to the first redistribution layer; The second chip is located on the side of the second redistribution layer away from the first chip and is connected to the second redistribution layer and the first metallized via.

2. The chip packaging structure according to claim 1, characterized in that, It also includes a third chip and a fourth chip, with the first filling layer also wrapping around the third chip, and the fourth chip being disposed in the same layer as the second chip; The first redistribution layer extends to one side of the third chip and is connected to the third chip; the second redistribution layer extends to one side of the fourth chip, and the fourth chip is connected to the second redistribution layer and the first metallized via.

3. The chip packaging structure according to claim 1 or 2, characterized in that, The first chip and the second chip are either high-speed interconnect chips or computing chips.

4. The chip packaging structure according to claim 3, characterized in that, The third chip and the fourth chip are either high-speed interconnect chips or computing chips.

5. The chip packaging structure according to claim 1 or 2, characterized in that, The first chip includes a chip redistribution layer, a transistor layer, and a power supply network layer; the chip redistribution layer is located on the side of the transistor layer facing the first redistribution layer and is connected to the transistor layer; The power supply network layer is located on the side of the transistor layer away from the first redistribution layer and is connected to the transistor layer.

6. The chip packaging structure according to claim 5, characterized in that, The first chip further includes a substrate and a second metallized via; the substrate is located between the transistor layer and the power supply network layer, and the second metallized via penetrates the substrate along its thickness direction; the transistor layer includes a field-effect transistor, and the power supply network layer is connected to the field-effect transistor through the second metallized via.

7. The chip packaging structure according to any one of claims 1-6, characterized in that, The second redistribution layer is located on the side of the first chip and the first filling layer away from the first redistribution layer, and is connected to the first redistribution layer through the first metallization via; The chip packaging structure also includes: The transition layer is located on the side of the first redistribution layer away from the second redistribution layer, and is connected to the first redistribution layer; The encapsulation redistribution layer is located on the side of the transition layer away from the first redistribution layer and is connected to the transition layer.

8. The chip packaging structure according to any one of claims 1-6, characterized in that, The second redistribution layer is located on the side of the first redistribution layer that is away from the first chip and the first fill layer; The chip packaging structure also includes: An interleaving layer is located between the first redistribution layer and the second redistribution layer, through which the first redistribution layer is connected to the second redistribution layer; A packaging redistribution layer is located on the side of the second chip and the first filling layer away from the second redistribution layer, and is connected to the second chip; The encapsulation redistribution layer is connected to the second redistribution layer through the first metallized via.

9. The chip packaging structure according to any one of claims 1-8, characterized in that, The chip packaging structure also includes: The second filling layer surrounds the second chip. The third metallized hole penetrates the second filler layer along the thickness direction of the second filler layer; The third redistribution layer is located on the side of the second chip and the second fill layer away from the second redistribution layer, and is connected to the second chip; The fifth chip is located on the side of the third redistribution layer away from the second chip and is connected to the third redistribution layer and the third metallization via.

10. The chip packaging structure according to any one of claims 1-9, characterized in that, The first chip is connected to the first redistribution layer by bonding, or the second chip is connected to the second redistribution layer by bonding, or the first chip is connected to the second redistribution layer by redistribution.

11. A method for fabricating a chip packaging structure, characterized in that, The manufacturing method includes: Create the first rewiring layer; A first chip, a first filling layer, and a first metallized via are fabricated and stacked on the first redistribution layer; the first metallized via penetrates the first filling layer along the thickness direction of the first filling layer, and the first redistribution layer is connected to the first chip and the first metallized via; wherein, the first filling layer surrounds the periphery of the first chip; A second redistribution layer is fabricated on top of the first chip and the first fill layer, and the second redistribution layer is connected to the first redistribution layer. A second chip is fabricated on the side of the second redistribution layer away from the first chip, and the second chip is connected to the second redistribution layer and the first metallization via.

12. An electronic device, characterized in that, The electronic device includes: Circuit board; The chip packaging structure as described in any one of claims 1-10 or the chip packaging structure fabricated using the method for fabricating the chip packaging structure as described in claim 11; The chip packaging structure is connected to the circuit board.

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