Back-contact solar cell, cell assembly, and photovoltaic system

Abstract

The present disclosure is applicable to the technical field of solar cells, and provides a back-contact solar cell, a cell assembly, and a photovoltaic system. The back-contact solar cell comprises: a silicon substrate, the silicon substrate having a back surface and a front surface disposed opposite to one another; a P-type doped polysilicon layer, located in a first region of the back surface of the silicon substrate; an N-type doped polysilicon layer, located in a second region of the back surface of the silicon substrate; a first metal electrode, disposed in the first region and in contact with the P-type doped polysilicon layer; and a second metal electrode, disposed in the second region and in contact with the N-type doped polysilicon layer. The depth at which a metal crystal of the first metal electrode enters the P-type doped polysilicon layer is greater than the depth at which a metal crystal of the second metal electrode enters the N-type doped polysilicon layer. The back-contact solar cell of the present disclosure can improve the contact effect between the metal electrode and the P-type doped polysilicon layer, thereby improving the conductivity between the metal electrode and the P-type doped polysilicon layer and improving the cell conversion efficiency.

Description

Back contact solar cell, cell assembly and photovoltaic system

[0001] Priority information

[0002] The present application claims priority to and the benefit of the filing date of Chinese Patent Application No. 202410821423.3, filed on June 24, 2024, and which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of solar cells, in particular to a back contact solar cell, a cell assembly and a photovoltaic system. BACKGROUND

[0004] Solar power generation is a sustainable clean energy source, which can convert sunlight into electrical energy by using the photovoltaic effect of semiconductors, and the conversion efficiency is an important indicator of solar cell performance. IBC (Interdigitated back contact) solar cell, also known as interdigital back contact cell, has both positive and negative electrodes designed on the back of the cell, so that the front surface is completely free from the obstruction of metal grid lines, eliminating the optical loss caused by the obstruction of metal grid lines, and the electrode width can be designed wider than existing ones, reducing the series resistance loss, thereby greatly improving the conversion efficiency of the cell. In addition, due to the design of no electrode on the front surface, the product appearance is more beautiful, which is suitable for various application scenarios.

[0005] In the prior art, the back surface of the back contact solar cell forms staggered P and N regions. Generally, the depth of the metal electrode corresponding to the P region into the P-type doped polysilicon layer is equal to the depth of the metal electrode corresponding to the N region into the N-type doped polysilicon layer. Since the contact effect of the P-type doped polysilicon layer and the metal electrode is relatively poor, the conductivity of the P-type doped polysilicon layer and the metal electrode is poor, which affects the conversion efficiency of the cell. SUMMARY

[0006] The present disclosure provides a back contact solar cell, which aims to solve the problem that the contact effect of the P-type doped polysilicon layer and the metal electrode is poor in the prior art back contact solar cell, which affects the conversion efficiency of the cell.

[0007] The present disclosure is implemented in this way, providing a back contact solar cell, comprising:

[0008] a silicon substrate having a back surface and a front surface arranged oppositely;

[0009] a P-type doped polysilicon layer located in a first region of the back surface of the silicon substrate;

[0010] An N-type doped polysilicon layer is located in a second region of the back surface of the silicon substrate, and the first region is different from the second region;

[0011] A first metal electrode is arranged in the first region and in contact with the P-type doped polysilicon layer;

[0012] A second metal electrode is arranged in the second region and in contact with the N-type doped polysilicon layer;

[0013] The depth of the metal crystal of the first metal electrode into the P-type doped polysilicon layer is greater than the depth of the metal crystal of the second metal electrode into the N-type doped polysilicon layer.

[0014] Preferably, the ratio of the depth of the metal crystal of the first metal electrode into the P-type doped polysilicon layer to the depth of the metal crystal of the second metal electrode into the N-type doped polysilicon layer is 1-4, and not equal to 1.

[0015] Preferably, the ratio of the depth of the metal crystal of the first metal electrode into the P-type doped polysilicon layer to the depth of the metal crystal of the second metal electrode into the N-type doped polysilicon layer is 1-2, and not equal to 1.

[0016] Preferably, the depth of the metal crystal of the first metal electrode into the P-type doped polysilicon layer is 2-300 nm, and the depth of the metal crystal of the second metal electrode into the N-type doped polysilicon layer is 1-200 nm.

[0017] Preferably, the first metal electrode and the second metal electrode each include silver, glass frit, and an organic material, and the content of the glass frit in the first metal electrode is greater than the content of the glass frit in the second metal electrode.

[0018] Preferably, the refractive index of the P-type doped polysilicon layer is less than the refractive index of the N-type doped polysilicon layer.

[0019] Preferably, a back passivation film layer is further arranged on the back surface of the P-type doped polysilicon layer and on the back surface of the N-type doped polysilicon layer, the metal crystal of the first metal electrode penetrates the back passivation film layer to enter the P-type doped polysilicon layer, and the metal crystal of the second metal electrode penetrates the back passivation film layer to enter the N-type doped polysilicon.

[0020] Preferably, the average grain size of the P-type doped polysilicon layer is greater than the average grain size of the N-type doped polysilicon layer.

[0021] Preferably, the ratio of the average grain size of the P-type doped polysilicon layer to the average grain size of the N-type doped polysilicon layer is 1-4, and not equal to 1.

[0022] Preferably, the thickness of the N-type doped polysilicon layer is greater than the thickness of the P-type doped polysilicon layer.

[0023] Preferably, the ratio of the thickness of the N-type doped polysilicon layer to the thickness of the P-type doped polysilicon layer is 1-2, and not equal to 1.

[0024] The present disclosure also provides a battery assembly comprising the back contact solar cell described above.

[0025] The present disclosure also provides a photovoltaic system comprising the battery assembly described above.

[0026] The back contact solar cell provided by the present disclosure increases the depth of the metal crystal of the first metal electrode into the P-type doped polysilicon layer, increases the contact area of the metal crystal of the first metal electrode with the P-type doped polysilicon layer, improves the contact effect of the first metal electrode with the P-type doped polysilicon layer, realizes good ohmic contact, improves the conductive performance of the first metal electrode with the P-type doped polysilicon layer, and thus improves the battery conversion efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0027] FIG. 1 is a schematic diagram of a back contact solar cell provided by an embodiment of the present disclosure;

[0028] FIG. 2 is a schematic diagram of a partial structure of a back contact solar cell provided by an embodiment of the present disclosure;

[0029] FIG. 3 is a scanning electron microscope photo of the metal crystal of the first metal electrode of a back contact solar cell provided by an embodiment of the present disclosure entering the P-type doped polysilicon layer;

[0030] FIG. 4 is a scanning electron microscope photo of the metal crystal of the second metal electrode of a back contact solar cell provided by an embodiment of the present disclosure entering the N-type doped polysilicon layer. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the present disclosure is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present disclosure, and are not used to limit the present disclosure.

[0032] The back contact solar cell provided by the embodiment of the present disclosure sets the depth of the metal crystal of the first metal electrode into the P-type doped polysilicon layer to be greater than the depth of the metal crystal of the second metal electrode into the N-type doped polysilicon layer, increases the depth of the metal crystal of the first metal electrode into the P-type doped polysilicon layer compared with the second metal electrode, increases the contact area of the metal crystal of the first metal electrode and the P-type doped polysilicon layer, improves the contact effect of the first metal electrode and the P-type doped polysilicon layer, realizes good ohmic contact, improves the conductive performance of the first metal electrode and the P-type doped polysilicon layer, and thus improves the conversion efficiency of the cell.

[0033] Please refer to FIG. 1, the back contact solar cell provided by the embodiment of the present disclosure includes:

[0034] The silicon substrate 1 has a back surface and a front surface arranged oppositely.

[0035] The P-type doped polysilicon layer 2 is located in the first region of the back surface of the silicon substrate 1.

[0036] The N-type doped polysilicon layer 3 is located in the second region of the back surface of the silicon substrate 1, and the first region is different from the second region.

[0037] The first metal electrode 6 is arranged in the first region and in contact with the P-type doped polysilicon layer 2.

[0038] The second metal electrode 7 is arranged in the second region and in contact with the N-type doped polysilicon layer 3.

[0039] The depth d3 of the metal crystal of the first metal electrode 6 into the P-type doped polysilicon layer 2 is greater than the depth d4 of the metal crystal of the second metal electrode 7 into the N-type doped polysilicon layer 3.

[0040] As shown in FIG. 1, the back surface of the silicon substrate 1 is the lower side, and the front surface is the upper side. The dashed line L1 and the dashed line L2 are only used to distinguish the first region and the second region, and are not actually present in the back contact solar cell. Referring to FIG. 1, the region on the left side of the dashed line L1 is the first region, and the region on the right side of the dashed line L2 is the second region. The first region and the second region are different regions. The P-type doped polysilicon layer 2 is located in the first region of the back surface of the silicon substrate 1, and the N-type doped polysilicon layer 3 is located in the second region of the back surface of the silicon substrate 1. The P-type doped polysilicon layer 2 is located in the region on the left side of the dashed line L1 of the back surface of the silicon substrate 1, and the N-type doped polysilicon layer 3 is located in the region on the right side of the dashed line L2 of the back surface of the silicon substrate 1.

[0041] In the embodiment of the present disclosure, the back contact solar cell is provided by setting the depth d3 of the metal crystal of the first metal electrode 6 into the P-type doped polysilicon layer 2 to be greater than the depth d4 of the metal crystal of the second metal electrode 7 into the N-type doped polysilicon layer 3, increasing the depth of the metal crystal of the first metal electrode 6 into the P-type doped polysilicon layer 3 under the premise that the depth of the metal crystal of the second metal electrode 7 into the N-type doped polysilicon layer 3 is unchanged, increasing the contact area of the metal crystal of the first metal electrode 6 with the P-type doped polysilicon layer 2, improving the contact effect of the first metal electrode 6 with the P-type doped polysilicon layer 2, thus improving the conductive performance of the first metal electrode 6 with the P-type doped polysilicon layer 2, thereby improving the conversion efficiency of the cell.

[0042] In the embodiment of the present disclosure, the first metal electrode 6 and the second metal electrode 7 can be printed by using slurries with different burn-through capabilities, so as to control the depths of the metal crystals of the metal electrodes into the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3. Specifically, the slurry burn-through capability of the first metal electrode 6 is greater than that of the second metal electrode 7, so that the depth of the metal crystal of the first metal electrode 6 into the P-type doped polysilicon layer 2 is greater than that of the metal crystal of the second metal electrode 7 into the N-type doped polysilicon layer 3.

[0043] As an embodiment of the present disclosure, the first metal electrode 6 and the second metal electrode 7 each include silver, glass frit and organic material, and the content of the glass frit in the first metal electrode 6 is greater than that in the second metal electrode 7.

[0044] In the embodiment, the first metal electrode 6 and the second metal electrode 7 each include silver, glass frit and organic material components; the glass frit includes at least one of PbO, Bi2O3, ZnO, SiO2 and MgO, and the content of the glass frit in the first metal electrode 6 is greater than that in the second metal electrode 7, so that the slurry burn-through capability of the first metal electrode 6 is greater than that of the second metal electrode 7, and thus the depth of the metal crystal of the first metal electrode 6 into the P-type doped polysilicon layer 2 is greater than that of the metal crystal of the second metal electrode 7 into the N-type doped polysilicon layer 3.

[0045] As one embodiment of the present disclosure, the depth d3 of the metal crystal of the first metal electrode 6 into the P-type doped polysilicon layer 2 is 2-300 nm; the depth d4 of the metal crystal of the second metal electrode 7 into the N-type doped polysilicon layer 3 is 1-200 nm. Among them, the depth d3 of the metal crystal of the first metal electrode 6 into the P-type doped polysilicon layer 2 and the depth d4 of the metal crystal of the second metal electrode 7 into the N-type doped polysilicon layer 3 can be flexibly set according to actual needs. Among them, the depth d3 of the metal crystal of the first metal electrode 6 into the P-type doped polysilicon layer 2 and the depth d4 of the metal crystal of the second metal electrode 7 into the N-type doped polysilicon layer 3 can be measured by a scanning electron microscope.

[0046] For example, the depth d3 of the metal crystal of the first metal electrode 6 into the P-type doped polysilicon layer 2 can be 2 nm, or 10 nm, or 30 nm, or 50 nm, or 70 nm, or 90 nm, or 100 nm, or 110 nm, or 120 nm, or 140 nm, or 160 nm, or 200 nm, or 240 nm, or 260 nm, or 280 nm, or 300 nm. The depth d4 of the metal crystal of the second metal electrode 7 into the N-type doped polysilicon layer 3 can be 1 nm, or 5 nm, or 20 nm, or 30 nm, or 50 nm, or 80 nm, or 90 nm, or 100 nm, or 120 nm, or 130 nm, or 150 nm, or 160 nm, or 180 m, or 190 nm, or 200 nm.

[0047] As one embodiment of the present disclosure, the ratio of the depth d3 of the metal crystal of the first metal electrode 6 into the P-type doped polysilicon layer 2 to the depth d4 of the metal crystal of the second metal electrode 7 into the N-type doped polysilicon layer 3 is 1-4, and not equal to 1.

[0048] In this embodiment, the ratio of the depth d3 of the metal crystal of the first metal electrode 6 into the P-type doped polysilicon layer 2 to the depth d4 of the metal crystal of the second metal electrode 7 into the N-type doped polysilicon layer 3 is greater than 1 and less than or equal to 4, which can not only reduce the metallization damage of the P-type doped polysilicon layer 2, reduce the P-area resistance, and improve the battery efficiency, but also can ensure good contact between the metal electrode and the P-type doped polysilicon layer 2, and improve the battery conversion efficiency.

[0049] For example, the ratio of the depth d3 of the metal crystal of the first metal electrode 6 into the P-type doped polysilicon layer 2 to the depth d4 of the metal crystal of the second metal electrode 7 into the N-type doped polysilicon layer 3 can be:

[0050] 1.01, or 1.05, or 1.1, or 1.15, or 1.2, or 1.25, or 1.3, or 1.35, or 1.4, or 1.45, or 1.5, or 1.55, or 1.6, or 1.65, or 1.7, or 1.75, or 1.8, or 1.85, or 1.9, or 1.92, or 2, or 2.2, or 2.5, or 2.7, or 2.8, or 3.0, or 3.3, or 3.5, or 4.0.

[0051] As an embodiment of the present disclosure, the ratio of the depth d3 of the metal crystal of the first metal electrode 6 into the P-type doped polysilicon layer 2 to the depth d4 of the metal crystal of the second metal electrode 7 into the N-type doped polysilicon layer 3 is 1-2, and not equal to 1.

[0052] In the embodiment, the ratio of the depth d3 of the metal crystal of the first metal electrode 6 into the P-type doped polysilicon layer 2 to the depth d4 of the metal crystal of the second metal electrode 7 into the N-type doped polysilicon layer 3 is greater than 1 and less than or equal to 2, so that the good contact of the metal electrode and the P-type doped polysilicon layer 2 can be ensured, and the process control of the depth d3 of the metal crystal of the first metal electrode 6 into the P-type doped polysilicon layer 2 and the depth d4 of the metal crystal of the second metal electrode 7 into the N-type doped polysilicon layer 3 is facilitated.

[0053] As an embodiment of the present disclosure, the depth of the metal crystal of the first metal electrode 6 into the P-type doped polysilicon layer 2 is 2-300 nm; the depth of the metal crystal of the second metal electrode 7 into the N-type doped polysilicon layer 3 is 1-200 nm, so as to avoid the depth of the metal crystal of the first metal electrode 6 into the P-type doped polysilicon layer 2 and the depth of the metal crystal of the second metal electrode 7 into the N-type doped polysilicon layer 3 being too deep or too shallow. The depth d3 of the metal crystal of the first metal electrode 6 into the P-type doped polysilicon layer 2 and the depth d4 of the metal crystal of the second metal electrode 7 into the N-type doped polysilicon layer 3 can be flexibly set according to actual needs.

[0054] For example, the depth d3 of the metal crystal of the first metal electrode 6 into the P-type doped polysilicon layer 2 can be 2 nm, or 10 nm, or 30 nm, or 50 nm, or 70 nm, or 90 nm, or 100 nm, or 110 nm, or 120 nm, or 140 nm, or 160 nm, or 200 nm, or 240 nm, or 260 nm, or 280 nm, or 300 nm. The depth d4 of the metal crystal of the second metal electrode 7 into the N-type doped polysilicon layer 3 can be 1 nm, or 5 nm, or 20 nm, or 30 nm, or 50 nm, or 80 nm, or 90 nm, or 100 nm, or 120 nm, or 130 nm, or 150 nm, or 160 nm, or 180 m, or 190 nm, or 200 nm.

[0055] For example, as shown in FIG. 3, the thickness d2 of the P-type doped polysilicon layer 2 is 105 nm, and the depth d3 of the metal crystal of the first metal electrode 6 into the P-type doped polysilicon layer 2 is 55.6 nm; as shown in FIG. 4, the thickness of the N-type doped polysilicon layer 2 is 107 nm, and the depth d4 of the metal crystal of the second metal electrode 7 into the N-type doped polysilicon layer 3 is 45.6 nm.

[0056] As an embodiment of the present disclosure, the thickness d1 of the N-type doped polysilicon layer 3 is greater than the thickness d2 of the P-type doped polysilicon layer 2.

[0057] In the embodiment, by setting the thickness d1 of the N-type doped polysilicon layer 3 to be greater than the thickness d2 of the P-type doped polysilicon layer 2, the thickness d2 of the P-type doped polysilicon layer 2 is reduced compared with the thickness d1 of the N-type doped polysilicon layer 3, the etching difficulty of the P-type doped polysilicon layer 2 is reduced, the patterning process difficulty is reduced, and the P-type doped polysilicon layer is facilitated to be subjected to the patterning process; moreover, the thickness d2 of the P-type doped polysilicon layer 2 is reduced, the boron diffusion difficulty is reduced, the boron diffusion process is facilitated, and a P-type doped polysilicon layer 2 with a higher concentration is facilitated to be prepared; moreover, the thickness d1 of the N-type doped polysilicon layer 3 is greater than the thickness d2 of the P-type doped polysilicon layer 2, the N-type doped polysilicon layer 3 is thicker than the P-type doped polysilicon layer 2, the passivation effect is enhanced, and the cell efficiency is improved.

[0058] As an embodiment of the present disclosure, the ratio of the thickness d1 of the N-type doped polysilicon layer 3 to the thickness d2 of the P-type doped polysilicon layer 2 is 1-2, and is not equal to 1.

[0059] In this embodiment, the ratio of the thickness d1 of the N-type doped polysilicon layer 3 to the thickness d2 of the P-type doped polysilicon layer 2 is greater than 1 and less than or equal to 2. In this way, the etching difficulty of the P-type doped polysilicon layer 2 can be reduced, the patterning process of the P-type doped polysilicon layer 2 is facilitated, the boron diffusion process is facilitated, the boron diffusion difficulty is reduced, and a P-type doped polysilicon layer 2 with a higher concentration can be prepared.

[0060] For example, the ratio of the thickness d1 of the N-type doped polysilicon layer 3 to the thickness d2 of the P-type doped polysilicon layer 2 can be:

[0061] 1.01, or 1.05, or 1.1, or 1.15, or 1.2, or 1.25, or 1.3, or 1.35, or 1.4, or 1.45, or 1.5, or 1.55, or 1.6, or 1.65, or 1.7, or 1.75, or 1.8, or 1.85, or 1.9, or 1.92, or 2.

[0062] Alternatively, when the ratio of d1 to d2 is 1 to 2, the thickness d1 of the N-type doped polysilicon layer 3 can be 100 nm to 600 nm, and the thickness d2 of the P-type doped polysilicon layer 2 can be 50 nm to 300 nm. When d1 and d2 are within the above range, both the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 can achieve good doping effects, both have good passivation effects, while ensuring that the metallization damage is small and the contact resistance is small, and the cost is relatively low; in addition, the etching difficulty of the P-type doped polysilicon can be reduced, the patterning process of the P-type doped polysilicon is facilitated, the preparation of the N-type doped polysilicon layer 3 is facilitated, the boron diffusion process is facilitated, the boron diffusion difficulty is reduced, and a P-type doped polysilicon layer 2 with a high concentration can be prepared.

[0063] As an embodiment of the present disclosure, the refractive index of the P-type doped polysilicon layer 2 is less than the refractive index of the N-type doped polysilicon layer 3.

[0064] It can be understood that the refractive index of the N-type doped polysilicon layer 3 remains unchanged, and the refractive index of the P-type doped polysilicon layer 2 is reduced so that the refractive index of the P-type doped polysilicon layer 2 is less than the refractive index of the N-type doped polysilicon layer 3. In this way, the parasitic absorption effect of the P region can be reduced, and the cell efficiency can be further improved. The refractive index of the P-type doped polysilicon layer 2 and the refractive index of the N-type doped polysilicon layer 3 are flexibly set according to actual needs, as long as the refractive index of the P-type doped polysilicon layer 2 is less than the refractive index of the N-type doped polysilicon layer 3.

[0065] As an embodiment of the present disclosure, the average grain size of the P-type doped polysilicon layer 2 is greater than the average grain size of the N-type doped polysilicon layer 3.

[0066] In the embodiment, the average grain size of the P-type doped polysilicon layer 2 and the average grain size of the N-type doped polysilicon layer 3 can be measured by using an X-ray diffraction (XRD) instrument, a scanning electronic microscope (SEM) or a transmission electron microscope (TEM). The average grain size of the P-type doped polysilicon layer 2 is greater than the average grain size of the N-type doped polysilicon layer 3. It can be understood that the average value of all grain sizes of the P-type doped polysilicon layer 2 per unit area is greater than the average value of all grain sizes of the N-type doped polysilicon layer 3 per unit area. That is, in a unit area, the number of grains in the N-type doped polysilicon layer 3 is greater, and compared with the N-type doped polysilicon layer 3 per unit area, the P-type doped polysilicon layer 2 per unit area has a smaller number of grain boundaries, so that the density of the P-type doped polysilicon layer 2 can be improved, the sheet resistance of the P-type doped polysilicon layer 2 can be reduced, the current loss can be reduced, and thus the battery efficiency can be further improved. Moreover, the P-type doped polysilicon layer 2 has a smaller number of grain boundaries, which can reduce the damage of the P-type doped polysilicon layer 2 in the battery metallization process, and also helps to improve the battery efficiency.

[0067] In practical applications, in the preparation process of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3, intrinsic amorphous silicon can be deposited first, and then doping diffusion is performed. The average grain size of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 can be controlled by controlling the diffusion temperature and diffusion time of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 during the doping diffusion process. For example, the doping diffusion temperature of the P-type doped polysilicon layer 2 can be set to be higher, and the diffusion time can be longer, so that the average grain size of the prepared P-type doped polysilicon layer 2 can be greater than the average grain size of the N-type doped polysilicon layer 3.

[0068] As an embodiment of the present disclosure, the ratio of the average grain size of the P-type doped polysilicon layer 2 to the average grain size of the N-type doped polysilicon layer 3 is 1-4, and not equal to 1.

[0069] In the embodiment, the ratio of the grain size of the P-type doped polysilicon layer 2 to the grain size of the N-type doped polysilicon layer 3 is greater than 1 and less than or equal to 4, so that the average grain size of the P-type doped polysilicon layer 2 and the average grain size of the N-type doped polysilicon layer 3 can be ensured to be within a suitable range, which can reduce the sheet resistance of the P-type doped polysilicon layer 2, improve the battery efficiency, and facilitate the preparation of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3.

[0070] As one embodiment of the present disclosure, the average grain size of the P-type doped polysilicon layer 2 is 50-600 nm; the average grain size of the N-type doped polysilicon layer 3 is 10-400 nm, which facilitates the preparation of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3.

[0071] As one embodiment of the present disclosure, the surface of the P-type doped polysilicon layer 2 close to the silicon substrate 1 has a first height difference h1 from the surface of the N-type doped polysilicon layer 3 close to the silicon substrate 1, and the surface of the P-type doped polysilicon layer 2 close to the silicon substrate 1 is farther away from the front surface of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 close to the silicon substrate 1.

[0072] In the present embodiment, the surface of the silicon substrate 1 close to the P-type doped polysilicon layer 2 is not in the same plane as the surface close to the N-type doped polysilicon layer 3; the surface of the P-type doped polysilicon layer 2 close to the silicon substrate 1 is farther away from the front surface of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 close to the silicon substrate 1, and the surface of the P-type doped polysilicon layer 2 close to the silicon substrate 1 has a first height difference h1 from the surface of the N-type doped polysilicon layer 3 close to the silicon substrate 1. The relative position of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 is more accurately controlled, and the position reference is more accurate. Moreover, the portion of the first doped polysilicon layer that needs to be etched is etched more cleanly before the second doped polysilicon layer is prepared, and the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 in the gap between the first region and the second region are etched more cleanly, and the electrical performance is better. The first height difference h1 can be flexibly set according to actual needs, which is not limited herein.

[0073] As one embodiment of the present disclosure, the surface of the P-type doped polysilicon layer 2 close to the silicon substrate 1 has a second height difference h2 from the surface of the N-type doped polysilicon layer 3 away from the silicon substrate 1, and the surface of the P-type doped polysilicon layer 2 close to the silicon substrate 1 is farther away from the front surface of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 away from the silicon substrate 1.

[0074] In the present embodiment, the surface of the P-type doped polysilicon layer 2 away from the silicon substrate 1 is farther away from the front surface of the silicon substrate 1 than the surface of the N-type doped polysilicon layer 3 away from the silicon substrate 1, and the surface of the P-type doped polysilicon layer 2 away from the silicon substrate 1 has a second height difference h2 from the surface of the N-type doped polysilicon layer 3 away from the silicon substrate 1, which achieves good isolation effect of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3, good electrical isolation effect, and lower risk of short circuit or electric leakage. The second height difference h2 can be flexibly set according to actual needs, which is not limited herein.

[0075] As an embodiment of the present disclosure, the front surface of the silicon substrate 1 can also be provided with a textured structure (not shown in the figure). The textured structure can achieve good light trapping effect and improve the conversion efficiency of the back contact solar cell.

[0076] As an embodiment of the present disclosure, the front surface of the back contact solar cell is also provided with a front passivation anti-reflection film layer 9, which further reduces light reflection and further improves the conversion efficiency of the back contact solar cell.

[0077] As an embodiment of the present disclosure, the back contact solar cell further comprises a back passivation film layer 5 located between the back surface of the P-type doped polysilicon layer 2 and the back surface of the N-type doped polysilicon layer 3. The metal crystal of the first metal electrode 6 penetrates the back passivation film layer 5 into the P-type doped polysilicon layer 2, and the metal crystal of the second metal electrode 7 penetrates the back passivation film layer 5 into the N-type doped polysilicon layer 3. By providing the back passivation film layer 5, the passivation effect of the back surface of the cell is further improved, and the conversion efficiency of the back contact solar cell is further improved.

[0078] As an embodiment of the present disclosure, the silicon substrate 1 is also provided with a groove 8 located between the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3. The groove 8 can physically isolate the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3, further improve the isolation effect of the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3, and further reduce the risk of short circuit or electric leakage. The width of the groove 8 can be flexibly set according to actual needs, which is not limited herein.

[0079] The present disclosure also provides a battery assembly comprising the back contact solar cell of the above-mentioned embodiments. It should be noted that the battery assembly and the back contact solar cell have the same or similar beneficial effects, and the related parts between the two can be referred to each other. In order to avoid repetition, it will not be described here.

[0080] The present disclosure also provides a photovoltaic system comprising the battery assembly of the above-mentioned embodiments. It should be noted that the battery assembly and the back contact solar cell have the same or similar beneficial effects, and the related parts between the two can be referred to each other. In order to avoid repetition, it will not be described here.

[0081] The back contact solar cell provided by the embodiment of the present disclosure sets the depth of the metal crystal of the first metal electrode into the P-type doped polysilicon layer to be greater than the depth of the metal crystal of the second metal electrode into the N-type doped polysilicon layer, increases the depth of the metal crystal of the first metal electrode into the P-type doped polysilicon layer under the premise that the depth of the metal crystal of the second metal electrode into the N-type doped polysilicon layer remains unchanged, can increase the contact area of the metal crystal of the first metal electrode and the P-type doped polysilicon layer, improve the contact effect of the first metal electrode and the P-type doped polysilicon layer, realize good ohmic contact, improve the conductive performance of the first metal electrode and the P-type doped polysilicon layer, and thus improve the conversion efficiency of the cell.

[0082] The above merely describes the preferred embodiments of the present disclosure and is not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A back-contact solar cell, wherein, include: A silicon substrate having a back side and a front side disposed opposite to each other; A P-type doped polycrystalline silicon layer is located in the first region on the back side of the silicon substrate; An N-type doped polycrystalline silicon layer is located in a second region on the back side of the silicon substrate, and the first region is different from the second region; A first metal electrode is disposed in the first region and in contact with the P-type doped polysilicon layer; A second metal electrode is disposed in the second region and in contact with the N-type doped polysilicon layer; Wherein, the depth to which the metal crystal of the first metal electrode penetrates the P-type doped polycrystalline silicon layer is greater than the depth to which the metal crystal of the second metal electrode penetrates the N-type doped polycrystalline silicon layer.

2. The back-contact solar cell according to claim 1, wherein, The ratio of the depth of the metal crystal of the first metal electrode entering the P-type doped polysilicon layer to the depth of the metal crystal of the second metal electrode entering the N-type doped polysilicon layer is 1 to 4, and not equal to 1.

3. The back-contact solar cell according to claim 1, wherein, The ratio of the depth of the metal crystal of the first metal electrode entering the P-type doped polysilicon layer to the depth of the metal crystal of the second metal electrode entering the N-type doped polysilicon layer is 1 to 2, and not equal to 1.

4. The back-contact solar cell according to claim 1, wherein, The depth of the metal crystal of the first metal electrode penetrating the P-type doped polycrystalline silicon layer is 2-300 nm; the depth of the metal crystal of the second metal electrode penetrating the N-type doped polycrystalline silicon layer is 1-200 nm.

5. The back-contact solar cell according to claim 1, wherein, Both the first metal electrode and the second metal electrode comprise silver, glass frit, and organic materials, and the glass frit content in the first metal electrode is greater than that in the second metal electrode.

6. The back-contact solar cell according to claim 1, wherein, The refractive index of the P-type doped polycrystalline silicon layer is less than that of the N-type doped polycrystalline silicon layer.

7. The back-contact solar cell according to claim 1, wherein, It also includes a back passivation film layer located on the back side of the P-type doped polysilicon layer and the back side of the N-type doped polysilicon layer, wherein the metal crystal of the first metal electrode passes through the back passivation film layer into the P-type doped polysilicon layer, and the metal crystal of the second metal electrode passes through the back passivation film layer into the N-type doped polysilicon layer.

8. The back-contact solar cell according to claim 1, wherein, The average grain size of the P-type doped polycrystalline silicon layer is greater than that of the N-type doped polycrystalline silicon layer.

9. The back-contact solar cell according to claim 8, wherein, The ratio of the average grain size of the P-type doped polycrystalline silicon layer to the average grain size of the N-type doped polycrystalline silicon layer is 1 to 4, and not equal to 1.

10. The back-contact solar cell according to claim 1, wherein, The thickness of the N-type doped polycrystalline silicon layer is greater than the thickness of the P-type doped polycrystalline silicon layer.

11. The back-contact solar cell according to claim 10, wherein, The ratio of the thickness of the N-type doped polycrystalline silicon layer to the thickness of the P-type doped polycrystalline silicon layer is 1 to 2, and is not equal to 1.

12. A battery assembly, wherein, Including the back-contact solar cell as described in any one of claims 1 to 11.

13. A photovoltaic system, wherein, Includes the battery assembly as described in claim 12.

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