Three-dimensional memory programming method

Abstract

A three-dimensional (3D) memory programming method, which relates to integrated circuit technology, and in particular to 3D memory technology. The present invention comprises the following steps: (1) floating at least one of a high-voltage level input line and a low-voltage level input line of an unselected memory cell; (2) applying a first level VH to a high-voltage level input line of a selected memory cell, and applying a second level VL to a low-voltage level input line of the selected memory cell, wherein the first level and the second level are characterized in that the first level VH and the second level VL meet the following relationships: VH>0 and VL<0, and a sum of an absolute value of the first level VH and an absolute value of the second level VL is equal to a preset programming voltage. The method of the present invention can reduce the load of a horizontal WL driving circuit, and overall reduce the leakage current and energy consumption thereof, thereby implementing a 3D memory of low power consumption and high reliability.

Description

Three-dimensional memory programming method TECHNICAL FIELD

[0001] The present invention relates to integrated circuit technology, and in particular to three-dimensional memory technology. BACKGROUND

[0002] As a prior art, US 2013 / 0043453 A1, see Fig. 1 and Fig. 2, the vertical bit line BL of a 3D memory device is selected by a lower bit line decoder array circuit, and the word line WL in each layer of the multi-layer stacked memory is also selected by a lower word line decoder array circuit. The previous programming method for such a memory generally adds a positive or negative voltage of the size of the programming voltage (Vpp) to the WL end, and the other end (corresponding to the BL) is grounded (Gnd), because the vertical BL dense point array arrangement, the lower selection tube is usually not suitable for using complex circuit to realize, so it is best to realize the bit line selection by the simplest mos tube. At this time, the BL selection mos tube can realize the voltage input of two states of 0V and floating (floating, or abbreviated as 'flt'), which respectively correspond to the selected BL and the unselected BL.

[0003] In order to better complete the independent work of different storage units, each storage unit will be accompanied by a separate diode rectifier unit, which is usually a pn junction diode or a Schottky diode. The rectification direction of the diode depends on the conduction type of the WL and BL. If the BL selection tube only has two states of 0V and floating, the WL needs to realize a positive or negative voltage of absolute value Vpp in the programming state. Table 1 shows the programming voltage of the 3D memory.

[0004] Table 1

[0005]

[0006] When the Vpp voltage is large, the energy consumption and leakage current of the driving circuit will also be large. In particular, in order to further improve the device performance of high-capacity and high-density memory, the horizontal electrode is preferably made of a metal material with extremely low resistivity which can form part of a Schottky diode, and the metal material which is mature in process and suitable for vertical etching with high aspect ratio, such as aluminum, titanium, etc., is generally an n-type conductive material. This means that if the BL selection tube only has two states of 0V and floating, the selection tube of the WL needs to realize a negative voltage of absolute value Vpp. The driving circuit of the negative voltage often consumes more energy and has larger leakage current.

[0007] Fig. 3 is another circuit structure of the prior art, and Table 2 shows its programming operation voltage (Vpp=6V, Vdd=2V).

[0008] Table 2

[0009]

[0010] flt: floating

[0011] SW: bit line selected

[0012] UW: bit line unselected

[0013] SB: word line selected

[0014] UB: word line unselected

[0015] rs: row select

[0016] cs: column select. Technical problem

[0017] The technical problem to be solved by the present application is to provide a three-dimensional memory programming method with lower leakage current and energy consumption, and higher stability. Technical solution

[0018] The technical solution adopted by the present application to solve the technical problem is a three-dimensional memory programming method, comprising the following steps:

[0019] (1) For unselected memory cells, at least one of the high-voltage level input line and the low-voltage level input line is floating;

[0020] (2) For selected memory cells, a first level VH is applied to the high-voltage level input line, and a second level VL is applied to the low-voltage level input line;

[0021] The first level VH and the second level VL satisfy the following relationship:

[0022] VH>0 and VL<0, and the sum of the absolute value of the first level VH and the absolute value of the second level VL is equal to a preset programming voltage. Advantages

[0023] The application still selects the vertical BL by using simple mos tubes, and uses the feature that the mos tube can realize lower voltage output, and by decomposing the programming voltage Vpp into Vpw and Vpb applied to WL and BL respectively, the absolute value sum of Vpw and Vpb is the required programming voltage Vpp, wherein Vpw and Vpb are negative voltage and positive voltage respectively, or vice versa, so that the voltage difference between the two ends is Vpp. The method of the application can reduce the burden of the horizontal WL driving circuit, reduce the leakage current size and energy consumption as a whole, and realize the 3D memory with low power consumption and high reliability.

[0024] The 3D data memory of the application uses the simplest mos tube as the selection tube to adapt to the vertical BL dense point array arrangement, thereby ensuring the high density feature of the 3D memory. Since the horizontal wire can be a more mature metal material with low conductivity, the high capacity and low cost features of the 3D memory are ensured. Moreover, under this architecture, even if the metal material of WL is an N-type Schottky conductor, the negative voltage driving circuit is also required, but the voltage output value of the negative voltage driving voltage can be appropriately reduced by splitting the higher programming voltage, thereby ensuring the low power consumption and high reliability features of the 3D memory. BRIEF DESCRIPTION OF DRAWINGS

[0025] FIG. 1 is a structural schematic diagram of the prior art.

[0026] FIG. 2 is a first circuit module diagram of the prior art.

[0027] FIG. 3 is a second circuit module diagram of the prior art.

[0028] FIG. 4 is a circuit module diagram of embodiment 1.

[0029] FIG. 5 is a circuit module diagram of embodiment 2.

[0030] FIG. 6 is a circuit module diagram of embodiment 3.

[0031] FIG. 7 is a circuit module diagram of embodiment 4. BEST MODE FOR CARRYING OUT THE INVENTION

[0032] Embodiment 1

[0033] Referring to FIG. 4, in the embodiment, the diode rectification direction is from the vertical bit line BL to the horizontal word line WL. For example, when Vpp=6V, the size of Vpb is usually 2.5V~0.9V according to the specification of the mos bit line selection tube, and Vpw is -3.5V~-5.1V. Table 3 is a write operation voltage table of the embodiment, which lists the case where Vpw and Vpb are -4V and 2V respectively. At this time, Vpw changes from the original -6V to -4V, reducing the output voltage value of the WL driving circuit.

[0034] Table 3

[0035]

[0036] Embodiment 2

[0037] Referring to FIG. 5, in the embodiment, the diode rectification direction is from the horizontal word line WL to the vertical bit line BL. For example, when Vpp=6V, the size of Vpb is usually -2.5V~-0.9V according to the specification of the mos bit line selection tube, and Vpw is 3.5V~5.1V.

[0038] Table 4 lists the case where Vpw and Vpb are 4V and -2V respectively. At this time, Vpw changes from the original 6V to 4V, reducing the output voltage value of the WL driving circuit.

[0039] Table 4

[0040]

[0041] Embodiment 3

[0042] Referring to FIG. 6, in the embodiment, all pmos tubes of the BL decoder array circuit share an N-type well N-Well. When working, N-Well is connected to high level Vdd (2V).

[0043] Through the row selection signal, the selected row line is set to 2V high level, and the unselected row line is set to 0V.

[0044] Table 5 shows the programming operation voltage (Vpw=-4V, Vdd=2V).

[0045] Table 5

[0046]

[0047] In this example, the vertical BL is the positive electrode of the diode, and the horizontal WL is the negative electrode of the diode. Therefore, n-type Schottky metal such as titanium and aluminum, which has high feasibility for vertical etching, can be used as the horizontal electrode WL, thereby greatly reducing the resistance of the horizontal electrode, facilitating the realization of high capacity of the storage, and using a simple structure of the pmos tube as the decoding array unit of the vertical BL of the 3D storage array to ensure high-density integration of the storage.

[0048] Embodiment 4

[0049] Referring to FIG. 7, on the basis of Embodiment 2, in order to prevent the gate insulating layer of the BL selection tube from being broken down after the BL potential is pulled up due to the high resistance state of the storage medium changing to a low resistance state, a high-voltage blocking device composed of a vertical pmos tube is inserted between the vertical BL and the selection tube, as shown in the dashed box in FIG. 7. In order to make the high-voltage blocking device work effectively, the mos channel needs to be in an always-on state, which is controlled by the gate opening voltage Vblock (such as 0V), and the thickness of the gate insulating layer needs to satisfy the non-breakdown condition. Compared with Example 3, this embodiment has higher reliability without affecting any operation performance.

Claims

1. A method for programming a three-dimensional memory, comprising the steps of: (1) for unselected memory cells, at least one of the high voltage level input line and the low voltage level input line is floating; (2) for selected memory cells, a first voltage level VH is applied to the high voltage level input line and a second voltage level VL is applied to the low voltage level input line; characterized in that the first voltage level VH and the second voltage level VL satisfy the following relationship: VH > 0 and VL < 0, and the sum of the absolute value of the first voltage level VH and the absolute value of the second voltage level VL equals a preset programming voltage.

2. The three-dimensional memory programming method of claim 1, wherein, the first voltage level VH is greater than 1V and the second voltage level VL is less than -1V.

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